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1// SPDX-License-Identifier: ISC
2/*
3 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
4 */
5
6/dts-v1/;
7
8#include "intel-ixp43x.dtsi"
9
10/ {
11 model = "Gateworks Cambria GW2358";
12 compatible = "gateworks,gw2358", "intel,ixp43x";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 memory@0 {
17 /* 128 MB SDRAM */
18 device_type = "memory";
19 reg = <0x00000000 0x8000000>;
20 };
21
22 chosen {
23 bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
24 stdout-path = "uart0:115200n8";
25 };
26
27 aliases {
28 serial0 = &uart0;
29 };
30
31 leds {
32 compatible = "gpio-leds";
33 led-user {
34 label = "gw2358:green:LED";
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
36 default-state = "on";
37 linux,default-trigger = "heartbeat";
38 };
39 };
40
41
42 i2c {
43 compatible = "i2c-gpio";
44 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
45 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 hwmon@28 {
50 compatible = "adi,ad7418";
51 reg = <0x28>;
52 };
53 rtc: ds1672@68 {
54 compatible = "dallas,ds1672";
55 reg = <0x68>;
56 };
57 eeprom@51 {
58 compatible = "atmel,24c08";
59 reg = <0x51>;
60 pagesize = <16>;
61 size = <1024>;
62 read-only;
63 };
64 pld0: pld@56 {
65 compatible = "gateworks,pld-gpio";
66 reg = <0x56>;
67 gpio-controller;
68 #gpio-cells = <2>;
69 };
70 /* This PLD just handles the LED and user button */
71 pld1: pld@57 {
72 compatible = "gateworks,pld-gpio";
73 reg = <0x57>;
74 gpio-controller;
75 #gpio-cells = <2>;
76 };
77 };
78
79 soc {
80 bus@50000000 {
81 flash@0 {
82 compatible = "intel,ixp4xx-flash", "cfi-flash";
83 bank-width = <2>;
84 /*
85 * 32 MB of Flash in 0x20000 byte blocks
86 * mapped in at CS0.
87 */
88 reg = <0x00000000 0x2000000>;
89
90 partitions {
91 compatible = "redboot-fis";
92 /* Eraseblock at 0x1fe0000 */
93 fis-index-block = <0xff>;
94 };
95 };
96 };
97
98 pci@c0000000 {
99 status = "ok";
100
101 /*
102 * In the boardfile for the Cambria from OpenWRT the interrupts
103 * are assigned one per IDSEL, so all 4 interrupts from IDSEL
104 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
105 * connected to IRQ 10 etc. I find this highly unlikely so I
106 * have instead assumed that they are rotated (swizzled) like
107 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
108 */
109 interrupt-map =
110 /* IDSEL 1 */
111 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
112 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
113 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
114 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
115 /* IDSEL 2 */
116 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
117 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
118 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
119 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
120 /* IDSEL 3 */
121 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
122 <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
123 <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
124 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
125 /* IDSEL 4 */
126 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
127 <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
128 <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
129 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
130 /* IDSEL 6 */
131 <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
132 <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
133 <0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
134 <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
135 /* IDSEL 15 */
136 <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
137 <0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
138 <0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
139 <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
140 };
141
142 ethernet@c800a000 {
143 status = "ok";
144 queue-rx = <&qmgr 4>;
145 queue-txready = <&qmgr 21>;
146 phy-mode = "rgmii";
147 phy-handle = <&phy1>;
148
149 mdio {
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 phy1: ethernet-phy@1 {
154 reg = <1>;
155 };
156
157 phy2: ethernet-phy@2 {
158 reg = <2>;
159 };
160 };
161 };
162
163 ethernet@c800c000 {
164 status = "ok";
165 queue-rx = <&qmgr 2>;
166 queue-txready = <&qmgr 19>;
167 phy-mode = "rgmii";
168 phy-handle = <&phy2>;
169 intel,npe-handle = <&npe 0>;
170 };
171 };
172};