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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8
9/ {
10 chosen {
11 stdout-path = &uart4;
12 };
13
14 memory@10000000 {
15 device_type = "memory";
16 reg = <0x10000000 0x80000000>;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_gpio_leds>;
23
24 user {
25 label = "debug";
26 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
27 };
28 };
29
30 gpio-keys {
31 compatible = "gpio-keys";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_gpio_keys>;
34
35 home {
36 label = "Home";
37 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
38 linux,code = <KEY_HOME>;
39 wakeup-source;
40 };
41
42 back {
43 label = "Back";
44 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
45 linux,code = <KEY_BACK>;
46 wakeup-source;
47 };
48
49 program {
50 label = "Program";
51 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
52 linux,code = <KEY_PROGRAM>;
53 wakeup-source;
54 };
55
56 volume-up {
57 label = "Volume Up";
58 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
59 linux,code = <KEY_VOLUMEUP>;
60 wakeup-source;
61 };
62
63 volume-down {
64 label = "Volume Down";
65 gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
66 linux,code = <KEY_VOLUMEDOWN>;
67 wakeup-source;
68 };
69 };
70
71 clocks {
72 codec_osc: anaclk2 {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <24576000>;
76 };
77 };
78
79 reg_audio: regulator-audio {
80 compatible = "regulator-fixed";
81 regulator-name = "cs42888_supply";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 regulator-always-on;
85 };
86
87 reg_usb_h1_vbus: regulator-usb-h1-vbus {
88 compatible = "regulator-fixed";
89 regulator-name = "usb_h1_vbus";
90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>;
92 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
93 enable-active-high;
94 };
95
96 reg_usb_otg_vbus: regulator-usb-otg-vbus {
97 compatible = "regulator-fixed";
98 regulator-name = "usb_otg_vbus";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
101 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
102 enable-active-high;
103 };
104
105 reg_can_en: regulator-can-en {
106 compatible = "regulator-fixed";
107 regulator-name = "can-en";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
111 enable-active-high;
112 };
113
114 reg_can_stby: regulator-can-stby {
115 compatible = "regulator-fixed";
116 regulator-name = "can-stby";
117 regulator-min-microvolt = <3300000>;
118 regulator-max-microvolt = <3300000>;
119 gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
120 enable-active-high;
121 vin-supply = <®_can_en>;
122 };
123
124 sound-cs42888 {
125 compatible = "fsl,imx6-sabreauto-cs42888",
126 "fsl,imx-audio-cs42888";
127 model = "imx-cs42888";
128 audio-cpu = <&esai>;
129 audio-asrc = <&asrc>;
130 audio-codec = <&codec>;
131 audio-routing =
132 "Line Out Jack", "AOUT1L",
133 "Line Out Jack", "AOUT1R",
134 "Line Out Jack", "AOUT2L",
135 "Line Out Jack", "AOUT2R",
136 "Line Out Jack", "AOUT3L",
137 "Line Out Jack", "AOUT3R",
138 "Line Out Jack", "AOUT4L",
139 "Line Out Jack", "AOUT4R",
140 "AIN1L", "Line In Jack",
141 "AIN1R", "Line In Jack",
142 "AIN2L", "Line In Jack",
143 "AIN2R", "Line In Jack";
144 };
145
146 sound-spdif {
147 compatible = "fsl,imx-audio-spdif",
148 "fsl,imx-sabreauto-spdif";
149 model = "imx-spdif";
150 spdif-controller = <&spdif>;
151 spdif-in;
152 };
153
154 backlight {
155 compatible = "pwm-backlight";
156 pwms = <&pwm3 0 5000000>;
157 brightness-levels = <0 4 8 16 32 64 128 255>;
158 default-brightness-level = <7>;
159 status = "okay";
160 };
161
162 i2cmux {
163 compatible = "i2c-mux-gpio";
164 #address-cells = <1>;
165 #size-cells = <0>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c3mux>;
168 mux-gpios = <&gpio5 4 0>;
169 i2c-parent = <&i2c3>;
170 idle-state = <0>;
171
172 i2c@1 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 reg = <1>;
176
177 adv7180: camera@21 {
178 compatible = "adi,adv7180";
179 reg = <0x21>;
180 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
181 interrupt-parent = <&gpio1>;
182 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
183
184 port {
185 adv7180_to_ipu1_csi0_mux: endpoint {
186 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
187 bus-width = <8>;
188 };
189 };
190 };
191
192 max7310_a: gpio@30 {
193 compatible = "maxim,max7310";
194 reg = <0x30>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 };
198
199 max7310_b: gpio@32 {
200 compatible = "maxim,max7310";
201 reg = <0x32>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_max7310>;
206 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
207 };
208
209 max7310_c: gpio@34 {
210 compatible = "maxim,max7310";
211 reg = <0x34>;
212 gpio-controller;
213 #gpio-cells = <2>;
214 };
215
216 light-sensor@44 {
217 compatible = "isil,isl29023";
218 reg = <0x44>;
219 interrupt-parent = <&gpio5>;
220 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
221 };
222
223 magnetometer@e {
224 compatible = "fsl,mag3110";
225 reg = <0x0e>;
226 interrupt-parent = <&gpio2>;
227 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
228 };
229
230 accelerometer@1c {
231 compatible = "fsl,mma8451";
232 reg = <0x1c>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_mma8451_int>;
235 interrupt-parent = <&gpio6>;
236 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
237 };
238 };
239 };
240};
241
242&ipu1_csi0_from_ipu1_csi0_mux {
243 bus-width = <8>;
244};
245
246&ipu1_csi0_mux_from_parallel_sensor {
247 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
248 bus-width = <8>;
249};
250
251&ipu1_csi0 {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_ipu1_csi0>;
254};
255
256&clks {
257 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
258 <&clks IMX6QDL_PLL4_BYPASS>,
259 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
260 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
261 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
262 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
263 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
264 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
265 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
266 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
267};
268
269&ecspi1 {
270 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
273 status = "disabled"; /* pin conflict with WEIM NOR */
274
275 flash: m25p80@0 {
276 #address-cells = <1>;
277 #size-cells = <1>;
278 compatible = "st,m25p32", "jedec,spi-nor";
279 spi-max-frequency = <20000000>;
280 reg = <0>;
281 };
282};
283
284&esai {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_esai>;
287 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
288 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
289 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
290 assigned-clock-rates = <0>, <24576000>;
291 status = "okay";
292};
293
294&fec {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_enet>;
297 phy-mode = "rgmii-id";
298 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
299 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
300 fsl,err006687-workaround-present;
301 fsl,magic-packet;
302 status = "okay";
303};
304
305&can1 {
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_flexcan1>;
308 xceiver-supply = <®_can_stby>;
309 status = "disabled"; /* pin conflict with fec */
310};
311
312&can2 {
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_flexcan2>;
315 xceiver-supply = <®_can_stby>;
316 status = "okay";
317};
318
319&gpmi {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_gpmi_nand>;
322 status = "okay";
323};
324
325&hdmi {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_hdmi_cec>;
328 ddc-i2c-bus = <&i2c2>;
329 status = "okay";
330};
331
332&i2c2 {
333 clock-frequency = <100000>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_i2c2>;
336 status = "okay";
337
338 pmic: pfuze100@8 {
339 compatible = "fsl,pfuze100";
340 reg = <0x08>;
341
342 regulators {
343 sw1a_reg: sw1ab {
344 regulator-min-microvolt = <300000>;
345 regulator-max-microvolt = <1875000>;
346 regulator-boot-on;
347 regulator-always-on;
348 regulator-ramp-delay = <6250>;
349 };
350
351 sw1c_reg: sw1c {
352 regulator-min-microvolt = <300000>;
353 regulator-max-microvolt = <1875000>;
354 regulator-boot-on;
355 regulator-always-on;
356 regulator-ramp-delay = <6250>;
357 };
358
359 sw2_reg: sw2 {
360 regulator-min-microvolt = <800000>;
361 regulator-max-microvolt = <3300000>;
362 regulator-boot-on;
363 regulator-always-on;
364 };
365
366 sw3a_reg: sw3a {
367 regulator-min-microvolt = <400000>;
368 regulator-max-microvolt = <1975000>;
369 regulator-boot-on;
370 regulator-always-on;
371 };
372
373 sw3b_reg: sw3b {
374 regulator-min-microvolt = <400000>;
375 regulator-max-microvolt = <1975000>;
376 regulator-boot-on;
377 regulator-always-on;
378 };
379
380 sw4_reg: sw4 {
381 regulator-min-microvolt = <800000>;
382 regulator-max-microvolt = <3300000>;
383 };
384
385 swbst_reg: swbst {
386 regulator-min-microvolt = <5000000>;
387 regulator-max-microvolt = <5150000>;
388 };
389
390 snvs_reg: vsnvs {
391 regulator-min-microvolt = <1000000>;
392 regulator-max-microvolt = <3000000>;
393 regulator-boot-on;
394 regulator-always-on;
395 };
396
397 vref_reg: vrefddr {
398 regulator-boot-on;
399 regulator-always-on;
400 };
401
402 vgen1_reg: vgen1 {
403 regulator-min-microvolt = <800000>;
404 regulator-max-microvolt = <1550000>;
405 };
406
407 vgen2_reg: vgen2 {
408 regulator-min-microvolt = <800000>;
409 regulator-max-microvolt = <1550000>;
410 };
411
412 vgen3_reg: vgen3 {
413 regulator-min-microvolt = <1800000>;
414 regulator-max-microvolt = <3300000>;
415 };
416
417 vgen4_reg: vgen4 {
418 regulator-min-microvolt = <1800000>;
419 regulator-max-microvolt = <3300000>;
420 regulator-always-on;
421 };
422
423 vgen5_reg: vgen5 {
424 regulator-min-microvolt = <1800000>;
425 regulator-max-microvolt = <3300000>;
426 regulator-always-on;
427 };
428
429 vgen6_reg: vgen6 {
430 regulator-min-microvolt = <1800000>;
431 regulator-max-microvolt = <3300000>;
432 regulator-always-on;
433 };
434 };
435 };
436
437 codec: cs42888@48 {
438 compatible = "cirrus,cs42888";
439 reg = <0x48>;
440 clocks = <&codec_osc>;
441 clock-names = "mclk";
442 VA-supply = <®_audio>;
443 VD-supply = <®_audio>;
444 VLS-supply = <®_audio>;
445 VLC-supply = <®_audio>;
446 };
447
448 touchscreen@4 {
449 compatible = "eeti,egalax_ts";
450 reg = <0x04>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_egalax_int>;
453 interrupt-parent = <&gpio2>;
454 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
455 wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
456 };
457};
458
459&i2c3 {
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_i2c3>;
462 status = "okay";
463};
464
465&iomuxc {
466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_hog>;
468
469 imx6qdl-sabreauto {
470 pinctrl_hog: hoggrp {
471 fsl,pins = <
472 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
473 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
474 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
475 >;
476 };
477
478 pinctrl_ecspi1: ecspi1grp {
479 fsl,pins = <
480 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
481 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
482 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
483 >;
484 };
485
486 pinctrl_ecspi1_cs: ecspi1cs {
487 fsl,pins = <
488 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
489 >;
490 };
491
492 pinctrl_egalax_int: egalax-intgrp {
493 fsl,pins = <
494 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
495 >;
496 };
497
498 pinctrl_enet: enetgrp {
499 fsl,pins = <
500 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
501 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
502 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
503 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
504 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
505 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
506 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
507 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
508 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
509 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
510 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
511 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
512 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
513 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
514 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
515 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
516 >;
517 };
518
519 pinctrl_esai: esaigrp {
520 fsl,pins = <
521 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
522 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
523 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
524 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
525 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
526 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
527 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
528 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
529 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
530 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
531 >;
532 };
533
534 pinctrl_flexcan1: flexcan1grp {
535 fsl,pins = <
536 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059
537 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059
538 >;
539 };
540
541 pinctrl_flexcan2: flexcan2grp {
542 fsl,pins = <
543 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059
544 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059
545 >;
546 };
547
548 pinctrl_gpio_keys: gpiokeysgrp {
549 fsl,pins = <
550 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
551 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
552 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
553 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
554 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
555 >;
556 };
557
558 pinctrl_gpio_leds: gpioledsgrp {
559 fsl,pins = <
560 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
561 >;
562 };
563
564 pinctrl_gpmi_nand: gpminandgrp {
565 fsl,pins = <
566 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
567 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
568 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
569 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
570 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
571 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
572 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
573 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
574 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
575 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
576 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
577 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
578 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
579 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
580 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
581 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
582 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
583 >;
584 };
585
586 pinctrl_hdmi_cec: hdmicecgrp {
587 fsl,pins = <
588 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
589 >;
590 };
591
592 pinctrl_i2c2: i2c2grp {
593 fsl,pins = <
594 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
595 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
596 >;
597 };
598
599 pinctrl_i2c3: i2c3grp {
600 fsl,pins = <
601 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
602 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
603 >;
604 };
605
606 pinctrl_i2c3mux: i2c3muxgrp {
607 fsl,pins = <
608 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
609 >;
610 };
611
612 pinctrl_ipu1_csi0: ipu1csi0grp {
613 fsl,pins = <
614 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
615 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
616 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
617 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
618 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
619 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
620 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
621 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
622 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
623 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
624 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
625 >;
626 };
627
628 pinctrl_max7310: max7310grp {
629 fsl,pins = <
630 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
631 >;
632 };
633
634 pinctrl_mma8451_int: mma8451intgrp {
635 fsl,pins = <
636 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1
637 >;
638 };
639
640 pinctrl_pwm3: pwm1grp {
641 fsl,pins = <
642 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
643 >;
644 };
645
646 pinctrl_gpt_input_capture0: gptinputcapture0grp {
647 fsl,pins = <
648 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
649 >;
650 };
651
652 pinctrl_gpt_input_capture1: gptinputcapture1grp {
653 fsl,pins = <
654 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
655 >;
656 };
657
658 pinctrl_spdif: spdifgrp {
659 fsl,pins = <
660 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
661 >;
662 };
663
664 pinctrl_uart4: uart4grp {
665 fsl,pins = <
666 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
667 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
668 >;
669 };
670
671 pinctrl_usbotg: usbotggrp {
672 fsl,pins = <
673 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
674 >;
675 };
676
677 pinctrl_usdhc3: usdhc3grp {
678 fsl,pins = <
679 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
680 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
681 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
682 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
683 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
684 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
685 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
686 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
687 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
688 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
689 >;
690 };
691
692 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
693 fsl,pins = <
694 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
695 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
696 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
697 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
698 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
699 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
700 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
701 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
702 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
703 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
704 >;
705 };
706
707 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
708 fsl,pins = <
709 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
710 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
711 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
712 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
713 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
714 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
715 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
716 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
717 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
718 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
719 >;
720 };
721
722 pinctrl_weim_cs0: weimcs0grp {
723 fsl,pins = <
724 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
725 >;
726 };
727
728 pinctrl_weim_nor: weimnorgrp {
729 fsl,pins = <
730 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
731 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
732 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
733 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
734 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
735 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
736 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
737 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
738 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
739 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
740 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
741 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
742 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
743 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
744 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
745 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
746 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
747 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
748 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
749 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
750 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
751 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
752 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
753 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
754 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
755 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
756 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
757 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
758 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
759 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
760 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
761 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
762 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
763 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
764 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
765 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
766 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
767 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
768 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
769 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
770 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
771 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
772 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
773 >;
774 };
775 };
776};
777
778&ldb {
779 status = "okay";
780
781 lvds-channel@0 {
782 fsl,data-mapping = "spwg";
783 fsl,data-width = <18>;
784 status = "okay";
785
786 display-timings {
787 native-mode = <&timing0>;
788 timing0: hsd100pxn1 {
789 clock-frequency = <65000000>;
790 hactive = <1024>;
791 vactive = <768>;
792 hback-porch = <220>;
793 hfront-porch = <40>;
794 vback-porch = <21>;
795 vfront-porch = <7>;
796 hsync-len = <60>;
797 vsync-len = <10>;
798 };
799 };
800 };
801};
802
803&pwm3 {
804 #pwm-cells = <2>;
805 pinctrl-names = "default";
806 pinctrl-0 = <&pinctrl_pwm3>;
807 status = "okay";
808};
809
810&pcie {
811 status = "okay";
812};
813
814&spdif {
815 pinctrl-names = "default";
816 pinctrl-0 = <&pinctrl_spdif>;
817 status = "okay";
818};
819
820&uart4 {
821 pinctrl-names = "default";
822 pinctrl-0 = <&pinctrl_uart4>;
823 status = "okay";
824};
825
826&usbh1 {
827 vbus-supply = <®_usb_h1_vbus>;
828 status = "okay";
829};
830
831&usbotg {
832 vbus-supply = <®_usb_otg_vbus>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_usbotg>;
835 status = "okay";
836};
837
838&usdhc3 {
839 pinctrl-names = "default", "state_100mhz", "state_200mhz";
840 pinctrl-0 = <&pinctrl_usdhc3>;
841 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
842 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
843 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
844 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
845 status = "okay";
846};
847
848&weim {
849 pinctrl-names = "default";
850 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
851 ranges = <0 0 0x08000000 0x08000000>;
852 status = "disabled"; /* pin conflict with SPI NOR */
853
854 nor@0,0 {
855 compatible = "cfi-flash";
856 reg = <0 0 0x02000000>;
857 #address-cells = <1>;
858 #size-cells = <1>;
859 bank-width = <2>;
860 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
861 0x0000c000 0x1404a38e 0x00000000>;
862 };
863};
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 memory@10000000 {
17 reg = <0x10000000 0x80000000>;
18 };
19
20 leds {
21 compatible = "gpio-leds";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_gpio_leds>;
24
25 user {
26 label = "debug";
27 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
28 };
29 };
30
31 clocks {
32 codec_osc: anaclk2 {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <24576000>;
36 };
37 };
38
39 regulators {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 reg_audio: regulator@0 {
45 compatible = "regulator-fixed";
46 reg = <0>;
47 regulator-name = "cs42888_supply";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 regulator-always-on;
51 };
52
53 reg_usb_h1_vbus: regulator@1 {
54 compatible = "regulator-fixed";
55 reg = <1>;
56 regulator-name = "usb_h1_vbus";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
60 enable-active-high;
61 };
62
63 reg_usb_otg_vbus: regulator@2 {
64 compatible = "regulator-fixed";
65 reg = <2>;
66 regulator-name = "usb_otg_vbus";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
69 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
70 enable-active-high;
71 };
72 };
73
74 sound-cs42888 {
75 compatible = "fsl,imx6-sabreauto-cs42888",
76 "fsl,imx-audio-cs42888";
77 model = "imx-cs42888";
78 audio-cpu = <&esai>;
79 audio-asrc = <&asrc>;
80 audio-codec = <&codec>;
81 audio-routing =
82 "Line Out Jack", "AOUT1L",
83 "Line Out Jack", "AOUT1R",
84 "Line Out Jack", "AOUT2L",
85 "Line Out Jack", "AOUT2R",
86 "Line Out Jack", "AOUT3L",
87 "Line Out Jack", "AOUT3R",
88 "Line Out Jack", "AOUT4L",
89 "Line Out Jack", "AOUT4R",
90 "AIN1L", "Line In Jack",
91 "AIN1R", "Line In Jack",
92 "AIN2L", "Line In Jack",
93 "AIN2R", "Line In Jack";
94 };
95
96 sound-spdif {
97 compatible = "fsl,imx-audio-spdif",
98 "fsl,imx-sabreauto-spdif";
99 model = "imx-spdif";
100 spdif-controller = <&spdif>;
101 spdif-in;
102 };
103
104 backlight {
105 compatible = "pwm-backlight";
106 pwms = <&pwm3 0 5000000>;
107 brightness-levels = <0 4 8 16 32 64 128 255>;
108 default-brightness-level = <7>;
109 status = "okay";
110 };
111
112 i2cmux {
113 compatible = "i2c-mux-gpio";
114 #address-cells = <1>;
115 #size-cells = <0>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c3mux>;
118 mux-gpios = <&gpio5 4 0>;
119 i2c-parent = <&i2c3>;
120 idle-state = <0>;
121
122 i2c@1 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <1>;
126
127 adv7180: camera@21 {
128 compatible = "adi,adv7180";
129 reg = <0x21>;
130 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
131 interrupt-parent = <&gpio1>;
132 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
133
134 port {
135 adv7180_to_ipu1_csi0_mux: endpoint {
136 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
137 bus-width = <8>;
138 };
139 };
140 };
141
142 max7310_a: gpio@30 {
143 compatible = "maxim,max7310";
144 reg = <0x30>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 };
148
149 max7310_b: gpio@32 {
150 compatible = "maxim,max7310";
151 reg = <0x32>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_max7310>;
156 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
157 };
158
159 max7310_c: gpio@34 {
160 compatible = "maxim,max7310";
161 reg = <0x34>;
162 gpio-controller;
163 #gpio-cells = <2>;
164 };
165 };
166 };
167};
168
169&ipu1_csi0_from_ipu1_csi0_mux {
170 bus-width = <8>;
171};
172
173&ipu1_csi0_mux_from_parallel_sensor {
174 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
175 bus-width = <8>;
176};
177
178&ipu1_csi0 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_ipu1_csi0>;
181};
182
183&clks {
184 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
185 <&clks IMX6QDL_PLL4_BYPASS>,
186 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
187 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
188 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
189 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
190 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
191 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
192 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
193 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
194};
195
196&ecspi1 {
197 cs-gpios = <&gpio3 19 0>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
200 status = "disabled"; /* pin conflict with WEIM NOR */
201
202 flash: m25p80@0 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "st,m25p32", "jedec,spi-nor";
206 spi-max-frequency = <20000000>;
207 reg = <0>;
208 };
209};
210
211&esai {
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_esai>;
214 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
215 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
216 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
217 assigned-clock-rates = <0>, <24576000>;
218 status = "okay";
219};
220
221&fec {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_enet>;
224 phy-mode = "rgmii";
225 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
226 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
227 fsl,err006687-workaround-present;
228 status = "okay";
229};
230
231&gpmi {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_gpmi_nand>;
234 status = "okay";
235};
236
237&hdmi {
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_hdmi_cec>;
240 ddc-i2c-bus = <&i2c2>;
241 status = "okay";
242};
243
244&i2c2 {
245 clock-frequency = <100000>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_i2c2>;
248 status = "okay";
249
250 pmic: pfuze100@8 {
251 compatible = "fsl,pfuze100";
252 reg = <0x08>;
253
254 regulators {
255 sw1a_reg: sw1ab {
256 regulator-min-microvolt = <300000>;
257 regulator-max-microvolt = <1875000>;
258 regulator-boot-on;
259 regulator-always-on;
260 regulator-ramp-delay = <6250>;
261 };
262
263 sw1c_reg: sw1c {
264 regulator-min-microvolt = <300000>;
265 regulator-max-microvolt = <1875000>;
266 regulator-boot-on;
267 regulator-always-on;
268 regulator-ramp-delay = <6250>;
269 };
270
271 sw2_reg: sw2 {
272 regulator-min-microvolt = <800000>;
273 regulator-max-microvolt = <3300000>;
274 regulator-boot-on;
275 regulator-always-on;
276 };
277
278 sw3a_reg: sw3a {
279 regulator-min-microvolt = <400000>;
280 regulator-max-microvolt = <1975000>;
281 regulator-boot-on;
282 regulator-always-on;
283 };
284
285 sw3b_reg: sw3b {
286 regulator-min-microvolt = <400000>;
287 regulator-max-microvolt = <1975000>;
288 regulator-boot-on;
289 regulator-always-on;
290 };
291
292 sw4_reg: sw4 {
293 regulator-min-microvolt = <800000>;
294 regulator-max-microvolt = <3300000>;
295 };
296
297 swbst_reg: swbst {
298 regulator-min-microvolt = <5000000>;
299 regulator-max-microvolt = <5150000>;
300 };
301
302 snvs_reg: vsnvs {
303 regulator-min-microvolt = <1000000>;
304 regulator-max-microvolt = <3000000>;
305 regulator-boot-on;
306 regulator-always-on;
307 };
308
309 vref_reg: vrefddr {
310 regulator-boot-on;
311 regulator-always-on;
312 };
313
314 vgen1_reg: vgen1 {
315 regulator-min-microvolt = <800000>;
316 regulator-max-microvolt = <1550000>;
317 };
318
319 vgen2_reg: vgen2 {
320 regulator-min-microvolt = <800000>;
321 regulator-max-microvolt = <1550000>;
322 };
323
324 vgen3_reg: vgen3 {
325 regulator-min-microvolt = <1800000>;
326 regulator-max-microvolt = <3300000>;
327 };
328
329 vgen4_reg: vgen4 {
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <3300000>;
332 regulator-always-on;
333 };
334
335 vgen5_reg: vgen5 {
336 regulator-min-microvolt = <1800000>;
337 regulator-max-microvolt = <3300000>;
338 regulator-always-on;
339 };
340
341 vgen6_reg: vgen6 {
342 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <3300000>;
344 regulator-always-on;
345 };
346 };
347 };
348
349 codec: cs42888@48 {
350 compatible = "cirrus,cs42888";
351 reg = <0x48>;
352 clocks = <&codec_osc>;
353 clock-names = "mclk";
354 VA-supply = <®_audio>;
355 VD-supply = <®_audio>;
356 VLS-supply = <®_audio>;
357 VLC-supply = <®_audio>;
358 };
359
360};
361
362&i2c3 {
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_i2c3>;
365 status = "okay";
366};
367
368&iomuxc {
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_hog>;
371
372 imx6qdl-sabreauto {
373 pinctrl_hog: hoggrp {
374 fsl,pins = <
375 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
376 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
377 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
378 >;
379 };
380
381 pinctrl_ecspi1: ecspi1grp {
382 fsl,pins = <
383 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
384 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
385 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
386 >;
387 };
388
389 pinctrl_ecspi1_cs: ecspi1cs {
390 fsl,pins = <
391 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
392 >;
393 };
394
395 pinctrl_enet: enetgrp {
396 fsl,pins = <
397 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
398 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
399 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
400 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
401 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
402 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
403 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
404 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
405 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
406 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
407 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
408 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
409 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
410 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
411 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
412 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
413 >;
414 };
415
416 pinctrl_esai: esaigrp {
417 fsl,pins = <
418 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
419 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
420 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
421 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
422 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
423 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
424 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
425 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
426 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
427 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
428 >;
429 };
430
431 pinctrl_gpio_leds: gpioledsgrp {
432 fsl,pins = <
433 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
434 >;
435 };
436
437 pinctrl_gpmi_nand: gpminandgrp {
438 fsl,pins = <
439 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
440 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
441 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
442 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
443 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
444 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
445 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
446 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
447 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
448 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
449 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
450 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
451 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
452 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
453 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
454 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
455 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
456 >;
457 };
458
459 pinctrl_hdmi_cec: hdmicecgrp {
460 fsl,pins = <
461 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
462 >;
463 };
464
465 pinctrl_i2c2: i2c2grp {
466 fsl,pins = <
467 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
468 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
469 >;
470 };
471
472 pinctrl_i2c3: i2c3grp {
473 fsl,pins = <
474 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
475 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
476 >;
477 };
478
479 pinctrl_i2c3mux: i2c3muxgrp {
480 fsl,pins = <
481 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
482 >;
483 };
484
485 pinctrl_ipu1_csi0: ipu1csi0grp {
486 fsl,pins = <
487 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
488 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
489 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
490 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
491 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
492 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
493 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
494 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
495 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
496 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
497 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
498 >;
499 };
500
501 pinctrl_max7310: max7310grp {
502 fsl,pins = <
503 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
504 >;
505 };
506
507 pinctrl_pwm3: pwm1grp {
508 fsl,pins = <
509 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
510 >;
511 };
512
513 pinctrl_gpt_input_capture0: gptinputcapture0grp {
514 fsl,pins = <
515 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
516 >;
517 };
518
519 pinctrl_gpt_input_capture1: gptinputcapture1grp {
520 fsl,pins = <
521 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
522 >;
523 };
524
525 pinctrl_spdif: spdifgrp {
526 fsl,pins = <
527 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
528 >;
529 };
530
531 pinctrl_uart4: uart4grp {
532 fsl,pins = <
533 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
534 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
535 >;
536 };
537
538 pinctrl_usbotg: usbotggrp {
539 fsl,pins = <
540 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
541 >;
542 };
543
544 pinctrl_usdhc3: usdhc3grp {
545 fsl,pins = <
546 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
547 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
548 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
549 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
550 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
551 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
552 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
553 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
554 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
555 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
556 >;
557 };
558
559 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
560 fsl,pins = <
561 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
562 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
563 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
564 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
565 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
566 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
567 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
568 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
569 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
570 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
571 >;
572 };
573
574 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
575 fsl,pins = <
576 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
577 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
578 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
579 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
580 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
581 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
582 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
583 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
584 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
585 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
586 >;
587 };
588
589 pinctrl_weim_cs0: weimcs0grp {
590 fsl,pins = <
591 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
592 >;
593 };
594
595 pinctrl_weim_nor: weimnorgrp {
596 fsl,pins = <
597 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
598 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
599 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
600 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
601 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
602 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
603 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
604 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
605 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
606 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
607 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
608 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
609 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
610 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
611 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
612 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
613 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
614 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
615 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
616 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
617 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
618 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
619 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
620 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
621 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
622 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
623 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
624 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
625 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
626 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
627 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
628 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
629 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
630 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
631 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
632 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
633 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
634 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
635 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
636 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
637 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
638 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
639 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
640 >;
641 };
642 };
643};
644
645&ldb {
646 status = "okay";
647
648 lvds-channel@0 {
649 fsl,data-mapping = "spwg";
650 fsl,data-width = <18>;
651 status = "okay";
652
653 display-timings {
654 native-mode = <&timing0>;
655 timing0: hsd100pxn1 {
656 clock-frequency = <65000000>;
657 hactive = <1024>;
658 vactive = <768>;
659 hback-porch = <220>;
660 hfront-porch = <40>;
661 vback-porch = <21>;
662 vfront-porch = <7>;
663 hsync-len = <60>;
664 vsync-len = <10>;
665 };
666 };
667 };
668};
669
670&pwm3 {
671 pinctrl-names = "default";
672 pinctrl-0 = <&pinctrl_pwm3>;
673 status = "okay";
674};
675
676&spdif {
677 pinctrl-names = "default";
678 pinctrl-0 = <&pinctrl_spdif>;
679 status = "okay";
680};
681
682&uart4 {
683 pinctrl-names = "default";
684 pinctrl-0 = <&pinctrl_uart4>;
685 status = "okay";
686};
687
688&usbh1 {
689 vbus-supply = <®_usb_h1_vbus>;
690 status = "okay";
691};
692
693&usbotg {
694 vbus-supply = <®_usb_otg_vbus>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&pinctrl_usbotg>;
697 status = "okay";
698};
699
700&usdhc3 {
701 pinctrl-names = "default", "state_100mhz", "state_200mhz";
702 pinctrl-0 = <&pinctrl_usdhc3>;
703 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
704 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
705 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
706 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
707 status = "okay";
708};
709
710&weim {
711 pinctrl-names = "default";
712 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
713 ranges = <0 0 0x08000000 0x08000000>;
714 status = "disabled"; /* pin conflict with SPI NOR */
715
716 nor@0,0 {
717 compatible = "cfi-flash";
718 reg = <0 0 0x02000000>;
719 #address-cells = <1>;
720 #size-cells = <1>;
721 bank-width = <2>;
722 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
723 0x0000c000 0x1404a38e 0x00000000>;
724 };
725};