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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2014 FEDEVEL, Inc.
4 *
5 * Author: Robert Nelson <robertcnelson@gmail.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12 chosen {
13 stdout-path = &uart1;
14 };
15
16 regulators {
17 compatible = "simple-bus";
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 reg_3p3v: regulator@0 {
22 compatible = "regulator-fixed";
23 reg = <0>;
24 regulator-name = "3P3V";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 regulator-always-on;
28 };
29
30 reg_usbh1_vbus: regulator@1 {
31 compatible = "regulator-fixed";
32 reg = <1>;
33 pinctrl-names = "default";
34 regulator-name = "usbh1_vbus";
35 regulator-min-microvolt = <5000000>;
36 regulator-max-microvolt = <5000000>;
37 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
38 enable-active-high;
39 };
40
41 reg_usb_otg_vbus: regulator@2 {
42 compatible = "regulator-fixed";
43 reg = <2>;
44 pinctrl-names = "default";
45 regulator-name = "usb_otg_vbus";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
49 enable-active-high;
50 };
51 };
52
53 leds {
54 compatible = "gpio-leds";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_led>;
57
58 led0: usr {
59 label = "usr";
60 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
61 default-state = "off";
62 linux,default-trigger = "heartbeat";
63 };
64 };
65
66 sound {
67 compatible = "fsl,imx6-rex-sgtl5000",
68 "fsl,imx-audio-sgtl5000";
69 model = "imx6-rex-sgtl5000";
70 ssi-controller = <&ssi1>;
71 audio-codec = <&codec>;
72 audio-routing =
73 "MIC_IN", "Mic Jack",
74 "Mic Jack", "Mic Bias",
75 "Headphone Jack", "HP_OUT";
76 mux-int-port = <1>;
77 mux-ext-port = <3>;
78 };
79};
80
81&audmux {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_audmux>;
84 status = "okay";
85};
86
87&ecspi2 {
88 cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_ecspi2>;
91 status = "okay";
92};
93
94&ecspi3 {
95 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_ecspi3>;
98 status = "okay";
99};
100
101&fec {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_enet>;
104 phy-mode = "rgmii";
105 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
106 status = "okay";
107};
108
109&hdmi {
110 ddc-i2c-bus = <&i2c2>;
111 status = "okay";
112};
113
114&i2c1 {
115 clock-frequency = <100000>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c1>;
118 status = "okay";
119
120 codec: sgtl5000@a {
121 compatible = "fsl,sgtl5000";
122 reg = <0x0a>;
123 clocks = <&clks IMX6QDL_CLK_CKO>;
124 VDDA-supply = <®_3p3v>;
125 VDDIO-supply = <®_3p3v>;
126 };
127};
128
129&i2c2 {
130 clock-frequency = <100000>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_i2c2>;
133 status = "okay";
134
135 pca9535: gpio-expander@27 {
136 compatible = "nxp,pca9535";
137 reg = <0x27>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_pca9535>;
142 interrupt-parent = <&gpio6>;
143 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
146 };
147
148 eeprom@57 {
149 compatible = "atmel,24c02";
150 reg = <0x57>;
151 };
152};
153
154&i2c3 {
155 clock-frequency = <100000>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_i2c3>;
158 status = "okay";
159};
160
161&iomuxc {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_hog>;
164
165 imx6qdl-rex {
166 pinctrl_hog: hoggrp {
167 fsl,pins = <
168 /* SGTL5000 sys_mclk */
169 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
170 >;
171 };
172
173 pinctrl_audmux: audmuxgrp {
174 fsl,pins = <
175 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
176 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
177 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
178 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
179 >;
180 };
181
182 pinctrl_ecspi2: ecspi2grp {
183 fsl,pins = <
184 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
185 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
186 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
187 /* CS */
188 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1
189 >;
190 };
191
192 pinctrl_ecspi3: ecspi3grp {
193 fsl,pins = <
194 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
195 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
196 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
197 /* CS */
198 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1
199 >;
200 };
201
202 pinctrl_enet: enetgrp {
203 fsl,pins = <
204 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
205 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
206 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
207 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
208 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
209 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
210 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
211 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
212 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
213 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
214 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
215 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
216 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
217 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
218 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
219 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
220 /* Phy reset */
221 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
222 >;
223 };
224
225 pinctrl_i2c1: i2c1grp {
226 fsl,pins = <
227 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
228 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
229 >;
230 };
231
232 pinctrl_i2c2: i2c2grp {
233 fsl,pins = <
234 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
235 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
236 >;
237 };
238
239 pinctrl_i2c3: i2c3grp {
240 fsl,pins = <
241 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
242 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
243 >;
244 };
245
246 pinctrl_led: ledgrp {
247 fsl,pins = <
248 /* user led */
249 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
250 >;
251 };
252
253 pinctrl_pca9535: pca9535grp {
254 fsl,pins = <
255 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059
256 >;
257 };
258
259 pinctrl_uart1: uart1grp {
260 fsl,pins = <
261 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
262 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
263 >;
264 };
265
266 pinctrl_uart2: uart2grp {
267 fsl,pins = <
268 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
269 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
270 >;
271 };
272
273 pinctrl_usbh1: usbh1grp {
274 fsl,pins = <
275 /* power enable, high active */
276 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0
277 >;
278 };
279
280 pinctrl_usbotg: usbotggrp {
281 fsl,pins = <
282 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
283 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
284 /* power enable, high active */
285 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0
286 >;
287 };
288
289 pinctrl_usdhc2: usdhc2grp {
290 fsl,pins = <
291 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
292 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
293 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
294 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
295 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
296 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
297 /* CD */
298 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
299 /* WP */
300 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0
301 >;
302 };
303
304 pinctrl_usdhc3: usdhc3grp {
305 fsl,pins = <
306 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
307 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
308 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
309 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
310 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
311 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
312 /* CD */
313 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
314 /* WP */
315 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0
316 >;
317 };
318 };
319};
320
321&ssi1 {
322 status = "okay";
323};
324
325&uart1 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_uart1>;
328 status = "okay";
329};
330
331&uart2 {
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_uart2>;
334 status = "okay";
335};
336
337&usbh1 {
338 vbus-supply = <®_usbh1_vbus>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_usbh1>;
341 status = "okay";
342};
343
344&usbotg {
345 vbus-supply = <®_usb_otg_vbus>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_usbotg>;
348 status = "okay";
349};
350
351&usdhc2 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_usdhc2>;
354 bus-width = <4>;
355 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
356 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
357 status = "okay";
358};
359
360&usdhc3 {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_usdhc3>;
363 bus-width = <4>;
364 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
365 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
366 status = "okay";
367};
1/*
2 * Copyright 2014 FEDEVEL, Inc.
3 *
4 * Author: Robert Nelson <robertcnelson@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14
15/ {
16 chosen {
17 stdout-path = &uart1;
18 };
19
20 regulators {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 reg_3p3v: regulator@0 {
26 compatible = "regulator-fixed";
27 reg = <0>;
28 regulator-name = "3P3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-always-on;
32 };
33
34 reg_usbh1_vbus: regulator@1 {
35 compatible = "regulator-fixed";
36 reg = <1>;
37 pinctrl-names = "default";
38 regulator-name = "usbh1_vbus";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
42 enable-active-high;
43 };
44
45 reg_usb_otg_vbus: regulator@2 {
46 compatible = "regulator-fixed";
47 reg = <2>;
48 pinctrl-names = "default";
49 regulator-name = "usb_otg_vbus";
50 regulator-min-microvolt = <5000000>;
51 regulator-max-microvolt = <5000000>;
52 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
53 enable-active-high;
54 };
55 };
56
57 leds {
58 compatible = "gpio-leds";
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_led>;
61
62 led0: usr {
63 label = "usr";
64 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
65 default-state = "off";
66 linux,default-trigger = "heartbeat";
67 };
68 };
69
70 sound {
71 compatible = "fsl,imx6-rex-sgtl5000",
72 "fsl,imx-audio-sgtl5000";
73 model = "imx6-rex-sgtl5000";
74 ssi-controller = <&ssi1>;
75 audio-codec = <&codec>;
76 audio-routing =
77 "MIC_IN", "Mic Jack",
78 "Mic Jack", "Mic Bias",
79 "Headphone Jack", "HP_OUT";
80 mux-int-port = <1>;
81 mux-ext-port = <3>;
82 };
83};
84
85&audmux {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_audmux>;
88 status = "okay";
89};
90
91&ecspi2 {
92 cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_ecspi2>;
95 status = "okay";
96};
97
98&ecspi3 {
99 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_ecspi3>;
102 status = "okay";
103};
104
105&fec {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_enet>;
108 phy-mode = "rgmii";
109 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
110 status = "okay";
111};
112
113&hdmi {
114 ddc-i2c-bus = <&i2c2>;
115 status = "okay";
116};
117
118&i2c1 {
119 clock-frequency = <100000>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_i2c1>;
122 status = "okay";
123
124 codec: sgtl5000@a {
125 compatible = "fsl,sgtl5000";
126 reg = <0x0a>;
127 clocks = <&clks IMX6QDL_CLK_CKO>;
128 VDDA-supply = <®_3p3v>;
129 VDDIO-supply = <®_3p3v>;
130 };
131};
132
133&i2c2 {
134 clock-frequency = <100000>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_i2c2>;
137 status = "okay";
138
139 eeprom@57 {
140 compatible = "atmel,24c02";
141 reg = <0x57>;
142 };
143};
144
145&i2c3 {
146 clock-frequency = <100000>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_i2c3>;
149 status = "okay";
150};
151
152&iomuxc {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_hog>;
155
156 imx6qdl-rex {
157 pinctrl_hog: hoggrp {
158 fsl,pins = <
159 /* SGTL5000 sys_mclk */
160 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
161 >;
162 };
163
164 pinctrl_audmux: audmuxgrp {
165 fsl,pins = <
166 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
167 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
168 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
169 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
170 >;
171 };
172
173 pinctrl_ecspi2: ecspi2grp {
174 fsl,pins = <
175 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
176 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
177 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
178 /* CS */
179 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1
180 >;
181 };
182
183 pinctrl_ecspi3: ecspi3grp {
184 fsl,pins = <
185 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
186 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
187 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
188 /* CS */
189 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1
190 >;
191 };
192
193 pinctrl_enet: enetgrp {
194 fsl,pins = <
195 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
196 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
197 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
198 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
199 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
200 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
201 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
202 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
203 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
204 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
205 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
206 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
207 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
208 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
209 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
210 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
211 /* Phy reset */
212 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
213 >;
214 };
215
216 pinctrl_i2c1: i2c1grp {
217 fsl,pins = <
218 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
219 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
220 >;
221 };
222
223 pinctrl_i2c2: i2c2grp {
224 fsl,pins = <
225 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
226 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
227 >;
228 };
229
230 pinctrl_i2c3: i2c3grp {
231 fsl,pins = <
232 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
233 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
234 >;
235 };
236
237 pinctrl_led: ledgrp {
238 fsl,pins = <
239 /* user led */
240 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
241 >;
242 };
243
244 pinctrl_uart1: uart1grp {
245 fsl,pins = <
246 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
247 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
248 >;
249 };
250
251 pinctrl_uart2: uart2grp {
252 fsl,pins = <
253 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
254 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
255 >;
256 };
257
258 pinctrl_usbh1: usbh1grp {
259 fsl,pins = <
260 /* power enable, high active */
261 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0
262 >;
263 };
264
265 pinctrl_usbotg: usbotggrp {
266 fsl,pins = <
267 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
268 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
269 /* power enable, high active */
270 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0
271 >;
272 };
273
274 pinctrl_usdhc2: usdhc2grp {
275 fsl,pins = <
276 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
277 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
278 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
279 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
280 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
281 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
282 /* CD */
283 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
284 /* WP */
285 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0
286 >;
287 };
288
289 pinctrl_usdhc3: usdhc3grp {
290 fsl,pins = <
291 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
292 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
293 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
294 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
295 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
296 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
297 /* CD */
298 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
299 /* WP */
300 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0
301 >;
302 };
303 };
304};
305
306&ssi1 {
307 status = "okay";
308};
309
310&uart1 {
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_uart1>;
313 status = "okay";
314};
315
316&uart2 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_uart2>;
319 status = "okay";
320};
321
322&usbh1 {
323 vbus-supply = <®_usbh1_vbus>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_usbh1>;
326 status = "okay";
327};
328
329&usbotg {
330 vbus-supply = <®_usb_otg_vbus>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_usbotg>;
333 status = "okay";
334};
335
336&usdhc2 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_usdhc2>;
339 bus-width = <4>;
340 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
341 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
342 status = "okay";
343};
344
345&usdhc3 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_usdhc3>;
348 bus-width = <4>;
349 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
350 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
351 status = "okay";
352};