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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2014-2020 Toradex
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11 model = "Toradex Colibri iMX6DL/S Module";
12 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
13
14 backlight: backlight {
15 compatible = "pwm-backlight";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_bl_on>;
18 pwms = <&pwm3 0 5000000>;
19 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
20 status = "disabled";
21 };
22
23 reg_module_3v3: regulator-module-3v3 {
24 compatible = "regulator-fixed";
25 regulator-name = "+V3.3";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
28 regulator-always-on;
29 };
30
31 reg_module_3v3_audio: regulator-module-3v3-audio {
32 compatible = "regulator-fixed";
33 regulator-name = "+V3.3_AUDIO";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 regulator-always-on;
37 };
38
39 reg_usb_host_vbus: regulator-usb-host-vbus {
40 compatible = "regulator-fixed";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
43 regulator-name = "usb_host_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
47 status = "disabled";
48 };
49
50 sound {
51 compatible = "fsl,imx-audio-sgtl5000";
52 model = "imx6dl-colibri-sgtl5000";
53 ssi-controller = <&ssi1>;
54 audio-codec = <&codec>;
55 audio-routing =
56 "Headphone Jack", "HP_OUT",
57 "LINE_IN", "Line In Jack",
58 "MIC_IN", "Mic Jack",
59 "Mic Jack", "Mic Bias";
60 mux-int-port = <1>;
61 mux-ext-port = <5>;
62 };
63
64 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
65 sound_spdif: sound-spdif {
66 compatible = "fsl,imx-audio-spdif";
67 model = "imx-spdif";
68 spdif-controller = <&spdif>;
69 spdif-in;
70 spdif-out;
71 status = "disabled";
72 };
73};
74
75&audmux {
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
78 status = "okay";
79};
80
81/* Optional on SODIMM 55/63 */
82&can1 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_flexcan1>;
85 status = "disabled";
86};
87
88/* Optional on SODIMM 178/188 */
89&can2 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_flexcan2>;
92 status = "disabled";
93};
94
95/* Colibri SSP */
96&ecspi4 {
97 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_ecspi4>;
100 status = "disabled";
101};
102
103&fec {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_enet>;
106 phy-mode = "rmii";
107 phy-handle = <ðphy>;
108 status = "okay";
109
110 mdio {
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 ethphy: ethernet-phy@0 {
115 reg = <0>;
116 micrel,led-mode = <0>;
117 };
118 };
119};
120
121&hdmi {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_hdmi_ddc>;
124 status = "disabled";
125};
126
127/*
128 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
129 * touch screen controller
130 */
131&i2c2 {
132 clock-frequency = <100000>;
133 pinctrl-names = "default", "gpio";
134 pinctrl-0 = <&pinctrl_i2c2>;
135 pinctrl-0 = <&pinctrl_i2c2_gpio>;
136 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
137 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
138 status = "okay";
139
140 pmic: pfuze100@8 {
141 compatible = "fsl,pfuze100";
142 reg = <0x08>;
143
144 regulators {
145 sw1a_reg: sw1ab {
146 regulator-min-microvolt = <300000>;
147 regulator-max-microvolt = <1875000>;
148 regulator-boot-on;
149 regulator-always-on;
150 regulator-ramp-delay = <6250>;
151 };
152
153 sw1c_reg: sw1c {
154 regulator-min-microvolt = <300000>;
155 regulator-max-microvolt = <1875000>;
156 regulator-boot-on;
157 regulator-always-on;
158 regulator-ramp-delay = <6250>;
159 };
160
161 sw3a_reg: sw3a {
162 regulator-min-microvolt = <400000>;
163 regulator-max-microvolt = <1975000>;
164 regulator-boot-on;
165 regulator-always-on;
166 };
167
168 swbst_reg: swbst {
169 regulator-min-microvolt = <5000000>;
170 regulator-max-microvolt = <5150000>;
171 regulator-boot-on;
172 regulator-always-on;
173 };
174
175 snvs_reg: vsnvs {
176 regulator-min-microvolt = <1000000>;
177 regulator-max-microvolt = <3000000>;
178 regulator-boot-on;
179 regulator-always-on;
180 };
181
182 vref_reg: vrefddr {
183 regulator-boot-on;
184 regulator-always-on;
185 };
186
187 /* vgen1: unused */
188
189 vgen2_reg: vgen2 {
190 regulator-min-microvolt = <800000>;
191 regulator-max-microvolt = <1550000>;
192 regulator-boot-on;
193 regulator-always-on;
194 };
195
196 /*
197 * +V3.3_1.8_SD1 coming off VGEN3 and supplying
198 * the i.MX 6 NVCC_SD1.
199 */
200 vgen3_reg: vgen3 {
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <3300000>;
203 regulator-boot-on;
204 regulator-always-on;
205 };
206
207 vgen4_reg: vgen4 {
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <1800000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 vgen5_reg: vgen5 {
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <3300000>;
217 regulator-boot-on;
218 regulator-always-on;
219 };
220
221 vgen6_reg: vgen6 {
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <3300000>;
224 regulator-boot-on;
225 regulator-always-on;
226 };
227 };
228 };
229
230 codec: sgtl5000@a {
231 compatible = "fsl,sgtl5000";
232 reg = <0x0a>;
233 clocks = <&clks IMX6QDL_CLK_CKO>;
234 VDDA-supply = <®_module_3v3_audio>;
235 VDDIO-supply = <®_module_3v3>;
236 VDDD-supply = <&vgen4_reg>;
237 lrclk-strength = <3>;
238 };
239
240 /* STMPE811 touch screen controller */
241 stmpe811@41 {
242 compatible = "st,stmpe811";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_touch_int>;
245 reg = <0x41>;
246 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
247 interrupt-parent = <&gpio6>;
248 interrupt-controller;
249 id = <0>;
250 blocks = <0x5>;
251 irq-trigger = <0x1>;
252 /* 3.25 MHz ADC clock speed */
253 st,adc-freq = <1>;
254 /* 12-bit ADC */
255 st,mod-12b = <1>;
256 /* internal ADC reference */
257 st,ref-sel = <0>;
258 /* ADC converstion time: 80 clocks */
259 st,sample-time = <4>;
260
261 stmpe_touchscreen {
262 compatible = "st,stmpe-ts";
263 /* 8 sample average control */
264 st,ave-ctrl = <3>;
265 /* 7 length fractional part in z */
266 st,fraction-z = <7>;
267 /*
268 * 50 mA typical 80 mA max touchscreen drivers
269 * current limit value
270 */
271 st,i-drive = <1>;
272 /* 1 ms panel driver settling time */
273 st,settling = <3>;
274 /* 5 ms touch detect interrupt delay */
275 st,touch-det-delay = <5>;
276 };
277
278 stmpe_adc {
279 compatible = "st,stmpe-adc";
280 /* forbid to use ADC channels 3-0 (touch) */
281 st,norequest-mask = <0x0F>;
282 };
283 };
284};
285
286/*
287 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
288 */
289&i2c3 {
290 clock-frequency = <100000>;
291 pinctrl-names = "default", "gpio";
292 pinctrl-0 = <&pinctrl_i2c3>;
293 pinctrl-1 = <&pinctrl_i2c3_gpio>;
294 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
295 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
296 status = "disabled";
297};
298
299/* Colibri PWM<B> */
300&pwm1 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_pwm1>;
303 status = "disabled";
304};
305
306/* Colibri PWM<D> */
307&pwm2 {
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_pwm2>;
310 status = "disabled";
311};
312
313/* Colibri PWM<A> */
314&pwm3 {
315 #pwm-cells = <2>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_pwm3>;
318 status = "disabled";
319};
320
321/* Colibri PWM<C> */
322&pwm4 {
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_pwm4>;
325 status = "disabled";
326};
327
328/* Optional S/PDIF out on SODIMM 137 */
329&spdif {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_spdif>;
332 status = "disabled";
333};
334
335&ssi1 {
336 status = "okay";
337};
338
339/* Colibri UART_A */
340&uart1 {
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
343 fsl,dte-mode;
344 uart-has-rtscts;
345 status = "disabled";
346};
347
348/* Colibri UART_B */
349&uart2 {
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_uart2_dte>;
352 fsl,dte-mode;
353 uart-has-rtscts;
354 status = "disabled";
355};
356
357/* Colibri UART_C */
358&uart3 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_uart3_dte>;
361 fsl,dte-mode;
362 status = "disabled";
363};
364
365&usbotg {
366 disable-over-current;
367 dr_mode = "peripheral";
368 status = "disabled";
369};
370
371/* Colibri MMC */
372&usdhc1 {
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
375 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
376 disable-wp;
377 vqmmc-supply = <®_module_3v3>;
378 bus-width = <4>;
379 no-1-8-v;
380 status = "disabled";
381};
382
383/* eMMC */
384&usdhc3 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_usdhc3>;
387 vqmmc-supply = <®_module_3v3>;
388 bus-width = <8>;
389 no-1-8-v;
390 non-removable;
391 status = "okay";
392};
393
394&weim {
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
397 &pinctrl_weim_cs1 &pinctrl_weim_cs2
398 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
399 #address-cells = <2>;
400 #size-cells = <1>;
401 status = "disabled";
402};
403
404&iomuxc {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_usbh_oc_1>;
407
408 pinctrl_audmux: audmuxgrp {
409 fsl,pins = <
410 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
411 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
412 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
413 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
414 /* SGTL5000 sys_mclk */
415 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
416 >;
417 };
418
419 pinctrl_cam_mclk: cammclkgrp {
420 fsl,pins = <
421 /* Parallel Camera CAM sys_mclk */
422 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
423 >;
424 };
425
426 pinctrl_ecspi4: ecspi4grp {
427 fsl,pins = <
428 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
429 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
430 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
431 /* SPI CS */
432 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
433 >;
434 };
435
436 pinctrl_enet: enetgrp {
437 fsl,pins = <
438 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
439 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
440 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
441 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
442 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
443 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
444 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
445 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
446 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
447 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
448 >;
449 };
450
451 pinctrl_flexcan1: flexcan1grp {
452 fsl,pins = <
453 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
454 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
455 >;
456 };
457
458 pinctrl_flexcan2: flexcan2grp {
459 fsl,pins = <
460 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
461 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
462 >;
463 };
464
465 pinctrl_gpio_bl_on: gpioblon {
466 fsl,pins = <
467 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
468 >;
469 };
470
471 pinctrl_gpio_keys: gpiokeys {
472 fsl,pins = <
473 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
474 >;
475 };
476
477 pinctrl_hdmi_ddc: hdmiddcgrp {
478 fsl,pins = <
479 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
480 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
481 >;
482 };
483
484 pinctrl_i2c2: i2c2grp {
485 fsl,pins = <
486 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
487 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
488 >;
489 };
490
491 pinctrl_i2c2_gpio: i2c2grp {
492 fsl,pins = <
493 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
494 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
495 >;
496 };
497
498 pinctrl_i2c3: i2c3grp {
499 fsl,pins = <
500 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
501 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
502 >;
503 };
504
505 pinctrl_i2c3_gpio: i2c3gpiogrp {
506 fsl,pins = <
507 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
508 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
509 >;
510 };
511
512 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
513 fsl,pins = <
514 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
515 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
516 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
517 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
518 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
519 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
520 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
521 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
522 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
523 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
524 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
525 /* Disable PWM pins on camera interface */
526 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
527 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
528 >;
529 };
530
531 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
532 fsl,pins = <
533 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
534 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
535 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
536 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
537 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
538 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
539 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
540 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
541 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
542 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
543 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
544 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
545 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
546 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
547 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
548 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
549 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
550 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
551 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
552 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
553 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
554 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
555 >;
556 };
557
558 pinctrl_mic_gnd: gpiomicgnd {
559 fsl,pins = <
560 /* Controls Mic GND, PU or '1' pull Mic GND to GND */
561 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
562 >;
563 };
564
565 pinctrl_mmc_cd: gpiommccd {
566 fsl,pins = <
567 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
568 >;
569 };
570
571 pinctrl_pwm1: pwm1grp {
572 fsl,pins = <
573 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
574 >;
575 };
576
577 pinctrl_pwm2: pwm2grp {
578 fsl,pins = <
579 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
580 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
581 >;
582 };
583
584 pinctrl_pwm3: pwm3grp {
585 fsl,pins = <
586 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
587 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
588 >;
589 };
590
591 pinctrl_pwm4: pwm4grp {
592 fsl,pins = <
593 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
594 >;
595 };
596
597 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
598 fsl,pins = <
599 /* USBH_EN */
600 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
601 >;
602 };
603
604 pinctrl_usbh_oc_1: usbhoc1grp {
605 fsl,pins = <
606 /* USBH_OC */
607 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
608 >;
609 };
610
611 pinctrl_spdif: spdifgrp {
612 fsl,pins = <
613 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
614 >;
615 };
616
617 pinctrl_touch_int: gpiotouchintgrp {
618 fsl,pins = <
619 /* STMPE811 interrupt */
620 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
621 >;
622 };
623
624 pinctrl_uart1_dce: uart1dcegrp {
625 fsl,pins = <
626 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
627 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
628 >;
629 };
630
631 /* DTE mode */
632 pinctrl_uart1_dte: uart1dtegrp {
633 fsl,pins = <
634 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
635 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
636 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
637 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
638 >;
639 };
640
641 /* Additional DTR, DSR, DCD */
642 pinctrl_uart1_ctrl: uart1ctrlgrp {
643 fsl,pins = <
644 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
645 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
646 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
647 >;
648 };
649
650 pinctrl_uart2_dte: uart2dtegrp {
651 fsl,pins = <
652 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
653 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
654 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
655 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
656 >;
657 };
658
659 pinctrl_uart3_dte: uart3dtegrp {
660 fsl,pins = <
661 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
662 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
663 >;
664 };
665
666 pinctrl_usbc_det: usbcdetgrp {
667 fsl,pins = <
668 /* USBC_DET */
669 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
670 /* USBC_DET_EN */
671 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
672 /* USBC_DET_OVERWRITE */
673 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
674 >;
675 };
676
677 pinctrl_usbc_id_1: usbc_id-1 {
678 fsl,pins = <
679 /* USBC_ID */
680 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
681 >;
682 };
683
684 pinctrl_usdhc1: usdhc1grp {
685 fsl,pins = <
686 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
687 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
688 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
689 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
690 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
691 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
692 >;
693 };
694
695 pinctrl_usdhc3: usdhc3grp {
696 fsl,pins = <
697 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
698 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
699 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
700 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
701 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
702 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
703 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
704 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
705 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
706 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
707 /* eMMC reset */
708 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
709 >;
710 };
711
712 pinctrl_weim_cs0: weimcs0grp {
713 fsl,pins = <
714 /* nEXT_CS0 */
715 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
716 >;
717 };
718
719 pinctrl_weim_cs1: weimcs1grp {
720 fsl,pins = <
721 /* nEXT_CS1 */
722 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
723 >;
724 };
725
726 pinctrl_weim_cs2: weimcs2grp {
727 fsl,pins = <
728 /* nEXT_CS2 */
729 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
730 >;
731 };
732
733 pinctrl_weim_sram: weimsramgrp {
734 fsl,pins = <
735 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
736 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
737 /* Data */
738 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
739 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
740 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
741 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
742 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
743 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
744 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
745 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
746 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
747 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
748 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
749 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
750 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
751 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
752 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
753 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
754 /* Address */
755 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
756 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
757 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
758 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
759 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
760 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
761 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
762 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
763 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
764 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
765 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
766 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
767 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
768 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
769 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
770 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
771 >;
772 };
773
774 pinctrl_weim_rdnwr: weimrdnwr {
775 fsl,pins = <
776 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
777 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
778 >;
779 };
780
781 pinctrl_weim_npwe: weimnpwe {
782 fsl,pins = <
783 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
784 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
785 >;
786 };
787
788 /* ADDRESS[16:18] [25] used as GPIO */
789 pinctrl_weim_gpio_1: weimgpio-1 {
790 fsl,pins = <
791 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
792 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
793 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
794 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
795 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
796 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
797 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
798 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
799 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
800 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
801 >;
802 };
803
804 /* ADDRESS[19:24] used as GPIO */
805 pinctrl_weim_gpio_2: weimgpio-2 {
806 fsl,pins = <
807 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
808 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
809 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
810 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
811 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
812 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
813 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
814 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
815 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
816 >;
817 };
818
819 /* DATA[16:31] used as GPIO */
820 pinctrl_weim_gpio_3: weimgpio-3 {
821 fsl,pins = <
822 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
823 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
824 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
825 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
826 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
827 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
828 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
829 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
830 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
831 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
832 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
833 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
834 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
835 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
836 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
837 >;
838 };
839
840 /* DQM[0:3] used as GPIO */
841 pinctrl_weim_gpio_4: weimgpio-4 {
842 fsl,pins = <
843 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
844 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
845 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
846 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
847 >;
848 };
849
850 /* RDY used as GPIO */
851 pinctrl_weim_gpio_5: weimgpio-5 {
852 fsl,pins = <
853 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
854 >;
855 };
856
857 /* ADDRESS[16] DATA[30] used as GPIO */
858 pinctrl_weim_gpio_6: weimgpio-6 {
859 fsl,pins = <
860 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
861 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
862 >;
863 };
864};
1/*
2 * Copyright 2014-2016 Toradex AG
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/gpio/gpio.h>
45
46/ {
47 model = "Toradex Colibri iMX6DL/S Module";
48 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
49
50 backlight: backlight {
51 compatible = "pwm-backlight";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_gpio_bl_on>;
54 pwms = <&pwm3 0 5000000>;
55 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
56 status = "disabled";
57 };
58
59 reg_1p8v: regulator-1p8v {
60 compatible = "regulator-fixed";
61 regulator-name = "1P8V";
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <1800000>;
64 regulator-always-on;
65 };
66
67 reg_2p5v: regulator-2p5v {
68 compatible = "regulator-fixed";
69 regulator-name = "2P5V";
70 regulator-min-microvolt = <2500000>;
71 regulator-max-microvolt = <2500000>;
72 regulator-always-on;
73 };
74
75 reg_3p3v: regulator-3p3v {
76 compatible = "regulator-fixed";
77 regulator-name = "3P3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-always-on;
81 };
82
83 reg_usb_host_vbus: regulator-usb-host-vbus {
84 compatible = "regulator-fixed";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
87 regulator-name = "usb_host_vbus";
88 regulator-min-microvolt = <5000000>;
89 regulator-max-microvolt = <5000000>;
90 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
91 status = "disabled";
92 };
93
94 sound {
95 compatible = "fsl,imx-audio-sgtl5000";
96 model = "imx6dl-colibri-sgtl5000";
97 ssi-controller = <&ssi1>;
98 audio-codec = <&codec>;
99 audio-routing =
100 "Headphone Jack", "HP_OUT",
101 "LINE_IN", "Line In Jack",
102 "MIC_IN", "Mic Jack",
103 "Mic Jack", "Mic Bias";
104 mux-int-port = <1>;
105 mux-ext-port = <5>;
106 };
107
108 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
109 sound_spdif: sound-spdif {
110 compatible = "fsl,imx-audio-spdif";
111 model = "imx-spdif";
112 spdif-controller = <&spdif>;
113 spdif-in;
114 spdif-out;
115 status = "disabled";
116 };
117};
118
119&audmux {
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
122 status = "okay";
123};
124
125/* Optional on SODIMM 55/63 */
126&can1 {
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_flexcan1>;
129 status = "disabled";
130};
131
132/* Optional on SODIMM 178/188 */
133&can2 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_flexcan2>;
136 status = "disabled";
137};
138
139/* Colibri SSP */
140&ecspi4 {
141 cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_ecspi4>;
144 status = "disabled";
145};
146
147&fec {
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_enet>;
150 phy-mode = "rmii";
151 status = "okay";
152};
153
154&hdmi {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_hdmi_ddc>;
157 status = "disabled";
158};
159
160/*
161 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
162 * touch screen controller
163 */
164&i2c2 {
165 clock-frequency = <100000>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c2>;
168 status = "okay";
169
170 pmic: pfuze100@8 {
171 compatible = "fsl,pfuze100";
172 reg = <0x08>;
173
174 regulators {
175 sw1a_reg: sw1ab {
176 regulator-min-microvolt = <300000>;
177 regulator-max-microvolt = <1875000>;
178 regulator-boot-on;
179 regulator-always-on;
180 regulator-ramp-delay = <6250>;
181 };
182
183 sw1c_reg: sw1c {
184 regulator-min-microvolt = <300000>;
185 regulator-max-microvolt = <1875000>;
186 regulator-boot-on;
187 regulator-always-on;
188 regulator-ramp-delay = <6250>;
189 };
190
191 sw3a_reg: sw3a {
192 regulator-min-microvolt = <400000>;
193 regulator-max-microvolt = <1975000>;
194 regulator-boot-on;
195 regulator-always-on;
196 };
197
198 swbst_reg: swbst {
199 regulator-min-microvolt = <5000000>;
200 regulator-max-microvolt = <5150000>;
201 regulator-boot-on;
202 regulator-always-on;
203 };
204
205 snvs_reg: vsnvs {
206 regulator-min-microvolt = <1000000>;
207 regulator-max-microvolt = <3000000>;
208 regulator-boot-on;
209 regulator-always-on;
210 };
211
212 vref_reg: vrefddr {
213 regulator-boot-on;
214 regulator-always-on;
215 };
216
217 /* vgen1: unused */
218
219 vgen2_reg: vgen2 {
220 regulator-min-microvolt = <800000>;
221 regulator-max-microvolt = <1550000>;
222 regulator-boot-on;
223 regulator-always-on;
224 };
225
226 /* vgen3: unused */
227
228 vgen4_reg: vgen4 {
229 regulator-min-microvolt = <1800000>;
230 regulator-max-microvolt = <3300000>;
231 regulator-boot-on;
232 regulator-always-on;
233 };
234
235 vgen5_reg: vgen5 {
236 regulator-min-microvolt = <1800000>;
237 regulator-max-microvolt = <3300000>;
238 regulator-boot-on;
239 regulator-always-on;
240 };
241
242 vgen6_reg: vgen6 {
243 regulator-min-microvolt = <1800000>;
244 regulator-max-microvolt = <3300000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248 };
249 };
250
251 codec: sgtl5000@a {
252 compatible = "fsl,sgtl5000";
253 reg = <0x0a>;
254 clocks = <&clks IMX6QDL_CLK_CKO>;
255 VDDA-supply = <®_2p5v>;
256 VDDIO-supply = <®_3p3v>;
257 lrclk-strength = <3>;
258 };
259
260 /* STMPE811 touch screen controller */
261 stmpe811@41 {
262 compatible = "st,stmpe811";
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_touch_int>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 reg = <0x41>;
268 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
269 interrupt-parent = <&gpio6>;
270 interrupt-controller;
271 id = <0>;
272 blocks = <0x5>;
273 irq-trigger = <0x1>;
274
275 stmpe_touchscreen {
276 compatible = "st,stmpe-ts";
277 /* 3.25 MHz ADC clock speed */
278 st,adc-freq = <1>;
279 /* 8 sample average control */
280 st,ave-ctrl = <3>;
281 /* 7 length fractional part in z */
282 st,fraction-z = <7>;
283 /*
284 * 50 mA typical 80 mA max touchscreen drivers
285 * current limit value
286 */
287 st,i-drive = <1>;
288 /* 12-bit ADC */
289 st,mod-12b = <1>;
290 /* internal ADC reference */
291 st,ref-sel = <0>;
292 /* ADC converstion time: 80 clocks */
293 st,sample-time = <4>;
294 /* 1 ms panel driver settling time */
295 st,settling = <3>;
296 /* 5 ms touch detect interrupt delay */
297 st,touch-det-delay = <5>;
298 };
299 };
300};
301
302/*
303 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
304 */
305&i2c3 {
306 clock-frequency = <100000>;
307 pinctrl-names = "default", "recovery";
308 pinctrl-0 = <&pinctrl_i2c3>;
309 pinctrl-1 = <&pinctrl_i2c3_recovery>;
310 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
311 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
312 status = "disabled";
313};
314
315/* Colibri PWM<B> */
316&pwm1 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_pwm1>;
319 status = "disabled";
320};
321
322/* Colibri PWM<D> */
323&pwm2 {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_pwm2>;
326 status = "disabled";
327};
328
329/* Colibri PWM<A> */
330&pwm3 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_pwm3>;
333 status = "disabled";
334};
335
336/* Colibri PWM<C> */
337&pwm4 {
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_pwm4>;
340 status = "disabled";
341};
342
343/* Optional S/PDIF out on SODIMM 137 */
344&spdif {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_spdif>;
347 status = "disabled";
348};
349
350&ssi1 {
351 status = "okay";
352};
353
354/* Colibri UART_A */
355&uart1 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
358 fsl,dte-mode;
359 uart-has-rtscts;
360 status = "disabled";
361};
362
363/* Colibri UART_B */
364&uart2 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_uart2_dte>;
367 fsl,dte-mode;
368 uart-has-rtscts;
369 status = "disabled";
370};
371
372/* Colibri UART_C */
373&uart3 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_uart3_dte>;
376 fsl,dte-mode;
377 status = "disabled";
378};
379
380&usbotg {
381 pinctrl-names = "default";
382 disable-over-current;
383 dr_mode = "peripheral";
384 status = "disabled";
385};
386
387/* Colibri MMC */
388&usdhc1 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_usdhc1>;
391 vqmmc-supply = <®_3p3v>;
392 bus-width = <4>;
393 voltage-ranges = <3300 3300>;
394 status = "disabled";
395};
396
397/* eMMC */
398&usdhc3 {
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_usdhc3>;
401 vqmmc-supply = <®_3p3v>;
402 bus-width = <8>;
403 voltage-ranges = <3300 3300>;
404 non-removable;
405 status = "okay";
406};
407
408&weim {
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
411 &pinctrl_weim_cs1 &pinctrl_weim_cs2
412 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
413 #address-cells = <2>;
414 #size-cells = <1>;
415 status = "disabled";
416};
417
418&iomuxc {
419 pinctrl_audmux: audmuxgrp {
420 fsl,pins = <
421 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
422 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
423 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
424 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
425 /* SGTL5000 sys_mclk */
426 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
427 >;
428 };
429
430 pinctrl_cam_mclk: cammclkgrp {
431 fsl,pins = <
432 /* Parallel Camera CAM sys_mclk */
433 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
434 >;
435 };
436
437 pinctrl_ecspi4: ecspi4grp {
438 fsl,pins = <
439 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
440 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
441 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
442 /* SPI CS */
443 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
444 >;
445 };
446
447 pinctrl_enet: enetgrp {
448 fsl,pins = <
449 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
450 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
451 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
452 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
453 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
454 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
455 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
456 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
457 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
458 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
459 >;
460 };
461
462 pinctrl_flexcan1: flexcan1grp {
463 fsl,pins = <
464 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
465 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
466 >;
467 };
468
469 pinctrl_flexcan2: flexcan2grp {
470 fsl,pins = <
471 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
472 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
473 >;
474 };
475
476 pinctrl_gpio_bl_on: gpioblon {
477 fsl,pins = <
478 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
479 >;
480 };
481
482 pinctrl_gpio_keys: gpiokeys {
483 fsl,pins = <
484 /* Power button */
485 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0
486 >;
487 };
488
489 pinctrl_hdmi_ddc: hdmiddcgrp {
490 fsl,pins = <
491 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
492 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
493 >;
494 };
495
496 pinctrl_i2c2: i2c2grp {
497 fsl,pins = <
498 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
499 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
500 >;
501 };
502
503 pinctrl_i2c3: i2c3grp {
504 fsl,pins = <
505 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
506 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
507 >;
508 };
509
510 pinctrl_i2c3_recovery: i2c3recoverygrp {
511 fsl,pins = <
512 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
513 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
514 >;
515 };
516
517 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
518 fsl,pins = <
519 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
520 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
521 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
522 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
523 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
524 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
525 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
526 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
527 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
528 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
529 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
530 /* Disable PWM pins on camera interface */
531 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
532 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
533 >;
534 };
535
536 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
537 fsl,pins = <
538 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
539 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
540 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
541 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
542 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
543 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
544 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
545 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
546 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
547 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
548 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
549 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
550 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
551 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
552 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
553 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
554 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
555 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
556 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
557 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
558 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
559 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
560 >;
561 };
562
563 pinctrl_mic_gnd: gpiomicgnd {
564 fsl,pins = <
565 /* Controls Mic GND, PU or '1' pull Mic GND to GND */
566 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
567 >;
568 };
569
570 pinctrl_mmc_cd: gpiommccd {
571 fsl,pins = <
572 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
573 >;
574 };
575
576 pinctrl_pwm1: pwm1grp {
577 fsl,pins = <
578 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
579 >;
580 };
581
582 pinctrl_pwm2: pwm2grp {
583 fsl,pins = <
584 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
585 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
586 >;
587 };
588
589 pinctrl_pwm3: pwm3grp {
590 fsl,pins = <
591 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
592 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
593 >;
594 };
595
596 pinctrl_pwm4: pwm4grp {
597 fsl,pins = <
598 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
599 >;
600 };
601
602 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
603 fsl,pins = <
604 /* USBH_EN */
605 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
606 >;
607 };
608
609 pinctrl_spdif: spdifgrp {
610 fsl,pins = <
611 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
612 >;
613 };
614
615 pinctrl_touch_int: gpiotouchintgrp {
616 fsl,pins = <
617 /* STMPE811 interrupt */
618 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
619 >;
620 };
621
622 pinctrl_uart1_dce: uart1dcegrp {
623 fsl,pins = <
624 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
625 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
626 >;
627 };
628
629 /* DTE mode */
630 pinctrl_uart1_dte: uart1dtegrp {
631 fsl,pins = <
632 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
633 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
634 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
635 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
636 >;
637 };
638
639 /* Additional DTR, DSR, DCD */
640 pinctrl_uart1_ctrl: uart1ctrlgrp {
641 fsl,pins = <
642 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
643 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
644 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
645 >;
646 };
647
648 pinctrl_uart2_dte: uart2dtegrp {
649 fsl,pins = <
650 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
651 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
652 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
653 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
654 >;
655 };
656
657 pinctrl_uart3_dte: uart3dtegrp {
658 fsl,pins = <
659 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
660 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
661 >;
662 };
663
664 pinctrl_usbc_det: usbcdetgrp {
665 fsl,pins = <
666 /* USBC_DET */
667 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
668 /* USBC_DET_EN */
669 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
670 /* USBC_DET_OVERWRITE */
671 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
672 >;
673 };
674
675 pinctrl_usdhc1: usdhc1grp {
676 fsl,pins = <
677 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
678 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
679 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
680 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
681 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
682 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
683 >;
684 };
685
686 pinctrl_usdhc3: usdhc3grp {
687 fsl,pins = <
688 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
689 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
690 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
691 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
692 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
693 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
694 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
695 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
696 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
697 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
698 /* eMMC reset */
699 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
700 >;
701 };
702
703 pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
704 fsl,pins = <
705 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
706 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
707 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
708 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
709 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
710 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
711 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
712 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
713 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
714 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
715 /* eMMC reset */
716 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
717 >;
718 };
719
720 pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
721 fsl,pins = <
722 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
723 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
724 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
725 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
726 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
727 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
728 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
729 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
730 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
731 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
732 /* eMMC reset */
733 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
734 >;
735 };
736
737 pinctrl_weim_cs0: weimcs0grp {
738 fsl,pins = <
739 /* nEXT_CS0 */
740 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
741 >;
742 };
743
744 pinctrl_weim_cs1: weimcs1grp {
745 fsl,pins = <
746 /* nEXT_CS1 */
747 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
748 >;
749 };
750
751 pinctrl_weim_cs2: weimcs2grp {
752 fsl,pins = <
753 /* nEXT_CS2 */
754 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
755 >;
756 };
757
758 pinctrl_weim_sram: weimsramgrp {
759 fsl,pins = <
760 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
761 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
762 /* Data */
763 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
764 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
765 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
766 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
767 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
768 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
769 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
770 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
771 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
772 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
773 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
774 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
775 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
776 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
777 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
778 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
779 /* Address */
780 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
781 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
782 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
783 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
784 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
785 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
786 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
787 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
788 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
789 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
790 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
791 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
792 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
793 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
794 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
795 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
796 >;
797 };
798
799 pinctrl_weim_rdnwr: weimrdnwr {
800 fsl,pins = <
801 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
802 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
803 >;
804 };
805
806 pinctrl_weim_npwe: weimnpwe {
807 fsl,pins = <
808 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
809 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
810 >;
811 };
812
813 /* ADDRESS[16:18] [25] used as GPIO */
814 pinctrl_weim_gpio_1: weimgpio-1 {
815 fsl,pins = <
816 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
817 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
818 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
819 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
820 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
821 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
822 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
823 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
824 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
825 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
826 >;
827 };
828
829 /* ADDRESS[19:24] used as GPIO */
830 pinctrl_weim_gpio_2: weimgpio-2 {
831 fsl,pins = <
832 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
833 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
834 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
835 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
836 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
837 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
838 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
839 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
840 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
841 >;
842 };
843
844 /* DATA[16:31] used as GPIO */
845 pinctrl_weim_gpio_3: weimgpio-3 {
846 fsl,pins = <
847 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
848 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
849 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
850 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
851 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
852 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
853 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
854 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
855 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
856 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
857 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
858 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
859 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
860 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
861 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
862 >;
863 };
864
865 /* DQM[0:3] used as GPIO */
866 pinctrl_weim_gpio_4: weimgpio-4 {
867 fsl,pins = <
868 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
869 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
870 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
871 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
872 >;
873 };
874
875 /* RDY used as GPIO */
876 pinctrl_weim_gpio_5: weimgpio-5 {
877 fsl,pins = <
878 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
879 >;
880 };
881
882 /* ADDRESS[16] DATA[30] used as GPIO */
883 pinctrl_weim_gpio_6: weimgpio-6 {
884 fsl,pins = <
885 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
886 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
887 >;
888 };
889};