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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
4 *
5 * Copyright (c) 2017 Marek Szyprowski
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
7 * http://www.samsung.com
8 */
9
10#include <dt-bindings/clock/samsung,s2mps11.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/gpio/gpio.h>
13#include "exynos5800.dtsi"
14#include "exynos5422-cpus.dtsi"
15
16/ {
17 memory@40000000 {
18 device_type = "memory";
19 reg = <0x40000000 0x7EA00000>;
20 };
21
22 chosen {
23 stdout-path = "serial2:115200n8";
24 };
25
26 firmware@2073000 {
27 compatible = "samsung,secure-firmware";
28 reg = <0x02073000 0x1000>;
29 };
30
31 fixed-rate-clocks {
32 oscclk {
33 compatible = "samsung,exynos5420-oscclk";
34 clock-frequency = <24000000>;
35 };
36 };
37
38 bus_wcore_opp_table: opp-table2 {
39 compatible = "operating-points-v2";
40
41 /* derived from 532MHz MPLL */
42 opp00 {
43 opp-hz = /bits/ 64 <88700000>;
44 opp-microvolt = <925000 925000 1400000>;
45 };
46 opp01 {
47 opp-hz = /bits/ 64 <133000000>;
48 opp-microvolt = <950000 950000 1400000>;
49 };
50 opp02 {
51 opp-hz = /bits/ 64 <177400000>;
52 opp-microvolt = <950000 950000 1400000>;
53 };
54 opp03 {
55 opp-hz = /bits/ 64 <266000000>;
56 opp-microvolt = <950000 950000 1400000>;
57 };
58 opp04 {
59 opp-hz = /bits/ 64 <532000000>;
60 opp-microvolt = <1000000 1000000 1400000>;
61 };
62 };
63
64 bus_noc_opp_table: opp-table3 {
65 compatible = "operating-points-v2";
66
67 /* derived from 666MHz CPLL */
68 opp00 {
69 opp-hz = /bits/ 64 <66600000>;
70 };
71 opp01 {
72 opp-hz = /bits/ 64 <74000000>;
73 };
74 opp02 {
75 opp-hz = /bits/ 64 <83250000>;
76 };
77 opp03 {
78 opp-hz = /bits/ 64 <111000000>;
79 };
80 };
81
82 bus_fsys_apb_opp_table: opp-table4 {
83 compatible = "operating-points-v2";
84
85 /* derived from 666MHz CPLL */
86 opp00 {
87 opp-hz = /bits/ 64 <111000000>;
88 };
89 opp01 {
90 opp-hz = /bits/ 64 <222000000>;
91 };
92 };
93
94 bus_fsys2_opp_table: opp-table5 {
95 compatible = "operating-points-v2";
96
97 /* derived from 600MHz DPLL */
98 opp00 {
99 opp-hz = /bits/ 64 <75000000>;
100 };
101 opp01 {
102 opp-hz = /bits/ 64 <120000000>;
103 };
104 opp02 {
105 opp-hz = /bits/ 64 <200000000>;
106 };
107 };
108
109 bus_mfc_opp_table: opp-table6 {
110 compatible = "operating-points-v2";
111
112 /* derived from 666MHz CPLL */
113 opp00 {
114 opp-hz = /bits/ 64 <83250000>;
115 };
116 opp01 {
117 opp-hz = /bits/ 64 <111000000>;
118 };
119 opp02 {
120 opp-hz = /bits/ 64 <166500000>;
121 };
122 opp03 {
123 opp-hz = /bits/ 64 <222000000>;
124 };
125 opp04 {
126 opp-hz = /bits/ 64 <333000000>;
127 };
128 };
129
130 bus_gen_opp_table: opp-table7 {
131 compatible = "operating-points-v2";
132
133 /* derived from 532MHz MPLL */
134 opp00 {
135 opp-hz = /bits/ 64 <88700000>;
136 };
137 opp01 {
138 opp-hz = /bits/ 64 <133000000>;
139 };
140 opp02 {
141 opp-hz = /bits/ 64 <178000000>;
142 };
143 opp03 {
144 opp-hz = /bits/ 64 <266000000>;
145 };
146 };
147
148 bus_peri_opp_table: opp-table8 {
149 compatible = "operating-points-v2";
150
151 /* derived from 666MHz CPLL */
152 opp00 {
153 opp-hz = /bits/ 64 <66600000>;
154 };
155 };
156
157 bus_g2d_opp_table: opp-table9 {
158 compatible = "operating-points-v2";
159
160 /* derived from 666MHz CPLL */
161 opp00 {
162 opp-hz = /bits/ 64 <83250000>;
163 };
164 opp01 {
165 opp-hz = /bits/ 64 <111000000>;
166 };
167 opp02 {
168 opp-hz = /bits/ 64 <166500000>;
169 };
170 opp03 {
171 opp-hz = /bits/ 64 <222000000>;
172 };
173 opp04 {
174 opp-hz = /bits/ 64 <333000000>;
175 };
176 };
177
178 bus_g2d_acp_opp_table: opp-table10 {
179 compatible = "operating-points-v2";
180
181 /* derived from 532MHz MPLL */
182 opp00 {
183 opp-hz = /bits/ 64 <66500000>;
184 };
185 opp01 {
186 opp-hz = /bits/ 64 <133000000>;
187 };
188 opp02 {
189 opp-hz = /bits/ 64 <178000000>;
190 };
191 opp03 {
192 opp-hz = /bits/ 64 <266000000>;
193 };
194 };
195
196 bus_jpeg_opp_table: opp-table11 {
197 compatible = "operating-points-v2";
198
199 /* derived from 600MHz DPLL */
200 opp00 {
201 opp-hz = /bits/ 64 <75000000>;
202 };
203 opp01 {
204 opp-hz = /bits/ 64 <150000000>;
205 };
206 opp02 {
207 opp-hz = /bits/ 64 <200000000>;
208 };
209 opp03 {
210 opp-hz = /bits/ 64 <300000000>;
211 };
212 };
213
214 bus_jpeg_apb_opp_table: opp-table12 {
215 compatible = "operating-points-v2";
216
217 /* derived from 666MHz CPLL */
218 opp00 {
219 opp-hz = /bits/ 64 <83250000>;
220 };
221 opp01 {
222 opp-hz = /bits/ 64 <111000000>;
223 };
224 opp02 {
225 opp-hz = /bits/ 64 <133000000>;
226 };
227 opp03 {
228 opp-hz = /bits/ 64 <166500000>;
229 };
230 };
231
232 bus_disp1_fimd_opp_table: opp-table13 {
233 compatible = "operating-points-v2";
234
235 /* derived from 600MHz DPLL */
236 opp00 {
237 opp-hz = /bits/ 64 <120000000>;
238 };
239 opp01 {
240 opp-hz = /bits/ 64 <200000000>;
241 };
242 };
243
244 bus_disp1_opp_table: opp-table14 {
245 compatible = "operating-points-v2";
246
247 /* derived from 600MHz DPLL */
248 opp00 {
249 opp-hz = /bits/ 64 <120000000>;
250 };
251 opp01 {
252 opp-hz = /bits/ 64 <200000000>;
253 };
254 opp02 {
255 opp-hz = /bits/ 64 <300000000>;
256 };
257 };
258
259 bus_gscl_opp_table: opp-table15 {
260 compatible = "operating-points-v2";
261
262 /* derived from 600MHz DPLL */
263 opp00 {
264 opp-hz = /bits/ 64 <150000000>;
265 };
266 opp01 {
267 opp-hz = /bits/ 64 <200000000>;
268 };
269 opp02 {
270 opp-hz = /bits/ 64 <300000000>;
271 };
272 };
273
274 bus_mscl_opp_table: opp-table16 {
275 compatible = "operating-points-v2";
276
277 /* derived from 666MHz CPLL */
278 opp00 {
279 opp-hz = /bits/ 64 <84000000>;
280 };
281 opp01 {
282 opp-hz = /bits/ 64 <167000000>;
283 };
284 opp02 {
285 opp-hz = /bits/ 64 <222000000>;
286 };
287 opp03 {
288 opp-hz = /bits/ 64 <333000000>;
289 };
290 opp04 {
291 opp-hz = /bits/ 64 <666000000>;
292 };
293 };
294
295 dmc_opp_table: opp-table17 {
296 compatible = "operating-points-v2";
297
298 opp00 {
299 opp-hz = /bits/ 64 <165000000>;
300 opp-microvolt = <875000>;
301 };
302 opp01 {
303 opp-hz = /bits/ 64 <206000000>;
304 opp-microvolt = <875000>;
305 };
306 opp02 {
307 opp-hz = /bits/ 64 <275000000>;
308 opp-microvolt = <875000>;
309 };
310 opp03 {
311 opp-hz = /bits/ 64 <413000000>;
312 opp-microvolt = <887500>;
313 };
314 opp04 {
315 opp-hz = /bits/ 64 <543000000>;
316 opp-microvolt = <937500>;
317 };
318 opp05 {
319 opp-hz = /bits/ 64 <633000000>;
320 opp-microvolt = <1012500>;
321 };
322 opp06 {
323 opp-hz = /bits/ 64 <728000000>;
324 opp-microvolt = <1037500>;
325 };
326 opp07 {
327 opp-hz = /bits/ 64 <825000000>;
328 opp-microvolt = <1050000>;
329 };
330 };
331
332 samsung_K3QF2F20DB: lpddr3 {
333 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
334 density = <16384>;
335 io-width = <32>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338
339 tRFC-min-tck = <17>;
340 tRRD-min-tck = <2>;
341 tRPab-min-tck = <2>;
342 tRPpb-min-tck = <2>;
343 tRCD-min-tck = <3>;
344 tRC-min-tck = <6>;
345 tRAS-min-tck = <5>;
346 tWTR-min-tck = <2>;
347 tWR-min-tck = <7>;
348 tRTP-min-tck = <2>;
349 tW2W-C2C-min-tck = <0>;
350 tR2R-C2C-min-tck = <0>;
351 tWL-min-tck = <8>;
352 tDQSCK-min-tck = <5>;
353 tRL-min-tck = <14>;
354 tFAW-min-tck = <5>;
355 tXSR-min-tck = <12>;
356 tXP-min-tck = <2>;
357 tCKE-min-tck = <2>;
358 tCKESR-min-tck = <2>;
359 tMRD-min-tck = <5>;
360
361 timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
362 compatible = "jedec,lpddr3-timings";
363 /* workaround: 'reg' shows max-freq */
364 reg = <800000000>;
365 min-freq = <100000000>;
366 tRFC = <65000>;
367 tRRD = <6000>;
368 tRPab = <12000>;
369 tRPpb = <12000>;
370 tRCD = <10000>;
371 tRC = <33750>;
372 tRAS = <23000>;
373 tWTR = <3750>;
374 tWR = <7500>;
375 tRTP = <3750>;
376 tW2W-C2C = <0>;
377 tR2R-C2C = <0>;
378 tFAW = <25000>;
379 tXSR = <70000>;
380 tXP = <3750>;
381 tCKE = <3750>;
382 tCKESR = <3750>;
383 tMRD = <7000>;
384 };
385 };
386};
387
388&adc {
389 vdd-supply = <&ldo4_reg>;
390 status = "okay";
391};
392
393&bus_wcore {
394 operating-points-v2 = <&bus_wcore_opp_table>;
395 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
396 <&nocp_mem1_0>, <&nocp_mem1_1>;
397 vdd-supply = <&buck3_reg>;
398 exynos,saturation-ratio = <100>;
399 status = "okay";
400};
401
402&bus_noc {
403 operating-points-v2 = <&bus_noc_opp_table>;
404 devfreq = <&bus_wcore>;
405 status = "okay";
406};
407
408&bus_fsys_apb {
409 operating-points-v2 = <&bus_fsys_apb_opp_table>;
410 devfreq = <&bus_wcore>;
411 status = "okay";
412};
413
414&bus_fsys2 {
415 operating-points-v2 = <&bus_fsys2_opp_table>;
416 devfreq = <&bus_wcore>;
417 status = "okay";
418};
419
420&bus_mfc {
421 operating-points-v2 = <&bus_mfc_opp_table>;
422 devfreq = <&bus_wcore>;
423 status = "okay";
424};
425
426&bus_gen {
427 operating-points-v2 = <&bus_gen_opp_table>;
428 devfreq = <&bus_wcore>;
429 status = "okay";
430};
431
432&bus_peri {
433 operating-points-v2 = <&bus_peri_opp_table>;
434 devfreq = <&bus_wcore>;
435 status = "okay";
436};
437
438&bus_g2d {
439 operating-points-v2 = <&bus_g2d_opp_table>;
440 devfreq = <&bus_wcore>;
441 status = "okay";
442};
443
444&bus_g2d_acp {
445 operating-points-v2 = <&bus_g2d_acp_opp_table>;
446 devfreq = <&bus_wcore>;
447 status = "okay";
448};
449
450&bus_jpeg {
451 operating-points-v2 = <&bus_jpeg_opp_table>;
452 devfreq = <&bus_wcore>;
453 status = "okay";
454};
455
456&bus_jpeg_apb {
457 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
458 devfreq = <&bus_wcore>;
459 status = "okay";
460};
461
462&bus_disp1_fimd {
463 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
464 devfreq = <&bus_wcore>;
465 status = "okay";
466};
467
468&bus_disp1 {
469 operating-points-v2 = <&bus_disp1_opp_table>;
470 devfreq = <&bus_wcore>;
471 status = "okay";
472};
473
474&bus_gscl_scaler {
475 operating-points-v2 = <&bus_gscl_opp_table>;
476 devfreq = <&bus_wcore>;
477 status = "okay";
478};
479
480&bus_mscl {
481 operating-points-v2 = <&bus_mscl_opp_table>;
482 devfreq = <&bus_wcore>;
483 status = "okay";
484};
485
486&cpu0 {
487 cpu-supply = <&buck6_reg>;
488};
489
490&cpu4 {
491 cpu-supply = <&buck2_reg>;
492};
493
494&dmc {
495 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
496 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
497 device-handle = <&samsung_K3QF2F20DB>;
498 operating-points-v2 = <&dmc_opp_table>;
499 vdd-supply = <&buck1_reg>;
500 status = "okay";
501};
502
503&hsi2c_4 {
504 status = "okay";
505
506 pmic@66 {
507 compatible = "samsung,s2mps11-pmic";
508 reg = <0x66>;
509 samsung,s2mps11-acokb-ground;
510
511 interrupt-parent = <&gpx0>;
512 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&s2mps11_irq>;
515 wakeup-source;
516
517 s2mps11_osc: clocks {
518 compatible = "samsung,s2mps11-clk";
519 #clock-cells = <1>;
520 clock-output-names = "s2mps11_ap",
521 "s2mps11_cp", "s2mps11_bt";
522 };
523
524 regulators {
525 ldo1_reg: LDO1 {
526 regulator-name = "vdd_ldo1";
527 regulator-min-microvolt = <1000000>;
528 regulator-max-microvolt = <1000000>;
529 regulator-always-on;
530 };
531
532 ldo2_reg: LDO2 {
533 regulator-name = "vdd_ldo2";
534 regulator-min-microvolt = <1800000>;
535 regulator-max-microvolt = <1800000>;
536 regulator-always-on;
537 };
538
539 ldo3_reg: LDO3 {
540 regulator-name = "vddq_mmc0";
541 regulator-min-microvolt = <1800000>;
542 regulator-max-microvolt = <1800000>;
543 };
544
545 ldo4_reg: LDO4 {
546 regulator-name = "vdd_adc";
547 regulator-min-microvolt = <1800000>;
548 regulator-max-microvolt = <1800000>;
549
550 regulator-state-mem {
551 regulator-off-in-suspend;
552 };
553 };
554
555 ldo5_reg: LDO5 {
556 regulator-name = "vdd_ldo5";
557 regulator-min-microvolt = <1800000>;
558 regulator-max-microvolt = <1800000>;
559 regulator-always-on;
560
561 regulator-state-mem {
562 regulator-off-in-suspend;
563 };
564 };
565
566 ldo6_reg: LDO6 {
567 regulator-name = "vdd_ldo6";
568 regulator-min-microvolt = <1000000>;
569 regulator-max-microvolt = <1000000>;
570 regulator-always-on;
571
572 regulator-state-mem {
573 regulator-off-in-suspend;
574 };
575 };
576
577 ldo7_reg: LDO7 {
578 regulator-name = "vdd_ldo7";
579 regulator-min-microvolt = <1800000>;
580 regulator-max-microvolt = <1800000>;
581 regulator-always-on;
582
583 regulator-state-mem {
584 regulator-off-in-suspend;
585 };
586 };
587
588 ldo8_reg: LDO8 {
589 regulator-name = "vdd_ldo8";
590 regulator-min-microvolt = <1800000>;
591 regulator-max-microvolt = <1800000>;
592 regulator-always-on;
593
594 regulator-state-mem {
595 regulator-off-in-suspend;
596 };
597 };
598
599 ldo9_reg: LDO9 {
600 regulator-name = "vdd_ldo9";
601 regulator-min-microvolt = <3000000>;
602 regulator-max-microvolt = <3000000>;
603 regulator-always-on;
604
605 regulator-state-mem {
606 regulator-off-in-suspend;
607 };
608 };
609
610 ldo10_reg: LDO10 {
611 regulator-name = "vdd_ldo10";
612 regulator-min-microvolt = <1800000>;
613 regulator-max-microvolt = <1800000>;
614 regulator-always-on;
615
616 regulator-state-mem {
617 regulator-off-in-suspend;
618 };
619 };
620
621 ldo11_reg: LDO11 {
622 regulator-name = "vdd_ldo11";
623 regulator-min-microvolt = <1000000>;
624 regulator-max-microvolt = <1000000>;
625 regulator-always-on;
626
627 regulator-state-mem {
628 regulator-off-in-suspend;
629 };
630 };
631
632 ldo12_reg: LDO12 {
633 /* Unused */
634 regulator-name = "vdd_ldo12";
635 regulator-min-microvolt = <800000>;
636 regulator-max-microvolt = <2375000>;
637 };
638
639 ldo13_reg: LDO13 {
640 regulator-name = "vddq_mmc2";
641 regulator-min-microvolt = <1800000>;
642 regulator-max-microvolt = <2800000>;
643
644 regulator-state-mem {
645 regulator-off-in-suspend;
646 };
647 };
648
649 ldo14_reg: LDO14 {
650 /* Unused */
651 regulator-name = "vdd_ldo14";
652 regulator-min-microvolt = <800000>;
653 regulator-max-microvolt = <3950000>;
654 };
655
656 ldo15_reg: LDO15 {
657 regulator-name = "vdd_ldo15";
658 regulator-min-microvolt = <3300000>;
659 regulator-max-microvolt = <3300000>;
660 regulator-always-on;
661
662 regulator-state-mem {
663 regulator-off-in-suspend;
664 };
665 };
666
667 ldo16_reg: LDO16 {
668 /* Unused */
669 regulator-name = "vdd_ldo16";
670 regulator-min-microvolt = <800000>;
671 regulator-max-microvolt = <3950000>;
672 };
673
674 ldo17_reg: LDO17 {
675 regulator-name = "vdd_ldo17";
676 regulator-min-microvolt = <3300000>;
677 regulator-max-microvolt = <3300000>;
678 regulator-always-on;
679
680 regulator-state-mem {
681 regulator-off-in-suspend;
682 };
683 };
684
685 ldo18_reg: LDO18 {
686 regulator-name = "vdd_emmc_1V8";
687 regulator-min-microvolt = <1800000>;
688 regulator-max-microvolt = <1800000>;
689
690 regulator-state-mem {
691 regulator-off-in-suspend;
692 };
693 };
694
695 ldo19_reg: LDO19 {
696 regulator-name = "vdd_sd";
697 regulator-min-microvolt = <2800000>;
698 regulator-max-microvolt = <2800000>;
699
700 regulator-state-mem {
701 regulator-off-in-suspend;
702 };
703 };
704
705 ldo20_reg: LDO20 {
706 /* Unused */
707 regulator-name = "vdd_ldo20";
708 regulator-min-microvolt = <800000>;
709 regulator-max-microvolt = <3950000>;
710 };
711
712 ldo21_reg: LDO21 {
713 /* Unused */
714 regulator-name = "vdd_ldo21";
715 regulator-min-microvolt = <800000>;
716 regulator-max-microvolt = <3950000>;
717 };
718
719 ldo22_reg: LDO22 {
720 /* Unused */
721 regulator-name = "vdd_ldo22";
722 regulator-min-microvolt = <800000>;
723 regulator-max-microvolt = <2375000>;
724 };
725
726 ldo23_reg: LDO23 {
727 regulator-name = "vdd_mifs";
728 regulator-min-microvolt = <1100000>;
729 regulator-max-microvolt = <1100000>;
730 regulator-always-on;
731
732 regulator-state-mem {
733 regulator-off-in-suspend;
734 };
735 };
736
737 ldo24_reg: LDO24 {
738 /* Unused */
739 regulator-name = "vdd_ldo24";
740 regulator-min-microvolt = <800000>;
741 regulator-max-microvolt = <3950000>;
742 };
743
744 ldo25_reg: LDO25 {
745 /* Unused */
746 regulator-name = "vdd_ldo25";
747 regulator-min-microvolt = <800000>;
748 regulator-max-microvolt = <3950000>;
749 };
750
751 ldo26_reg: LDO26 {
752 /* Used on XU3, XU3-Lite and XU4 */
753 regulator-name = "vdd_ldo26";
754 regulator-min-microvolt = <800000>;
755 regulator-max-microvolt = <3950000>;
756
757 regulator-state-mem {
758 regulator-off-in-suspend;
759 };
760 };
761
762 ldo27_reg: LDO27 {
763 regulator-name = "vdd_g3ds";
764 regulator-min-microvolt = <1000000>;
765 regulator-max-microvolt = <1000000>;
766 regulator-always-on;
767
768 regulator-state-mem {
769 regulator-off-in-suspend;
770 };
771 };
772
773 ldo28_reg: LDO28 {
774 /* Used on XU3 */
775 regulator-name = "vdd_ldo28";
776 regulator-min-microvolt = <800000>;
777 regulator-max-microvolt = <3950000>;
778
779 regulator-state-mem {
780 regulator-off-in-suspend;
781 };
782 };
783
784 ldo29_reg: LDO29 {
785 /* Unused */
786 regulator-name = "vdd_ldo29";
787 regulator-min-microvolt = <800000>;
788 regulator-max-microvolt = <3950000>;
789 };
790
791 ldo30_reg: LDO30 {
792 /* Unused */
793 regulator-name = "vdd_ldo30";
794 regulator-min-microvolt = <800000>;
795 regulator-max-microvolt = <3950000>;
796 };
797
798 ldo31_reg: LDO31 {
799 /* Unused */
800 regulator-name = "vdd_ldo31";
801 regulator-min-microvolt = <800000>;
802 regulator-max-microvolt = <3950000>;
803 };
804
805 ldo32_reg: LDO32 {
806 /* Unused */
807 regulator-name = "vdd_ldo32";
808 regulator-min-microvolt = <800000>;
809 regulator-max-microvolt = <3950000>;
810 };
811
812 ldo33_reg: LDO33 {
813 /* Unused */
814 regulator-name = "vdd_ldo33";
815 regulator-min-microvolt = <800000>;
816 regulator-max-microvolt = <3950000>;
817 };
818
819 ldo34_reg: LDO34 {
820 /* Unused */
821 regulator-name = "vdd_ldo34";
822 regulator-min-microvolt = <800000>;
823 regulator-max-microvolt = <3950000>;
824 };
825
826 ldo35_reg: LDO35 {
827 /* Unused */
828 regulator-name = "vdd_ldo35";
829 regulator-min-microvolt = <800000>;
830 regulator-max-microvolt = <2375000>;
831 };
832
833 ldo36_reg: LDO36 {
834 /* Unused */
835 regulator-name = "vdd_ldo36";
836 regulator-min-microvolt = <800000>;
837 regulator-max-microvolt = <3950000>;
838 };
839
840 ldo37_reg: LDO37 {
841 /* Unused */
842 regulator-name = "vdd_ldo37";
843 regulator-min-microvolt = <800000>;
844 regulator-max-microvolt = <3950000>;
845 };
846
847 ldo38_reg: LDO38 {
848 /* Unused */
849 regulator-name = "vdd_ldo38";
850 regulator-min-microvolt = <800000>;
851 regulator-max-microvolt = <3950000>;
852 };
853
854 buck1_reg: BUCK1 {
855 regulator-name = "vdd_mif";
856 regulator-min-microvolt = <800000>;
857 regulator-max-microvolt = <1300000>;
858 regulator-always-on;
859 regulator-boot-on;
860
861 regulator-state-mem {
862 regulator-off-in-suspend;
863 };
864 };
865
866 buck2_reg: BUCK2 {
867 regulator-name = "vdd_arm";
868 regulator-min-microvolt = <800000>;
869 regulator-max-microvolt = <1500000>;
870 regulator-always-on;
871 regulator-boot-on;
872 regulator-coupled-with = <&buck3_reg>;
873 regulator-coupled-max-spread = <300000>;
874
875 regulator-state-mem {
876 regulator-off-in-suspend;
877 };
878 };
879
880 buck3_reg: BUCK3 {
881 regulator-name = "vdd_int";
882 regulator-min-microvolt = <800000>;
883 regulator-max-microvolt = <1400000>;
884 regulator-always-on;
885 regulator-boot-on;
886 regulator-coupled-with = <&buck2_reg>;
887 regulator-coupled-max-spread = <300000>;
888
889 regulator-state-mem {
890 regulator-off-in-suspend;
891 };
892 };
893
894 buck4_reg: BUCK4 {
895 regulator-name = "vdd_g3d";
896 regulator-min-microvolt = <800000>;
897 regulator-max-microvolt = <1400000>;
898 regulator-boot-on;
899 regulator-always-on;
900
901 regulator-state-mem {
902 regulator-off-in-suspend;
903 };
904 };
905
906 buck5_reg: BUCK5 {
907 regulator-name = "vdd_mem";
908 regulator-min-microvolt = <800000>;
909 regulator-max-microvolt = <1400000>;
910 regulator-always-on;
911 regulator-boot-on;
912 };
913
914 buck6_reg: BUCK6 {
915 regulator-name = "vdd_kfc";
916 regulator-min-microvolt = <800000>;
917 regulator-max-microvolt = <1500000>;
918 regulator-always-on;
919 regulator-boot-on;
920
921 regulator-state-mem {
922 regulator-off-in-suspend;
923 };
924 };
925
926 buck7_reg: BUCK7 {
927 regulator-name = "vdd_1.35v_ldo";
928 regulator-min-microvolt = <1200000>;
929 regulator-max-microvolt = <1500000>;
930 regulator-always-on;
931 regulator-boot-on;
932 };
933
934 buck8_reg: BUCK8 {
935 regulator-name = "vdd_2.0v_ldo";
936 regulator-min-microvolt = <1800000>;
937 regulator-max-microvolt = <2100000>;
938 regulator-always-on;
939 regulator-boot-on;
940 };
941
942 buck9_reg: BUCK9 {
943 regulator-name = "vdd_2.8v_ldo";
944 regulator-min-microvolt = <3000000>;
945 regulator-max-microvolt = <3750000>;
946 regulator-always-on;
947 regulator-boot-on;
948
949 regulator-state-mem {
950 regulator-off-in-suspend;
951 };
952 };
953
954 buck10_reg: BUCK10 {
955 regulator-name = "vdd_vmem";
956 regulator-min-microvolt = <2850000>;
957 regulator-max-microvolt = <2850000>;
958
959 regulator-state-mem {
960 regulator-off-in-suspend;
961 };
962 };
963 };
964 };
965};
966
967&mmc_2 {
968 status = "okay";
969 card-detect-delay = <200>;
970 samsung,dw-mshc-ciu-div = <3>;
971 samsung,dw-mshc-sdr-timing = <0 4>;
972 samsung,dw-mshc-ddr-timing = <0 2>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
975 bus-width = <4>;
976 cap-sd-highspeed;
977 max-frequency = <200000000>;
978 vmmc-supply = <&ldo19_reg>;
979 vqmmc-supply = <&ldo13_reg>;
980 sd-uhs-sdr50;
981 sd-uhs-sdr104;
982 sd-uhs-ddr50;
983};
984
985&nocp_mem0_0 {
986 status = "okay";
987};
988
989&nocp_mem0_1 {
990 status = "okay";
991};
992
993&nocp_mem1_0 {
994 status = "okay";
995};
996
997&nocp_mem1_1 {
998 status = "okay";
999};
1000
1001&pinctrl_0 {
1002 s2mps11_irq: s2mps11-irq {
1003 samsung,pins = "gpx0-4";
1004 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
1005 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1006 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1007 };
1008};
1009
1010&ppmu_dmc0_0 {
1011 status = "okay";
1012};
1013
1014&ppmu_dmc0_1 {
1015 status = "okay";
1016};
1017
1018&ppmu_dmc1_0 {
1019 status = "okay";
1020};
1021
1022&ppmu_dmc1_1 {
1023 status = "okay";
1024};
1025
1026&tmu_cpu0 {
1027 vtmu-supply = <&ldo7_reg>;
1028};
1029
1030&tmu_cpu1 {
1031 vtmu-supply = <&ldo7_reg>;
1032};
1033
1034&tmu_cpu2 {
1035 vtmu-supply = <&ldo7_reg>;
1036};
1037
1038&tmu_cpu3 {
1039 vtmu-supply = <&ldo7_reg>;
1040};
1041
1042&tmu_gpu {
1043 vtmu-supply = <&ldo7_reg>;
1044};
1045
1046&gpu {
1047 mali-supply = <&buck4_reg>;
1048 status = "okay";
1049};
1050
1051&rtc {
1052 status = "okay";
1053 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
1054 clock-names = "rtc", "rtc_src";
1055};
1056
1057&usbdrd_dwc3_0 {
1058 dr_mode = "host";
1059};
1060
1061/* usbdrd_dwc3_1 mode customized in each board */
1062
1063&usbdrd3_0 {
1064 vdd33-supply = <&ldo9_reg>;
1065 vdd10-supply = <&ldo11_reg>;
1066};
1067
1068&usbdrd3_1 {
1069 vdd33-supply = <&ldo9_reg>;
1070 vdd10-supply = <&ldo11_reg>;
1071};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Hardkernel Odroid XU3/XU4/HC1 boards core device tree source
4 *
5 * Copyright (c) 2017 Marek Szyprowski
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
7 * http://www.samsung.com
8 */
9
10#include <dt-bindings/clock/samsung,s2mps11.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/gpio/gpio.h>
13#include "exynos5800.dtsi"
14#include "exynos5422-cpus.dtsi"
15
16/ {
17 memory@40000000 {
18 device_type = "memory";
19 reg = <0x40000000 0x7EA00000>;
20 };
21
22 chosen {
23 stdout-path = "serial2:115200n8";
24 };
25
26 firmware@02073000 {
27 compatible = "samsung,secure-firmware";
28 reg = <0x02073000 0x1000>;
29 };
30
31 fixed-rate-clocks {
32 oscclk {
33 compatible = "samsung,exynos5420-oscclk";
34 clock-frequency = <24000000>;
35 };
36 };
37};
38
39&bus_wcore {
40 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
41 <&nocp_mem1_0>, <&nocp_mem1_1>;
42 vdd-supply = <&buck3_reg>;
43 exynos,saturation-ratio = <100>;
44 status = "okay";
45};
46
47&bus_noc {
48 devfreq = <&bus_wcore>;
49 status = "okay";
50};
51
52&bus_fsys_apb {
53 devfreq = <&bus_wcore>;
54 status = "okay";
55};
56
57&bus_fsys {
58 devfreq = <&bus_wcore>;
59 status = "okay";
60};
61
62&bus_fsys2 {
63 devfreq = <&bus_wcore>;
64 status = "okay";
65};
66
67&bus_mfc {
68 devfreq = <&bus_wcore>;
69 status = "okay";
70};
71
72&bus_gen {
73 devfreq = <&bus_wcore>;
74 status = "okay";
75};
76
77&bus_peri {
78 devfreq = <&bus_wcore>;
79 status = "okay";
80};
81
82&bus_g2d {
83 devfreq = <&bus_wcore>;
84 status = "okay";
85};
86
87&bus_g2d_acp {
88 devfreq = <&bus_wcore>;
89 status = "okay";
90};
91
92&bus_jpeg {
93 devfreq = <&bus_wcore>;
94 status = "okay";
95};
96
97&bus_jpeg_apb {
98 devfreq = <&bus_wcore>;
99 status = "okay";
100};
101
102&bus_disp1_fimd {
103 devfreq = <&bus_wcore>;
104 status = "okay";
105};
106
107&bus_disp1 {
108 devfreq = <&bus_wcore>;
109 status = "okay";
110};
111
112&bus_gscl_scaler {
113 devfreq = <&bus_wcore>;
114 status = "okay";
115};
116
117&bus_mscl {
118 devfreq = <&bus_wcore>;
119 status = "okay";
120};
121
122&cpu0 {
123 cpu-supply = <&buck6_reg>;
124};
125
126&cpu4 {
127 cpu-supply = <&buck2_reg>;
128};
129
130&hsi2c_4 {
131 status = "okay";
132
133 s2mps11_pmic@66 {
134 compatible = "samsung,s2mps11-pmic";
135 reg = <0x66>;
136 samsung,s2mps11-acokb-ground;
137
138 interrupt-parent = <&gpx0>;
139 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&s2mps11_irq>;
142
143 s2mps11_osc: clocks {
144 #clock-cells = <1>;
145 clock-output-names = "s2mps11_ap",
146 "s2mps11_cp", "s2mps11_bt";
147 };
148
149 regulators {
150 ldo1_reg: LDO1 {
151 regulator-name = "vdd_ldo1";
152 regulator-min-microvolt = <1000000>;
153 regulator-max-microvolt = <1000000>;
154 regulator-always-on;
155 };
156
157 ldo3_reg: LDO3 {
158 regulator-name = "vddq_mmc0";
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 };
162
163 ldo4_reg: LDO4 {
164 regulator-name = "vdd_adc";
165 regulator-min-microvolt = <1800000>;
166 regulator-max-microvolt = <1800000>;
167 };
168
169 ldo5_reg: LDO5 {
170 regulator-name = "vdd_ldo5";
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1800000>;
173 regulator-always-on;
174 };
175
176 ldo6_reg: LDO6 {
177 regulator-name = "vdd_ldo6";
178 regulator-min-microvolt = <1000000>;
179 regulator-max-microvolt = <1000000>;
180 regulator-always-on;
181 };
182
183 ldo7_reg: LDO7 {
184 regulator-name = "vdd_ldo7";
185 regulator-min-microvolt = <1800000>;
186 regulator-max-microvolt = <1800000>;
187 regulator-always-on;
188 };
189
190 ldo8_reg: LDO8 {
191 regulator-name = "vdd_ldo8";
192 regulator-min-microvolt = <1800000>;
193 regulator-max-microvolt = <1800000>;
194 regulator-always-on;
195 };
196
197 ldo9_reg: LDO9 {
198 regulator-name = "vdd_ldo9";
199 regulator-min-microvolt = <3000000>;
200 regulator-max-microvolt = <3000000>;
201 regulator-always-on;
202 };
203
204 ldo10_reg: LDO10 {
205 regulator-name = "vdd_ldo10";
206 regulator-min-microvolt = <1800000>;
207 regulator-max-microvolt = <1800000>;
208 regulator-always-on;
209 };
210
211 ldo11_reg: LDO11 {
212 regulator-name = "vdd_ldo11";
213 regulator-min-microvolt = <1000000>;
214 regulator-max-microvolt = <1000000>;
215 regulator-always-on;
216 };
217
218 ldo12_reg: LDO12 {
219 regulator-name = "vdd_ldo12";
220 regulator-min-microvolt = <1800000>;
221 regulator-max-microvolt = <1800000>;
222 regulator-always-on;
223 };
224
225 ldo13_reg: LDO13 {
226 regulator-name = "vddq_mmc2";
227 regulator-min-microvolt = <2800000>;
228 regulator-max-microvolt = <2800000>;
229 };
230
231 ldo15_reg: LDO15 {
232 regulator-name = "vdd_ldo15";
233 regulator-min-microvolt = <3300000>;
234 regulator-max-microvolt = <3300000>;
235 regulator-always-on;
236 };
237
238 ldo16_reg: LDO16 {
239 regulator-name = "vdd_ldo16";
240 regulator-min-microvolt = <2200000>;
241 regulator-max-microvolt = <2200000>;
242 regulator-always-on;
243 };
244
245 ldo17_reg: LDO17 {
246 regulator-name = "vdd_ldo17";
247 regulator-min-microvolt = <3300000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-always-on;
250 };
251
252 ldo18_reg: LDO18 {
253 regulator-name = "vdd_emmc_1V8";
254 regulator-min-microvolt = <1800000>;
255 regulator-max-microvolt = <1800000>;
256 };
257
258 ldo19_reg: LDO19 {
259 regulator-name = "vdd_sd";
260 regulator-min-microvolt = <2800000>;
261 regulator-max-microvolt = <2800000>;
262 };
263
264 ldo24_reg: LDO24 {
265 regulator-name = "tsp_io";
266 regulator-min-microvolt = <2800000>;
267 regulator-max-microvolt = <2800000>;
268 regulator-always-on;
269 };
270
271 ldo26_reg: LDO26 {
272 regulator-name = "vdd_ldo26";
273 regulator-min-microvolt = <3000000>;
274 regulator-max-microvolt = <3000000>;
275 regulator-always-on;
276 };
277
278 buck1_reg: BUCK1 {
279 regulator-name = "vdd_mif";
280 regulator-min-microvolt = <800000>;
281 regulator-max-microvolt = <1300000>;
282 regulator-always-on;
283 regulator-boot-on;
284 };
285
286 buck2_reg: BUCK2 {
287 regulator-name = "vdd_arm";
288 regulator-min-microvolt = <800000>;
289 regulator-max-microvolt = <1500000>;
290 regulator-always-on;
291 regulator-boot-on;
292 };
293
294 buck3_reg: BUCK3 {
295 regulator-name = "vdd_int";
296 regulator-min-microvolt = <800000>;
297 regulator-max-microvolt = <1400000>;
298 regulator-always-on;
299 regulator-boot-on;
300 };
301
302 buck4_reg: BUCK4 {
303 regulator-name = "vdd_g3d";
304 regulator-min-microvolt = <800000>;
305 regulator-max-microvolt = <1400000>;
306 regulator-always-on;
307 regulator-boot-on;
308 };
309
310 buck5_reg: BUCK5 {
311 regulator-name = "vdd_mem";
312 regulator-min-microvolt = <800000>;
313 regulator-max-microvolt = <1400000>;
314 regulator-always-on;
315 regulator-boot-on;
316 };
317
318 buck6_reg: BUCK6 {
319 regulator-name = "vdd_kfc";
320 regulator-min-microvolt = <800000>;
321 regulator-max-microvolt = <1500000>;
322 regulator-always-on;
323 regulator-boot-on;
324 };
325
326 buck7_reg: BUCK7 {
327 regulator-name = "vdd_1.0v_ldo";
328 regulator-min-microvolt = <800000>;
329 regulator-max-microvolt = <1500000>;
330 regulator-always-on;
331 regulator-boot-on;
332 };
333
334 buck8_reg: BUCK8 {
335 regulator-name = "vdd_1.8v_ldo";
336 regulator-min-microvolt = <800000>;
337 regulator-max-microvolt = <1500000>;
338 regulator-always-on;
339 regulator-boot-on;
340 };
341
342 buck9_reg: BUCK9 {
343 regulator-name = "vdd_2.8v_ldo";
344 regulator-min-microvolt = <3000000>;
345 regulator-max-microvolt = <3750000>;
346 regulator-always-on;
347 regulator-boot-on;
348 };
349
350 buck10_reg: BUCK10 {
351 regulator-name = "vdd_vmem";
352 regulator-min-microvolt = <2850000>;
353 regulator-max-microvolt = <2850000>;
354 regulator-always-on;
355 regulator-boot-on;
356 };
357 };
358 };
359};
360
361&mmc_2 {
362 status = "okay";
363 card-detect-delay = <200>;
364 samsung,dw-mshc-ciu-div = <3>;
365 samsung,dw-mshc-sdr-timing = <0 4>;
366 samsung,dw-mshc-ddr-timing = <0 2>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
369 bus-width = <4>;
370 cap-sd-highspeed;
371 vmmc-supply = <&ldo19_reg>;
372 vqmmc-supply = <&ldo13_reg>;
373};
374
375&nocp_mem0_0 {
376 status = "okay";
377};
378
379&nocp_mem0_1 {
380 status = "okay";
381};
382
383&nocp_mem1_0 {
384 status = "okay";
385};
386
387&nocp_mem1_1 {
388 status = "okay";
389};
390
391&pinctrl_0 {
392 s2mps11_irq: s2mps11-irq {
393 samsung,pins = "gpx0-4";
394 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
395 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
396 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
397 };
398};
399
400&tmu_cpu0 {
401 vtmu-supply = <&ldo7_reg>;
402};
403
404&tmu_cpu1 {
405 vtmu-supply = <&ldo7_reg>;
406};
407
408&tmu_cpu2 {
409 vtmu-supply = <&ldo7_reg>;
410};
411
412&tmu_cpu3 {
413 vtmu-supply = <&ldo7_reg>;
414};
415
416&tmu_gpu {
417 vtmu-supply = <&ldo7_reg>;
418};
419
420&rtc {
421 status = "okay";
422 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
423 clock-names = "rtc", "rtc_src";
424};
425
426&usbdrd_dwc3_0 {
427 dr_mode = "host";
428};
429
430/* usbdrd_dwc3_1 mode customized in each board */
431
432&usbdrd3_0 {
433 vdd33-supply = <&ldo9_reg>;
434 vdd10-supply = <&ldo11_reg>;
435};
436
437&usbdrd3_1 {
438 vdd33-supply = <&ldo9_reg>;
439 vdd10-supply = <&ldo11_reg>;
440};