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1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/bus/ti-sysc.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/pinctrl/am33xx.h>
14#include <dt-bindings/clock/am3.h>
15
16/ {
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21 chosen { };
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &uart2;
30 serial3 = &uart3;
31 serial4 = &uart4;
32 serial5 = &uart5;
33 d-can0 = &dcan0;
34 d-can1 = &dcan1;
35 usb0 = &usb0;
36 usb1 = &usb1;
37 phy0 = &usb0_phy;
38 phy1 = &usb1_phy;
39 ethernet0 = &cpsw_emac0;
40 ethernet1 = &cpsw_emac1;
41 spi0 = &spi0;
42 spi1 = &spi1;
43 mmc0 = &mmc1;
44 mmc1 = &mmc2;
45 mmc2 = &mmc3;
46 };
47
48 cpus {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 cpu@0 {
52 compatible = "arm,cortex-a8";
53 enable-method = "ti,am3352";
54 device_type = "cpu";
55 reg = <0>;
56
57 operating-points-v2 = <&cpu0_opp_table>;
58
59 clocks = <&dpll_mpu_ck>;
60 clock-names = "cpu";
61
62 clock-latency = <300000>; /* From omap-cpufreq driver */
63 cpu-idle-states = <&mpu_gate>;
64 };
65
66 idle-states {
67 mpu_gate: mpu_gate {
68 compatible = "arm,idle-state";
69 entry-latency-us = <40>;
70 exit-latency-us = <90>;
71 min-residency-us = <300>;
72 ti,idle-wkup-m3;
73 };
74 };
75 };
76
77 cpu0_opp_table: opp-table {
78 compatible = "operating-points-v2-ti-cpu";
79 syscon = <&scm_conf>;
80
81 /*
82 * The three following nodes are marked with opp-suspend
83 * because the can not be enabled simultaneously on a
84 * single SoC.
85 */
86 opp50-300000000 {
87 opp-hz = /bits/ 64 <300000000>;
88 opp-microvolt = <950000 931000 969000>;
89 opp-supported-hw = <0x06 0x0010>;
90 opp-suspend;
91 };
92
93 opp100-275000000 {
94 opp-hz = /bits/ 64 <275000000>;
95 opp-microvolt = <1100000 1078000 1122000>;
96 opp-supported-hw = <0x01 0x00FF>;
97 opp-suspend;
98 };
99
100 opp100-300000000 {
101 opp-hz = /bits/ 64 <300000000>;
102 opp-microvolt = <1100000 1078000 1122000>;
103 opp-supported-hw = <0x06 0x0020>;
104 opp-suspend;
105 };
106
107 opp100-500000000 {
108 opp-hz = /bits/ 64 <500000000>;
109 opp-microvolt = <1100000 1078000 1122000>;
110 opp-supported-hw = <0x01 0xFFFF>;
111 };
112
113 opp100-600000000 {
114 opp-hz = /bits/ 64 <600000000>;
115 opp-microvolt = <1100000 1078000 1122000>;
116 opp-supported-hw = <0x06 0x0040>;
117 };
118
119 opp120-600000000 {
120 opp-hz = /bits/ 64 <600000000>;
121 opp-microvolt = <1200000 1176000 1224000>;
122 opp-supported-hw = <0x01 0xFFFF>;
123 };
124
125 opp120-720000000 {
126 opp-hz = /bits/ 64 <720000000>;
127 opp-microvolt = <1200000 1176000 1224000>;
128 opp-supported-hw = <0x06 0x0080>;
129 };
130
131 oppturbo-720000000 {
132 opp-hz = /bits/ 64 <720000000>;
133 opp-microvolt = <1260000 1234800 1285200>;
134 opp-supported-hw = <0x01 0xFFFF>;
135 };
136
137 oppturbo-800000000 {
138 opp-hz = /bits/ 64 <800000000>;
139 opp-microvolt = <1260000 1234800 1285200>;
140 opp-supported-hw = <0x06 0x0100>;
141 };
142
143 oppnitro-1000000000 {
144 opp-hz = /bits/ 64 <1000000000>;
145 opp-microvolt = <1325000 1298500 1351500>;
146 opp-supported-hw = <0x04 0x0200>;
147 };
148 };
149
150 target-module@4b000000 {
151 compatible = "ti,sysc-omap4-simple", "ti,sysc";
152 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
153 clock-names = "fck";
154 ti,no-idle;
155 #address-cells = <1>;
156 #size-cells = <1>;
157 ranges = <0x0 0x4b000000 0x1000000>;
158
159 target-module@140000 {
160 compatible = "ti,sysc-omap4-simple", "ti,sysc";
161 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
162 clock-names = "fck";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges = <0x0 0x140000 0xec0000>;
166
167 pmu@0 {
168 compatible = "arm,cortex-a8-pmu";
169 interrupts = <3>;
170 };
171 };
172 };
173
174 /*
175 * The soc node represents the soc top level view. It is used for IPs
176 * that are not memory mapped in the MPU view or for the MPU itself.
177 */
178 soc {
179 compatible = "ti,omap-infra";
180 };
181
182 /*
183 * XXX: Use a flat representation of the AM33XX interconnect.
184 * The real AM33XX interconnect network is quite complex. Since
185 * it will not bring real advantage to represent that in DT
186 * for the moment, just use a fake OCP bus entry to represent
187 * the whole bus hierarchy.
188 */
189 ocp: ocp {
190 compatible = "simple-pm-bus";
191 power-domains = <&prm_per>;
192 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
193 clock-names = "fck";
194 #address-cells = <1>;
195 #size-cells = <1>;
196 ranges;
197
198 l4_wkup: interconnect@44c00000 {
199 };
200 l4_per: interconnect@48000000 {
201 };
202 l4_fw: interconnect@47c00000 {
203 };
204 l4_fast: interconnect@4a000000 {
205 };
206 l4_mpuss: interconnect@4b140000 {
207 };
208
209 intc: interrupt-controller@48200000 {
210 compatible = "ti,am33xx-intc";
211 interrupt-controller;
212 #interrupt-cells = <1>;
213 reg = <0x48200000 0x1000>;
214 };
215
216 target-module@49000000 {
217 compatible = "ti,sysc-omap4", "ti,sysc";
218 reg = <0x49000000 0x4>;
219 reg-names = "rev";
220 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
221 clock-names = "fck";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0x0 0x49000000 0x10000>;
225
226 edma: dma@0 {
227 compatible = "ti,edma3-tpcc";
228 reg = <0 0x10000>;
229 reg-names = "edma3_cc";
230 interrupts = <12 13 14>;
231 interrupt-names = "edma3_ccint", "edma3_mperr",
232 "edma3_ccerrint";
233 dma-requests = <64>;
234 #dma-cells = <2>;
235
236 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
237 <&edma_tptc2 0>;
238
239 ti,edma-memcpy-channels = <20 21>;
240 };
241 };
242
243 target-module@49800000 {
244 compatible = "ti,sysc-omap4", "ti,sysc";
245 reg = <0x49800000 0x4>,
246 <0x49800010 0x4>;
247 reg-names = "rev", "sysc";
248 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
249 ti,sysc-midle = <SYSC_IDLE_FORCE>;
250 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
251 <SYSC_IDLE_SMART>;
252 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
253 clock-names = "fck";
254 #address-cells = <1>;
255 #size-cells = <1>;
256 ranges = <0x0 0x49800000 0x100000>;
257
258 edma_tptc0: dma@0 {
259 compatible = "ti,edma3-tptc";
260 reg = <0 0x100000>;
261 interrupts = <112>;
262 interrupt-names = "edma3_tcerrint";
263 };
264 };
265
266 target-module@49900000 {
267 compatible = "ti,sysc-omap4", "ti,sysc";
268 reg = <0x49900000 0x4>,
269 <0x49900010 0x4>;
270 reg-names = "rev", "sysc";
271 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
272 ti,sysc-midle = <SYSC_IDLE_FORCE>;
273 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
274 <SYSC_IDLE_SMART>;
275 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
276 clock-names = "fck";
277 #address-cells = <1>;
278 #size-cells = <1>;
279 ranges = <0x0 0x49900000 0x100000>;
280
281 edma_tptc1: dma@0 {
282 compatible = "ti,edma3-tptc";
283 reg = <0 0x100000>;
284 interrupts = <113>;
285 interrupt-names = "edma3_tcerrint";
286 };
287 };
288
289 target-module@49a00000 {
290 compatible = "ti,sysc-omap4", "ti,sysc";
291 reg = <0x49a00000 0x4>,
292 <0x49a00010 0x4>;
293 reg-names = "rev", "sysc";
294 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
295 ti,sysc-midle = <SYSC_IDLE_FORCE>;
296 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
297 <SYSC_IDLE_SMART>;
298 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
299 clock-names = "fck";
300 #address-cells = <1>;
301 #size-cells = <1>;
302 ranges = <0x0 0x49a00000 0x100000>;
303
304 edma_tptc2: dma@0 {
305 compatible = "ti,edma3-tptc";
306 reg = <0 0x100000>;
307 interrupts = <114>;
308 interrupt-names = "edma3_tcerrint";
309 };
310 };
311
312 target-module@47810000 {
313 compatible = "ti,sysc-omap2", "ti,sysc";
314 reg = <0x478102fc 0x4>,
315 <0x47810110 0x4>,
316 <0x47810114 0x4>;
317 reg-names = "rev", "sysc", "syss";
318 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
319 SYSC_OMAP2_ENAWAKEUP |
320 SYSC_OMAP2_SOFTRESET |
321 SYSC_OMAP2_AUTOIDLE)>;
322 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
323 <SYSC_IDLE_NO>,
324 <SYSC_IDLE_SMART>;
325 ti,syss-mask = <1>;
326 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
327 clock-names = "fck";
328 #address-cells = <1>;
329 #size-cells = <1>;
330 ranges = <0x0 0x47810000 0x1000>;
331
332 mmc3: mmc@0 {
333 compatible = "ti,am335-sdhci";
334 ti,needs-special-reset;
335 interrupts = <29>;
336 reg = <0x0 0x1000>;
337 status = "disabled";
338 };
339 };
340
341 usb: target-module@47400000 {
342 compatible = "ti,sysc-omap4", "ti,sysc";
343 reg = <0x47400000 0x4>,
344 <0x47400010 0x4>;
345 reg-names = "rev", "sysc";
346 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
347 SYSC_OMAP4_SOFTRESET)>;
348 ti,sysc-midle = <SYSC_IDLE_FORCE>,
349 <SYSC_IDLE_NO>,
350 <SYSC_IDLE_SMART>;
351 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
352 <SYSC_IDLE_NO>,
353 <SYSC_IDLE_SMART>,
354 <SYSC_IDLE_SMART_WKUP>;
355 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
356 clock-names = "fck";
357 #address-cells = <1>;
358 #size-cells = <1>;
359 ranges = <0x0 0x47400000 0x8000>;
360
361 usb0_phy: usb-phy@1300 {
362 compatible = "ti,am335x-usb-phy";
363 reg = <0x1300 0x100>;
364 reg-names = "phy";
365 ti,ctrl_mod = <&usb_ctrl_mod>;
366 #phy-cells = <0>;
367 };
368
369 usb0: usb@1400 {
370 compatible = "ti,musb-am33xx";
371 reg = <0x1400 0x400>,
372 <0x1000 0x200>;
373 reg-names = "mc", "control";
374
375 interrupts = <18>;
376 interrupt-names = "mc";
377 dr_mode = "otg";
378 mentor,multipoint = <1>;
379 mentor,num-eps = <16>;
380 mentor,ram-bits = <12>;
381 mentor,power = <500>;
382 phys = <&usb0_phy>;
383
384 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
385 &cppi41dma 2 0 &cppi41dma 3 0
386 &cppi41dma 4 0 &cppi41dma 5 0
387 &cppi41dma 6 0 &cppi41dma 7 0
388 &cppi41dma 8 0 &cppi41dma 9 0
389 &cppi41dma 10 0 &cppi41dma 11 0
390 &cppi41dma 12 0 &cppi41dma 13 0
391 &cppi41dma 14 0 &cppi41dma 0 1
392 &cppi41dma 1 1 &cppi41dma 2 1
393 &cppi41dma 3 1 &cppi41dma 4 1
394 &cppi41dma 5 1 &cppi41dma 6 1
395 &cppi41dma 7 1 &cppi41dma 8 1
396 &cppi41dma 9 1 &cppi41dma 10 1
397 &cppi41dma 11 1 &cppi41dma 12 1
398 &cppi41dma 13 1 &cppi41dma 14 1>;
399 dma-names =
400 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
401 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
402 "rx14", "rx15",
403 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
404 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
405 "tx14", "tx15";
406 };
407
408 usb1_phy: usb-phy@1b00 {
409 compatible = "ti,am335x-usb-phy";
410 reg = <0x1b00 0x100>;
411 reg-names = "phy";
412 ti,ctrl_mod = <&usb_ctrl_mod>;
413 #phy-cells = <0>;
414 };
415
416 usb1: usb@1800 {
417 compatible = "ti,musb-am33xx";
418 reg = <0x1c00 0x400>,
419 <0x1800 0x200>;
420 reg-names = "mc", "control";
421 interrupts = <19>;
422 interrupt-names = "mc";
423 dr_mode = "otg";
424 mentor,multipoint = <1>;
425 mentor,num-eps = <16>;
426 mentor,ram-bits = <12>;
427 mentor,power = <500>;
428 phys = <&usb1_phy>;
429
430 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
431 &cppi41dma 17 0 &cppi41dma 18 0
432 &cppi41dma 19 0 &cppi41dma 20 0
433 &cppi41dma 21 0 &cppi41dma 22 0
434 &cppi41dma 23 0 &cppi41dma 24 0
435 &cppi41dma 25 0 &cppi41dma 26 0
436 &cppi41dma 27 0 &cppi41dma 28 0
437 &cppi41dma 29 0 &cppi41dma 15 1
438 &cppi41dma 16 1 &cppi41dma 17 1
439 &cppi41dma 18 1 &cppi41dma 19 1
440 &cppi41dma 20 1 &cppi41dma 21 1
441 &cppi41dma 22 1 &cppi41dma 23 1
442 &cppi41dma 24 1 &cppi41dma 25 1
443 &cppi41dma 26 1 &cppi41dma 27 1
444 &cppi41dma 28 1 &cppi41dma 29 1>;
445 dma-names =
446 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
447 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
448 "rx14", "rx15",
449 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
450 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
451 "tx14", "tx15";
452 };
453
454 cppi41dma: dma-controller@2000 {
455 compatible = "ti,am3359-cppi41";
456 reg = <0x0000 0x1000>,
457 <0x2000 0x1000>,
458 <0x3000 0x1000>,
459 <0x4000 0x4000>;
460 reg-names = "glue", "controller", "scheduler", "queuemgr";
461 interrupts = <17>;
462 interrupt-names = "glue";
463 #dma-cells = <2>;
464 #dma-channels = <30>;
465 #dma-requests = <256>;
466 };
467 };
468
469 target-module@40300000 {
470 compatible = "ti,sysc-omap4-simple", "ti,sysc";
471 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
472 clock-names = "fck";
473 ti,no-idle;
474 #address-cells = <1>;
475 #size-cells = <1>;
476 ranges = <0 0x40300000 0x10000>;
477
478 ocmcram: sram@0 {
479 compatible = "mmio-sram";
480 reg = <0 0x10000>; /* 64k */
481 ranges = <0 0 0x10000>;
482 #address-cells = <1>;
483 #size-cells = <1>;
484
485 pm_sram_code: pm-code-sram@0 {
486 compatible = "ti,sram";
487 reg = <0x0 0x1000>;
488 protect-exec;
489 };
490
491 pm_sram_data: pm-data-sram@1000 {
492 compatible = "ti,sram";
493 reg = <0x1000 0x1000>;
494 pool;
495 };
496 };
497 };
498
499 target-module@4c000000 {
500 compatible = "ti,sysc-omap4-simple", "ti,sysc";
501 reg = <0x4c000000 0x4>;
502 reg-names = "rev";
503 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
504 clock-names = "fck";
505 ti,no-idle;
506 #address-cells = <1>;
507 #size-cells = <1>;
508 ranges = <0x0 0x4c000000 0x1000000>;
509
510 emif: emif@0 {
511 compatible = "ti,emif-am3352";
512 reg = <0 0x1000000>;
513 interrupts = <101>;
514 sram = <&pm_sram_code
515 &pm_sram_data>;
516 };
517 };
518
519 target-module@50000000 {
520 compatible = "ti,sysc-omap2", "ti,sysc";
521 reg = <0x50000000 4>,
522 <0x50000010 4>,
523 <0x50000014 4>;
524 reg-names = "rev", "sysc", "syss";
525 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
526 <SYSC_IDLE_NO>,
527 <SYSC_IDLE_SMART>;
528 ti,syss-mask = <1>;
529 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
530 clock-names = "fck";
531 #address-cells = <1>;
532 #size-cells = <1>;
533 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
534 <0x00000000 0x00000000 0x40000000>; /* data */
535
536 gpmc: gpmc@50000000 {
537 compatible = "ti,am3352-gpmc";
538 reg = <0x50000000 0x2000>;
539 interrupts = <100>;
540 dmas = <&edma 52 0>;
541 dma-names = "rxtx";
542 gpmc,num-cs = <7>;
543 gpmc,num-waitpins = <2>;
544 #address-cells = <2>;
545 #size-cells = <1>;
546 interrupt-controller;
547 #interrupt-cells = <2>;
548 gpio-controller;
549 #gpio-cells = <2>;
550 status = "disabled";
551 };
552 };
553
554 sham_target: target-module@53100000 {
555 compatible = "ti,sysc-omap3-sham", "ti,sysc";
556 reg = <0x53100100 0x4>,
557 <0x53100110 0x4>,
558 <0x53100114 0x4>;
559 reg-names = "rev", "sysc", "syss";
560 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
561 SYSC_OMAP2_AUTOIDLE)>;
562 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
563 <SYSC_IDLE_NO>,
564 <SYSC_IDLE_SMART>;
565 ti,syss-mask = <1>;
566 /* Domains (P, C): per_pwrdm, l3_clkdm */
567 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
568 clock-names = "fck";
569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges = <0x0 0x53100000 0x1000>;
572
573 sham: sham@0 {
574 compatible = "ti,omap4-sham";
575 reg = <0 0x200>;
576 interrupts = <109>;
577 dmas = <&edma 36 0>;
578 dma-names = "rx";
579 };
580 };
581
582 aes_target: target-module@53500000 {
583 compatible = "ti,sysc-omap2", "ti,sysc";
584 reg = <0x53500080 0x4>,
585 <0x53500084 0x4>,
586 <0x53500088 0x4>;
587 reg-names = "rev", "sysc", "syss";
588 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
589 SYSC_OMAP2_AUTOIDLE)>;
590 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
591 <SYSC_IDLE_NO>,
592 <SYSC_IDLE_SMART>,
593 <SYSC_IDLE_SMART_WKUP>;
594 ti,syss-mask = <1>;
595 /* Domains (P, C): per_pwrdm, l3_clkdm */
596 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
597 clock-names = "fck";
598 #address-cells = <1>;
599 #size-cells = <1>;
600 ranges = <0x0 0x53500000 0x1000>;
601
602 aes: aes@0 {
603 compatible = "ti,omap4-aes";
604 reg = <0 0xa0>;
605 interrupts = <103>;
606 dmas = <&edma 6 0>,
607 <&edma 5 0>;
608 dma-names = "tx", "rx";
609 };
610 };
611
612 target-module@56000000 {
613 compatible = "ti,sysc-omap4", "ti,sysc";
614 reg = <0x5600fe00 0x4>,
615 <0x5600fe10 0x4>;
616 reg-names = "rev", "sysc";
617 ti,sysc-midle = <SYSC_IDLE_FORCE>,
618 <SYSC_IDLE_NO>,
619 <SYSC_IDLE_SMART>;
620 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
621 <SYSC_IDLE_NO>,
622 <SYSC_IDLE_SMART>;
623 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
624 clock-names = "fck";
625 power-domains = <&prm_gfx>;
626 resets = <&prm_gfx 0>;
627 reset-names = "rstctrl";
628 #address-cells = <1>;
629 #size-cells = <1>;
630 ranges = <0 0x56000000 0x1000000>;
631
632 /*
633 * Closed source PowerVR driver, no child device
634 * binding or driver in mainline
635 */
636 };
637 };
638};
639
640#include "am33xx-l4.dtsi"
641#include "am33xx-clocks.dtsi"
642
643&prcm {
644 prm_per: prm@c00 {
645 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
646 reg = <0xc00 0x100>;
647 #reset-cells = <1>;
648 #power-domain-cells = <0>;
649 };
650
651 prm_wkup: prm@d00 {
652 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
653 reg = <0xd00 0x100>;
654 #reset-cells = <1>;
655 #power-domain-cells = <0>;
656 };
657
658 prm_mpu: prm@e00 {
659 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
660 reg = <0xe00 0x100>;
661 #power-domain-cells = <0>;
662 };
663
664 prm_device: prm@f00 {
665 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
666 reg = <0xf00 0x100>;
667 #reset-cells = <1>;
668 };
669
670 prm_rtc: prm@1000 {
671 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
672 reg = <0x1000 0x100>;
673 #power-domain-cells = <0>;
674 };
675
676 prm_gfx: prm@1100 {
677 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
678 reg = <0x1100 0x100>;
679 #power-domain-cells = <0>;
680 #reset-cells = <1>;
681 };
682
683 prm_cefuse: prm@1200 {
684 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
685 reg = <0x1200 0x100>;
686 #power-domain-cells = <0>;
687 };
688};
689
690/* Preferred always-on timer for clocksource */
691&timer1_target {
692 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
693 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
694 clock-names = "fck", "ick";
695 ti,no-reset-on-init;
696 ti,no-idle;
697 timer@0 {
698 assigned-clocks = <&timer1_fck>;
699 assigned-clock-parents = <&sys_clkin_ck>;
700 };
701};
702
703/* Preferred timer for clockevent */
704&timer2_target {
705 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
706 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
707 clock-names = "fck", "ick";
708 ti,no-reset-on-init;
709 ti,no-idle;
710 timer@0 {
711 assigned-clocks = <&timer2_fck>;
712 assigned-clock-parents = <&sys_clkin_ck>;
713 };
714};
1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/am33xx.h>
13#include <dt-bindings/clock/am3.h>
14
15/ {
16 compatible = "ti,am33xx";
17 interrupt-parent = <&intc>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 serial0 = &uart0;
27 serial1 = &uart1;
28 serial2 = &uart2;
29 serial3 = &uart3;
30 serial4 = &uart4;
31 serial5 = &uart5;
32 d_can0 = &dcan0;
33 d_can1 = &dcan1;
34 usb0 = &usb0;
35 usb1 = &usb1;
36 phy0 = &usb0_phy;
37 phy1 = &usb1_phy;
38 ethernet0 = &cpsw_emac0;
39 ethernet1 = &cpsw_emac1;
40 spi0 = &spi0;
41 spi1 = &spi1;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 cpu@0 {
48 compatible = "arm,cortex-a8";
49 device_type = "cpu";
50 reg = <0>;
51
52 operating-points-v2 = <&cpu0_opp_table>;
53
54 clocks = <&dpll_mpu_ck>;
55 clock-names = "cpu";
56
57 clock-latency = <300000>; /* From omap-cpufreq driver */
58 };
59 };
60
61 cpu0_opp_table: opp-table {
62 compatible = "operating-points-v2-ti-cpu";
63 syscon = <&scm_conf>;
64
65 /*
66 * The three following nodes are marked with opp-suspend
67 * because the can not be enabled simultaneously on a
68 * single SoC.
69 */
70 opp50-300000000 {
71 opp-hz = /bits/ 64 <300000000>;
72 opp-microvolt = <950000 931000 969000>;
73 opp-supported-hw = <0x06 0x0010>;
74 opp-suspend;
75 };
76
77 opp100-275000000 {
78 opp-hz = /bits/ 64 <275000000>;
79 opp-microvolt = <1100000 1078000 1122000>;
80 opp-supported-hw = <0x01 0x00FF>;
81 opp-suspend;
82 };
83
84 opp100-300000000 {
85 opp-hz = /bits/ 64 <300000000>;
86 opp-microvolt = <1100000 1078000 1122000>;
87 opp-supported-hw = <0x06 0x0020>;
88 opp-suspend;
89 };
90
91 opp100-500000000 {
92 opp-hz = /bits/ 64 <500000000>;
93 opp-microvolt = <1100000 1078000 1122000>;
94 opp-supported-hw = <0x01 0xFFFF>;
95 };
96
97 opp100-600000000 {
98 opp-hz = /bits/ 64 <600000000>;
99 opp-microvolt = <1100000 1078000 1122000>;
100 opp-supported-hw = <0x06 0x0040>;
101 };
102
103 opp120-600000000 {
104 opp-hz = /bits/ 64 <600000000>;
105 opp-microvolt = <1200000 1176000 1224000>;
106 opp-supported-hw = <0x01 0xFFFF>;
107 };
108
109 opp120-720000000 {
110 opp-hz = /bits/ 64 <720000000>;
111 opp-microvolt = <1200000 1176000 1224000>;
112 opp-supported-hw = <0x06 0x0080>;
113 };
114
115 oppturbo-720000000 {
116 opp-hz = /bits/ 64 <720000000>;
117 opp-microvolt = <1260000 1234800 1285200>;
118 opp-supported-hw = <0x01 0xFFFF>;
119 };
120
121 oppturbo-800000000 {
122 opp-hz = /bits/ 64 <800000000>;
123 opp-microvolt = <1260000 1234800 1285200>;
124 opp-supported-hw = <0x06 0x0100>;
125 };
126
127 oppnitro-1000000000 {
128 opp-hz = /bits/ 64 <1000000000>;
129 opp-microvolt = <1325000 1298500 1351500>;
130 opp-supported-hw = <0x04 0x0200>;
131 };
132 };
133
134 pmu@4b000000 {
135 compatible = "arm,cortex-a8-pmu";
136 interrupts = <3>;
137 reg = <0x4b000000 0x1000000>;
138 ti,hwmods = "debugss";
139 };
140
141 /*
142 * The soc node represents the soc top level view. It is used for IPs
143 * that are not memory mapped in the MPU view or for the MPU itself.
144 */
145 soc {
146 compatible = "ti,omap-infra";
147 mpu {
148 compatible = "ti,omap3-mpu";
149 ti,hwmods = "mpu";
150 pm-sram = <&pm_sram_code
151 &pm_sram_data>;
152 };
153 };
154
155 /*
156 * XXX: Use a flat representation of the AM33XX interconnect.
157 * The real AM33XX interconnect network is quite complex. Since
158 * it will not bring real advantage to represent that in DT
159 * for the moment, just use a fake OCP bus entry to represent
160 * the whole bus hierarchy.
161 */
162 ocp {
163 compatible = "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges;
167 ti,hwmods = "l3_main";
168
169 l4_wkup: l4_wkup@44c00000 {
170 compatible = "ti,am3-l4-wkup", "simple-bus";
171 #address-cells = <1>;
172 #size-cells = <1>;
173 ranges = <0 0x44c00000 0x280000>;
174
175 wkup_m3: wkup_m3@100000 {
176 compatible = "ti,am3352-wkup-m3";
177 reg = <0x100000 0x4000>,
178 <0x180000 0x2000>;
179 reg-names = "umem", "dmem";
180 ti,hwmods = "wkup_m3";
181 ti,pm-firmware = "am335x-pm-firmware.elf";
182 };
183
184 prcm: prcm@200000 {
185 compatible = "ti,am3-prcm", "simple-bus";
186 reg = <0x200000 0x4000>;
187 #address-cells = <1>;
188 #size-cells = <1>;
189 ranges = <0 0x200000 0x4000>;
190
191 prcm_clocks: clocks {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 };
195
196 prcm_clockdomains: clockdomains {
197 };
198 };
199
200 scm: scm@210000 {
201 compatible = "ti,am3-scm", "simple-bus";
202 reg = <0x210000 0x2000>;
203 #address-cells = <1>;
204 #size-cells = <1>;
205 #pinctrl-cells = <1>;
206 ranges = <0 0x210000 0x2000>;
207
208 am33xx_pinmux: pinmux@800 {
209 compatible = "pinctrl-single";
210 reg = <0x800 0x238>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 #pinctrl-cells = <1>;
214 pinctrl-single,register-width = <32>;
215 pinctrl-single,function-mask = <0x7f>;
216 };
217
218 scm_conf: scm_conf@0 {
219 compatible = "syscon", "simple-bus";
220 reg = <0x0 0x800>;
221 #address-cells = <1>;
222 #size-cells = <1>;
223 ranges = <0 0 0x800>;
224
225 scm_clocks: clocks {
226 #address-cells = <1>;
227 #size-cells = <0>;
228 };
229 };
230
231 wkup_m3_ipc: wkup_m3_ipc@1324 {
232 compatible = "ti,am3352-wkup-m3-ipc";
233 reg = <0x1324 0x24>;
234 interrupts = <78>;
235 ti,rproc = <&wkup_m3>;
236 mboxes = <&mailbox &mbox_wkupm3>;
237 };
238
239 edma_xbar: dma-router@f90 {
240 compatible = "ti,am335x-edma-crossbar";
241 reg = <0xf90 0x40>;
242 #dma-cells = <3>;
243 dma-requests = <32>;
244 dma-masters = <&edma>;
245 };
246
247 scm_clockdomains: clockdomains {
248 };
249 };
250 };
251
252 intc: interrupt-controller@48200000 {
253 compatible = "ti,am33xx-intc";
254 interrupt-controller;
255 #interrupt-cells = <1>;
256 reg = <0x48200000 0x1000>;
257 };
258
259 edma: edma@49000000 {
260 compatible = "ti,edma3-tpcc";
261 ti,hwmods = "tpcc";
262 reg = <0x49000000 0x10000>;
263 reg-names = "edma3_cc";
264 interrupts = <12 13 14>;
265 interrupt-names = "edma3_ccint", "edma3_mperr",
266 "edma3_ccerrint";
267 dma-requests = <64>;
268 #dma-cells = <2>;
269
270 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
271 <&edma_tptc2 0>;
272
273 ti,edma-memcpy-channels = <20 21>;
274 };
275
276 edma_tptc0: tptc@49800000 {
277 compatible = "ti,edma3-tptc";
278 ti,hwmods = "tptc0";
279 reg = <0x49800000 0x100000>;
280 interrupts = <112>;
281 interrupt-names = "edma3_tcerrint";
282 };
283
284 edma_tptc1: tptc@49900000 {
285 compatible = "ti,edma3-tptc";
286 ti,hwmods = "tptc1";
287 reg = <0x49900000 0x100000>;
288 interrupts = <113>;
289 interrupt-names = "edma3_tcerrint";
290 };
291
292 edma_tptc2: tptc@49a00000 {
293 compatible = "ti,edma3-tptc";
294 ti,hwmods = "tptc2";
295 reg = <0x49a00000 0x100000>;
296 interrupts = <114>;
297 interrupt-names = "edma3_tcerrint";
298 };
299
300 gpio0: gpio@44e07000 {
301 compatible = "ti,omap4-gpio";
302 ti,hwmods = "gpio1";
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 reg = <0x44e07000 0x1000>;
308 interrupts = <96>;
309 };
310
311 gpio1: gpio@4804c000 {
312 compatible = "ti,omap4-gpio";
313 ti,hwmods = "gpio2";
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
318 reg = <0x4804c000 0x1000>;
319 interrupts = <98>;
320 };
321
322 gpio2: gpio@481ac000 {
323 compatible = "ti,omap4-gpio";
324 ti,hwmods = "gpio3";
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 reg = <0x481ac000 0x1000>;
330 interrupts = <32>;
331 };
332
333 gpio3: gpio@481ae000 {
334 compatible = "ti,omap4-gpio";
335 ti,hwmods = "gpio4";
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 reg = <0x481ae000 0x1000>;
341 interrupts = <62>;
342 };
343
344 uart0: serial@44e09000 {
345 compatible = "ti,am3352-uart", "ti,omap3-uart";
346 ti,hwmods = "uart1";
347 clock-frequency = <48000000>;
348 reg = <0x44e09000 0x2000>;
349 interrupts = <72>;
350 status = "disabled";
351 dmas = <&edma 26 0>, <&edma 27 0>;
352 dma-names = "tx", "rx";
353 };
354
355 uart1: serial@48022000 {
356 compatible = "ti,am3352-uart", "ti,omap3-uart";
357 ti,hwmods = "uart2";
358 clock-frequency = <48000000>;
359 reg = <0x48022000 0x2000>;
360 interrupts = <73>;
361 status = "disabled";
362 dmas = <&edma 28 0>, <&edma 29 0>;
363 dma-names = "tx", "rx";
364 };
365
366 uart2: serial@48024000 {
367 compatible = "ti,am3352-uart", "ti,omap3-uart";
368 ti,hwmods = "uart3";
369 clock-frequency = <48000000>;
370 reg = <0x48024000 0x2000>;
371 interrupts = <74>;
372 status = "disabled";
373 dmas = <&edma 30 0>, <&edma 31 0>;
374 dma-names = "tx", "rx";
375 };
376
377 uart3: serial@481a6000 {
378 compatible = "ti,am3352-uart", "ti,omap3-uart";
379 ti,hwmods = "uart4";
380 clock-frequency = <48000000>;
381 reg = <0x481a6000 0x2000>;
382 interrupts = <44>;
383 status = "disabled";
384 };
385
386 uart4: serial@481a8000 {
387 compatible = "ti,am3352-uart", "ti,omap3-uart";
388 ti,hwmods = "uart5";
389 clock-frequency = <48000000>;
390 reg = <0x481a8000 0x2000>;
391 interrupts = <45>;
392 status = "disabled";
393 };
394
395 uart5: serial@481aa000 {
396 compatible = "ti,am3352-uart", "ti,omap3-uart";
397 ti,hwmods = "uart6";
398 clock-frequency = <48000000>;
399 reg = <0x481aa000 0x2000>;
400 interrupts = <46>;
401 status = "disabled";
402 };
403
404 i2c0: i2c@44e0b000 {
405 compatible = "ti,omap4-i2c";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 ti,hwmods = "i2c1";
409 reg = <0x44e0b000 0x1000>;
410 interrupts = <70>;
411 status = "disabled";
412 };
413
414 i2c1: i2c@4802a000 {
415 compatible = "ti,omap4-i2c";
416 #address-cells = <1>;
417 #size-cells = <0>;
418 ti,hwmods = "i2c2";
419 reg = <0x4802a000 0x1000>;
420 interrupts = <71>;
421 status = "disabled";
422 };
423
424 i2c2: i2c@4819c000 {
425 compatible = "ti,omap4-i2c";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 ti,hwmods = "i2c3";
429 reg = <0x4819c000 0x1000>;
430 interrupts = <30>;
431 status = "disabled";
432 };
433
434 mmc1: mmc@48060000 {
435 compatible = "ti,omap4-hsmmc";
436 ti,hwmods = "mmc1";
437 ti,dual-volt;
438 ti,needs-special-reset;
439 ti,needs-special-hs-handling;
440 dmas = <&edma_xbar 24 0 0
441 &edma_xbar 25 0 0>;
442 dma-names = "tx", "rx";
443 interrupts = <64>;
444 reg = <0x48060000 0x1000>;
445 status = "disabled";
446 };
447
448 mmc2: mmc@481d8000 {
449 compatible = "ti,omap4-hsmmc";
450 ti,hwmods = "mmc2";
451 ti,needs-special-reset;
452 dmas = <&edma 2 0
453 &edma 3 0>;
454 dma-names = "tx", "rx";
455 interrupts = <28>;
456 reg = <0x481d8000 0x1000>;
457 status = "disabled";
458 };
459
460 mmc3: mmc@47810000 {
461 compatible = "ti,omap4-hsmmc";
462 ti,hwmods = "mmc3";
463 ti,needs-special-reset;
464 interrupts = <29>;
465 reg = <0x47810000 0x1000>;
466 status = "disabled";
467 };
468
469 hwspinlock: spinlock@480ca000 {
470 compatible = "ti,omap4-hwspinlock";
471 reg = <0x480ca000 0x1000>;
472 ti,hwmods = "spinlock";
473 #hwlock-cells = <1>;
474 };
475
476 wdt2: wdt@44e35000 {
477 compatible = "ti,omap3-wdt";
478 ti,hwmods = "wd_timer2";
479 reg = <0x44e35000 0x1000>;
480 interrupts = <91>;
481 };
482
483 dcan0: can@481cc000 {
484 compatible = "ti,am3352-d_can";
485 ti,hwmods = "d_can0";
486 reg = <0x481cc000 0x2000>;
487 clocks = <&dcan0_fck>;
488 clock-names = "fck";
489 syscon-raminit = <&scm_conf 0x644 0>;
490 interrupts = <52>;
491 status = "disabled";
492 };
493
494 dcan1: can@481d0000 {
495 compatible = "ti,am3352-d_can";
496 ti,hwmods = "d_can1";
497 reg = <0x481d0000 0x2000>;
498 clocks = <&dcan1_fck>;
499 clock-names = "fck";
500 syscon-raminit = <&scm_conf 0x644 1>;
501 interrupts = <55>;
502 status = "disabled";
503 };
504
505 mailbox: mailbox@480c8000 {
506 compatible = "ti,omap4-mailbox";
507 reg = <0x480C8000 0x200>;
508 interrupts = <77>;
509 ti,hwmods = "mailbox";
510 #mbox-cells = <1>;
511 ti,mbox-num-users = <4>;
512 ti,mbox-num-fifos = <8>;
513 mbox_wkupm3: wkup_m3 {
514 ti,mbox-send-noirq;
515 ti,mbox-tx = <0 0 0>;
516 ti,mbox-rx = <0 0 3>;
517 };
518 };
519
520 timer1: timer@44e31000 {
521 compatible = "ti,am335x-timer-1ms";
522 reg = <0x44e31000 0x400>;
523 interrupts = <67>;
524 ti,hwmods = "timer1";
525 ti,timer-alwon;
526 clocks = <&timer1_fck>;
527 clock-names = "fck";
528 };
529
530 timer2: timer@48040000 {
531 compatible = "ti,am335x-timer";
532 reg = <0x48040000 0x400>;
533 interrupts = <68>;
534 ti,hwmods = "timer2";
535 clocks = <&timer2_fck>;
536 clock-names = "fck";
537 };
538
539 timer3: timer@48042000 {
540 compatible = "ti,am335x-timer";
541 reg = <0x48042000 0x400>;
542 interrupts = <69>;
543 ti,hwmods = "timer3";
544 };
545
546 timer4: timer@48044000 {
547 compatible = "ti,am335x-timer";
548 reg = <0x48044000 0x400>;
549 interrupts = <92>;
550 ti,hwmods = "timer4";
551 ti,timer-pwm;
552 };
553
554 timer5: timer@48046000 {
555 compatible = "ti,am335x-timer";
556 reg = <0x48046000 0x400>;
557 interrupts = <93>;
558 ti,hwmods = "timer5";
559 ti,timer-pwm;
560 };
561
562 timer6: timer@48048000 {
563 compatible = "ti,am335x-timer";
564 reg = <0x48048000 0x400>;
565 interrupts = <94>;
566 ti,hwmods = "timer6";
567 ti,timer-pwm;
568 };
569
570 timer7: timer@4804a000 {
571 compatible = "ti,am335x-timer";
572 reg = <0x4804a000 0x400>;
573 interrupts = <95>;
574 ti,hwmods = "timer7";
575 ti,timer-pwm;
576 };
577
578 rtc: rtc@44e3e000 {
579 compatible = "ti,am3352-rtc", "ti,da830-rtc";
580 reg = <0x44e3e000 0x1000>;
581 interrupts = <75
582 76>;
583 ti,hwmods = "rtc";
584 clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
585 clock-names = "int-clk";
586 };
587
588 spi0: spi@48030000 {
589 compatible = "ti,omap4-mcspi";
590 #address-cells = <1>;
591 #size-cells = <0>;
592 reg = <0x48030000 0x400>;
593 interrupts = <65>;
594 ti,spi-num-cs = <2>;
595 ti,hwmods = "spi0";
596 dmas = <&edma 16 0
597 &edma 17 0
598 &edma 18 0
599 &edma 19 0>;
600 dma-names = "tx0", "rx0", "tx1", "rx1";
601 status = "disabled";
602 };
603
604 spi1: spi@481a0000 {
605 compatible = "ti,omap4-mcspi";
606 #address-cells = <1>;
607 #size-cells = <0>;
608 reg = <0x481a0000 0x400>;
609 interrupts = <125>;
610 ti,spi-num-cs = <2>;
611 ti,hwmods = "spi1";
612 dmas = <&edma 42 0
613 &edma 43 0
614 &edma 44 0
615 &edma 45 0>;
616 dma-names = "tx0", "rx0", "tx1", "rx1";
617 status = "disabled";
618 };
619
620 usb: usb@47400000 {
621 compatible = "ti,am33xx-usb";
622 reg = <0x47400000 0x1000>;
623 ranges;
624 #address-cells = <1>;
625 #size-cells = <1>;
626 ti,hwmods = "usb_otg_hs";
627 status = "disabled";
628
629 usb_ctrl_mod: control@44e10620 {
630 compatible = "ti,am335x-usb-ctrl-module";
631 reg = <0x44e10620 0x10
632 0x44e10648 0x4>;
633 reg-names = "phy_ctrl", "wakeup";
634 status = "disabled";
635 };
636
637 usb0_phy: usb-phy@47401300 {
638 compatible = "ti,am335x-usb-phy";
639 reg = <0x47401300 0x100>;
640 reg-names = "phy";
641 status = "disabled";
642 ti,ctrl_mod = <&usb_ctrl_mod>;
643 #phy-cells = <0>;
644 };
645
646 usb0: usb@47401000 {
647 compatible = "ti,musb-am33xx";
648 status = "disabled";
649 reg = <0x47401400 0x400
650 0x47401000 0x200>;
651 reg-names = "mc", "control";
652
653 interrupts = <18>;
654 interrupt-names = "mc";
655 dr_mode = "otg";
656 mentor,multipoint = <1>;
657 mentor,num-eps = <16>;
658 mentor,ram-bits = <12>;
659 mentor,power = <500>;
660 phys = <&usb0_phy>;
661
662 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
663 &cppi41dma 2 0 &cppi41dma 3 0
664 &cppi41dma 4 0 &cppi41dma 5 0
665 &cppi41dma 6 0 &cppi41dma 7 0
666 &cppi41dma 8 0 &cppi41dma 9 0
667 &cppi41dma 10 0 &cppi41dma 11 0
668 &cppi41dma 12 0 &cppi41dma 13 0
669 &cppi41dma 14 0 &cppi41dma 0 1
670 &cppi41dma 1 1 &cppi41dma 2 1
671 &cppi41dma 3 1 &cppi41dma 4 1
672 &cppi41dma 5 1 &cppi41dma 6 1
673 &cppi41dma 7 1 &cppi41dma 8 1
674 &cppi41dma 9 1 &cppi41dma 10 1
675 &cppi41dma 11 1 &cppi41dma 12 1
676 &cppi41dma 13 1 &cppi41dma 14 1>;
677 dma-names =
678 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
679 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
680 "rx14", "rx15",
681 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
682 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
683 "tx14", "tx15";
684 };
685
686 usb1_phy: usb-phy@47401b00 {
687 compatible = "ti,am335x-usb-phy";
688 reg = <0x47401b00 0x100>;
689 reg-names = "phy";
690 status = "disabled";
691 ti,ctrl_mod = <&usb_ctrl_mod>;
692 #phy-cells = <0>;
693 };
694
695 usb1: usb@47401800 {
696 compatible = "ti,musb-am33xx";
697 status = "disabled";
698 reg = <0x47401c00 0x400
699 0x47401800 0x200>;
700 reg-names = "mc", "control";
701 interrupts = <19>;
702 interrupt-names = "mc";
703 dr_mode = "otg";
704 mentor,multipoint = <1>;
705 mentor,num-eps = <16>;
706 mentor,ram-bits = <12>;
707 mentor,power = <500>;
708 phys = <&usb1_phy>;
709
710 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
711 &cppi41dma 17 0 &cppi41dma 18 0
712 &cppi41dma 19 0 &cppi41dma 20 0
713 &cppi41dma 21 0 &cppi41dma 22 0
714 &cppi41dma 23 0 &cppi41dma 24 0
715 &cppi41dma 25 0 &cppi41dma 26 0
716 &cppi41dma 27 0 &cppi41dma 28 0
717 &cppi41dma 29 0 &cppi41dma 15 1
718 &cppi41dma 16 1 &cppi41dma 17 1
719 &cppi41dma 18 1 &cppi41dma 19 1
720 &cppi41dma 20 1 &cppi41dma 21 1
721 &cppi41dma 22 1 &cppi41dma 23 1
722 &cppi41dma 24 1 &cppi41dma 25 1
723 &cppi41dma 26 1 &cppi41dma 27 1
724 &cppi41dma 28 1 &cppi41dma 29 1>;
725 dma-names =
726 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
727 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
728 "rx14", "rx15",
729 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
730 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
731 "tx14", "tx15";
732 };
733
734 cppi41dma: dma-controller@47402000 {
735 compatible = "ti,am3359-cppi41";
736 reg = <0x47400000 0x1000
737 0x47402000 0x1000
738 0x47403000 0x1000
739 0x47404000 0x4000>;
740 reg-names = "glue", "controller", "scheduler", "queuemgr";
741 interrupts = <17>;
742 interrupt-names = "glue";
743 #dma-cells = <2>;
744 #dma-channels = <30>;
745 #dma-requests = <256>;
746 status = "disabled";
747 };
748 };
749
750 epwmss0: epwmss@48300000 {
751 compatible = "ti,am33xx-pwmss";
752 reg = <0x48300000 0x10>;
753 ti,hwmods = "epwmss0";
754 #address-cells = <1>;
755 #size-cells = <1>;
756 status = "disabled";
757 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
758 0x48300180 0x48300180 0x80 /* EQEP */
759 0x48300200 0x48300200 0x80>; /* EHRPWM */
760
761 ecap0: ecap@48300100 {
762 compatible = "ti,am3352-ecap",
763 "ti,am33xx-ecap";
764 #pwm-cells = <3>;
765 reg = <0x48300100 0x80>;
766 clocks = <&l4ls_gclk>;
767 clock-names = "fck";
768 interrupts = <31>;
769 interrupt-names = "ecap0";
770 status = "disabled";
771 };
772
773 ehrpwm0: pwm@48300200 {
774 compatible = "ti,am3352-ehrpwm",
775 "ti,am33xx-ehrpwm";
776 #pwm-cells = <3>;
777 reg = <0x48300200 0x80>;
778 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
779 clock-names = "tbclk", "fck";
780 status = "disabled";
781 };
782 };
783
784 epwmss1: epwmss@48302000 {
785 compatible = "ti,am33xx-pwmss";
786 reg = <0x48302000 0x10>;
787 ti,hwmods = "epwmss1";
788 #address-cells = <1>;
789 #size-cells = <1>;
790 status = "disabled";
791 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
792 0x48302180 0x48302180 0x80 /* EQEP */
793 0x48302200 0x48302200 0x80>; /* EHRPWM */
794
795 ecap1: ecap@48302100 {
796 compatible = "ti,am3352-ecap",
797 "ti,am33xx-ecap";
798 #pwm-cells = <3>;
799 reg = <0x48302100 0x80>;
800 clocks = <&l4ls_gclk>;
801 clock-names = "fck";
802 interrupts = <47>;
803 interrupt-names = "ecap1";
804 status = "disabled";
805 };
806
807 ehrpwm1: pwm@48302200 {
808 compatible = "ti,am3352-ehrpwm",
809 "ti,am33xx-ehrpwm";
810 #pwm-cells = <3>;
811 reg = <0x48302200 0x80>;
812 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
813 clock-names = "tbclk", "fck";
814 status = "disabled";
815 };
816 };
817
818 epwmss2: epwmss@48304000 {
819 compatible = "ti,am33xx-pwmss";
820 reg = <0x48304000 0x10>;
821 ti,hwmods = "epwmss2";
822 #address-cells = <1>;
823 #size-cells = <1>;
824 status = "disabled";
825 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
826 0x48304180 0x48304180 0x80 /* EQEP */
827 0x48304200 0x48304200 0x80>; /* EHRPWM */
828
829 ecap2: ecap@48304100 {
830 compatible = "ti,am3352-ecap",
831 "ti,am33xx-ecap";
832 #pwm-cells = <3>;
833 reg = <0x48304100 0x80>;
834 clocks = <&l4ls_gclk>;
835 clock-names = "fck";
836 interrupts = <61>;
837 interrupt-names = "ecap2";
838 status = "disabled";
839 };
840
841 ehrpwm2: pwm@48304200 {
842 compatible = "ti,am3352-ehrpwm",
843 "ti,am33xx-ehrpwm";
844 #pwm-cells = <3>;
845 reg = <0x48304200 0x80>;
846 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
847 clock-names = "tbclk", "fck";
848 status = "disabled";
849 };
850 };
851
852 mac: ethernet@4a100000 {
853 compatible = "ti,am335x-cpsw","ti,cpsw";
854 ti,hwmods = "cpgmac0";
855 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
856 clock-names = "fck", "cpts";
857 cpdma_channels = <8>;
858 ale_entries = <1024>;
859 bd_ram_size = <0x2000>;
860 mac_control = <0x20>;
861 slaves = <2>;
862 active_slave = <0>;
863 cpts_clock_mult = <0x80000000>;
864 cpts_clock_shift = <29>;
865 reg = <0x4a100000 0x800
866 0x4a101200 0x100>;
867 #address-cells = <1>;
868 #size-cells = <1>;
869 /*
870 * c0_rx_thresh_pend
871 * c0_rx_pend
872 * c0_tx_pend
873 * c0_misc_pend
874 */
875 interrupts = <40 41 42 43>;
876 ranges;
877 syscon = <&scm_conf>;
878 status = "disabled";
879
880 davinci_mdio: mdio@4a101000 {
881 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
882 #address-cells = <1>;
883 #size-cells = <0>;
884 ti,hwmods = "davinci_mdio";
885 bus_freq = <1000000>;
886 reg = <0x4a101000 0x100>;
887 status = "disabled";
888 };
889
890 cpsw_emac0: slave@4a100200 {
891 /* Filled in by U-Boot */
892 mac-address = [ 00 00 00 00 00 00 ];
893 };
894
895 cpsw_emac1: slave@4a100300 {
896 /* Filled in by U-Boot */
897 mac-address = [ 00 00 00 00 00 00 ];
898 };
899
900 phy_sel: cpsw-phy-sel@44e10650 {
901 compatible = "ti,am3352-cpsw-phy-sel";
902 reg= <0x44e10650 0x4>;
903 reg-names = "gmii-sel";
904 };
905 };
906
907 ocmcram: ocmcram@40300000 {
908 compatible = "mmio-sram";
909 reg = <0x40300000 0x10000>; /* 64k */
910 ranges = <0x0 0x40300000 0x10000>;
911 #address-cells = <1>;
912 #size-cells = <1>;
913
914 pm_sram_code: pm-sram-code@0 {
915 compatible = "ti,sram";
916 reg = <0x0 0x1000>;
917 protect-exec;
918 };
919
920 pm_sram_data: pm-sram-data@1000 {
921 compatible = "ti,sram";
922 reg = <0x1000 0x1000>;
923 pool;
924 };
925 };
926
927 elm: elm@48080000 {
928 compatible = "ti,am3352-elm";
929 reg = <0x48080000 0x2000>;
930 interrupts = <4>;
931 ti,hwmods = "elm";
932 status = "disabled";
933 };
934
935 lcdc: lcdc@4830e000 {
936 compatible = "ti,am33xx-tilcdc";
937 reg = <0x4830e000 0x1000>;
938 interrupts = <36>;
939 ti,hwmods = "lcdc";
940 status = "disabled";
941 };
942
943 tscadc: tscadc@44e0d000 {
944 compatible = "ti,am3359-tscadc";
945 reg = <0x44e0d000 0x1000>;
946 interrupts = <16>;
947 ti,hwmods = "adc_tsc";
948 status = "disabled";
949 dmas = <&edma 53 0>, <&edma 57 0>;
950 dma-names = "fifo0", "fifo1";
951
952 tsc {
953 compatible = "ti,am3359-tsc";
954 };
955 am335x_adc: adc {
956 #io-channel-cells = <1>;
957 compatible = "ti,am3359-adc";
958 };
959 };
960
961 emif: emif@4c000000 {
962 compatible = "ti,emif-am3352";
963 reg = <0x4c000000 0x1000000>;
964 ti,hwmods = "emif";
965 interrupts = <101>;
966 sram = <&pm_sram_code
967 &pm_sram_data>;
968 ti,no-idle;
969 };
970
971 gpmc: gpmc@50000000 {
972 compatible = "ti,am3352-gpmc";
973 ti,hwmods = "gpmc";
974 ti,no-idle-on-init;
975 reg = <0x50000000 0x2000>;
976 interrupts = <100>;
977 dmas = <&edma 52 0>;
978 dma-names = "rxtx";
979 gpmc,num-cs = <7>;
980 gpmc,num-waitpins = <2>;
981 #address-cells = <2>;
982 #size-cells = <1>;
983 interrupt-controller;
984 #interrupt-cells = <2>;
985 gpio-controller;
986 #gpio-cells = <2>;
987 status = "disabled";
988 };
989
990 sham: sham@53100000 {
991 compatible = "ti,omap4-sham";
992 ti,hwmods = "sham";
993 reg = <0x53100000 0x200>;
994 interrupts = <109>;
995 dmas = <&edma 36 0>;
996 dma-names = "rx";
997 };
998
999 aes: aes@53500000 {
1000 compatible = "ti,omap4-aes";
1001 ti,hwmods = "aes";
1002 reg = <0x53500000 0xa0>;
1003 interrupts = <103>;
1004 dmas = <&edma 6 0>,
1005 <&edma 5 0>;
1006 dma-names = "tx", "rx";
1007 };
1008
1009 mcasp0: mcasp@48038000 {
1010 compatible = "ti,am33xx-mcasp-audio";
1011 ti,hwmods = "mcasp0";
1012 reg = <0x48038000 0x2000>,
1013 <0x46000000 0x400000>;
1014 reg-names = "mpu", "dat";
1015 interrupts = <80>, <81>;
1016 interrupt-names = "tx", "rx";
1017 status = "disabled";
1018 dmas = <&edma 8 2>,
1019 <&edma 9 2>;
1020 dma-names = "tx", "rx";
1021 };
1022
1023 mcasp1: mcasp@4803c000 {
1024 compatible = "ti,am33xx-mcasp-audio";
1025 ti,hwmods = "mcasp1";
1026 reg = <0x4803C000 0x2000>,
1027 <0x46400000 0x400000>;
1028 reg-names = "mpu", "dat";
1029 interrupts = <82>, <83>;
1030 interrupt-names = "tx", "rx";
1031 status = "disabled";
1032 dmas = <&edma 10 2>,
1033 <&edma 11 2>;
1034 dma-names = "tx", "rx";
1035 };
1036
1037 rng: rng@48310000 {
1038 compatible = "ti,omap4-rng";
1039 ti,hwmods = "rng";
1040 reg = <0x48310000 0x2000>;
1041 interrupts = <111>;
1042 };
1043 };
1044};
1045
1046#include "am33xx-clocks.dtsi"