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1/*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Madhav Chauhan <madhav.chauhan@intel.com>
25 * Jani Nikula <jani.nikula@intel.com>
26 */
27
28#include <drm/drm_atomic_helper.h>
29#include <drm/drm_mipi_dsi.h>
30
31#include "intel_atomic.h"
32#include "intel_combo_phy.h"
33#include "intel_connector.h"
34#include "intel_crtc.h"
35#include "intel_ddi.h"
36#include "intel_de.h"
37#include "intel_dsi.h"
38#include "intel_panel.h"
39#include "intel_vdsc.h"
40#include "skl_scaler.h"
41#include "skl_universal_plane.h"
42
43static int header_credits_available(struct drm_i915_private *dev_priv,
44 enum transcoder dsi_trans)
45{
46 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
47 >> FREE_HEADER_CREDIT_SHIFT;
48}
49
50static int payload_credits_available(struct drm_i915_private *dev_priv,
51 enum transcoder dsi_trans)
52{
53 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
54 >> FREE_PLOAD_CREDIT_SHIFT;
55}
56
57static void wait_for_header_credits(struct drm_i915_private *dev_priv,
58 enum transcoder dsi_trans)
59{
60 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
61 MAX_HEADER_CREDIT, 100))
62 drm_err(&dev_priv->drm, "DSI header credits not released\n");
63}
64
65static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
66 enum transcoder dsi_trans)
67{
68 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
69 MAX_PLOAD_CREDIT, 100))
70 drm_err(&dev_priv->drm, "DSI payload credits not released\n");
71}
72
73static enum transcoder dsi_port_to_transcoder(enum port port)
74{
75 if (port == PORT_A)
76 return TRANSCODER_DSI_0;
77 else
78 return TRANSCODER_DSI_1;
79}
80
81static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
82{
83 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
84 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
85 struct mipi_dsi_device *dsi;
86 enum port port;
87 enum transcoder dsi_trans;
88 int ret;
89
90 /* wait for header/payload credits to be released */
91 for_each_dsi_port(port, intel_dsi->ports) {
92 dsi_trans = dsi_port_to_transcoder(port);
93 wait_for_header_credits(dev_priv, dsi_trans);
94 wait_for_payload_credits(dev_priv, dsi_trans);
95 }
96
97 /* send nop DCS command */
98 for_each_dsi_port(port, intel_dsi->ports) {
99 dsi = intel_dsi->dsi_hosts[port]->device;
100 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
101 dsi->channel = 0;
102 ret = mipi_dsi_dcs_nop(dsi);
103 if (ret < 0)
104 drm_err(&dev_priv->drm,
105 "error sending DCS NOP command\n");
106 }
107
108 /* wait for header credits to be released */
109 for_each_dsi_port(port, intel_dsi->ports) {
110 dsi_trans = dsi_port_to_transcoder(port);
111 wait_for_header_credits(dev_priv, dsi_trans);
112 }
113
114 /* wait for LP TX in progress bit to be cleared */
115 for_each_dsi_port(port, intel_dsi->ports) {
116 dsi_trans = dsi_port_to_transcoder(port);
117 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
118 LPTX_IN_PROGRESS), 20))
119 drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
120 }
121}
122
123static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
124 u32 len)
125{
126 struct intel_dsi *intel_dsi = host->intel_dsi;
127 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
128 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
129 int free_credits;
130 int i, j;
131
132 for (i = 0; i < len; i += 4) {
133 u32 tmp = 0;
134
135 free_credits = payload_credits_available(dev_priv, dsi_trans);
136 if (free_credits < 1) {
137 drm_err(&dev_priv->drm,
138 "Payload credit not available\n");
139 return false;
140 }
141
142 for (j = 0; j < min_t(u32, len - i, 4); j++)
143 tmp |= *data++ << 8 * j;
144
145 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp);
146 }
147
148 return true;
149}
150
151static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
152 struct mipi_dsi_packet pkt, bool enable_lpdt)
153{
154 struct intel_dsi *intel_dsi = host->intel_dsi;
155 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
156 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
157 u32 tmp;
158 int free_credits;
159
160 /* check if header credit available */
161 free_credits = header_credits_available(dev_priv, dsi_trans);
162 if (free_credits < 1) {
163 drm_err(&dev_priv->drm,
164 "send pkt header failed, not enough hdr credits\n");
165 return -1;
166 }
167
168 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
169
170 if (pkt.payload)
171 tmp |= PAYLOAD_PRESENT;
172 else
173 tmp &= ~PAYLOAD_PRESENT;
174
175 tmp &= ~VBLANK_FENCE;
176
177 if (enable_lpdt)
178 tmp |= LP_DATA_TRANSFER;
179
180 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
181 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
182 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
183 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
184 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
185 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
186
187 return 0;
188}
189
190static int dsi_send_pkt_payld(struct intel_dsi_host *host,
191 struct mipi_dsi_packet pkt)
192{
193 struct intel_dsi *intel_dsi = host->intel_dsi;
194 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
195
196 /* payload queue can accept *256 bytes*, check limit */
197 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
198 drm_err(&i915->drm, "payload size exceeds max queue limit\n");
199 return -1;
200 }
201
202 /* load data into command payload queue */
203 if (!add_payld_to_queue(host, pkt.payload,
204 pkt.payload_length)) {
205 drm_err(&i915->drm, "adding payload to queue failed\n");
206 return -1;
207 }
208
209 return 0;
210}
211
212void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
213{
214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
216 u32 tmp, mode_flags;
217 enum port port;
218
219 mode_flags = crtc_state->mode_flags;
220
221 /*
222 * case 1 also covers dual link
223 * In case of dual link, frame update should be set on
224 * DSI_0
225 */
226 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
227 port = PORT_A;
228 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
229 port = PORT_B;
230 else
231 return;
232
233 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
234 tmp |= DSI_FRAME_UPDATE_REQUEST;
235 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
236}
237
238static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
239{
240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
241 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
242 enum phy phy;
243 u32 tmp;
244 int lane;
245
246 for_each_dsi_phy(phy, intel_dsi->phys) {
247 /*
248 * Program voltage swing and pre-emphasis level values as per
249 * table in BSPEC under DDI buffer programing
250 */
251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
252 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
253 tmp |= SCALING_MODE_SEL(0x2);
254 tmp |= TAP2_DISABLE | TAP3_DISABLE;
255 tmp |= RTERM_SELECT(0x6);
256 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
257
258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
259 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
260 tmp |= SCALING_MODE_SEL(0x2);
261 tmp |= TAP2_DISABLE | TAP3_DISABLE;
262 tmp |= RTERM_SELECT(0x6);
263 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
264
265 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
266 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
267 RCOMP_SCALAR_MASK);
268 tmp |= SWING_SEL_UPPER(0x2);
269 tmp |= SWING_SEL_LOWER(0x2);
270 tmp |= RCOMP_SCALAR(0x98);
271 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
272
273 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
274 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
275 RCOMP_SCALAR_MASK);
276 tmp |= SWING_SEL_UPPER(0x2);
277 tmp |= SWING_SEL_LOWER(0x2);
278 tmp |= RCOMP_SCALAR(0x98);
279 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
280
281 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
282 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
283 CURSOR_COEFF_MASK);
284 tmp |= POST_CURSOR_1(0x0);
285 tmp |= POST_CURSOR_2(0x0);
286 tmp |= CURSOR_COEFF(0x3f);
287 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
288
289 for (lane = 0; lane <= 3; lane++) {
290 /* Bspec: must not use GRP register for write */
291 tmp = intel_de_read(dev_priv,
292 ICL_PORT_TX_DW4_LN(lane, phy));
293 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
294 CURSOR_COEFF_MASK);
295 tmp |= POST_CURSOR_1(0x0);
296 tmp |= POST_CURSOR_2(0x0);
297 tmp |= CURSOR_COEFF(0x3f);
298 intel_de_write(dev_priv,
299 ICL_PORT_TX_DW4_LN(lane, phy), tmp);
300 }
301 }
302}
303
304static void configure_dual_link_mode(struct intel_encoder *encoder,
305 const struct intel_crtc_state *pipe_config)
306{
307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
309 u32 dss_ctl1;
310
311 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
312 dss_ctl1 |= SPLITTER_ENABLE;
313 dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
314 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
315
316 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
317 const struct drm_display_mode *adjusted_mode =
318 &pipe_config->hw.adjusted_mode;
319 u32 dss_ctl2;
320 u16 hactive = adjusted_mode->crtc_hdisplay;
321 u16 dl_buffer_depth;
322
323 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
324 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
325
326 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
327 drm_err(&dev_priv->drm,
328 "DL buffer depth exceed max value\n");
329
330 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
331 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
332 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
333 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
334 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
335 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2);
336 } else {
337 /* Interleave */
338 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
339 }
340
341 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1);
342}
343
344/* aka DSI 8X clock */
345static int afe_clk(struct intel_encoder *encoder,
346 const struct intel_crtc_state *crtc_state)
347{
348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
349 int bpp;
350
351 if (crtc_state->dsc.compression_enable)
352 bpp = crtc_state->dsc.compressed_bpp;
353 else
354 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
355
356 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
357}
358
359static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
360 const struct intel_crtc_state *crtc_state)
361{
362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
364 enum port port;
365 int afe_clk_khz;
366 int theo_word_clk, act_word_clk;
367 u32 esc_clk_div_m, esc_clk_div_m_phy;
368
369 afe_clk_khz = afe_clk(encoder, crtc_state);
370
371 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
372 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
373 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
374 esc_clk_div_m = act_word_clk * 8;
375 esc_clk_div_m_phy = (act_word_clk - 1) / 2;
376 } else {
377 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
378 }
379
380 for_each_dsi_port(port, intel_dsi->ports) {
381 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
382 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
383 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
384 }
385
386 for_each_dsi_port(port, intel_dsi->ports) {
387 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
388 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
389 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
390 }
391
392 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
393 for_each_dsi_port(port, intel_dsi->ports) {
394 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
395 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
396 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
397 }
398 }
399}
400
401static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
402 struct intel_dsi *intel_dsi)
403{
404 enum port port;
405
406 for_each_dsi_port(port, intel_dsi->ports) {
407 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
408 intel_dsi->io_wakeref[port] =
409 intel_display_power_get(dev_priv,
410 port == PORT_A ?
411 POWER_DOMAIN_PORT_DDI_A_IO :
412 POWER_DOMAIN_PORT_DDI_B_IO);
413 }
414}
415
416static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
417{
418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
420 enum port port;
421 u32 tmp;
422
423 for_each_dsi_port(port, intel_dsi->ports) {
424 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
425 tmp |= COMBO_PHY_MODE_DSI;
426 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
427 }
428
429 get_dsi_io_power_domains(dev_priv, intel_dsi);
430}
431
432static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
433{
434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
435 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
436 enum phy phy;
437
438 for_each_dsi_phy(phy, intel_dsi->phys)
439 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
440 intel_dsi->lane_count, false);
441}
442
443static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
444{
445 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
446 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
447 enum phy phy;
448 u32 tmp;
449 int lane;
450
451 /* Step 4b(i) set loadgen select for transmit and aux lanes */
452 for_each_dsi_phy(phy, intel_dsi->phys) {
453 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
454 tmp &= ~LOADGEN_SELECT;
455 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
456 for (lane = 0; lane <= 3; lane++) {
457 tmp = intel_de_read(dev_priv,
458 ICL_PORT_TX_DW4_LN(lane, phy));
459 tmp &= ~LOADGEN_SELECT;
460 if (lane != 2)
461 tmp |= LOADGEN_SELECT;
462 intel_de_write(dev_priv,
463 ICL_PORT_TX_DW4_LN(lane, phy), tmp);
464 }
465 }
466
467 /* Step 4b(ii) set latency optimization for transmit and aux lanes */
468 for_each_dsi_phy(phy, intel_dsi->phys) {
469 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
470 tmp &= ~FRC_LATENCY_OPTIM_MASK;
471 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
472 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
473 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
474 tmp &= ~FRC_LATENCY_OPTIM_MASK;
475 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
476 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
477
478 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
479 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
480 tmp = intel_de_read(dev_priv,
481 ICL_PORT_PCS_DW1_AUX(phy));
482 tmp &= ~LATENCY_OPTIM_MASK;
483 tmp |= LATENCY_OPTIM_VAL(0);
484 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
485 tmp);
486
487 tmp = intel_de_read(dev_priv,
488 ICL_PORT_PCS_DW1_LN0(phy));
489 tmp &= ~LATENCY_OPTIM_MASK;
490 tmp |= LATENCY_OPTIM_VAL(0x1);
491 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
492 tmp);
493 }
494 }
495
496}
497
498static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
499{
500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
501 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
502 u32 tmp;
503 enum phy phy;
504
505 /* clear common keeper enable bit */
506 for_each_dsi_phy(phy, intel_dsi->phys) {
507 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
508 tmp &= ~COMMON_KEEPER_EN;
509 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
510 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
511 tmp &= ~COMMON_KEEPER_EN;
512 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp);
513 }
514
515 /*
516 * Set SUS Clock Config bitfield to 11b
517 * Note: loadgen select program is done
518 * as part of lane phy sequence configuration
519 */
520 for_each_dsi_phy(phy, intel_dsi->phys) {
521 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
522 tmp |= SUS_CLOCK_CONFIG;
523 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp);
524 }
525
526 /* Clear training enable to change swing values */
527 for_each_dsi_phy(phy, intel_dsi->phys) {
528 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
529 tmp &= ~TX_TRAINING_EN;
530 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
531 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
532 tmp &= ~TX_TRAINING_EN;
533 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
534 }
535
536 /* Program swing and de-emphasis */
537 dsi_program_swing_and_deemphasis(encoder);
538
539 /* Set training enable to trigger update */
540 for_each_dsi_phy(phy, intel_dsi->phys) {
541 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
542 tmp |= TX_TRAINING_EN;
543 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
544 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
545 tmp |= TX_TRAINING_EN;
546 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
547 }
548}
549
550static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
551{
552 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
553 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
554 u32 tmp;
555 enum port port;
556
557 for_each_dsi_port(port, intel_dsi->ports) {
558 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
559 tmp |= DDI_BUF_CTL_ENABLE;
560 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
561
562 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
563 DDI_BUF_IS_IDLE),
564 500))
565 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
566 port_name(port));
567 }
568}
569
570static void
571gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
572 const struct intel_crtc_state *crtc_state)
573{
574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
575 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
576 u32 tmp;
577 enum port port;
578 enum phy phy;
579
580 /* Program T-INIT master registers */
581 for_each_dsi_port(port, intel_dsi->ports) {
582 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port));
583 tmp &= ~MASTER_INIT_TIMER_MASK;
584 tmp |= intel_dsi->init_count;
585 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp);
586 }
587
588 /* Program DPHY clock lanes timings */
589 for_each_dsi_port(port, intel_dsi->ports) {
590 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
591 intel_dsi->dphy_reg);
592
593 /* shadow register inside display core */
594 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
595 intel_dsi->dphy_reg);
596 }
597
598 /* Program DPHY data lanes timings */
599 for_each_dsi_port(port, intel_dsi->ports) {
600 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
601 intel_dsi->dphy_data_lane_reg);
602
603 /* shadow register inside display core */
604 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
605 intel_dsi->dphy_data_lane_reg);
606 }
607
608 /*
609 * If DSI link operating at or below an 800 MHz,
610 * TA_SURE should be override and programmed to
611 * a value '0' inside TA_PARAM_REGISTERS otherwise
612 * leave all fields at HW default values.
613 */
614 if (DISPLAY_VER(dev_priv) == 11) {
615 if (afe_clk(encoder, crtc_state) <= 800000) {
616 for_each_dsi_port(port, intel_dsi->ports) {
617 tmp = intel_de_read(dev_priv,
618 DPHY_TA_TIMING_PARAM(port));
619 tmp &= ~TA_SURE_MASK;
620 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
621 intel_de_write(dev_priv,
622 DPHY_TA_TIMING_PARAM(port),
623 tmp);
624
625 /* shadow register inside display core */
626 tmp = intel_de_read(dev_priv,
627 DSI_TA_TIMING_PARAM(port));
628 tmp &= ~TA_SURE_MASK;
629 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
630 intel_de_write(dev_priv,
631 DSI_TA_TIMING_PARAM(port), tmp);
632 }
633 }
634 }
635
636 if (IS_JSL_EHL(dev_priv)) {
637 for_each_dsi_phy(phy, intel_dsi->phys) {
638 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
639 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
640 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp);
641 }
642 }
643}
644
645static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
646{
647 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
648 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
649 u32 tmp;
650 enum phy phy;
651
652 mutex_lock(&dev_priv->dpll.lock);
653 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
654 for_each_dsi_phy(phy, intel_dsi->phys)
655 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
656
657 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
658 mutex_unlock(&dev_priv->dpll.lock);
659}
660
661static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
662{
663 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
664 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
665 u32 tmp;
666 enum phy phy;
667
668 mutex_lock(&dev_priv->dpll.lock);
669 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
670 for_each_dsi_phy(phy, intel_dsi->phys)
671 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
672
673 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
674 mutex_unlock(&dev_priv->dpll.lock);
675}
676
677static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
678{
679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
680 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
681 bool clock_enabled = false;
682 enum phy phy;
683 u32 tmp;
684
685 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
686
687 for_each_dsi_phy(phy, intel_dsi->phys) {
688 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
689 clock_enabled = true;
690 }
691
692 return clock_enabled;
693}
694
695static void gen11_dsi_map_pll(struct intel_encoder *encoder,
696 const struct intel_crtc_state *crtc_state)
697{
698 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
699 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
700 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
701 enum phy phy;
702 u32 val;
703
704 mutex_lock(&dev_priv->dpll.lock);
705
706 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
707 for_each_dsi_phy(phy, intel_dsi->phys) {
708 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
709 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
710 }
711 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
712
713 for_each_dsi_phy(phy, intel_dsi->phys) {
714 if (DISPLAY_VER(dev_priv) >= 12)
715 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
716 else
717 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
718 }
719 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
720
721 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
722
723 mutex_unlock(&dev_priv->dpll.lock);
724}
725
726static void
727gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
728 const struct intel_crtc_state *pipe_config)
729{
730 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
731 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
732 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
733 enum pipe pipe = intel_crtc->pipe;
734 u32 tmp;
735 enum port port;
736 enum transcoder dsi_trans;
737
738 for_each_dsi_port(port, intel_dsi->ports) {
739 dsi_trans = dsi_port_to_transcoder(port);
740 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
741
742 if (intel_dsi->eotp_pkt)
743 tmp &= ~EOTP_DISABLED;
744 else
745 tmp |= EOTP_DISABLED;
746
747 /* enable link calibration if freq > 1.5Gbps */
748 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
749 tmp &= ~LINK_CALIBRATION_MASK;
750 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
751 }
752
753 /* configure continuous clock */
754 tmp &= ~CONTINUOUS_CLK_MASK;
755 if (intel_dsi->clock_stop)
756 tmp |= CLK_ENTER_LP_AFTER_DATA;
757 else
758 tmp |= CLK_HS_CONTINUOUS;
759
760 /* configure buffer threshold limit to minimum */
761 tmp &= ~PIX_BUF_THRESHOLD_MASK;
762 tmp |= PIX_BUF_THRESHOLD_1_4;
763
764 /* set virtual channel to '0' */
765 tmp &= ~PIX_VIRT_CHAN_MASK;
766 tmp |= PIX_VIRT_CHAN(0);
767
768 /* program BGR transmission */
769 if (intel_dsi->bgr_enabled)
770 tmp |= BGR_TRANSMISSION;
771
772 /* select pixel format */
773 tmp &= ~PIX_FMT_MASK;
774 if (pipe_config->dsc.compression_enable) {
775 tmp |= PIX_FMT_COMPRESSED;
776 } else {
777 switch (intel_dsi->pixel_format) {
778 default:
779 MISSING_CASE(intel_dsi->pixel_format);
780 fallthrough;
781 case MIPI_DSI_FMT_RGB565:
782 tmp |= PIX_FMT_RGB565;
783 break;
784 case MIPI_DSI_FMT_RGB666_PACKED:
785 tmp |= PIX_FMT_RGB666_PACKED;
786 break;
787 case MIPI_DSI_FMT_RGB666:
788 tmp |= PIX_FMT_RGB666_LOOSE;
789 break;
790 case MIPI_DSI_FMT_RGB888:
791 tmp |= PIX_FMT_RGB888;
792 break;
793 }
794 }
795
796 if (DISPLAY_VER(dev_priv) >= 12) {
797 if (is_vid_mode(intel_dsi))
798 tmp |= BLANKING_PACKET_ENABLE;
799 }
800
801 /* program DSI operation mode */
802 if (is_vid_mode(intel_dsi)) {
803 tmp &= ~OP_MODE_MASK;
804 switch (intel_dsi->video_mode_format) {
805 default:
806 MISSING_CASE(intel_dsi->video_mode_format);
807 fallthrough;
808 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
809 tmp |= VIDEO_MODE_SYNC_EVENT;
810 break;
811 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
812 tmp |= VIDEO_MODE_SYNC_PULSE;
813 break;
814 }
815 } else {
816 /*
817 * FIXME: Retrieve this info from VBT.
818 * As per the spec when dsi transcoder is operating
819 * in TE GATE mode, TE comes from GPIO
820 * which is UTIL PIN for DSI 0.
821 * Also this GPIO would not be used for other
822 * purposes is an assumption.
823 */
824 tmp &= ~OP_MODE_MASK;
825 tmp |= CMD_MODE_TE_GATE;
826 tmp |= TE_SOURCE_GPIO;
827 }
828
829 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
830 }
831
832 /* enable port sync mode if dual link */
833 if (intel_dsi->dual_link) {
834 for_each_dsi_port(port, intel_dsi->ports) {
835 dsi_trans = dsi_port_to_transcoder(port);
836 tmp = intel_de_read(dev_priv,
837 TRANS_DDI_FUNC_CTL2(dsi_trans));
838 tmp |= PORT_SYNC_MODE_ENABLE;
839 intel_de_write(dev_priv,
840 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
841 }
842
843 /* configure stream splitting */
844 configure_dual_link_mode(encoder, pipe_config);
845 }
846
847 for_each_dsi_port(port, intel_dsi->ports) {
848 dsi_trans = dsi_port_to_transcoder(port);
849
850 /* select data lane width */
851 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
852 tmp &= ~DDI_PORT_WIDTH_MASK;
853 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
854
855 /* select input pipe */
856 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
857 switch (pipe) {
858 default:
859 MISSING_CASE(pipe);
860 fallthrough;
861 case PIPE_A:
862 tmp |= TRANS_DDI_EDP_INPUT_A_ON;
863 break;
864 case PIPE_B:
865 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
866 break;
867 case PIPE_C:
868 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
869 break;
870 case PIPE_D:
871 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
872 break;
873 }
874
875 /* enable DDI buffer */
876 tmp |= TRANS_DDI_FUNC_ENABLE;
877 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
878 }
879
880 /* wait for link ready */
881 for_each_dsi_port(port, intel_dsi->ports) {
882 dsi_trans = dsi_port_to_transcoder(port);
883 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
884 LINK_READY), 2500))
885 drm_err(&dev_priv->drm, "DSI link not ready\n");
886 }
887}
888
889static void
890gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
891 const struct intel_crtc_state *crtc_state)
892{
893 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
894 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
895 const struct drm_display_mode *adjusted_mode =
896 &crtc_state->hw.adjusted_mode;
897 enum port port;
898 enum transcoder dsi_trans;
899 /* horizontal timings */
900 u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
901 u16 hback_porch;
902 /* vertical timings */
903 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
904 int mul = 1, div = 1;
905
906 /*
907 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
908 * for slower link speed if DSC is enabled.
909 *
910 * The compression frequency ratio is the ratio between compressed and
911 * non-compressed link speeds, and simplifies down to the ratio between
912 * compressed and non-compressed bpp.
913 */
914 if (crtc_state->dsc.compression_enable) {
915 mul = crtc_state->dsc.compressed_bpp;
916 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
917 }
918
919 hactive = adjusted_mode->crtc_hdisplay;
920
921 if (is_vid_mode(intel_dsi))
922 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
923 else
924 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
925
926 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
927 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
928 hsync_size = hsync_end - hsync_start;
929 hback_porch = (adjusted_mode->crtc_htotal -
930 adjusted_mode->crtc_hsync_end);
931 vactive = adjusted_mode->crtc_vdisplay;
932
933 if (is_vid_mode(intel_dsi)) {
934 vtotal = adjusted_mode->crtc_vtotal;
935 } else {
936 int bpp, line_time_us, byte_clk_period_ns;
937
938 if (crtc_state->dsc.compression_enable)
939 bpp = crtc_state->dsc.compressed_bpp;
940 else
941 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
942
943 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
944 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
945 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
946 }
947 vsync_start = adjusted_mode->crtc_vsync_start;
948 vsync_end = adjusted_mode->crtc_vsync_end;
949 vsync_shift = hsync_start - htotal / 2;
950
951 if (intel_dsi->dual_link) {
952 hactive /= 2;
953 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
954 hactive += intel_dsi->pixel_overlap;
955 htotal /= 2;
956 }
957
958 /* minimum hactive as per bspec: 256 pixels */
959 if (adjusted_mode->crtc_hdisplay < 256)
960 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
961
962 /* if RGB666 format, then hactive must be multiple of 4 pixels */
963 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
964 drm_err(&dev_priv->drm,
965 "hactive pixels are not multiple of 4\n");
966
967 /* program TRANS_HTOTAL register */
968 for_each_dsi_port(port, intel_dsi->ports) {
969 dsi_trans = dsi_port_to_transcoder(port);
970 intel_de_write(dev_priv, HTOTAL(dsi_trans),
971 (hactive - 1) | ((htotal - 1) << 16));
972 }
973
974 /* TRANS_HSYNC register to be programmed only for video mode */
975 if (is_vid_mode(intel_dsi)) {
976 if (intel_dsi->video_mode_format ==
977 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
978 /* BSPEC: hsync size should be atleast 16 pixels */
979 if (hsync_size < 16)
980 drm_err(&dev_priv->drm,
981 "hsync size < 16 pixels\n");
982 }
983
984 if (hback_porch < 16)
985 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
986
987 if (intel_dsi->dual_link) {
988 hsync_start /= 2;
989 hsync_end /= 2;
990 }
991
992 for_each_dsi_port(port, intel_dsi->ports) {
993 dsi_trans = dsi_port_to_transcoder(port);
994 intel_de_write(dev_priv, HSYNC(dsi_trans),
995 (hsync_start - 1) | ((hsync_end - 1) << 16));
996 }
997 }
998
999 /* program TRANS_VTOTAL register */
1000 for_each_dsi_port(port, intel_dsi->ports) {
1001 dsi_trans = dsi_port_to_transcoder(port);
1002 /*
1003 * FIXME: Programing this by assuming progressive mode, since
1004 * non-interlaced info from VBT is not saved inside
1005 * struct drm_display_mode.
1006 * For interlace mode: program required pixel minus 2
1007 */
1008 intel_de_write(dev_priv, VTOTAL(dsi_trans),
1009 (vactive - 1) | ((vtotal - 1) << 16));
1010 }
1011
1012 if (vsync_end < vsync_start || vsync_end > vtotal)
1013 drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
1014
1015 if (vsync_start < vactive)
1016 drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
1017
1018 /* program TRANS_VSYNC register for video mode only */
1019 if (is_vid_mode(intel_dsi)) {
1020 for_each_dsi_port(port, intel_dsi->ports) {
1021 dsi_trans = dsi_port_to_transcoder(port);
1022 intel_de_write(dev_priv, VSYNC(dsi_trans),
1023 (vsync_start - 1) | ((vsync_end - 1) << 16));
1024 }
1025 }
1026
1027 /*
1028 * FIXME: It has to be programmed only for video modes and interlaced
1029 * modes. Put the check condition here once interlaced
1030 * info available as described above.
1031 * program TRANS_VSYNCSHIFT register
1032 */
1033 if (is_vid_mode(intel_dsi)) {
1034 for_each_dsi_port(port, intel_dsi->ports) {
1035 dsi_trans = dsi_port_to_transcoder(port);
1036 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans),
1037 vsync_shift);
1038 }
1039 }
1040
1041 /* program TRANS_VBLANK register, should be same as vtotal programmed */
1042 if (DISPLAY_VER(dev_priv) >= 12) {
1043 for_each_dsi_port(port, intel_dsi->ports) {
1044 dsi_trans = dsi_port_to_transcoder(port);
1045 intel_de_write(dev_priv, VBLANK(dsi_trans),
1046 (vactive - 1) | ((vtotal - 1) << 16));
1047 }
1048 }
1049}
1050
1051static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1052{
1053 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1054 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1055 enum port port;
1056 enum transcoder dsi_trans;
1057 u32 tmp;
1058
1059 for_each_dsi_port(port, intel_dsi->ports) {
1060 dsi_trans = dsi_port_to_transcoder(port);
1061 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1062 tmp |= PIPECONF_ENABLE;
1063 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1064
1065 /* wait for transcoder to be enabled */
1066 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
1067 I965_PIPECONF_ACTIVE, 10))
1068 drm_err(&dev_priv->drm,
1069 "DSI transcoder not enabled\n");
1070 }
1071}
1072
1073static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1074 const struct intel_crtc_state *crtc_state)
1075{
1076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1077 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1078 enum port port;
1079 enum transcoder dsi_trans;
1080 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1081
1082 /*
1083 * escape clock count calculation:
1084 * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1085 * UI (nsec) = (10^6)/Bitrate
1086 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1087 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
1088 */
1089 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1090 mul = 8 * 1000000;
1091 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1092 divisor);
1093 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1094 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1095
1096 for_each_dsi_port(port, intel_dsi->ports) {
1097 dsi_trans = dsi_port_to_transcoder(port);
1098
1099 /* program hst_tx_timeout */
1100 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans));
1101 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
1102 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
1103 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp);
1104
1105 /* FIXME: DSI_CALIB_TO */
1106
1107 /* program lp_rx_host timeout */
1108 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans));
1109 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
1110 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
1111 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp);
1112
1113 /* FIXME: DSI_PWAIT_TO */
1114
1115 /* program turn around timeout */
1116 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans));
1117 tmp &= ~TA_TIMEOUT_VALUE_MASK;
1118 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
1119 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp);
1120 }
1121}
1122
1123static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1124 bool enable)
1125{
1126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1127 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1128 u32 tmp;
1129
1130 /*
1131 * used as TE i/p for DSI0,
1132 * for dual link/DSI1 TE is from slave DSI1
1133 * through GPIO.
1134 */
1135 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1136 return;
1137
1138 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1139
1140 if (enable) {
1141 tmp |= UTIL_PIN_DIRECTION_INPUT;
1142 tmp |= UTIL_PIN_ENABLE;
1143 } else {
1144 tmp &= ~UTIL_PIN_ENABLE;
1145 }
1146 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1147}
1148
1149static void
1150gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1151 const struct intel_crtc_state *crtc_state)
1152{
1153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1154
1155 /* step 4a: power up all lanes of the DDI used by DSI */
1156 gen11_dsi_power_up_lanes(encoder);
1157
1158 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1159 gen11_dsi_config_phy_lanes_sequence(encoder);
1160
1161 /* step 4c: configure voltage swing and skew */
1162 gen11_dsi_voltage_swing_program_seq(encoder);
1163
1164 /* enable DDI buffer */
1165 gen11_dsi_enable_ddi_buffer(encoder);
1166
1167 /* setup D-PHY timings */
1168 gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1169
1170 /* Since transcoder is configured to take events from GPIO */
1171 gen11_dsi_config_util_pin(encoder, true);
1172
1173 /* step 4h: setup DSI protocol timeouts */
1174 gen11_dsi_setup_timeouts(encoder, crtc_state);
1175
1176 /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1177 gen11_dsi_configure_transcoder(encoder, crtc_state);
1178
1179 /* Step 4l: Gate DDI clocks */
1180 if (DISPLAY_VER(dev_priv) == 11)
1181 gen11_dsi_gate_clocks(encoder);
1182}
1183
1184static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1185{
1186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1187 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1188 struct mipi_dsi_device *dsi;
1189 enum port port;
1190 enum transcoder dsi_trans;
1191 u32 tmp;
1192 int ret;
1193
1194 /* set maximum return packet size */
1195 for_each_dsi_port(port, intel_dsi->ports) {
1196 dsi_trans = dsi_port_to_transcoder(port);
1197
1198 /*
1199 * FIXME: This uses the number of DW's currently in the payload
1200 * receive queue. This is probably not what we want here.
1201 */
1202 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1203 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1204 /* multiply "Number Rx Payload DW" by 4 to get max value */
1205 tmp = tmp * 4;
1206 dsi = intel_dsi->dsi_hosts[port]->device;
1207 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1208 if (ret < 0)
1209 drm_err(&dev_priv->drm,
1210 "error setting max return pkt size%d\n", tmp);
1211 }
1212
1213 /* panel power on related mipi dsi vbt sequences */
1214 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1215 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
1216 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1217 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1218 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1219
1220 /* ensure all panel commands dispatched before enabling transcoder */
1221 wait_for_cmds_dispatched_to_panel(encoder);
1222}
1223
1224static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1225 struct intel_encoder *encoder,
1226 const struct intel_crtc_state *crtc_state,
1227 const struct drm_connector_state *conn_state)
1228{
1229 /* step2: enable IO power */
1230 gen11_dsi_enable_io_power(encoder);
1231
1232 /* step3: enable DSI PLL */
1233 gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1234}
1235
1236static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1237 struct intel_encoder *encoder,
1238 const struct intel_crtc_state *pipe_config,
1239 const struct drm_connector_state *conn_state)
1240{
1241 /* step3b */
1242 gen11_dsi_map_pll(encoder, pipe_config);
1243
1244 /* step4: enable DSI port and DPHY */
1245 gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1246
1247 /* step5: program and powerup panel */
1248 gen11_dsi_powerup_panel(encoder);
1249
1250 intel_dsc_enable(encoder, pipe_config);
1251
1252 /* step6c: configure transcoder timings */
1253 gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1254}
1255
1256/*
1257 * Wa_1409054076:icl,jsl,ehl
1258 * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1259 * the AMT KVMR feature will incorrectly see pipe A as enabled.
1260 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1261 * it set while DSI is enabled on pipe B
1262 */
1263static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1264 enum pipe pipe, bool enable)
1265{
1266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1267
1268 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
1269 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1270 IGNORE_KVMR_PIPE_A,
1271 enable ? IGNORE_KVMR_PIPE_A : 0);
1272}
1273static void gen11_dsi_enable(struct intel_atomic_state *state,
1274 struct intel_encoder *encoder,
1275 const struct intel_crtc_state *crtc_state,
1276 const struct drm_connector_state *conn_state)
1277{
1278 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1279 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
1280
1281 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
1282
1283 /* Wa_1409054076:icl,jsl,ehl */
1284 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
1285
1286 /* step6d: enable dsi transcoder */
1287 gen11_dsi_enable_transcoder(encoder);
1288
1289 /* step7: enable backlight */
1290 intel_panel_enable_backlight(crtc_state, conn_state);
1291 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1292
1293 intel_crtc_vblank_on(crtc_state);
1294}
1295
1296static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1297{
1298 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1299 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1300 enum port port;
1301 enum transcoder dsi_trans;
1302 u32 tmp;
1303
1304 for_each_dsi_port(port, intel_dsi->ports) {
1305 dsi_trans = dsi_port_to_transcoder(port);
1306
1307 /* disable transcoder */
1308 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1309 tmp &= ~PIPECONF_ENABLE;
1310 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1311
1312 /* wait for transcoder to be disabled */
1313 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1314 I965_PIPECONF_ACTIVE, 50))
1315 drm_err(&dev_priv->drm,
1316 "DSI trancoder not disabled\n");
1317 }
1318}
1319
1320static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1321{
1322 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1323
1324 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1325 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1326 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1327
1328 /* ensure cmds dispatched to panel */
1329 wait_for_cmds_dispatched_to_panel(encoder);
1330}
1331
1332static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1333{
1334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1335 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1336 enum port port;
1337 enum transcoder dsi_trans;
1338 u32 tmp;
1339
1340 /* disable periodic update mode */
1341 if (is_cmd_mode(intel_dsi)) {
1342 for_each_dsi_port(port, intel_dsi->ports) {
1343 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
1344 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
1345 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
1346 }
1347 }
1348
1349 /* put dsi link in ULPS */
1350 for_each_dsi_port(port, intel_dsi->ports) {
1351 dsi_trans = dsi_port_to_transcoder(port);
1352 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1353 tmp |= LINK_ENTER_ULPS;
1354 tmp &= ~LINK_ULPS_TYPE_LP11;
1355 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1356
1357 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1358 LINK_IN_ULPS),
1359 10))
1360 drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1361 }
1362
1363 /* disable ddi function */
1364 for_each_dsi_port(port, intel_dsi->ports) {
1365 dsi_trans = dsi_port_to_transcoder(port);
1366 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1367 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1368 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1369 }
1370
1371 /* disable port sync mode if dual link */
1372 if (intel_dsi->dual_link) {
1373 for_each_dsi_port(port, intel_dsi->ports) {
1374 dsi_trans = dsi_port_to_transcoder(port);
1375 tmp = intel_de_read(dev_priv,
1376 TRANS_DDI_FUNC_CTL2(dsi_trans));
1377 tmp &= ~PORT_SYNC_MODE_ENABLE;
1378 intel_de_write(dev_priv,
1379 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1380 }
1381 }
1382}
1383
1384static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1385{
1386 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1387 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1388 u32 tmp;
1389 enum port port;
1390
1391 gen11_dsi_ungate_clocks(encoder);
1392 for_each_dsi_port(port, intel_dsi->ports) {
1393 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1394 tmp &= ~DDI_BUF_CTL_ENABLE;
1395 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
1396
1397 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1398 DDI_BUF_IS_IDLE),
1399 8))
1400 drm_err(&dev_priv->drm,
1401 "DDI port:%c buffer not idle\n",
1402 port_name(port));
1403 }
1404 gen11_dsi_gate_clocks(encoder);
1405}
1406
1407static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1408{
1409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1410 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1411 enum port port;
1412 u32 tmp;
1413
1414 for_each_dsi_port(port, intel_dsi->ports) {
1415 intel_wakeref_t wakeref;
1416
1417 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1418 intel_display_power_put(dev_priv,
1419 port == PORT_A ?
1420 POWER_DOMAIN_PORT_DDI_A_IO :
1421 POWER_DOMAIN_PORT_DDI_B_IO,
1422 wakeref);
1423 }
1424
1425 /* set mode to DDI */
1426 for_each_dsi_port(port, intel_dsi->ports) {
1427 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
1428 tmp &= ~COMBO_PHY_MODE_DSI;
1429 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
1430 }
1431}
1432
1433static void gen11_dsi_disable(struct intel_atomic_state *state,
1434 struct intel_encoder *encoder,
1435 const struct intel_crtc_state *old_crtc_state,
1436 const struct drm_connector_state *old_conn_state)
1437{
1438 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1439 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc);
1440
1441 /* step1: turn off backlight */
1442 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1443 intel_panel_disable_backlight(old_conn_state);
1444
1445 /* step2d,e: disable transcoder and wait */
1446 gen11_dsi_disable_transcoder(encoder);
1447
1448 /* Wa_1409054076:icl,jsl,ehl */
1449 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
1450
1451 /* step2f,g: powerdown panel */
1452 gen11_dsi_powerdown_panel(encoder);
1453
1454 /* step2h,i,j: deconfig trancoder */
1455 gen11_dsi_deconfigure_trancoder(encoder);
1456
1457 /* step3: disable port */
1458 gen11_dsi_disable_port(encoder);
1459
1460 gen11_dsi_config_util_pin(encoder, false);
1461
1462 /* step4: disable IO power */
1463 gen11_dsi_disable_io_power(encoder);
1464}
1465
1466static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1467 struct intel_encoder *encoder,
1468 const struct intel_crtc_state *old_crtc_state,
1469 const struct drm_connector_state *old_conn_state)
1470{
1471 intel_crtc_vblank_off(old_crtc_state);
1472
1473 intel_dsc_disable(old_crtc_state);
1474
1475 skl_scaler_disable(old_crtc_state);
1476}
1477
1478static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1479 struct drm_display_mode *mode)
1480{
1481 /* FIXME: DSC? */
1482 return intel_dsi_mode_valid(connector, mode);
1483}
1484
1485static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1486 struct intel_crtc_state *pipe_config)
1487{
1488 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1489 struct drm_display_mode *adjusted_mode =
1490 &pipe_config->hw.adjusted_mode;
1491
1492 if (pipe_config->dsc.compressed_bpp) {
1493 int div = pipe_config->dsc.compressed_bpp;
1494 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1495
1496 adjusted_mode->crtc_htotal =
1497 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1498 adjusted_mode->crtc_hsync_start =
1499 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1500 adjusted_mode->crtc_hsync_end =
1501 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1502 }
1503
1504 if (intel_dsi->dual_link) {
1505 adjusted_mode->crtc_hdisplay *= 2;
1506 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1507 adjusted_mode->crtc_hdisplay -=
1508 intel_dsi->pixel_overlap;
1509 adjusted_mode->crtc_htotal *= 2;
1510 }
1511 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1512 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1513
1514 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1515 if (intel_dsi->dual_link) {
1516 adjusted_mode->crtc_hsync_start *= 2;
1517 adjusted_mode->crtc_hsync_end *= 2;
1518 }
1519 }
1520 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1521 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1522}
1523
1524static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1525{
1526 struct drm_device *dev = intel_dsi->base.base.dev;
1527 struct drm_i915_private *dev_priv = to_i915(dev);
1528 enum transcoder dsi_trans;
1529 u32 val;
1530
1531 if (intel_dsi->ports == BIT(PORT_B))
1532 dsi_trans = TRANSCODER_DSI_1;
1533 else
1534 dsi_trans = TRANSCODER_DSI_0;
1535
1536 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1537 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1538}
1539
1540static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1541 struct intel_crtc_state *pipe_config)
1542{
1543 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1544 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1545 I915_MODE_FLAG_DSI_USE_TE0;
1546 else if (intel_dsi->ports == BIT(PORT_B))
1547 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1548 else
1549 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1550}
1551
1552static void gen11_dsi_get_config(struct intel_encoder *encoder,
1553 struct intel_crtc_state *pipe_config)
1554{
1555 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1556 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1557
1558 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));
1559
1560 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1561 if (intel_dsi->dual_link)
1562 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1563
1564 gen11_dsi_get_timings(encoder, pipe_config);
1565 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1566 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1567
1568 /* Get the details on which TE should be enabled */
1569 if (is_cmd_mode(intel_dsi))
1570 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1571
1572 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1573 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1574}
1575
1576static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1577 const struct intel_crtc_state *crtc_state)
1578{
1579 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1580 struct intel_crtc *intel_crtc;
1581 enum pipe pipe;
1582
1583 if (!crtc_state)
1584 return;
1585
1586 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1587 pipe = intel_crtc->pipe;
1588
1589 /* wa verify 1409054076:icl,jsl,ehl */
1590 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
1591 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1592 drm_dbg_kms(&dev_priv->drm,
1593 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1594 encoder->base.base.id,
1595 encoder->base.name);
1596}
1597
1598static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1599 struct intel_crtc_state *crtc_state)
1600{
1601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1602 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1603 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
1604 bool use_dsc;
1605 int ret;
1606
1607 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1608 if (!use_dsc)
1609 return 0;
1610
1611 if (crtc_state->pipe_bpp < 8 * 3)
1612 return -EINVAL;
1613
1614 /* FIXME: split only when necessary */
1615 if (crtc_state->dsc.slice_count > 1)
1616 crtc_state->dsc.dsc_split = true;
1617
1618 vdsc_cfg->convert_rgb = true;
1619
1620 /* FIXME: initialize from VBT */
1621 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1622
1623 ret = intel_dsc_compute_params(encoder, crtc_state);
1624 if (ret)
1625 return ret;
1626
1627 /* DSI specific sanity checks on the common code */
1628 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1629 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1630 drm_WARN_ON(&dev_priv->drm,
1631 vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1632 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1633 drm_WARN_ON(&dev_priv->drm,
1634 vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1635
1636 ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1637 if (ret)
1638 return ret;
1639
1640 crtc_state->dsc.compression_enable = true;
1641
1642 return 0;
1643}
1644
1645static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1646 struct intel_crtc_state *pipe_config,
1647 struct drm_connector_state *conn_state)
1648{
1649 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1650 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1651 base);
1652 struct intel_connector *intel_connector = intel_dsi->attached_connector;
1653 const struct drm_display_mode *fixed_mode =
1654 intel_connector->panel.fixed_mode;
1655 struct drm_display_mode *adjusted_mode =
1656 &pipe_config->hw.adjusted_mode;
1657 int ret;
1658
1659 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1660 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
1661
1662 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1663 if (ret)
1664 return ret;
1665
1666 adjusted_mode->flags = 0;
1667
1668 /* Dual link goes to trancoder DSI'0' */
1669 if (intel_dsi->ports == BIT(PORT_B))
1670 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1671 else
1672 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1673
1674 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1675 pipe_config->pipe_bpp = 24;
1676 else
1677 pipe_config->pipe_bpp = 18;
1678
1679 pipe_config->clock_set = true;
1680
1681 if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1682 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1683
1684 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1685
1686 /*
1687 * In case of TE GATE cmd mode, we
1688 * receive TE from the slave if
1689 * dual link is enabled
1690 */
1691 if (is_cmd_mode(intel_dsi))
1692 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1693
1694 return 0;
1695}
1696
1697static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1698 struct intel_crtc_state *crtc_state)
1699{
1700 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1701
1702 get_dsi_io_power_domains(i915,
1703 enc_to_intel_dsi(encoder));
1704}
1705
1706static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1707 enum pipe *pipe)
1708{
1709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1710 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1711 enum transcoder dsi_trans;
1712 intel_wakeref_t wakeref;
1713 enum port port;
1714 bool ret = false;
1715 u32 tmp;
1716
1717 wakeref = intel_display_power_get_if_enabled(dev_priv,
1718 encoder->power_domain);
1719 if (!wakeref)
1720 return false;
1721
1722 for_each_dsi_port(port, intel_dsi->ports) {
1723 dsi_trans = dsi_port_to_transcoder(port);
1724 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1725 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1726 case TRANS_DDI_EDP_INPUT_A_ON:
1727 *pipe = PIPE_A;
1728 break;
1729 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1730 *pipe = PIPE_B;
1731 break;
1732 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1733 *pipe = PIPE_C;
1734 break;
1735 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1736 *pipe = PIPE_D;
1737 break;
1738 default:
1739 drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1740 goto out;
1741 }
1742
1743 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1744 ret = tmp & PIPECONF_ENABLE;
1745 }
1746out:
1747 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1748 return ret;
1749}
1750
1751static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1752 struct intel_crtc_state *crtc_state)
1753{
1754 if (crtc_state->dsc.compression_enable) {
1755 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1756 crtc_state->uapi.mode_changed = true;
1757
1758 return false;
1759 }
1760
1761 return true;
1762}
1763
1764static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1765{
1766 intel_encoder_destroy(encoder);
1767}
1768
1769static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1770 .destroy = gen11_dsi_encoder_destroy,
1771};
1772
1773static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1774 .detect = intel_panel_detect,
1775 .late_register = intel_connector_register,
1776 .early_unregister = intel_connector_unregister,
1777 .destroy = intel_connector_destroy,
1778 .fill_modes = drm_helper_probe_single_connector_modes,
1779 .atomic_get_property = intel_digital_connector_atomic_get_property,
1780 .atomic_set_property = intel_digital_connector_atomic_set_property,
1781 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1782 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1783};
1784
1785static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1786 .get_modes = intel_dsi_get_modes,
1787 .mode_valid = gen11_dsi_mode_valid,
1788 .atomic_check = intel_digital_connector_atomic_check,
1789};
1790
1791static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1792 struct mipi_dsi_device *dsi)
1793{
1794 return 0;
1795}
1796
1797static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1798 struct mipi_dsi_device *dsi)
1799{
1800 return 0;
1801}
1802
1803static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1804 const struct mipi_dsi_msg *msg)
1805{
1806 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1807 struct mipi_dsi_packet dsi_pkt;
1808 ssize_t ret;
1809 bool enable_lpdt = false;
1810
1811 ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1812 if (ret < 0)
1813 return ret;
1814
1815 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1816 enable_lpdt = true;
1817
1818 /* send packet header */
1819 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
1820 if (ret < 0)
1821 return ret;
1822
1823 /* only long packet contains payload */
1824 if (mipi_dsi_packet_format_is_long(msg->type)) {
1825 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
1826 if (ret < 0)
1827 return ret;
1828 }
1829
1830 //TODO: add payload receive code if needed
1831
1832 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1833
1834 return ret;
1835}
1836
1837static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1838 .attach = gen11_dsi_host_attach,
1839 .detach = gen11_dsi_host_detach,
1840 .transfer = gen11_dsi_host_transfer,
1841};
1842
1843#define ICL_PREPARE_CNT_MAX 0x7
1844#define ICL_CLK_ZERO_CNT_MAX 0xf
1845#define ICL_TRAIL_CNT_MAX 0x7
1846#define ICL_TCLK_PRE_CNT_MAX 0x3
1847#define ICL_TCLK_POST_CNT_MAX 0x7
1848#define ICL_HS_ZERO_CNT_MAX 0xf
1849#define ICL_EXIT_ZERO_CNT_MAX 0x7
1850
1851static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1852{
1853 struct drm_device *dev = intel_dsi->base.base.dev;
1854 struct drm_i915_private *dev_priv = to_i915(dev);
1855 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1856 u32 tlpx_ns;
1857 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1858 u32 ths_prepare_ns, tclk_trail_ns;
1859 u32 hs_zero_cnt;
1860 u32 tclk_pre_cnt, tclk_post_cnt;
1861
1862 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1863
1864 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1865 ths_prepare_ns = max(mipi_config->ths_prepare,
1866 mipi_config->tclk_prepare);
1867
1868 /*
1869 * prepare cnt in escape clocks
1870 * this field represents a hexadecimal value with a precision
1871 * of 1.2 – i.e. the most significant bit is the integer
1872 * and the least significant 2 bits are fraction bits.
1873 * so, the field can represent a range of 0.25 to 1.75
1874 */
1875 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1876 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1877 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1878 prepare_cnt);
1879 prepare_cnt = ICL_PREPARE_CNT_MAX;
1880 }
1881
1882 /* clk zero count in escape clocks */
1883 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1884 ths_prepare_ns, tlpx_ns);
1885 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1886 drm_dbg_kms(&dev_priv->drm,
1887 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1888 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1889 }
1890
1891 /* trail cnt in escape clocks*/
1892 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1893 if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1894 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1895 trail_cnt);
1896 trail_cnt = ICL_TRAIL_CNT_MAX;
1897 }
1898
1899 /* tclk pre count in escape clocks */
1900 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1901 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1902 drm_dbg_kms(&dev_priv->drm,
1903 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1904 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1905 }
1906
1907 /* tclk post count in escape clocks */
1908 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1909 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1910 drm_dbg_kms(&dev_priv->drm,
1911 "tclk_post_cnt out of range (%d)\n",
1912 tclk_post_cnt);
1913 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1914 }
1915
1916 /* hs zero cnt in escape clocks */
1917 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1918 ths_prepare_ns, tlpx_ns);
1919 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1920 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1921 hs_zero_cnt);
1922 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1923 }
1924
1925 /* hs exit zero cnt in escape clocks */
1926 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1927 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1928 drm_dbg_kms(&dev_priv->drm,
1929 "exit_zero_cnt out of range (%d)\n",
1930 exit_zero_cnt);
1931 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1932 }
1933
1934 /* clock lane dphy timings */
1935 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1936 CLK_PREPARE(prepare_cnt) |
1937 CLK_ZERO_OVERRIDE |
1938 CLK_ZERO(clk_zero_cnt) |
1939 CLK_PRE_OVERRIDE |
1940 CLK_PRE(tclk_pre_cnt) |
1941 CLK_POST_OVERRIDE |
1942 CLK_POST(tclk_post_cnt) |
1943 CLK_TRAIL_OVERRIDE |
1944 CLK_TRAIL(trail_cnt));
1945
1946 /* data lanes dphy timings */
1947 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1948 HS_PREPARE(prepare_cnt) |
1949 HS_ZERO_OVERRIDE |
1950 HS_ZERO(hs_zero_cnt) |
1951 HS_TRAIL_OVERRIDE |
1952 HS_TRAIL(trail_cnt) |
1953 HS_EXIT_OVERRIDE |
1954 HS_EXIT(exit_zero_cnt));
1955
1956 intel_dsi_log_params(intel_dsi);
1957}
1958
1959static void icl_dsi_add_properties(struct intel_connector *connector)
1960{
1961 u32 allowed_scalers;
1962
1963 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
1964 BIT(DRM_MODE_SCALE_FULLSCREEN) |
1965 BIT(DRM_MODE_SCALE_CENTER);
1966
1967 drm_connector_attach_scaling_mode_property(&connector->base,
1968 allowed_scalers);
1969
1970 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1971
1972 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1973 intel_dsi_get_panel_orientation(connector),
1974 connector->panel.fixed_mode->hdisplay,
1975 connector->panel.fixed_mode->vdisplay);
1976}
1977
1978void icl_dsi_init(struct drm_i915_private *dev_priv)
1979{
1980 struct drm_device *dev = &dev_priv->drm;
1981 struct intel_dsi *intel_dsi;
1982 struct intel_encoder *encoder;
1983 struct intel_connector *intel_connector;
1984 struct drm_connector *connector;
1985 struct drm_display_mode *fixed_mode;
1986 enum port port;
1987
1988 if (!intel_bios_is_dsi_present(dev_priv, &port))
1989 return;
1990
1991 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1992 if (!intel_dsi)
1993 return;
1994
1995 intel_connector = intel_connector_alloc();
1996 if (!intel_connector) {
1997 kfree(intel_dsi);
1998 return;
1999 }
2000
2001 encoder = &intel_dsi->base;
2002 intel_dsi->attached_connector = intel_connector;
2003 connector = &intel_connector->base;
2004
2005 /* register DSI encoder with DRM subsystem */
2006 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
2007 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
2008
2009 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
2010 encoder->pre_enable = gen11_dsi_pre_enable;
2011 encoder->enable = gen11_dsi_enable;
2012 encoder->disable = gen11_dsi_disable;
2013 encoder->post_disable = gen11_dsi_post_disable;
2014 encoder->port = port;
2015 encoder->get_config = gen11_dsi_get_config;
2016 encoder->sync_state = gen11_dsi_sync_state;
2017 encoder->update_pipe = intel_panel_update_backlight;
2018 encoder->compute_config = gen11_dsi_compute_config;
2019 encoder->get_hw_state = gen11_dsi_get_hw_state;
2020 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
2021 encoder->type = INTEL_OUTPUT_DSI;
2022 encoder->cloneable = 0;
2023 encoder->pipe_mask = ~0;
2024 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
2025 encoder->get_power_domains = gen11_dsi_get_power_domains;
2026 encoder->disable_clock = gen11_dsi_gate_clocks;
2027 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
2028
2029 /* register DSI connector with DRM subsystem */
2030 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
2031 DRM_MODE_CONNECTOR_DSI);
2032 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
2033 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2034 connector->interlace_allowed = false;
2035 connector->doublescan_allowed = false;
2036 intel_connector->get_hw_state = intel_connector_get_hw_state;
2037
2038 /* attach connector to encoder */
2039 intel_connector_attach_encoder(intel_connector, encoder);
2040
2041 mutex_lock(&dev->mode_config.mutex);
2042 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
2043 mutex_unlock(&dev->mode_config.mutex);
2044
2045 if (!fixed_mode) {
2046 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
2047 goto err;
2048 }
2049
2050 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
2051 intel_panel_setup_backlight(connector, INVALID_PIPE);
2052
2053 if (dev_priv->vbt.dsi.config->dual_link)
2054 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
2055 else
2056 intel_dsi->ports = BIT(port);
2057
2058 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
2059 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
2060
2061 for_each_dsi_port(port, intel_dsi->ports) {
2062 struct intel_dsi_host *host;
2063
2064 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
2065 if (!host)
2066 goto err;
2067
2068 intel_dsi->dsi_hosts[port] = host;
2069 }
2070
2071 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2072 drm_dbg_kms(&dev_priv->drm, "no device found\n");
2073 goto err;
2074 }
2075
2076 icl_dphy_param_init(intel_dsi);
2077
2078 icl_dsi_add_properties(intel_connector);
2079 return;
2080
2081err:
2082 drm_connector_cleanup(connector);
2083 drm_encoder_cleanup(&encoder->base);
2084 kfree(intel_dsi);
2085 kfree(intel_connector);
2086}