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1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "cikd.h"
29
30#include "bif/bif_4_1_d.h"
31#include "bif/bif_4_1_sh_mask.h"
32
33#include "oss/oss_2_0_d.h"
34#include "oss/oss_2_0_sh_mask.h"
35
36/*
37 * Interrupts
38 * Starting with r6xx, interrupts are handled via a ring buffer.
39 * Ring buffers are areas of GPU accessible memory that the GPU
40 * writes interrupt vectors into and the host reads vectors out of.
41 * There is a rptr (read pointer) that determines where the
42 * host is currently reading, and a wptr (write pointer)
43 * which determines where the GPU has written. When the
44 * pointers are equal, the ring is idle. When the GPU
45 * writes vectors to the ring buffer, it increments the
46 * wptr. When there is an interrupt, the host then starts
47 * fetching commands and processing them until the pointers are
48 * equal again at which point it updates the rptr.
49 */
50
51static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
52
53/**
54 * cik_ih_enable_interrupts - Enable the interrupt ring buffer
55 *
56 * @adev: amdgpu_device pointer
57 *
58 * Enable the interrupt ring buffer (CIK).
59 */
60static void cik_ih_enable_interrupts(struct amdgpu_device *adev)
61{
62 u32 ih_cntl = RREG32(mmIH_CNTL);
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
64
65 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK;
66 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK;
67 WREG32(mmIH_CNTL, ih_cntl);
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
69 adev->irq.ih.enabled = true;
70}
71
72/**
73 * cik_ih_disable_interrupts - Disable the interrupt ring buffer
74 *
75 * @adev: amdgpu_device pointer
76 *
77 * Disable the interrupt ring buffer (CIK).
78 */
79static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
80{
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
82 u32 ih_cntl = RREG32(mmIH_CNTL);
83
84 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK;
85 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK;
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
87 WREG32(mmIH_CNTL, ih_cntl);
88 /* set rptr, wptr to 0 */
89 WREG32(mmIH_RB_RPTR, 0);
90 WREG32(mmIH_RB_WPTR, 0);
91 adev->irq.ih.enabled = false;
92 adev->irq.ih.rptr = 0;
93}
94
95/**
96 * cik_ih_irq_init - init and enable the interrupt ring
97 *
98 * @adev: amdgpu_device pointer
99 *
100 * Allocate a ring buffer for the interrupt controller,
101 * enable the RLC, disable interrupts, enable the IH
102 * ring buffer and enable it (CIK).
103 * Called at device load and reume.
104 * Returns 0 for success, errors for failure.
105 */
106static int cik_ih_irq_init(struct amdgpu_device *adev)
107{
108 struct amdgpu_ih_ring *ih = &adev->irq.ih;
109 int rb_bufsz;
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
111
112 /* disable irqs */
113 cik_ih_disable_interrupts(adev);
114
115 /* setup interrupt control */
116 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
118 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
119 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
120 */
121 interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK;
122 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
123 interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK;
124 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
125
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
128
129 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK |
130 IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK |
131 (rb_bufsz << 1));
132
133 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
134
135 /* set the writeback address whether it's enabled or not */
136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
138
139 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
140
141 /* set rptr, wptr to 0 */
142 WREG32(mmIH_RB_RPTR, 0);
143 WREG32(mmIH_RB_WPTR, 0);
144
145 /* Default settings for IH_CNTL (disabled at first) */
146 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) |
147 (0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) |
148 (0 << IH_CNTL__MC_VMID__SHIFT);
149 /* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
150 if (adev->irq.msi_enabled)
151 ih_cntl |= IH_CNTL__RPTR_REARM_MASK;
152 WREG32(mmIH_CNTL, ih_cntl);
153
154 pci_set_master(adev->pdev);
155
156 /* enable irqs */
157 cik_ih_enable_interrupts(adev);
158
159 return 0;
160}
161
162/**
163 * cik_ih_irq_disable - disable interrupts
164 *
165 * @adev: amdgpu_device pointer
166 *
167 * Disable interrupts on the hw (CIK).
168 */
169static void cik_ih_irq_disable(struct amdgpu_device *adev)
170{
171 cik_ih_disable_interrupts(adev);
172 /* Wait and acknowledge irq */
173 mdelay(1);
174}
175
176/**
177 * cik_ih_get_wptr - get the IH ring buffer wptr
178 *
179 * @adev: amdgpu_device pointer
180 * @ih: IH ring buffer to fetch wptr
181 *
182 * Get the IH ring buffer wptr from either the register
183 * or the writeback memory buffer (CIK). Also check for
184 * ring buffer overflow and deal with it.
185 * Used by cik_irq_process().
186 * Returns the value of the wptr.
187 */
188static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
189 struct amdgpu_ih_ring *ih)
190{
191 u32 wptr, tmp;
192
193 wptr = le32_to_cpu(*ih->wptr_cpu);
194
195 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
196 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
197 /* When a ring buffer overflow happen start parsing interrupt
198 * from the last not overwritten vector (wptr + 16). Hopefully
199 * this should allow us to catchup.
200 */
201 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
203 ih->rptr = (wptr + 16) & ih->ptr_mask;
204 tmp = RREG32(mmIH_RB_CNTL);
205 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
206 WREG32(mmIH_RB_CNTL, tmp);
207 }
208 return (wptr & ih->ptr_mask);
209}
210
211/* CIK IV Ring
212 * Each IV ring entry is 128 bits:
213 * [7:0] - interrupt source id
214 * [31:8] - reserved
215 * [59:32] - interrupt source data
216 * [63:60] - reserved
217 * [71:64] - RINGID
218 * CP:
219 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
220 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
221 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
222 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
223 * PIPE_ID - ME0 0=3D
224 * - ME1&2 compute dispatcher (4 pipes each)
225 * SDMA:
226 * INSTANCE_ID [1:0], QUEUE_ID[1:0]
227 * INSTANCE_ID - 0 = sdma0, 1 = sdma1
228 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
229 * [79:72] - VMID
230 * [95:80] - PASID
231 * [127:96] - reserved
232 */
233
234 /**
235 * cik_ih_decode_iv - decode an interrupt vector
236 *
237 * @adev: amdgpu_device pointer
238 *
239 * Decodes the interrupt vector at the current rptr
240 * position and also advance the position.
241 */
242static void cik_ih_decode_iv(struct amdgpu_device *adev,
243 struct amdgpu_ih_ring *ih,
244 struct amdgpu_iv_entry *entry)
245{
246 /* wptr/rptr are in bytes! */
247 u32 ring_index = ih->rptr >> 2;
248 uint32_t dw[4];
249
250 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
251 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
252 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
253 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
254
255 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
256 entry->src_id = dw[0] & 0xff;
257 entry->src_data[0] = dw[1] & 0xfffffff;
258 entry->ring_id = dw[2] & 0xff;
259 entry->vmid = (dw[2] >> 8) & 0xff;
260 entry->pasid = (dw[2] >> 16) & 0xffff;
261
262 /* wptr/rptr are in bytes! */
263 ih->rptr += 16;
264}
265
266/**
267 * cik_ih_set_rptr - set the IH ring buffer rptr
268 *
269 * @adev: amdgpu_device pointer
270 * @ih: IH ring buffer to set wptr
271 *
272 * Set the IH ring buffer rptr.
273 */
274static void cik_ih_set_rptr(struct amdgpu_device *adev,
275 struct amdgpu_ih_ring *ih)
276{
277 WREG32(mmIH_RB_RPTR, ih->rptr);
278}
279
280static int cik_ih_early_init(void *handle)
281{
282 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
283 int ret;
284
285 ret = amdgpu_irq_add_domain(adev);
286 if (ret)
287 return ret;
288
289 cik_ih_set_interrupt_funcs(adev);
290
291 return 0;
292}
293
294static int cik_ih_sw_init(void *handle)
295{
296 int r;
297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
298
299 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
300 if (r)
301 return r;
302
303 r = amdgpu_irq_init(adev);
304
305 return r;
306}
307
308static int cik_ih_sw_fini(void *handle)
309{
310 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
311
312 amdgpu_irq_fini_sw(adev);
313 amdgpu_irq_remove_domain(adev);
314
315 return 0;
316}
317
318static int cik_ih_hw_init(void *handle)
319{
320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
321
322 return cik_ih_irq_init(adev);
323}
324
325static int cik_ih_hw_fini(void *handle)
326{
327 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
328
329 cik_ih_irq_disable(adev);
330
331 return 0;
332}
333
334static int cik_ih_suspend(void *handle)
335{
336 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
337
338 return cik_ih_hw_fini(adev);
339}
340
341static int cik_ih_resume(void *handle)
342{
343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
344
345 return cik_ih_hw_init(adev);
346}
347
348static bool cik_ih_is_idle(void *handle)
349{
350 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
351 u32 tmp = RREG32(mmSRBM_STATUS);
352
353 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
354 return false;
355
356 return true;
357}
358
359static int cik_ih_wait_for_idle(void *handle)
360{
361 unsigned i;
362 u32 tmp;
363 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
364
365 for (i = 0; i < adev->usec_timeout; i++) {
366 /* read MC_STATUS */
367 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
368 if (!tmp)
369 return 0;
370 udelay(1);
371 }
372 return -ETIMEDOUT;
373}
374
375static int cik_ih_soft_reset(void *handle)
376{
377 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
378
379 u32 srbm_soft_reset = 0;
380 u32 tmp = RREG32(mmSRBM_STATUS);
381
382 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
383 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
384
385 if (srbm_soft_reset) {
386 tmp = RREG32(mmSRBM_SOFT_RESET);
387 tmp |= srbm_soft_reset;
388 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
389 WREG32(mmSRBM_SOFT_RESET, tmp);
390 tmp = RREG32(mmSRBM_SOFT_RESET);
391
392 udelay(50);
393
394 tmp &= ~srbm_soft_reset;
395 WREG32(mmSRBM_SOFT_RESET, tmp);
396 tmp = RREG32(mmSRBM_SOFT_RESET);
397
398 /* Wait a little for things to settle down */
399 udelay(50);
400 }
401
402 return 0;
403}
404
405static int cik_ih_set_clockgating_state(void *handle,
406 enum amd_clockgating_state state)
407{
408 return 0;
409}
410
411static int cik_ih_set_powergating_state(void *handle,
412 enum amd_powergating_state state)
413{
414 return 0;
415}
416
417static const struct amd_ip_funcs cik_ih_ip_funcs = {
418 .name = "cik_ih",
419 .early_init = cik_ih_early_init,
420 .late_init = NULL,
421 .sw_init = cik_ih_sw_init,
422 .sw_fini = cik_ih_sw_fini,
423 .hw_init = cik_ih_hw_init,
424 .hw_fini = cik_ih_hw_fini,
425 .suspend = cik_ih_suspend,
426 .resume = cik_ih_resume,
427 .is_idle = cik_ih_is_idle,
428 .wait_for_idle = cik_ih_wait_for_idle,
429 .soft_reset = cik_ih_soft_reset,
430 .set_clockgating_state = cik_ih_set_clockgating_state,
431 .set_powergating_state = cik_ih_set_powergating_state,
432};
433
434static const struct amdgpu_ih_funcs cik_ih_funcs = {
435 .get_wptr = cik_ih_get_wptr,
436 .decode_iv = cik_ih_decode_iv,
437 .set_rptr = cik_ih_set_rptr
438};
439
440static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
441{
442 adev->irq.ih_funcs = &cik_ih_funcs;
443}
444
445const struct amdgpu_ip_block_version cik_ih_ip_block =
446{
447 .type = AMD_IP_BLOCK_TYPE_IH,
448 .major = 2,
449 .minor = 0,
450 .rev = 0,
451 .funcs = &cik_ih_ip_funcs,
452};
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <drm/drmP.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "cikd.h"
27
28#include "bif/bif_4_1_d.h"
29#include "bif/bif_4_1_sh_mask.h"
30
31#include "oss/oss_2_0_d.h"
32#include "oss/oss_2_0_sh_mask.h"
33
34/*
35 * Interrupts
36 * Starting with r6xx, interrupts are handled via a ring buffer.
37 * Ring buffers are areas of GPU accessible memory that the GPU
38 * writes interrupt vectors into and the host reads vectors out of.
39 * There is a rptr (read pointer) that determines where the
40 * host is currently reading, and a wptr (write pointer)
41 * which determines where the GPU has written. When the
42 * pointers are equal, the ring is idle. When the GPU
43 * writes vectors to the ring buffer, it increments the
44 * wptr. When there is an interrupt, the host then starts
45 * fetching commands and processing them until the pointers are
46 * equal again at which point it updates the rptr.
47 */
48
49static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
50
51/**
52 * cik_ih_enable_interrupts - Enable the interrupt ring buffer
53 *
54 * @adev: amdgpu_device pointer
55 *
56 * Enable the interrupt ring buffer (CIK).
57 */
58static void cik_ih_enable_interrupts(struct amdgpu_device *adev)
59{
60 u32 ih_cntl = RREG32(mmIH_CNTL);
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
62
63 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK;
64 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK;
65 WREG32(mmIH_CNTL, ih_cntl);
66 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
67 adev->irq.ih.enabled = true;
68}
69
70/**
71 * cik_ih_disable_interrupts - Disable the interrupt ring buffer
72 *
73 * @adev: amdgpu_device pointer
74 *
75 * Disable the interrupt ring buffer (CIK).
76 */
77static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
78{
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
80 u32 ih_cntl = RREG32(mmIH_CNTL);
81
82 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK;
83 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK;
84 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
85 WREG32(mmIH_CNTL, ih_cntl);
86 /* set rptr, wptr to 0 */
87 WREG32(mmIH_RB_RPTR, 0);
88 WREG32(mmIH_RB_WPTR, 0);
89 adev->irq.ih.enabled = false;
90 adev->irq.ih.rptr = 0;
91}
92
93/**
94 * cik_ih_irq_init - init and enable the interrupt ring
95 *
96 * @adev: amdgpu_device pointer
97 *
98 * Allocate a ring buffer for the interrupt controller,
99 * enable the RLC, disable interrupts, enable the IH
100 * ring buffer and enable it (CIK).
101 * Called at device load and reume.
102 * Returns 0 for success, errors for failure.
103 */
104static int cik_ih_irq_init(struct amdgpu_device *adev)
105{
106 int rb_bufsz;
107 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
108 u64 wptr_off;
109
110 /* disable irqs */
111 cik_ih_disable_interrupts(adev);
112
113 /* setup interrupt control */
114 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
116 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
117 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
118 */
119 interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK;
120 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
121 interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK;
122 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
123
124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
126
127 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK |
128 IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK |
129 (rb_bufsz << 1));
130
131 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
132
133 /* set the writeback address whether it's enabled or not */
134 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
135 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
136 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
137
138 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
139
140 /* set rptr, wptr to 0 */
141 WREG32(mmIH_RB_RPTR, 0);
142 WREG32(mmIH_RB_WPTR, 0);
143
144 /* Default settings for IH_CNTL (disabled at first) */
145 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) |
146 (0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) |
147 (0 << IH_CNTL__MC_VMID__SHIFT);
148 /* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
149 if (adev->irq.msi_enabled)
150 ih_cntl |= IH_CNTL__RPTR_REARM_MASK;
151 WREG32(mmIH_CNTL, ih_cntl);
152
153 pci_set_master(adev->pdev);
154
155 /* enable irqs */
156 cik_ih_enable_interrupts(adev);
157
158 return 0;
159}
160
161/**
162 * cik_ih_irq_disable - disable interrupts
163 *
164 * @adev: amdgpu_device pointer
165 *
166 * Disable interrupts on the hw (CIK).
167 */
168static void cik_ih_irq_disable(struct amdgpu_device *adev)
169{
170 cik_ih_disable_interrupts(adev);
171 /* Wait and acknowledge irq */
172 mdelay(1);
173}
174
175/**
176 * cik_ih_get_wptr - get the IH ring buffer wptr
177 *
178 * @adev: amdgpu_device pointer
179 *
180 * Get the IH ring buffer wptr from either the register
181 * or the writeback memory buffer (CIK). Also check for
182 * ring buffer overflow and deal with it.
183 * Used by cik_irq_process().
184 * Returns the value of the wptr.
185 */
186static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
187{
188 u32 wptr, tmp;
189
190 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
191
192 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
193 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
194 /* When a ring buffer overflow happen start parsing interrupt
195 * from the last not overwritten vector (wptr + 16). Hopefully
196 * this should allow us to catchup.
197 */
198 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
199 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
200 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
201 tmp = RREG32(mmIH_RB_CNTL);
202 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
203 WREG32(mmIH_RB_CNTL, tmp);
204 }
205 return (wptr & adev->irq.ih.ptr_mask);
206}
207
208/* CIK IV Ring
209 * Each IV ring entry is 128 bits:
210 * [7:0] - interrupt source id
211 * [31:8] - reserved
212 * [59:32] - interrupt source data
213 * [63:60] - reserved
214 * [71:64] - RINGID
215 * CP:
216 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
217 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
218 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
219 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
220 * PIPE_ID - ME0 0=3D
221 * - ME1&2 compute dispatcher (4 pipes each)
222 * SDMA:
223 * INSTANCE_ID [1:0], QUEUE_ID[1:0]
224 * INSTANCE_ID - 0 = sdma0, 1 = sdma1
225 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
226 * [79:72] - VMID
227 * [95:80] - PASID
228 * [127:96] - reserved
229 */
230
231/**
232 * cik_ih_prescreen_iv - prescreen an interrupt vector
233 *
234 * @adev: amdgpu_device pointer
235 *
236 * Returns true if the interrupt vector should be further processed.
237 */
238static bool cik_ih_prescreen_iv(struct amdgpu_device *adev)
239{
240 u32 ring_index = adev->irq.ih.rptr >> 2;
241 u16 pasid;
242
243 switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
244 case 146:
245 case 147:
246 pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
247 if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
248 return true;
249 break;
250 default:
251 /* Not a VM fault */
252 return true;
253 }
254
255 adev->irq.ih.rptr += 16;
256 return false;
257}
258
259 /**
260 * cik_ih_decode_iv - decode an interrupt vector
261 *
262 * @adev: amdgpu_device pointer
263 *
264 * Decodes the interrupt vector at the current rptr
265 * position and also advance the position.
266 */
267static void cik_ih_decode_iv(struct amdgpu_device *adev,
268 struct amdgpu_iv_entry *entry)
269{
270 /* wptr/rptr are in bytes! */
271 u32 ring_index = adev->irq.ih.rptr >> 2;
272 uint32_t dw[4];
273
274 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
275 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
276 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
277 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
278
279 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
280 entry->src_id = dw[0] & 0xff;
281 entry->src_data[0] = dw[1] & 0xfffffff;
282 entry->ring_id = dw[2] & 0xff;
283 entry->vmid = (dw[2] >> 8) & 0xff;
284 entry->pasid = (dw[2] >> 16) & 0xffff;
285
286 /* wptr/rptr are in bytes! */
287 adev->irq.ih.rptr += 16;
288}
289
290/**
291 * cik_ih_set_rptr - set the IH ring buffer rptr
292 *
293 * @adev: amdgpu_device pointer
294 *
295 * Set the IH ring buffer rptr.
296 */
297static void cik_ih_set_rptr(struct amdgpu_device *adev)
298{
299 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
300}
301
302static int cik_ih_early_init(void *handle)
303{
304 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
305 int ret;
306
307 ret = amdgpu_irq_add_domain(adev);
308 if (ret)
309 return ret;
310
311 cik_ih_set_interrupt_funcs(adev);
312
313 return 0;
314}
315
316static int cik_ih_sw_init(void *handle)
317{
318 int r;
319 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
320
321 r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
322 if (r)
323 return r;
324
325 r = amdgpu_irq_init(adev);
326
327 return r;
328}
329
330static int cik_ih_sw_fini(void *handle)
331{
332 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
333
334 amdgpu_irq_fini(adev);
335 amdgpu_ih_ring_fini(adev);
336 amdgpu_irq_remove_domain(adev);
337
338 return 0;
339}
340
341static int cik_ih_hw_init(void *handle)
342{
343 int r;
344 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
345
346 r = cik_ih_irq_init(adev);
347 if (r)
348 return r;
349
350 return 0;
351}
352
353static int cik_ih_hw_fini(void *handle)
354{
355 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
356
357 cik_ih_irq_disable(adev);
358
359 return 0;
360}
361
362static int cik_ih_suspend(void *handle)
363{
364 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
365
366 return cik_ih_hw_fini(adev);
367}
368
369static int cik_ih_resume(void *handle)
370{
371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
372
373 return cik_ih_hw_init(adev);
374}
375
376static bool cik_ih_is_idle(void *handle)
377{
378 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
379 u32 tmp = RREG32(mmSRBM_STATUS);
380
381 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
382 return false;
383
384 return true;
385}
386
387static int cik_ih_wait_for_idle(void *handle)
388{
389 unsigned i;
390 u32 tmp;
391 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
392
393 for (i = 0; i < adev->usec_timeout; i++) {
394 /* read MC_STATUS */
395 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
396 if (!tmp)
397 return 0;
398 udelay(1);
399 }
400 return -ETIMEDOUT;
401}
402
403static int cik_ih_soft_reset(void *handle)
404{
405 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
406
407 u32 srbm_soft_reset = 0;
408 u32 tmp = RREG32(mmSRBM_STATUS);
409
410 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
411 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
412
413 if (srbm_soft_reset) {
414 tmp = RREG32(mmSRBM_SOFT_RESET);
415 tmp |= srbm_soft_reset;
416 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
417 WREG32(mmSRBM_SOFT_RESET, tmp);
418 tmp = RREG32(mmSRBM_SOFT_RESET);
419
420 udelay(50);
421
422 tmp &= ~srbm_soft_reset;
423 WREG32(mmSRBM_SOFT_RESET, tmp);
424 tmp = RREG32(mmSRBM_SOFT_RESET);
425
426 /* Wait a little for things to settle down */
427 udelay(50);
428 }
429
430 return 0;
431}
432
433static int cik_ih_set_clockgating_state(void *handle,
434 enum amd_clockgating_state state)
435{
436 return 0;
437}
438
439static int cik_ih_set_powergating_state(void *handle,
440 enum amd_powergating_state state)
441{
442 return 0;
443}
444
445static const struct amd_ip_funcs cik_ih_ip_funcs = {
446 .name = "cik_ih",
447 .early_init = cik_ih_early_init,
448 .late_init = NULL,
449 .sw_init = cik_ih_sw_init,
450 .sw_fini = cik_ih_sw_fini,
451 .hw_init = cik_ih_hw_init,
452 .hw_fini = cik_ih_hw_fini,
453 .suspend = cik_ih_suspend,
454 .resume = cik_ih_resume,
455 .is_idle = cik_ih_is_idle,
456 .wait_for_idle = cik_ih_wait_for_idle,
457 .soft_reset = cik_ih_soft_reset,
458 .set_clockgating_state = cik_ih_set_clockgating_state,
459 .set_powergating_state = cik_ih_set_powergating_state,
460};
461
462static const struct amdgpu_ih_funcs cik_ih_funcs = {
463 .get_wptr = cik_ih_get_wptr,
464 .prescreen_iv = cik_ih_prescreen_iv,
465 .decode_iv = cik_ih_decode_iv,
466 .set_rptr = cik_ih_set_rptr
467};
468
469static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
470{
471 if (adev->irq.ih_funcs == NULL)
472 adev->irq.ih_funcs = &cik_ih_funcs;
473}
474
475const struct amdgpu_ip_block_version cik_ih_ip_block =
476{
477 .type = AMD_IP_BLOCK_TYPE_IH,
478 .major = 2,
479 .minor = 0,
480 .rev = 0,
481 .funcs = &cik_ih_ip_funcs,
482};