Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 Texas Instruments
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#ifndef __TILCDC_DRV_H__
8#define __TILCDC_DRV_H__
9
10#include <linux/cpufreq.h>
11#include <linux/irqreturn.h>
12
13#include <drm/drm_print.h>
14
15struct clk;
16struct workqueue_struct;
17
18struct drm_connector;
19struct drm_connector_helper_funcs;
20struct drm_crtc;
21struct drm_device;
22struct drm_display_mode;
23struct drm_encoder;
24struct drm_framebuffer;
25struct drm_minor;
26struct drm_pending_vblank_event;
27struct drm_plane;
28
29/* Defaulting to pixel clock defined on AM335x */
30#define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000
31/* Maximum display width for LCDC V1 */
32#define TILCDC_DEFAULT_MAX_WIDTH_V1 1024
33/* ... and for LCDC V2 found on AM335x: */
34#define TILCDC_DEFAULT_MAX_WIDTH_V2 2048
35/*
36 * This may need some tweaking, but want to allow at least 1280x1024@60
37 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
38 * be supportable
39 */
40#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
41
42
43struct tilcdc_drm_private {
44 void __iomem *mmio;
45
46 struct clk *clk; /* functional clock */
47 int rev; /* IP revision */
48
49 /* don't attempt resolutions w/ higher W * H * Hz: */
50 uint32_t max_bandwidth;
51 /*
52 * Pixel Clock will be restricted to some value as
53 * defined in the device datasheet measured in KHz
54 */
55 uint32_t max_pixelclock;
56 /*
57 * Max allowable width is limited on a per device basis
58 * measured in pixels
59 */
60 uint32_t max_width;
61
62 /* Supported pixel formats */
63 const uint32_t *pixelformats;
64 uint32_t num_pixelformats;
65
66#ifdef CONFIG_CPU_FREQ
67 struct notifier_block freq_transition;
68#endif
69
70 struct workqueue_struct *wq;
71
72 struct drm_crtc *crtc;
73
74 unsigned int num_encoders;
75 struct drm_encoder *encoders[8];
76
77 unsigned int num_connectors;
78 struct drm_connector *connectors[8];
79
80 struct drm_encoder *external_encoder;
81 struct drm_connector *external_connector;
82
83 bool is_registered;
84 bool is_componentized;
85};
86
87/* Sub-module for display. Since we don't know at compile time what panels
88 * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
89 * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
90 * separate drivers. If they are probed and found to be present, they
91 * register themselves with tilcdc_register_module().
92 */
93struct tilcdc_module;
94
95struct tilcdc_module_ops {
96 /* create appropriate encoders/connectors: */
97 int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
98#ifdef CONFIG_DEBUG_FS
99 /* create debugfs nodes (can be NULL): */
100 int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
101#endif
102};
103
104struct tilcdc_module {
105 const char *name;
106 struct list_head list;
107 const struct tilcdc_module_ops *funcs;
108};
109
110void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
111 const struct tilcdc_module_ops *funcs);
112void tilcdc_module_cleanup(struct tilcdc_module *mod);
113
114/* Panel config that needs to be set in the crtc, but is not coming from
115 * the mode timings. The display module is expected to call
116 * tilcdc_crtc_set_panel_info() to set this during modeset.
117 */
118struct tilcdc_panel_info {
119
120 /* AC Bias Pin Frequency */
121 uint32_t ac_bias;
122
123 /* AC Bias Pin Transitions per Interrupt */
124 uint32_t ac_bias_intrpt;
125
126 /* DMA burst size */
127 uint32_t dma_burst_sz;
128
129 /* Bits per pixel */
130 uint32_t bpp;
131
132 /* FIFO DMA Request Delay */
133 uint32_t fdd;
134
135 /* TFT Alternative Signal Mapping (Only for active) */
136 bool tft_alt_mode;
137
138 /* Invert pixel clock */
139 bool invert_pxl_clk;
140
141 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
142 uint32_t sync_edge;
143
144 /* Horizontal and Vertical Sync: Control: 0=ignore */
145 uint32_t sync_ctrl;
146
147 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
148 uint32_t raster_order;
149
150 /* DMA FIFO threshold */
151 uint32_t fifo_th;
152};
153
154#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
155
156int tilcdc_crtc_create(struct drm_device *dev);
157irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
158void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
159void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
160 const struct tilcdc_panel_info *info);
161void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
162 bool simulate_vesa_sync);
163void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
164int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
165 struct drm_framebuffer *fb,
166 struct drm_pending_vblank_event *event);
167
168int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
169
170#endif /* __TILCDC_DRV_H__ */
1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __TILCDC_DRV_H__
19#define __TILCDC_DRV_H__
20
21#include <linux/clk.h>
22#include <linux/cpufreq.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/pm.h>
26#include <linux/pm_runtime.h>
27#include <linux/slab.h>
28#include <linux/of.h>
29#include <linux/of_device.h>
30#include <linux/list.h>
31
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_gem_cma_helper.h>
35#include <drm/drm_fb_cma_helper.h>
36#include <drm/drm_bridge.h>
37
38/* Defaulting to pixel clock defined on AM335x */
39#define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000
40/* Defaulting to max width as defined on AM335x */
41#define TILCDC_DEFAULT_MAX_WIDTH 2048
42/*
43 * This may need some tweaking, but want to allow at least 1280x1024@60
44 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
45 * be supportable
46 */
47#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
48
49
50struct tilcdc_drm_private {
51 void __iomem *mmio;
52
53 struct clk *clk; /* functional clock */
54 int rev; /* IP revision */
55
56 /* don't attempt resolutions w/ higher W * H * Hz: */
57 uint32_t max_bandwidth;
58 /*
59 * Pixel Clock will be restricted to some value as
60 * defined in the device datasheet measured in KHz
61 */
62 uint32_t max_pixelclock;
63 /*
64 * Max allowable width is limited on a per device basis
65 * measured in pixels
66 */
67 uint32_t max_width;
68
69 /* Supported pixel formats */
70 const uint32_t *pixelformats;
71 uint32_t num_pixelformats;
72
73 /* The context for pm susped/resume cycle is stored here */
74 struct drm_atomic_state *saved_state;
75
76#ifdef CONFIG_CPU_FREQ
77 struct notifier_block freq_transition;
78#endif
79
80 struct workqueue_struct *wq;
81
82 struct drm_fbdev_cma *fbdev;
83
84 struct drm_crtc *crtc;
85
86 unsigned int num_encoders;
87 struct drm_encoder *encoders[8];
88
89 unsigned int num_connectors;
90 struct drm_connector *connectors[8];
91
92 struct drm_encoder *external_encoder;
93 struct drm_connector *external_connector;
94 const struct drm_connector_helper_funcs *connector_funcs;
95
96 bool is_registered;
97 bool is_componentized;
98};
99
100/* Sub-module for display. Since we don't know at compile time what panels
101 * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
102 * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
103 * separate drivers. If they are probed and found to be present, they
104 * register themselves with tilcdc_register_module().
105 */
106struct tilcdc_module;
107
108struct tilcdc_module_ops {
109 /* create appropriate encoders/connectors: */
110 int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
111#ifdef CONFIG_DEBUG_FS
112 /* create debugfs nodes (can be NULL): */
113 int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
114 /* cleanup debugfs nodes (can be NULL): */
115 void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor);
116#endif
117};
118
119struct tilcdc_module {
120 const char *name;
121 struct list_head list;
122 const struct tilcdc_module_ops *funcs;
123};
124
125void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
126 const struct tilcdc_module_ops *funcs);
127void tilcdc_module_cleanup(struct tilcdc_module *mod);
128
129/* Panel config that needs to be set in the crtc, but is not coming from
130 * the mode timings. The display module is expected to call
131 * tilcdc_crtc_set_panel_info() to set this during modeset.
132 */
133struct tilcdc_panel_info {
134
135 /* AC Bias Pin Frequency */
136 uint32_t ac_bias;
137
138 /* AC Bias Pin Transitions per Interrupt */
139 uint32_t ac_bias_intrpt;
140
141 /* DMA burst size */
142 uint32_t dma_burst_sz;
143
144 /* Bits per pixel */
145 uint32_t bpp;
146
147 /* FIFO DMA Request Delay */
148 uint32_t fdd;
149
150 /* TFT Alternative Signal Mapping (Only for active) */
151 bool tft_alt_mode;
152
153 /* Invert pixel clock */
154 bool invert_pxl_clk;
155
156 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
157 uint32_t sync_edge;
158
159 /* Horizontal and Vertical Sync: Control: 0=ignore */
160 uint32_t sync_ctrl;
161
162 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
163 uint32_t raster_order;
164
165 /* DMA FIFO threshold */
166 uint32_t fifo_th;
167};
168
169#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
170
171int tilcdc_crtc_create(struct drm_device *dev);
172irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
173void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
174void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
175 const struct tilcdc_panel_info *info);
176void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
177 bool simulate_vesa_sync);
178int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
179int tilcdc_crtc_max_width(struct drm_crtc *crtc);
180void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
181int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
182 struct drm_framebuffer *fb,
183 struct drm_pending_vblank_event *event);
184
185int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
186
187#endif /* __TILCDC_DRV_H__ */