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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7/* LCDC DRM driver, based on da8xx-fb */
8
9#include <linux/component.h>
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/pinctrl/consumer.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_debugfs.h>
18#include <drm/drm_drv.h>
19#include <drm/drm_fb_helper.h>
20#include <drm/drm_fourcc.h>
21#include <drm/drm_gem_cma_helper.h>
22#include <drm/drm_gem_framebuffer_helper.h>
23#include <drm/drm_irq.h>
24#include <drm/drm_mm.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_vblank.h>
27
28
29#include "tilcdc_drv.h"
30#include "tilcdc_external.h"
31#include "tilcdc_panel.h"
32#include "tilcdc_regs.h"
33
34static LIST_HEAD(module_list);
35
36static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
37
38static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
39 DRM_FORMAT_BGR888,
40 DRM_FORMAT_XBGR8888 };
41
42static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
43 DRM_FORMAT_RGB888,
44 DRM_FORMAT_XRGB8888 };
45
46static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
47 DRM_FORMAT_RGB888,
48 DRM_FORMAT_XRGB8888 };
49
50void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
51 const struct tilcdc_module_ops *funcs)
52{
53 mod->name = name;
54 mod->funcs = funcs;
55 INIT_LIST_HEAD(&mod->list);
56 list_add(&mod->list, &module_list);
57}
58
59void tilcdc_module_cleanup(struct tilcdc_module *mod)
60{
61 list_del(&mod->list);
62}
63
64static struct of_device_id tilcdc_of_match[];
65
66static int tilcdc_atomic_check(struct drm_device *dev,
67 struct drm_atomic_state *state)
68{
69 int ret;
70
71 ret = drm_atomic_helper_check_modeset(dev, state);
72 if (ret)
73 return ret;
74
75 ret = drm_atomic_helper_check_planes(dev, state);
76 if (ret)
77 return ret;
78
79 /*
80 * tilcdc ->atomic_check can update ->mode_changed if pixel format
81 * changes, hence will we check modeset changes again.
82 */
83 ret = drm_atomic_helper_check_modeset(dev, state);
84 if (ret)
85 return ret;
86
87 return ret;
88}
89
90static const struct drm_mode_config_funcs mode_config_funcs = {
91 .fb_create = drm_gem_fb_create,
92 .atomic_check = tilcdc_atomic_check,
93 .atomic_commit = drm_atomic_helper_commit,
94};
95
96static void modeset_init(struct drm_device *dev)
97{
98 struct tilcdc_drm_private *priv = dev->dev_private;
99 struct tilcdc_module *mod;
100
101 list_for_each_entry(mod, &module_list, list) {
102 DBG("loading module: %s", mod->name);
103 mod->funcs->modeset_init(mod, dev);
104 }
105
106 dev->mode_config.min_width = 0;
107 dev->mode_config.min_height = 0;
108 dev->mode_config.max_width = priv->max_width;
109 dev->mode_config.max_height = 2048;
110 dev->mode_config.funcs = &mode_config_funcs;
111}
112
113#ifdef CONFIG_CPU_FREQ
114static int cpufreq_transition(struct notifier_block *nb,
115 unsigned long val, void *data)
116{
117 struct tilcdc_drm_private *priv = container_of(nb,
118 struct tilcdc_drm_private, freq_transition);
119
120 if (val == CPUFREQ_POSTCHANGE)
121 tilcdc_crtc_update_clk(priv->crtc);
122
123 return 0;
124}
125#endif
126
127/*
128 * DRM operations:
129 */
130
131static void tilcdc_fini(struct drm_device *dev)
132{
133 struct tilcdc_drm_private *priv = dev->dev_private;
134
135#ifdef CONFIG_CPU_FREQ
136 if (priv->freq_transition.notifier_call)
137 cpufreq_unregister_notifier(&priv->freq_transition,
138 CPUFREQ_TRANSITION_NOTIFIER);
139#endif
140
141 if (priv->crtc)
142 tilcdc_crtc_shutdown(priv->crtc);
143
144 if (priv->is_registered)
145 drm_dev_unregister(dev);
146
147 drm_kms_helper_poll_fini(dev);
148 drm_irq_uninstall(dev);
149 drm_mode_config_cleanup(dev);
150
151 if (priv->clk)
152 clk_put(priv->clk);
153
154 if (priv->mmio)
155 iounmap(priv->mmio);
156
157 if (priv->wq) {
158 flush_workqueue(priv->wq);
159 destroy_workqueue(priv->wq);
160 }
161
162 dev->dev_private = NULL;
163
164 pm_runtime_disable(dev->dev);
165
166 drm_dev_put(dev);
167}
168
169static int tilcdc_init(const struct drm_driver *ddrv, struct device *dev)
170{
171 struct drm_device *ddev;
172 struct platform_device *pdev = to_platform_device(dev);
173 struct device_node *node = dev->of_node;
174 struct tilcdc_drm_private *priv;
175 struct resource *res;
176 u32 bpp = 0;
177 int ret;
178
179 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
180 if (!priv)
181 return -ENOMEM;
182
183 ddev = drm_dev_alloc(ddrv, dev);
184 if (IS_ERR(ddev))
185 return PTR_ERR(ddev);
186
187 ddev->dev_private = priv;
188 platform_set_drvdata(pdev, ddev);
189 drm_mode_config_init(ddev);
190
191 priv->is_componentized =
192 tilcdc_get_external_components(dev, NULL) > 0;
193
194 priv->wq = alloc_ordered_workqueue("tilcdc", 0);
195 if (!priv->wq) {
196 ret = -ENOMEM;
197 goto init_failed;
198 }
199
200 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
201 if (!res) {
202 dev_err(dev, "failed to get memory resource\n");
203 ret = -EINVAL;
204 goto init_failed;
205 }
206
207 priv->mmio = ioremap(res->start, resource_size(res));
208 if (!priv->mmio) {
209 dev_err(dev, "failed to ioremap\n");
210 ret = -ENOMEM;
211 goto init_failed;
212 }
213
214 priv->clk = clk_get(dev, "fck");
215 if (IS_ERR(priv->clk)) {
216 dev_err(dev, "failed to get functional clock\n");
217 ret = -ENODEV;
218 goto init_failed;
219 }
220
221 pm_runtime_enable(dev);
222
223 /* Determine LCD IP Version */
224 pm_runtime_get_sync(dev);
225 switch (tilcdc_read(ddev, LCDC_PID_REG)) {
226 case 0x4c100102:
227 priv->rev = 1;
228 break;
229 case 0x4f200800:
230 case 0x4f201000:
231 priv->rev = 2;
232 break;
233 default:
234 dev_warn(dev, "Unknown PID Reg value 0x%08x, "
235 "defaulting to LCD revision 1\n",
236 tilcdc_read(ddev, LCDC_PID_REG));
237 priv->rev = 1;
238 break;
239 }
240
241 pm_runtime_put_sync(dev);
242
243 if (priv->rev == 1) {
244 DBG("Revision 1 LCDC supports only RGB565 format");
245 priv->pixelformats = tilcdc_rev1_formats;
246 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
247 bpp = 16;
248 } else {
249 const char *str = "\0";
250
251 of_property_read_string(node, "blue-and-red-wiring", &str);
252 if (0 == strcmp(str, "crossed")) {
253 DBG("Configured for crossed blue and red wires");
254 priv->pixelformats = tilcdc_crossed_formats;
255 priv->num_pixelformats =
256 ARRAY_SIZE(tilcdc_crossed_formats);
257 bpp = 32; /* Choose bpp with RGB support for fbdef */
258 } else if (0 == strcmp(str, "straight")) {
259 DBG("Configured for straight blue and red wires");
260 priv->pixelformats = tilcdc_straight_formats;
261 priv->num_pixelformats =
262 ARRAY_SIZE(tilcdc_straight_formats);
263 bpp = 16; /* Choose bpp with RGB support for fbdef */
264 } else {
265 DBG("Blue and red wiring '%s' unknown, use legacy mode",
266 str);
267 priv->pixelformats = tilcdc_legacy_formats;
268 priv->num_pixelformats =
269 ARRAY_SIZE(tilcdc_legacy_formats);
270 bpp = 16; /* This is just a guess */
271 }
272 }
273
274 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
275 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
276
277 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
278
279 if (of_property_read_u32(node, "max-width", &priv->max_width)) {
280 if (priv->rev == 1)
281 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V1;
282 else
283 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V2;
284 }
285
286 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
287
288 if (of_property_read_u32(node, "max-pixelclock",
289 &priv->max_pixelclock))
290 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
291
292 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
293
294 ret = tilcdc_crtc_create(ddev);
295 if (ret < 0) {
296 dev_err(dev, "failed to create crtc\n");
297 goto init_failed;
298 }
299 modeset_init(ddev);
300
301#ifdef CONFIG_CPU_FREQ
302 priv->freq_transition.notifier_call = cpufreq_transition;
303 ret = cpufreq_register_notifier(&priv->freq_transition,
304 CPUFREQ_TRANSITION_NOTIFIER);
305 if (ret) {
306 dev_err(dev, "failed to register cpufreq notifier\n");
307 priv->freq_transition.notifier_call = NULL;
308 goto init_failed;
309 }
310#endif
311
312 if (priv->is_componentized) {
313 ret = component_bind_all(dev, ddev);
314 if (ret < 0)
315 goto init_failed;
316
317 ret = tilcdc_add_component_encoder(ddev);
318 if (ret < 0)
319 goto init_failed;
320 } else {
321 ret = tilcdc_attach_external_device(ddev);
322 if (ret)
323 goto init_failed;
324 }
325
326 if (!priv->external_connector &&
327 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
328 dev_err(dev, "no encoders/connectors found\n");
329 ret = -EPROBE_DEFER;
330 goto init_failed;
331 }
332
333 ret = drm_vblank_init(ddev, 1);
334 if (ret < 0) {
335 dev_err(dev, "failed to initialize vblank\n");
336 goto init_failed;
337 }
338
339 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
340 if (ret < 0) {
341 dev_err(dev, "failed to install IRQ handler\n");
342 goto init_failed;
343 }
344
345 drm_mode_config_reset(ddev);
346
347 drm_kms_helper_poll_init(ddev);
348
349 ret = drm_dev_register(ddev, 0);
350 if (ret)
351 goto init_failed;
352 priv->is_registered = true;
353
354 drm_fbdev_generic_setup(ddev, bpp);
355 return 0;
356
357init_failed:
358 tilcdc_fini(ddev);
359
360 return ret;
361}
362
363static irqreturn_t tilcdc_irq(int irq, void *arg)
364{
365 struct drm_device *dev = arg;
366 struct tilcdc_drm_private *priv = dev->dev_private;
367 return tilcdc_crtc_irq(priv->crtc);
368}
369
370#if defined(CONFIG_DEBUG_FS)
371static const struct {
372 const char *name;
373 uint8_t rev;
374 uint8_t save;
375 uint32_t reg;
376} registers[] = {
377#define REG(rev, save, reg) { #reg, rev, save, reg }
378 /* exists in revision 1: */
379 REG(1, false, LCDC_PID_REG),
380 REG(1, true, LCDC_CTRL_REG),
381 REG(1, false, LCDC_STAT_REG),
382 REG(1, true, LCDC_RASTER_CTRL_REG),
383 REG(1, true, LCDC_RASTER_TIMING_0_REG),
384 REG(1, true, LCDC_RASTER_TIMING_1_REG),
385 REG(1, true, LCDC_RASTER_TIMING_2_REG),
386 REG(1, true, LCDC_DMA_CTRL_REG),
387 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
388 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
389 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
390 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
391 /* new in revision 2: */
392 REG(2, false, LCDC_RAW_STAT_REG),
393 REG(2, false, LCDC_MASKED_STAT_REG),
394 REG(2, true, LCDC_INT_ENABLE_SET_REG),
395 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
396 REG(2, false, LCDC_END_OF_INT_IND_REG),
397 REG(2, true, LCDC_CLK_ENABLE_REG),
398#undef REG
399};
400
401#endif
402
403#ifdef CONFIG_DEBUG_FS
404static int tilcdc_regs_show(struct seq_file *m, void *arg)
405{
406 struct drm_info_node *node = (struct drm_info_node *) m->private;
407 struct drm_device *dev = node->minor->dev;
408 struct tilcdc_drm_private *priv = dev->dev_private;
409 unsigned i;
410
411 pm_runtime_get_sync(dev->dev);
412
413 seq_printf(m, "revision: %d\n", priv->rev);
414
415 for (i = 0; i < ARRAY_SIZE(registers); i++)
416 if (priv->rev >= registers[i].rev)
417 seq_printf(m, "%s:\t %08x\n", registers[i].name,
418 tilcdc_read(dev, registers[i].reg));
419
420 pm_runtime_put_sync(dev->dev);
421
422 return 0;
423}
424
425static int tilcdc_mm_show(struct seq_file *m, void *arg)
426{
427 struct drm_info_node *node = (struct drm_info_node *) m->private;
428 struct drm_device *dev = node->minor->dev;
429 struct drm_printer p = drm_seq_file_printer(m);
430 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
431 return 0;
432}
433
434static struct drm_info_list tilcdc_debugfs_list[] = {
435 { "regs", tilcdc_regs_show, 0, NULL },
436 { "mm", tilcdc_mm_show, 0, NULL },
437};
438
439static void tilcdc_debugfs_init(struct drm_minor *minor)
440{
441 struct tilcdc_module *mod;
442
443 drm_debugfs_create_files(tilcdc_debugfs_list,
444 ARRAY_SIZE(tilcdc_debugfs_list),
445 minor->debugfs_root, minor);
446
447 list_for_each_entry(mod, &module_list, list)
448 if (mod->funcs->debugfs_init)
449 mod->funcs->debugfs_init(mod, minor);
450}
451#endif
452
453DEFINE_DRM_GEM_CMA_FOPS(fops);
454
455static const struct drm_driver tilcdc_driver = {
456 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
457 .irq_handler = tilcdc_irq,
458 DRM_GEM_CMA_DRIVER_OPS,
459#ifdef CONFIG_DEBUG_FS
460 .debugfs_init = tilcdc_debugfs_init,
461#endif
462 .fops = &fops,
463 .name = "tilcdc",
464 .desc = "TI LCD Controller DRM",
465 .date = "20121205",
466 .major = 1,
467 .minor = 0,
468};
469
470/*
471 * Power management:
472 */
473
474#ifdef CONFIG_PM_SLEEP
475static int tilcdc_pm_suspend(struct device *dev)
476{
477 struct drm_device *ddev = dev_get_drvdata(dev);
478 int ret = 0;
479
480 ret = drm_mode_config_helper_suspend(ddev);
481
482 /* Select sleep pin state */
483 pinctrl_pm_select_sleep_state(dev);
484
485 return ret;
486}
487
488static int tilcdc_pm_resume(struct device *dev)
489{
490 struct drm_device *ddev = dev_get_drvdata(dev);
491
492 /* Select default pin state */
493 pinctrl_pm_select_default_state(dev);
494 return drm_mode_config_helper_resume(ddev);
495}
496#endif
497
498static const struct dev_pm_ops tilcdc_pm_ops = {
499 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
500};
501
502/*
503 * Platform driver:
504 */
505static int tilcdc_bind(struct device *dev)
506{
507 return tilcdc_init(&tilcdc_driver, dev);
508}
509
510static void tilcdc_unbind(struct device *dev)
511{
512 struct drm_device *ddev = dev_get_drvdata(dev);
513
514 /* Check if a subcomponent has already triggered the unloading. */
515 if (!ddev->dev_private)
516 return;
517
518 tilcdc_fini(dev_get_drvdata(dev));
519}
520
521static const struct component_master_ops tilcdc_comp_ops = {
522 .bind = tilcdc_bind,
523 .unbind = tilcdc_unbind,
524};
525
526static int tilcdc_pdev_probe(struct platform_device *pdev)
527{
528 struct component_match *match = NULL;
529 int ret;
530
531 /* bail out early if no DT data: */
532 if (!pdev->dev.of_node) {
533 dev_err(&pdev->dev, "device-tree data is missing\n");
534 return -ENXIO;
535 }
536
537 ret = tilcdc_get_external_components(&pdev->dev, &match);
538 if (ret < 0)
539 return ret;
540 else if (ret == 0)
541 return tilcdc_init(&tilcdc_driver, &pdev->dev);
542 else
543 return component_master_add_with_match(&pdev->dev,
544 &tilcdc_comp_ops,
545 match);
546}
547
548static int tilcdc_pdev_remove(struct platform_device *pdev)
549{
550 int ret;
551
552 ret = tilcdc_get_external_components(&pdev->dev, NULL);
553 if (ret < 0)
554 return ret;
555 else if (ret == 0)
556 tilcdc_fini(platform_get_drvdata(pdev));
557 else
558 component_master_del(&pdev->dev, &tilcdc_comp_ops);
559
560 return 0;
561}
562
563static struct of_device_id tilcdc_of_match[] = {
564 { .compatible = "ti,am33xx-tilcdc", },
565 { .compatible = "ti,da850-tilcdc", },
566 { },
567};
568MODULE_DEVICE_TABLE(of, tilcdc_of_match);
569
570static struct platform_driver tilcdc_platform_driver = {
571 .probe = tilcdc_pdev_probe,
572 .remove = tilcdc_pdev_remove,
573 .driver = {
574 .name = "tilcdc",
575 .pm = &tilcdc_pm_ops,
576 .of_match_table = tilcdc_of_match,
577 },
578};
579
580static int __init tilcdc_drm_init(void)
581{
582 DBG("init");
583 tilcdc_panel_init();
584 return platform_driver_register(&tilcdc_platform_driver);
585}
586
587static void __exit tilcdc_drm_fini(void)
588{
589 DBG("fini");
590 platform_driver_unregister(&tilcdc_platform_driver);
591 tilcdc_panel_fini();
592}
593
594module_init(tilcdc_drm_init);
595module_exit(tilcdc_drm_fini);
596
597MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
598MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
599MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/* LCDC DRM driver, based on da8xx-fb */
19
20#include <linux/component.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/suspend.h>
23#include <drm/drm_atomic.h>
24#include <drm/drm_atomic_helper.h>
25
26#include "tilcdc_drv.h"
27#include "tilcdc_regs.h"
28#include "tilcdc_tfp410.h"
29#include "tilcdc_panel.h"
30#include "tilcdc_external.h"
31
32#include "drm_fb_helper.h"
33
34static LIST_HEAD(module_list);
35
36static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
37
38static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
39 DRM_FORMAT_BGR888,
40 DRM_FORMAT_XBGR8888 };
41
42static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
43 DRM_FORMAT_RGB888,
44 DRM_FORMAT_XRGB8888 };
45
46static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
47 DRM_FORMAT_RGB888,
48 DRM_FORMAT_XRGB8888 };
49
50void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
51 const struct tilcdc_module_ops *funcs)
52{
53 mod->name = name;
54 mod->funcs = funcs;
55 INIT_LIST_HEAD(&mod->list);
56 list_add(&mod->list, &module_list);
57}
58
59void tilcdc_module_cleanup(struct tilcdc_module *mod)
60{
61 list_del(&mod->list);
62}
63
64static struct of_device_id tilcdc_of_match[];
65
66static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
67 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
68{
69 return drm_fb_cma_create(dev, file_priv, mode_cmd);
70}
71
72static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
73{
74 struct tilcdc_drm_private *priv = dev->dev_private;
75 drm_fbdev_cma_hotplug_event(priv->fbdev);
76}
77
78static int tilcdc_atomic_check(struct drm_device *dev,
79 struct drm_atomic_state *state)
80{
81 int ret;
82
83 ret = drm_atomic_helper_check_modeset(dev, state);
84 if (ret)
85 return ret;
86
87 ret = drm_atomic_helper_check_planes(dev, state);
88 if (ret)
89 return ret;
90
91 /*
92 * tilcdc ->atomic_check can update ->mode_changed if pixel format
93 * changes, hence will we check modeset changes again.
94 */
95 ret = drm_atomic_helper_check_modeset(dev, state);
96 if (ret)
97 return ret;
98
99 return ret;
100}
101
102static int tilcdc_commit(struct drm_device *dev,
103 struct drm_atomic_state *state,
104 bool async)
105{
106 int ret;
107
108 ret = drm_atomic_helper_prepare_planes(dev, state);
109 if (ret)
110 return ret;
111
112 drm_atomic_helper_swap_state(state, true);
113
114 /*
115 * Everything below can be run asynchronously without the need to grab
116 * any modeset locks at all under one condition: It must be guaranteed
117 * that the asynchronous work has either been cancelled (if the driver
118 * supports it, which at least requires that the framebuffers get
119 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
120 * before the new state gets committed on the software side with
121 * drm_atomic_helper_swap_state().
122 *
123 * This scheme allows new atomic state updates to be prepared and
124 * checked in parallel to the asynchronous completion of the previous
125 * update. Which is important since compositors need to figure out the
126 * composition of the next frame right after having submitted the
127 * current layout.
128 */
129
130 drm_atomic_helper_commit_modeset_disables(dev, state);
131
132 drm_atomic_helper_commit_planes(dev, state, 0);
133
134 drm_atomic_helper_commit_modeset_enables(dev, state);
135
136 drm_atomic_helper_wait_for_vblanks(dev, state);
137
138 drm_atomic_helper_cleanup_planes(dev, state);
139
140 return 0;
141}
142
143static const struct drm_mode_config_funcs mode_config_funcs = {
144 .fb_create = tilcdc_fb_create,
145 .output_poll_changed = tilcdc_fb_output_poll_changed,
146 .atomic_check = tilcdc_atomic_check,
147 .atomic_commit = tilcdc_commit,
148};
149
150static void modeset_init(struct drm_device *dev)
151{
152 struct tilcdc_drm_private *priv = dev->dev_private;
153 struct tilcdc_module *mod;
154
155 list_for_each_entry(mod, &module_list, list) {
156 DBG("loading module: %s", mod->name);
157 mod->funcs->modeset_init(mod, dev);
158 }
159
160 dev->mode_config.min_width = 0;
161 dev->mode_config.min_height = 0;
162 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
163 dev->mode_config.max_height = 2048;
164 dev->mode_config.funcs = &mode_config_funcs;
165}
166
167#ifdef CONFIG_CPU_FREQ
168static int cpufreq_transition(struct notifier_block *nb,
169 unsigned long val, void *data)
170{
171 struct tilcdc_drm_private *priv = container_of(nb,
172 struct tilcdc_drm_private, freq_transition);
173
174 if (val == CPUFREQ_POSTCHANGE)
175 tilcdc_crtc_update_clk(priv->crtc);
176
177 return 0;
178}
179#endif
180
181/*
182 * DRM operations:
183 */
184
185static void tilcdc_fini(struct drm_device *dev)
186{
187 struct tilcdc_drm_private *priv = dev->dev_private;
188
189 if (priv->crtc)
190 tilcdc_crtc_shutdown(priv->crtc);
191
192 if (priv->is_registered)
193 drm_dev_unregister(dev);
194
195 drm_kms_helper_poll_fini(dev);
196
197 if (priv->fbdev)
198 drm_fbdev_cma_fini(priv->fbdev);
199
200 drm_irq_uninstall(dev);
201 drm_mode_config_cleanup(dev);
202 tilcdc_remove_external_device(dev);
203
204#ifdef CONFIG_CPU_FREQ
205 if (priv->freq_transition.notifier_call)
206 cpufreq_unregister_notifier(&priv->freq_transition,
207 CPUFREQ_TRANSITION_NOTIFIER);
208#endif
209
210 if (priv->clk)
211 clk_put(priv->clk);
212
213 if (priv->mmio)
214 iounmap(priv->mmio);
215
216 if (priv->wq) {
217 flush_workqueue(priv->wq);
218 destroy_workqueue(priv->wq);
219 }
220
221 dev->dev_private = NULL;
222
223 pm_runtime_disable(dev->dev);
224
225 drm_dev_unref(dev);
226}
227
228static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
229{
230 struct drm_device *ddev;
231 struct platform_device *pdev = to_platform_device(dev);
232 struct device_node *node = dev->of_node;
233 struct tilcdc_drm_private *priv;
234 struct resource *res;
235 u32 bpp = 0;
236 int ret;
237
238 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
239 if (!priv) {
240 dev_err(dev, "failed to allocate private data\n");
241 return -ENOMEM;
242 }
243
244 ddev = drm_dev_alloc(ddrv, dev);
245 if (IS_ERR(ddev))
246 return PTR_ERR(ddev);
247
248 ddev->platformdev = pdev;
249 ddev->dev_private = priv;
250 platform_set_drvdata(pdev, ddev);
251 drm_mode_config_init(ddev);
252
253 priv->is_componentized =
254 tilcdc_get_external_components(dev, NULL) > 0;
255
256 priv->wq = alloc_ordered_workqueue("tilcdc", 0);
257 if (!priv->wq) {
258 ret = -ENOMEM;
259 goto init_failed;
260 }
261
262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
263 if (!res) {
264 dev_err(dev, "failed to get memory resource\n");
265 ret = -EINVAL;
266 goto init_failed;
267 }
268
269 priv->mmio = ioremap_nocache(res->start, resource_size(res));
270 if (!priv->mmio) {
271 dev_err(dev, "failed to ioremap\n");
272 ret = -ENOMEM;
273 goto init_failed;
274 }
275
276 priv->clk = clk_get(dev, "fck");
277 if (IS_ERR(priv->clk)) {
278 dev_err(dev, "failed to get functional clock\n");
279 ret = -ENODEV;
280 goto init_failed;
281 }
282
283#ifdef CONFIG_CPU_FREQ
284 priv->freq_transition.notifier_call = cpufreq_transition;
285 ret = cpufreq_register_notifier(&priv->freq_transition,
286 CPUFREQ_TRANSITION_NOTIFIER);
287 if (ret) {
288 dev_err(dev, "failed to register cpufreq notifier\n");
289 priv->freq_transition.notifier_call = NULL;
290 goto init_failed;
291 }
292#endif
293
294 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
295 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
296
297 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
298
299 if (of_property_read_u32(node, "max-width", &priv->max_width))
300 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
301
302 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
303
304 if (of_property_read_u32(node, "max-pixelclock",
305 &priv->max_pixelclock))
306 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
307
308 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
309
310 pm_runtime_enable(dev);
311
312 /* Determine LCD IP Version */
313 pm_runtime_get_sync(dev);
314 switch (tilcdc_read(ddev, LCDC_PID_REG)) {
315 case 0x4c100102:
316 priv->rev = 1;
317 break;
318 case 0x4f200800:
319 case 0x4f201000:
320 priv->rev = 2;
321 break;
322 default:
323 dev_warn(dev, "Unknown PID Reg value 0x%08x, "
324 "defaulting to LCD revision 1\n",
325 tilcdc_read(ddev, LCDC_PID_REG));
326 priv->rev = 1;
327 break;
328 }
329
330 pm_runtime_put_sync(dev);
331
332 if (priv->rev == 1) {
333 DBG("Revision 1 LCDC supports only RGB565 format");
334 priv->pixelformats = tilcdc_rev1_formats;
335 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
336 bpp = 16;
337 } else {
338 const char *str = "\0";
339
340 of_property_read_string(node, "blue-and-red-wiring", &str);
341 if (0 == strcmp(str, "crossed")) {
342 DBG("Configured for crossed blue and red wires");
343 priv->pixelformats = tilcdc_crossed_formats;
344 priv->num_pixelformats =
345 ARRAY_SIZE(tilcdc_crossed_formats);
346 bpp = 32; /* Choose bpp with RGB support for fbdef */
347 } else if (0 == strcmp(str, "straight")) {
348 DBG("Configured for straight blue and red wires");
349 priv->pixelformats = tilcdc_straight_formats;
350 priv->num_pixelformats =
351 ARRAY_SIZE(tilcdc_straight_formats);
352 bpp = 16; /* Choose bpp with RGB support for fbdef */
353 } else {
354 DBG("Blue and red wiring '%s' unknown, use legacy mode",
355 str);
356 priv->pixelformats = tilcdc_legacy_formats;
357 priv->num_pixelformats =
358 ARRAY_SIZE(tilcdc_legacy_formats);
359 bpp = 16; /* This is just a guess */
360 }
361 }
362
363 ret = tilcdc_crtc_create(ddev);
364 if (ret < 0) {
365 dev_err(dev, "failed to create crtc\n");
366 goto init_failed;
367 }
368 modeset_init(ddev);
369
370 if (priv->is_componentized) {
371 ret = component_bind_all(dev, ddev);
372 if (ret < 0)
373 goto init_failed;
374
375 ret = tilcdc_add_component_encoder(ddev);
376 if (ret < 0)
377 goto init_failed;
378 } else {
379 ret = tilcdc_attach_external_device(ddev);
380 if (ret)
381 goto init_failed;
382 }
383
384 if (!priv->external_connector &&
385 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
386 dev_err(dev, "no encoders/connectors found\n");
387 ret = -ENXIO;
388 goto init_failed;
389 }
390
391 ret = drm_vblank_init(ddev, 1);
392 if (ret < 0) {
393 dev_err(dev, "failed to initialize vblank\n");
394 goto init_failed;
395 }
396
397 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
398 if (ret < 0) {
399 dev_err(dev, "failed to install IRQ handler\n");
400 goto init_failed;
401 }
402
403 drm_mode_config_reset(ddev);
404
405 priv->fbdev = drm_fbdev_cma_init(ddev, bpp,
406 ddev->mode_config.num_crtc,
407 ddev->mode_config.num_connector);
408 if (IS_ERR(priv->fbdev)) {
409 ret = PTR_ERR(priv->fbdev);
410 goto init_failed;
411 }
412
413 drm_kms_helper_poll_init(ddev);
414
415 ret = drm_dev_register(ddev, 0);
416 if (ret)
417 goto init_failed;
418
419 priv->is_registered = true;
420 return 0;
421
422init_failed:
423 tilcdc_fini(ddev);
424
425 return ret;
426}
427
428static void tilcdc_lastclose(struct drm_device *dev)
429{
430 struct tilcdc_drm_private *priv = dev->dev_private;
431 drm_fbdev_cma_restore_mode(priv->fbdev);
432}
433
434static irqreturn_t tilcdc_irq(int irq, void *arg)
435{
436 struct drm_device *dev = arg;
437 struct tilcdc_drm_private *priv = dev->dev_private;
438 return tilcdc_crtc_irq(priv->crtc);
439}
440
441static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
442{
443 return 0;
444}
445
446static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
447{
448 return;
449}
450
451#if defined(CONFIG_DEBUG_FS)
452static const struct {
453 const char *name;
454 uint8_t rev;
455 uint8_t save;
456 uint32_t reg;
457} registers[] = {
458#define REG(rev, save, reg) { #reg, rev, save, reg }
459 /* exists in revision 1: */
460 REG(1, false, LCDC_PID_REG),
461 REG(1, true, LCDC_CTRL_REG),
462 REG(1, false, LCDC_STAT_REG),
463 REG(1, true, LCDC_RASTER_CTRL_REG),
464 REG(1, true, LCDC_RASTER_TIMING_0_REG),
465 REG(1, true, LCDC_RASTER_TIMING_1_REG),
466 REG(1, true, LCDC_RASTER_TIMING_2_REG),
467 REG(1, true, LCDC_DMA_CTRL_REG),
468 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
469 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
470 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
471 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
472 /* new in revision 2: */
473 REG(2, false, LCDC_RAW_STAT_REG),
474 REG(2, false, LCDC_MASKED_STAT_REG),
475 REG(2, true, LCDC_INT_ENABLE_SET_REG),
476 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
477 REG(2, false, LCDC_END_OF_INT_IND_REG),
478 REG(2, true, LCDC_CLK_ENABLE_REG),
479#undef REG
480};
481
482#endif
483
484#ifdef CONFIG_DEBUG_FS
485static int tilcdc_regs_show(struct seq_file *m, void *arg)
486{
487 struct drm_info_node *node = (struct drm_info_node *) m->private;
488 struct drm_device *dev = node->minor->dev;
489 struct tilcdc_drm_private *priv = dev->dev_private;
490 unsigned i;
491
492 pm_runtime_get_sync(dev->dev);
493
494 seq_printf(m, "revision: %d\n", priv->rev);
495
496 for (i = 0; i < ARRAY_SIZE(registers); i++)
497 if (priv->rev >= registers[i].rev)
498 seq_printf(m, "%s:\t %08x\n", registers[i].name,
499 tilcdc_read(dev, registers[i].reg));
500
501 pm_runtime_put_sync(dev->dev);
502
503 return 0;
504}
505
506static int tilcdc_mm_show(struct seq_file *m, void *arg)
507{
508 struct drm_info_node *node = (struct drm_info_node *) m->private;
509 struct drm_device *dev = node->minor->dev;
510 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
511}
512
513static struct drm_info_list tilcdc_debugfs_list[] = {
514 { "regs", tilcdc_regs_show, 0 },
515 { "mm", tilcdc_mm_show, 0 },
516 { "fb", drm_fb_cma_debugfs_show, 0 },
517};
518
519static int tilcdc_debugfs_init(struct drm_minor *minor)
520{
521 struct drm_device *dev = minor->dev;
522 struct tilcdc_module *mod;
523 int ret;
524
525 ret = drm_debugfs_create_files(tilcdc_debugfs_list,
526 ARRAY_SIZE(tilcdc_debugfs_list),
527 minor->debugfs_root, minor);
528
529 list_for_each_entry(mod, &module_list, list)
530 if (mod->funcs->debugfs_init)
531 mod->funcs->debugfs_init(mod, minor);
532
533 if (ret) {
534 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
535 return ret;
536 }
537
538 return ret;
539}
540
541static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
542{
543 struct tilcdc_module *mod;
544 drm_debugfs_remove_files(tilcdc_debugfs_list,
545 ARRAY_SIZE(tilcdc_debugfs_list), minor);
546
547 list_for_each_entry(mod, &module_list, list)
548 if (mod->funcs->debugfs_cleanup)
549 mod->funcs->debugfs_cleanup(mod, minor);
550}
551#endif
552
553static const struct file_operations fops = {
554 .owner = THIS_MODULE,
555 .open = drm_open,
556 .release = drm_release,
557 .unlocked_ioctl = drm_ioctl,
558 .compat_ioctl = drm_compat_ioctl,
559 .poll = drm_poll,
560 .read = drm_read,
561 .llseek = no_llseek,
562 .mmap = drm_gem_cma_mmap,
563};
564
565static struct drm_driver tilcdc_driver = {
566 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
567 DRIVER_PRIME | DRIVER_ATOMIC),
568 .lastclose = tilcdc_lastclose,
569 .irq_handler = tilcdc_irq,
570 .get_vblank_counter = drm_vblank_no_hw_counter,
571 .enable_vblank = tilcdc_enable_vblank,
572 .disable_vblank = tilcdc_disable_vblank,
573 .gem_free_object_unlocked = drm_gem_cma_free_object,
574 .gem_vm_ops = &drm_gem_cma_vm_ops,
575 .dumb_create = drm_gem_cma_dumb_create,
576 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
577 .dumb_destroy = drm_gem_dumb_destroy,
578
579 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
580 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
581 .gem_prime_import = drm_gem_prime_import,
582 .gem_prime_export = drm_gem_prime_export,
583 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
584 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
585 .gem_prime_vmap = drm_gem_cma_prime_vmap,
586 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
587 .gem_prime_mmap = drm_gem_cma_prime_mmap,
588#ifdef CONFIG_DEBUG_FS
589 .debugfs_init = tilcdc_debugfs_init,
590 .debugfs_cleanup = tilcdc_debugfs_cleanup,
591#endif
592 .fops = &fops,
593 .name = "tilcdc",
594 .desc = "TI LCD Controller DRM",
595 .date = "20121205",
596 .major = 1,
597 .minor = 0,
598};
599
600/*
601 * Power management:
602 */
603
604#ifdef CONFIG_PM_SLEEP
605static int tilcdc_pm_suspend(struct device *dev)
606{
607 struct drm_device *ddev = dev_get_drvdata(dev);
608 struct tilcdc_drm_private *priv = ddev->dev_private;
609
610 priv->saved_state = drm_atomic_helper_suspend(ddev);
611
612 /* Select sleep pin state */
613 pinctrl_pm_select_sleep_state(dev);
614
615 return 0;
616}
617
618static int tilcdc_pm_resume(struct device *dev)
619{
620 struct drm_device *ddev = dev_get_drvdata(dev);
621 struct tilcdc_drm_private *priv = ddev->dev_private;
622 int ret = 0;
623
624 /* Select default pin state */
625 pinctrl_pm_select_default_state(dev);
626
627 if (priv->saved_state)
628 ret = drm_atomic_helper_resume(ddev, priv->saved_state);
629
630 return ret;
631}
632#endif
633
634static const struct dev_pm_ops tilcdc_pm_ops = {
635 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
636};
637
638/*
639 * Platform driver:
640 */
641static int tilcdc_bind(struct device *dev)
642{
643 return tilcdc_init(&tilcdc_driver, dev);
644}
645
646static void tilcdc_unbind(struct device *dev)
647{
648 struct drm_device *ddev = dev_get_drvdata(dev);
649
650 /* Check if a subcomponent has already triggered the unloading. */
651 if (!ddev->dev_private)
652 return;
653
654 tilcdc_fini(dev_get_drvdata(dev));
655}
656
657static const struct component_master_ops tilcdc_comp_ops = {
658 .bind = tilcdc_bind,
659 .unbind = tilcdc_unbind,
660};
661
662static int tilcdc_pdev_probe(struct platform_device *pdev)
663{
664 struct component_match *match = NULL;
665 int ret;
666
667 /* bail out early if no DT data: */
668 if (!pdev->dev.of_node) {
669 dev_err(&pdev->dev, "device-tree data is missing\n");
670 return -ENXIO;
671 }
672
673 ret = tilcdc_get_external_components(&pdev->dev, &match);
674 if (ret < 0)
675 return ret;
676 else if (ret == 0)
677 return tilcdc_init(&tilcdc_driver, &pdev->dev);
678 else
679 return component_master_add_with_match(&pdev->dev,
680 &tilcdc_comp_ops,
681 match);
682}
683
684static int tilcdc_pdev_remove(struct platform_device *pdev)
685{
686 int ret;
687
688 ret = tilcdc_get_external_components(&pdev->dev, NULL);
689 if (ret < 0)
690 return ret;
691 else if (ret == 0)
692 tilcdc_fini(platform_get_drvdata(pdev));
693 else
694 component_master_del(&pdev->dev, &tilcdc_comp_ops);
695
696 return 0;
697}
698
699static struct of_device_id tilcdc_of_match[] = {
700 { .compatible = "ti,am33xx-tilcdc", },
701 { .compatible = "ti,da850-tilcdc", },
702 { },
703};
704MODULE_DEVICE_TABLE(of, tilcdc_of_match);
705
706static struct platform_driver tilcdc_platform_driver = {
707 .probe = tilcdc_pdev_probe,
708 .remove = tilcdc_pdev_remove,
709 .driver = {
710 .name = "tilcdc",
711 .pm = &tilcdc_pm_ops,
712 .of_match_table = tilcdc_of_match,
713 },
714};
715
716static int __init tilcdc_drm_init(void)
717{
718 DBG("init");
719 tilcdc_tfp410_init();
720 tilcdc_panel_init();
721 return platform_driver_register(&tilcdc_platform_driver);
722}
723
724static void __exit tilcdc_drm_fini(void)
725{
726 DBG("fini");
727 platform_driver_unregister(&tilcdc_platform_driver);
728 tilcdc_panel_fini();
729 tilcdc_tfp410_fini();
730}
731
732module_init(tilcdc_drm_init);
733module_exit(tilcdc_drm_fini);
734
735MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
736MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
737MODULE_LICENSE("GPL");