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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/drm_cache.h>
29#include "amdgpu.h"
30#include "gmc_v6_0.h"
31#include "amdgpu_ucode.h"
32#include "amdgpu_gem.h"
33
34#include "bif/bif_3_0_d.h"
35#include "bif/bif_3_0_sh_mask.h"
36#include "oss/oss_1_0_d.h"
37#include "oss/oss_1_0_sh_mask.h"
38#include "gmc/gmc_6_0_d.h"
39#include "gmc/gmc_6_0_sh_mask.h"
40#include "dce/dce_6_0_d.h"
41#include "dce/dce_6_0_sh_mask.h"
42#include "si_enums.h"
43
44static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
45static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
46static int gmc_v6_0_wait_for_idle(void *handle);
47
48MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
49MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
50MODULE_FIRMWARE("amdgpu/verde_mc.bin");
51MODULE_FIRMWARE("amdgpu/oland_mc.bin");
52MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
53MODULE_FIRMWARE("amdgpu/si58_mc.bin");
54
55#define MC_SEQ_MISC0__MT__MASK 0xf0000000
56#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
57#define MC_SEQ_MISC0__MT__DDR2 0x20000000
58#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
59#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
60#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
61#define MC_SEQ_MISC0__MT__HBM 0x60000000
62#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
63
64static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
65{
66 u32 blackout;
67
68 gmc_v6_0_wait_for_idle((void *)adev);
69
70 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
71 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
72 /* Block CPU access */
73 WREG32(mmBIF_FB_EN, 0);
74 /* blackout the MC */
75 blackout = REG_SET_FIELD(blackout,
76 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
77 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
78 }
79 /* wait for the MC to settle */
80 udelay(100);
81
82}
83
84static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
85{
86 u32 tmp;
87
88 /* unblackout the MC */
89 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
90 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
91 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
92 /* allow CPU access */
93 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
94 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
95 WREG32(mmBIF_FB_EN, tmp);
96}
97
98static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
99{
100 const char *chip_name;
101 char fw_name[30];
102 int err;
103 bool is_58_fw = false;
104
105 DRM_DEBUG("\n");
106
107 switch (adev->asic_type) {
108 case CHIP_TAHITI:
109 chip_name = "tahiti";
110 break;
111 case CHIP_PITCAIRN:
112 chip_name = "pitcairn";
113 break;
114 case CHIP_VERDE:
115 chip_name = "verde";
116 break;
117 case CHIP_OLAND:
118 chip_name = "oland";
119 break;
120 case CHIP_HAINAN:
121 chip_name = "hainan";
122 break;
123 default: BUG();
124 }
125
126 /* this memory configuration requires special firmware */
127 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
128 is_58_fw = true;
129
130 if (is_58_fw)
131 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin");
132 else
133 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
134 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
135 if (err)
136 goto out;
137
138 err = amdgpu_ucode_validate(adev->gmc.fw);
139
140out:
141 if (err) {
142 dev_err(adev->dev,
143 "si_mc: Failed to load firmware \"%s\"\n",
144 fw_name);
145 release_firmware(adev->gmc.fw);
146 adev->gmc.fw = NULL;
147 }
148 return err;
149}
150
151static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
152{
153 const __le32 *new_fw_data = NULL;
154 u32 running;
155 const __le32 *new_io_mc_regs = NULL;
156 int i, regs_size, ucode_size;
157 const struct mc_firmware_header_v1_0 *hdr;
158
159 if (!adev->gmc.fw)
160 return -EINVAL;
161
162 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
163
164 amdgpu_ucode_print_mc_hdr(&hdr->header);
165
166 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
167 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
168 new_io_mc_regs = (const __le32 *)
169 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
170 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
171 new_fw_data = (const __le32 *)
172 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
173
174 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
175
176 if (running == 0) {
177
178 /* reset the engine and set to writable */
179 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
180 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
181
182 /* load mc io regs */
183 for (i = 0; i < regs_size; i++) {
184 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
185 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
186 }
187 /* load the MC ucode */
188 for (i = 0; i < ucode_size; i++) {
189 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
190 }
191
192 /* put the engine back into the active state */
193 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
194 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
195 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
196
197 /* wait for training to complete */
198 for (i = 0; i < adev->usec_timeout; i++) {
199 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
200 break;
201 udelay(1);
202 }
203 for (i = 0; i < adev->usec_timeout; i++) {
204 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
205 break;
206 udelay(1);
207 }
208
209 }
210
211 return 0;
212}
213
214static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
215 struct amdgpu_gmc *mc)
216{
217 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
218 base <<= 24;
219
220 amdgpu_gmc_vram_location(adev, mc, base);
221 amdgpu_gmc_gart_location(adev, mc);
222}
223
224static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
225{
226 int i, j;
227
228 /* Initialize HDP */
229 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
230 WREG32((0xb05 + j), 0x00000000);
231 WREG32((0xb06 + j), 0x00000000);
232 WREG32((0xb07 + j), 0x00000000);
233 WREG32((0xb08 + j), 0x00000000);
234 WREG32((0xb09 + j), 0x00000000);
235 }
236 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
237
238 if (gmc_v6_0_wait_for_idle((void *)adev)) {
239 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
240 }
241
242 if (adev->mode_info.num_crtc) {
243 u32 tmp;
244
245 /* Lockout access through VGA aperture*/
246 tmp = RREG32(mmVGA_HDP_CONTROL);
247 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
248 WREG32(mmVGA_HDP_CONTROL, tmp);
249
250 /* disable VGA render */
251 tmp = RREG32(mmVGA_RENDER_CONTROL);
252 tmp &= ~VGA_VSTATUS_CNTL;
253 WREG32(mmVGA_RENDER_CONTROL, tmp);
254 }
255 /* Update configuration */
256 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
257 adev->gmc.vram_start >> 12);
258 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
259 adev->gmc.vram_end >> 12);
260 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
261 adev->vram_scratch.gpu_addr >> 12);
262 WREG32(mmMC_VM_AGP_BASE, 0);
263 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
264 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
265
266 if (gmc_v6_0_wait_for_idle((void *)adev)) {
267 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
268 }
269}
270
271static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
272{
273
274 u32 tmp;
275 int chansize, numchan;
276 int r;
277
278 tmp = RREG32(mmMC_ARB_RAMCFG);
279 if (tmp & (1 << 11)) {
280 chansize = 16;
281 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
282 chansize = 64;
283 } else {
284 chansize = 32;
285 }
286 tmp = RREG32(mmMC_SHARED_CHMAP);
287 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
288 case 0:
289 default:
290 numchan = 1;
291 break;
292 case 1:
293 numchan = 2;
294 break;
295 case 2:
296 numchan = 4;
297 break;
298 case 3:
299 numchan = 8;
300 break;
301 case 4:
302 numchan = 3;
303 break;
304 case 5:
305 numchan = 6;
306 break;
307 case 6:
308 numchan = 10;
309 break;
310 case 7:
311 numchan = 12;
312 break;
313 case 8:
314 numchan = 16;
315 break;
316 }
317 adev->gmc.vram_width = numchan * chansize;
318 /* size in MB on si */
319 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
320 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
321
322 if (!(adev->flags & AMD_IS_APU)) {
323 r = amdgpu_device_resize_fb_bar(adev);
324 if (r)
325 return r;
326 }
327 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
328 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
329 adev->gmc.visible_vram_size = adev->gmc.aper_size;
330
331 /* set the gart size */
332 if (amdgpu_gart_size == -1) {
333 switch (adev->asic_type) {
334 case CHIP_HAINAN: /* no MM engines */
335 default:
336 adev->gmc.gart_size = 256ULL << 20;
337 break;
338 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
339 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
340 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
341 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
342 adev->gmc.gart_size = 1024ULL << 20;
343 break;
344 }
345 } else {
346 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
347 }
348
349 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
350 gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
351
352 return 0;
353}
354
355static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
356 uint32_t vmhub, uint32_t flush_type)
357{
358 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
359}
360
361static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
362 unsigned vmid, uint64_t pd_addr)
363{
364 uint32_t reg;
365
366 /* write new base address */
367 if (vmid < 8)
368 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
369 else
370 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
371 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
372
373 /* bits 0-15 are the VM contexts0-15 */
374 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
375
376 return pd_addr;
377}
378
379static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
380 uint64_t *addr, uint64_t *flags)
381{
382 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
383}
384
385static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev,
386 struct amdgpu_bo_va_mapping *mapping,
387 uint64_t *flags)
388{
389 *flags &= ~AMDGPU_PTE_EXECUTABLE;
390 *flags &= ~AMDGPU_PTE_PRT;
391}
392
393static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
394 bool value)
395{
396 u32 tmp;
397
398 tmp = RREG32(mmVM_CONTEXT1_CNTL);
399 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
400 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
401 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
402 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
403 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
404 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
405 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
406 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
407 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
408 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
409 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
410 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
411 WREG32(mmVM_CONTEXT1_CNTL, tmp);
412}
413
414 /**
415 + * gmc_v8_0_set_prt - set PRT VM fault
416 + *
417 + * @adev: amdgpu_device pointer
418 + * @enable: enable/disable VM fault handling for PRT
419 +*/
420static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
421{
422 u32 tmp;
423
424 if (enable && !adev->gmc.prt_warning) {
425 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
426 adev->gmc.prt_warning = true;
427 }
428
429 tmp = RREG32(mmVM_PRT_CNTL);
430 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
431 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
432 enable);
433 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
434 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
435 enable);
436 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
437 L2_CACHE_STORE_INVALID_ENTRIES,
438 enable);
439 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
440 L1_TLB_STORE_INVALID_ENTRIES,
441 enable);
442 WREG32(mmVM_PRT_CNTL, tmp);
443
444 if (enable) {
445 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
446 uint32_t high = adev->vm_manager.max_pfn -
447 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
448
449 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
450 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
451 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
452 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
453 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
454 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
455 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
456 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
457 } else {
458 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
459 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
460 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
461 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
462 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
463 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
464 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
465 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
466 }
467}
468
469static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
470{
471 uint64_t table_addr;
472 int r, i;
473 u32 field;
474
475 if (adev->gart.bo == NULL) {
476 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
477 return -EINVAL;
478 }
479 r = amdgpu_gart_table_vram_pin(adev);
480 if (r)
481 return r;
482
483 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
484
485 /* Setup TLB control */
486 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
487 (0xA << 7) |
488 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
489 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
490 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
491 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
492 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
493 /* Setup L2 cache */
494 WREG32(mmVM_L2_CNTL,
495 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
496 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
497 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
498 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
499 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
500 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
501 WREG32(mmVM_L2_CNTL2,
502 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
503 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
504
505 field = adev->vm_manager.fragment_size;
506 WREG32(mmVM_L2_CNTL3,
507 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
508 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
509 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
510 /* setup context0 */
511 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
512 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
513 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
514 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
515 (u32)(adev->dummy_page_addr >> 12));
516 WREG32(mmVM_CONTEXT0_CNTL2, 0);
517 WREG32(mmVM_CONTEXT0_CNTL,
518 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
519 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
520 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
521
522 WREG32(0x575, 0);
523 WREG32(0x576, 0);
524 WREG32(0x577, 0);
525
526 /* empty context1-15 */
527 /* set vm size, must be a multiple of 4 */
528 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
529 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
530 /* Assign the pt base to something valid for now; the pts used for
531 * the VMs are determined by the application and setup and assigned
532 * on the fly in the vm part of radeon_gart.c
533 */
534 for (i = 1; i < AMDGPU_NUM_VMID; i++) {
535 if (i < 8)
536 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
537 table_addr >> 12);
538 else
539 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
540 table_addr >> 12);
541 }
542
543 /* enable context1-15 */
544 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
545 (u32)(adev->dummy_page_addr >> 12));
546 WREG32(mmVM_CONTEXT1_CNTL2, 4);
547 WREG32(mmVM_CONTEXT1_CNTL,
548 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
549 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
550 ((adev->vm_manager.block_size - 9)
551 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
552 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
553 gmc_v6_0_set_fault_enable_default(adev, false);
554 else
555 gmc_v6_0_set_fault_enable_default(adev, true);
556
557 gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0);
558 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
559 (unsigned)(adev->gmc.gart_size >> 20),
560 (unsigned long long)table_addr);
561 adev->gart.ready = true;
562 return 0;
563}
564
565static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
566{
567 int r;
568
569 if (adev->gart.bo) {
570 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
571 return 0;
572 }
573 r = amdgpu_gart_init(adev);
574 if (r)
575 return r;
576 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
577 adev->gart.gart_pte_flags = 0;
578 return amdgpu_gart_table_vram_alloc(adev);
579}
580
581static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
582{
583 /*unsigned i;
584
585 for (i = 1; i < 16; ++i) {
586 uint32_t reg;
587 if (i < 8)
588 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
589 else
590 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
591 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
592 }*/
593
594 /* Disable all tables */
595 WREG32(mmVM_CONTEXT0_CNTL, 0);
596 WREG32(mmVM_CONTEXT1_CNTL, 0);
597 /* Setup TLB control */
598 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
599 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
600 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
601 /* Setup L2 cache */
602 WREG32(mmVM_L2_CNTL,
603 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
604 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
605 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
606 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
607 WREG32(mmVM_L2_CNTL2, 0);
608 WREG32(mmVM_L2_CNTL3,
609 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
610 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
611 amdgpu_gart_table_vram_unpin(adev);
612}
613
614static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
615 u32 status, u32 addr, u32 mc_client)
616{
617 u32 mc_id;
618 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
619 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
620 PROTECTIONS);
621 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
622 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
623
624 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
625 MEMORY_CLIENT_ID);
626
627 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
628 protections, vmid, addr,
629 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
630 MEMORY_CLIENT_RW) ?
631 "write" : "read", block, mc_client, mc_id);
632}
633
634/*
635static const u32 mc_cg_registers[] = {
636 MC_HUB_MISC_HUB_CG,
637 MC_HUB_MISC_SIP_CG,
638 MC_HUB_MISC_VM_CG,
639 MC_XPB_CLK_GAT,
640 ATC_MISC_CG,
641 MC_CITF_MISC_WR_CG,
642 MC_CITF_MISC_RD_CG,
643 MC_CITF_MISC_VM_CG,
644 VM_L2_CG,
645};
646
647static const u32 mc_cg_ls_en[] = {
648 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
649 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
650 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
651 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
652 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
653 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
654 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
655 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
656 VM_L2_CG__MEM_LS_ENABLE_MASK,
657};
658
659static const u32 mc_cg_en[] = {
660 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
661 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
662 MC_HUB_MISC_VM_CG__ENABLE_MASK,
663 MC_XPB_CLK_GAT__ENABLE_MASK,
664 ATC_MISC_CG__ENABLE_MASK,
665 MC_CITF_MISC_WR_CG__ENABLE_MASK,
666 MC_CITF_MISC_RD_CG__ENABLE_MASK,
667 MC_CITF_MISC_VM_CG__ENABLE_MASK,
668 VM_L2_CG__ENABLE_MASK,
669};
670
671static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
672 bool enable)
673{
674 int i;
675 u32 orig, data;
676
677 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
678 orig = data = RREG32(mc_cg_registers[i]);
679 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
680 data |= mc_cg_ls_en[i];
681 else
682 data &= ~mc_cg_ls_en[i];
683 if (data != orig)
684 WREG32(mc_cg_registers[i], data);
685 }
686}
687
688static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
689 bool enable)
690{
691 int i;
692 u32 orig, data;
693
694 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
695 orig = data = RREG32(mc_cg_registers[i]);
696 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
697 data |= mc_cg_en[i];
698 else
699 data &= ~mc_cg_en[i];
700 if (data != orig)
701 WREG32(mc_cg_registers[i], data);
702 }
703}
704
705static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
706 bool enable)
707{
708 u32 orig, data;
709
710 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
711
712 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
713 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
714 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
715 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
716 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
717 } else {
718 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
719 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
720 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
721 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
722 }
723
724 if (orig != data)
725 WREG32_PCIE(ixPCIE_CNTL2, data);
726}
727
728static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
729 bool enable)
730{
731 u32 orig, data;
732
733 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
734
735 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
736 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
737 else
738 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
739
740 if (orig != data)
741 WREG32(mmHDP_HOST_PATH_CNTL, data);
742}
743
744static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
745 bool enable)
746{
747 u32 orig, data;
748
749 orig = data = RREG32(mmHDP_MEM_POWER_LS);
750
751 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
752 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
753 else
754 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
755
756 if (orig != data)
757 WREG32(mmHDP_MEM_POWER_LS, data);
758}
759*/
760
761static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
762{
763 switch (mc_seq_vram_type) {
764 case MC_SEQ_MISC0__MT__GDDR1:
765 return AMDGPU_VRAM_TYPE_GDDR1;
766 case MC_SEQ_MISC0__MT__DDR2:
767 return AMDGPU_VRAM_TYPE_DDR2;
768 case MC_SEQ_MISC0__MT__GDDR3:
769 return AMDGPU_VRAM_TYPE_GDDR3;
770 case MC_SEQ_MISC0__MT__GDDR4:
771 return AMDGPU_VRAM_TYPE_GDDR4;
772 case MC_SEQ_MISC0__MT__GDDR5:
773 return AMDGPU_VRAM_TYPE_GDDR5;
774 case MC_SEQ_MISC0__MT__DDR3:
775 return AMDGPU_VRAM_TYPE_DDR3;
776 default:
777 return AMDGPU_VRAM_TYPE_UNKNOWN;
778 }
779}
780
781static int gmc_v6_0_early_init(void *handle)
782{
783 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
784
785 gmc_v6_0_set_gmc_funcs(adev);
786 gmc_v6_0_set_irq_funcs(adev);
787
788 return 0;
789}
790
791static int gmc_v6_0_late_init(void *handle)
792{
793 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
794
795 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
796 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
797 else
798 return 0;
799}
800
801static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
802{
803 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
804 unsigned size;
805
806 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
807 size = AMDGPU_VBIOS_VGA_ALLOCATION;
808 } else {
809 u32 viewport = RREG32(mmVIEWPORT_SIZE);
810 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
811 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
812 4);
813 }
814 return size;
815}
816
817static int gmc_v6_0_sw_init(void *handle)
818{
819 int r;
820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
821
822 adev->num_vmhubs = 1;
823
824 if (adev->flags & AMD_IS_APU) {
825 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
826 } else {
827 u32 tmp = RREG32(mmMC_SEQ_MISC0);
828 tmp &= MC_SEQ_MISC0__MT__MASK;
829 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
830 }
831
832 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
833 if (r)
834 return r;
835
836 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
837 if (r)
838 return r;
839
840 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
841
842 adev->gmc.mc_mask = 0xffffffffffULL;
843
844 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
845 if (r) {
846 dev_warn(adev->dev, "No suitable DMA available.\n");
847 return r;
848 }
849 adev->need_swiotlb = drm_need_swiotlb(44);
850
851 r = gmc_v6_0_init_microcode(adev);
852 if (r) {
853 dev_err(adev->dev, "Failed to load mc firmware!\n");
854 return r;
855 }
856
857 r = gmc_v6_0_mc_init(adev);
858 if (r)
859 return r;
860
861 amdgpu_gmc_get_vbios_allocations(adev);
862
863 r = amdgpu_bo_init(adev);
864 if (r)
865 return r;
866
867 r = gmc_v6_0_gart_init(adev);
868 if (r)
869 return r;
870
871 /*
872 * number of VMs
873 * VMID 0 is reserved for System
874 * amdgpu graphics/compute will use VMIDs 1-7
875 * amdkfd will use VMIDs 8-15
876 */
877 adev->vm_manager.first_kfd_vmid = 8;
878 amdgpu_vm_manager_init(adev);
879
880 /* base offset of vram pages */
881 if (adev->flags & AMD_IS_APU) {
882 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
883
884 tmp <<= 22;
885 adev->vm_manager.vram_base_offset = tmp;
886 } else {
887 adev->vm_manager.vram_base_offset = 0;
888 }
889
890 return 0;
891}
892
893static int gmc_v6_0_sw_fini(void *handle)
894{
895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
896
897 amdgpu_gem_force_release(adev);
898 amdgpu_vm_manager_fini(adev);
899 amdgpu_gart_table_vram_free(adev);
900 amdgpu_bo_fini(adev);
901 release_firmware(adev->gmc.fw);
902 adev->gmc.fw = NULL;
903
904 return 0;
905}
906
907static int gmc_v6_0_hw_init(void *handle)
908{
909 int r;
910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
911
912 gmc_v6_0_mc_program(adev);
913
914 if (!(adev->flags & AMD_IS_APU)) {
915 r = gmc_v6_0_mc_load_microcode(adev);
916 if (r) {
917 dev_err(adev->dev, "Failed to load MC firmware!\n");
918 return r;
919 }
920 }
921
922 r = gmc_v6_0_gart_enable(adev);
923 if (r)
924 return r;
925
926 return r;
927}
928
929static int gmc_v6_0_hw_fini(void *handle)
930{
931 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
932
933 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
934 gmc_v6_0_gart_disable(adev);
935
936 return 0;
937}
938
939static int gmc_v6_0_suspend(void *handle)
940{
941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
942
943 gmc_v6_0_hw_fini(adev);
944
945 return 0;
946}
947
948static int gmc_v6_0_resume(void *handle)
949{
950 int r;
951 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
952
953 r = gmc_v6_0_hw_init(adev);
954 if (r)
955 return r;
956
957 amdgpu_vmid_reset_all(adev);
958
959 return 0;
960}
961
962static bool gmc_v6_0_is_idle(void *handle)
963{
964 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
965 u32 tmp = RREG32(mmSRBM_STATUS);
966
967 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
968 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
969 return false;
970
971 return true;
972}
973
974static int gmc_v6_0_wait_for_idle(void *handle)
975{
976 unsigned i;
977 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
978
979 for (i = 0; i < adev->usec_timeout; i++) {
980 if (gmc_v6_0_is_idle(handle))
981 return 0;
982 udelay(1);
983 }
984 return -ETIMEDOUT;
985
986}
987
988static int gmc_v6_0_soft_reset(void *handle)
989{
990 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
991 u32 srbm_soft_reset = 0;
992 u32 tmp = RREG32(mmSRBM_STATUS);
993
994 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
995 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
996 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
997
998 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
999 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1000 if (!(adev->flags & AMD_IS_APU))
1001 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1002 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1003 }
1004
1005 if (srbm_soft_reset) {
1006 gmc_v6_0_mc_stop(adev);
1007 if (gmc_v6_0_wait_for_idle(adev)) {
1008 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1009 }
1010
1011
1012 tmp = RREG32(mmSRBM_SOFT_RESET);
1013 tmp |= srbm_soft_reset;
1014 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1015 WREG32(mmSRBM_SOFT_RESET, tmp);
1016 tmp = RREG32(mmSRBM_SOFT_RESET);
1017
1018 udelay(50);
1019
1020 tmp &= ~srbm_soft_reset;
1021 WREG32(mmSRBM_SOFT_RESET, tmp);
1022 tmp = RREG32(mmSRBM_SOFT_RESET);
1023
1024 udelay(50);
1025
1026 gmc_v6_0_mc_resume(adev);
1027 udelay(50);
1028 }
1029
1030 return 0;
1031}
1032
1033static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1034 struct amdgpu_irq_src *src,
1035 unsigned type,
1036 enum amdgpu_interrupt_state state)
1037{
1038 u32 tmp;
1039 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1040 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1041 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1042 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1043 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1044 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1045
1046 switch (state) {
1047 case AMDGPU_IRQ_STATE_DISABLE:
1048 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1049 tmp &= ~bits;
1050 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1051 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1052 tmp &= ~bits;
1053 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1054 break;
1055 case AMDGPU_IRQ_STATE_ENABLE:
1056 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1057 tmp |= bits;
1058 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1059 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1060 tmp |= bits;
1061 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1062 break;
1063 default:
1064 break;
1065 }
1066
1067 return 0;
1068}
1069
1070static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1071 struct amdgpu_irq_src *source,
1072 struct amdgpu_iv_entry *entry)
1073{
1074 u32 addr, status;
1075
1076 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1077 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1078 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1079
1080 if (!addr && !status)
1081 return 0;
1082
1083 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1084 gmc_v6_0_set_fault_enable_default(adev, false);
1085
1086 if (printk_ratelimit()) {
1087 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1088 entry->src_id, entry->src_data[0]);
1089 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1090 addr);
1091 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1092 status);
1093 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1094 }
1095
1096 return 0;
1097}
1098
1099static int gmc_v6_0_set_clockgating_state(void *handle,
1100 enum amd_clockgating_state state)
1101{
1102 return 0;
1103}
1104
1105static int gmc_v6_0_set_powergating_state(void *handle,
1106 enum amd_powergating_state state)
1107{
1108 return 0;
1109}
1110
1111static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1112 .name = "gmc_v6_0",
1113 .early_init = gmc_v6_0_early_init,
1114 .late_init = gmc_v6_0_late_init,
1115 .sw_init = gmc_v6_0_sw_init,
1116 .sw_fini = gmc_v6_0_sw_fini,
1117 .hw_init = gmc_v6_0_hw_init,
1118 .hw_fini = gmc_v6_0_hw_fini,
1119 .suspend = gmc_v6_0_suspend,
1120 .resume = gmc_v6_0_resume,
1121 .is_idle = gmc_v6_0_is_idle,
1122 .wait_for_idle = gmc_v6_0_wait_for_idle,
1123 .soft_reset = gmc_v6_0_soft_reset,
1124 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1125 .set_powergating_state = gmc_v6_0_set_powergating_state,
1126};
1127
1128static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1129 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1130 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1131 .set_prt = gmc_v6_0_set_prt,
1132 .get_vm_pde = gmc_v6_0_get_vm_pde,
1133 .get_vm_pte = gmc_v6_0_get_vm_pte,
1134 .get_vbios_fb_size = gmc_v6_0_get_vbios_fb_size,
1135};
1136
1137static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1138 .set = gmc_v6_0_vm_fault_interrupt_state,
1139 .process = gmc_v6_0_process_interrupt,
1140};
1141
1142static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1143{
1144 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1145}
1146
1147static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1148{
1149 adev->gmc.vm_fault.num_types = 1;
1150 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1151}
1152
1153const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1154{
1155 .type = AMD_IP_BLOCK_TYPE_GMC,
1156 .major = 6,
1157 .minor = 0,
1158 .rev = 0,
1159 .funcs = &gmc_v6_0_ip_funcs,
1160};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v6_0.h"
27#include "amdgpu_ucode.h"
28
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gmc/gmc_6_0_d.h"
34#include "gmc/gmc_6_0_sh_mask.h"
35#include "dce/dce_6_0_d.h"
36#include "dce/dce_6_0_sh_mask.h"
37#include "si_enums.h"
38
39static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
40static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41static int gmc_v6_0_wait_for_idle(void *handle);
42
43MODULE_FIRMWARE("radeon/tahiti_mc.bin");
44MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
45MODULE_FIRMWARE("radeon/verde_mc.bin");
46MODULE_FIRMWARE("radeon/oland_mc.bin");
47MODULE_FIRMWARE("radeon/si58_mc.bin");
48
49#define MC_SEQ_MISC0__MT__MASK 0xf0000000
50#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
51#define MC_SEQ_MISC0__MT__DDR2 0x20000000
52#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
53#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
54#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
55#define MC_SEQ_MISC0__MT__HBM 0x60000000
56#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
57
58
59static const u32 crtc_offsets[6] =
60{
61 SI_CRTC0_REGISTER_OFFSET,
62 SI_CRTC1_REGISTER_OFFSET,
63 SI_CRTC2_REGISTER_OFFSET,
64 SI_CRTC3_REGISTER_OFFSET,
65 SI_CRTC4_REGISTER_OFFSET,
66 SI_CRTC5_REGISTER_OFFSET
67};
68
69static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
70 struct amdgpu_mode_mc_save *save)
71{
72 u32 blackout;
73
74 if (adev->mode_info.num_crtc)
75 amdgpu_display_stop_mc_access(adev, save);
76
77 gmc_v6_0_wait_for_idle((void *)adev);
78
79 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
80 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
81 /* Block CPU access */
82 WREG32(mmBIF_FB_EN, 0);
83 /* blackout the MC */
84 blackout = REG_SET_FIELD(blackout,
85 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
86 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
87 }
88 /* wait for the MC to settle */
89 udelay(100);
90
91}
92
93static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
94 struct amdgpu_mode_mc_save *save)
95{
96 u32 tmp;
97
98 /* unblackout the MC */
99 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
100 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
101 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
102 /* allow CPU access */
103 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
104 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
105 WREG32(mmBIF_FB_EN, tmp);
106
107 if (adev->mode_info.num_crtc)
108 amdgpu_display_resume_mc_access(adev, save);
109
110}
111
112static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
113{
114 const char *chip_name;
115 char fw_name[30];
116 int err;
117 bool is_58_fw = false;
118
119 DRM_DEBUG("\n");
120
121 switch (adev->asic_type) {
122 case CHIP_TAHITI:
123 chip_name = "tahiti";
124 break;
125 case CHIP_PITCAIRN:
126 chip_name = "pitcairn";
127 break;
128 case CHIP_VERDE:
129 chip_name = "verde";
130 break;
131 case CHIP_OLAND:
132 chip_name = "oland";
133 break;
134 case CHIP_HAINAN:
135 chip_name = "hainan";
136 break;
137 default: BUG();
138 }
139
140 /* this memory configuration requires special firmware */
141 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
142 is_58_fw = true;
143
144 if (is_58_fw)
145 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
146 else
147 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
148 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
149 if (err)
150 goto out;
151
152 err = amdgpu_ucode_validate(adev->mc.fw);
153
154out:
155 if (err) {
156 dev_err(adev->dev,
157 "si_mc: Failed to load firmware \"%s\"\n",
158 fw_name);
159 release_firmware(adev->mc.fw);
160 adev->mc.fw = NULL;
161 }
162 return err;
163}
164
165static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
166{
167 const __le32 *new_fw_data = NULL;
168 u32 running;
169 const __le32 *new_io_mc_regs = NULL;
170 int i, regs_size, ucode_size;
171 const struct mc_firmware_header_v1_0 *hdr;
172
173 if (!adev->mc.fw)
174 return -EINVAL;
175
176 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
177
178 amdgpu_ucode_print_mc_hdr(&hdr->header);
179
180 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
181 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
182 new_io_mc_regs = (const __le32 *)
183 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
184 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
185 new_fw_data = (const __le32 *)
186 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
187
188 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
189
190 if (running == 0) {
191
192 /* reset the engine and set to writable */
193 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
194 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
195
196 /* load mc io regs */
197 for (i = 0; i < regs_size; i++) {
198 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
199 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
200 }
201 /* load the MC ucode */
202 for (i = 0; i < ucode_size; i++) {
203 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
204 }
205
206 /* put the engine back into the active state */
207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
209 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
210
211 /* wait for training to complete */
212 for (i = 0; i < adev->usec_timeout; i++) {
213 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
214 break;
215 udelay(1);
216 }
217 for (i = 0; i < adev->usec_timeout; i++) {
218 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
219 break;
220 udelay(1);
221 }
222
223 }
224
225 return 0;
226}
227
228static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
229 struct amdgpu_mc *mc)
230{
231 if (mc->mc_vram_size > 0xFFC0000000ULL) {
232 dev_warn(adev->dev, "limiting VRAM\n");
233 mc->real_vram_size = 0xFFC0000000ULL;
234 mc->mc_vram_size = 0xFFC0000000ULL;
235 }
236 amdgpu_vram_location(adev, &adev->mc, 0);
237 adev->mc.gtt_base_align = 0;
238 amdgpu_gtt_location(adev, mc);
239}
240
241static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
242{
243 struct amdgpu_mode_mc_save save;
244 u32 tmp;
245 int i, j;
246
247 /* Initialize HDP */
248 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
249 WREG32((0xb05 + j), 0x00000000);
250 WREG32((0xb06 + j), 0x00000000);
251 WREG32((0xb07 + j), 0x00000000);
252 WREG32((0xb08 + j), 0x00000000);
253 WREG32((0xb09 + j), 0x00000000);
254 }
255 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
256
257 if (adev->mode_info.num_crtc)
258 amdgpu_display_set_vga_render_state(adev, false);
259
260 gmc_v6_0_mc_stop(adev, &save);
261
262 if (gmc_v6_0_wait_for_idle((void *)adev)) {
263 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
264 }
265
266 WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
267 /* Update configuration */
268 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
269 adev->mc.vram_start >> 12);
270 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
271 adev->mc.vram_end >> 12);
272 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
273 adev->vram_scratch.gpu_addr >> 12);
274 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
275 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
276 WREG32(mmMC_VM_FB_LOCATION, tmp);
277 /* XXX double check these! */
278 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
279 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
280 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
281 WREG32(mmMC_VM_AGP_BASE, 0);
282 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
283 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
284
285 if (gmc_v6_0_wait_for_idle((void *)adev)) {
286 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
287 }
288 gmc_v6_0_mc_resume(adev, &save);
289}
290
291static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
292{
293
294 u32 tmp;
295 int chansize, numchan;
296
297 tmp = RREG32(mmMC_ARB_RAMCFG);
298 if (tmp & (1 << 11)) {
299 chansize = 16;
300 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
301 chansize = 64;
302 } else {
303 chansize = 32;
304 }
305 tmp = RREG32(mmMC_SHARED_CHMAP);
306 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
307 case 0:
308 default:
309 numchan = 1;
310 break;
311 case 1:
312 numchan = 2;
313 break;
314 case 2:
315 numchan = 4;
316 break;
317 case 3:
318 numchan = 8;
319 break;
320 case 4:
321 numchan = 3;
322 break;
323 case 5:
324 numchan = 6;
325 break;
326 case 6:
327 numchan = 10;
328 break;
329 case 7:
330 numchan = 12;
331 break;
332 case 8:
333 numchan = 16;
334 break;
335 }
336 adev->mc.vram_width = numchan * chansize;
337 /* Could aper size report 0 ? */
338 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
339 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
340 /* size in MB on si */
341 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
342 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
343 adev->mc.visible_vram_size = adev->mc.aper_size;
344
345 /* unless the user had overridden it, set the gart
346 * size equal to the 1024 or vram, whichever is larger.
347 */
348 if (amdgpu_gart_size == -1)
349 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
350 else
351 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
352
353 gmc_v6_0_vram_gtt_location(adev, &adev->mc);
354
355 return 0;
356}
357
358static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
359 uint32_t vmid)
360{
361 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
362
363 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
364}
365
366static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
367 void *cpu_pt_addr,
368 uint32_t gpu_page_idx,
369 uint64_t addr,
370 uint32_t flags)
371{
372 void __iomem *ptr = (void *)cpu_pt_addr;
373 uint64_t value;
374
375 value = addr & 0xFFFFFFFFFFFFF000ULL;
376 value |= flags;
377 writeq(value, ptr + (gpu_page_idx * 8));
378
379 return 0;
380}
381
382static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
383 bool value)
384{
385 u32 tmp;
386
387 tmp = RREG32(mmVM_CONTEXT1_CNTL);
388 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
389 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
390 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
391 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
392 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
393 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
394 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
395 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
396 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
397 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
398 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
399 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
400 WREG32(mmVM_CONTEXT1_CNTL, tmp);
401}
402
403static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
404{
405 int r, i;
406
407 if (adev->gart.robj == NULL) {
408 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
409 return -EINVAL;
410 }
411 r = amdgpu_gart_table_vram_pin(adev);
412 if (r)
413 return r;
414 /* Setup TLB control */
415 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
416 (0xA << 7) |
417 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
418 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
419 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
420 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
421 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
422 /* Setup L2 cache */
423 WREG32(mmVM_L2_CNTL,
424 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
425 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
426 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
427 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
428 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
429 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
430 WREG32(mmVM_L2_CNTL2,
431 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
432 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
433 WREG32(mmVM_L2_CNTL3,
434 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
435 (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
436 (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
437 /* setup context0 */
438 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
439 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
440 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
441 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
442 (u32)(adev->dummy_page.addr >> 12));
443 WREG32(mmVM_CONTEXT0_CNTL2, 0);
444 WREG32(mmVM_CONTEXT0_CNTL,
445 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
446 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
447 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
448
449 WREG32(0x575, 0);
450 WREG32(0x576, 0);
451 WREG32(0x577, 0);
452
453 /* empty context1-15 */
454 /* set vm size, must be a multiple of 4 */
455 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
456 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
457 /* Assign the pt base to something valid for now; the pts used for
458 * the VMs are determined by the application and setup and assigned
459 * on the fly in the vm part of radeon_gart.c
460 */
461 for (i = 1; i < 16; i++) {
462 if (i < 8)
463 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
464 adev->gart.table_addr >> 12);
465 else
466 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
467 adev->gart.table_addr >> 12);
468 }
469
470 /* enable context1-15 */
471 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
472 (u32)(adev->dummy_page.addr >> 12));
473 WREG32(mmVM_CONTEXT1_CNTL2, 4);
474 WREG32(mmVM_CONTEXT1_CNTL,
475 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
476 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
477 ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
478 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
479 gmc_v6_0_set_fault_enable_default(adev, false);
480 else
481 gmc_v6_0_set_fault_enable_default(adev, true);
482
483 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
484 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
485 (unsigned)(adev->mc.gtt_size >> 20),
486 (unsigned long long)adev->gart.table_addr);
487 adev->gart.ready = true;
488 return 0;
489}
490
491static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
492{
493 int r;
494
495 if (adev->gart.robj) {
496 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
497 return 0;
498 }
499 r = amdgpu_gart_init(adev);
500 if (r)
501 return r;
502 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
503 return amdgpu_gart_table_vram_alloc(adev);
504}
505
506static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
507{
508 /*unsigned i;
509
510 for (i = 1; i < 16; ++i) {
511 uint32_t reg;
512 if (i < 8)
513 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
514 else
515 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
516 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
517 }*/
518
519 /* Disable all tables */
520 WREG32(mmVM_CONTEXT0_CNTL, 0);
521 WREG32(mmVM_CONTEXT1_CNTL, 0);
522 /* Setup TLB control */
523 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
524 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
525 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
526 /* Setup L2 cache */
527 WREG32(mmVM_L2_CNTL,
528 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
529 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
530 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
531 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
532 WREG32(mmVM_L2_CNTL2, 0);
533 WREG32(mmVM_L2_CNTL3,
534 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
535 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
536 amdgpu_gart_table_vram_unpin(adev);
537}
538
539static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
540{
541 amdgpu_gart_table_vram_free(adev);
542 amdgpu_gart_fini(adev);
543}
544
545static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
546{
547 /*
548 * number of VMs
549 * VMID 0 is reserved for System
550 * amdgpu graphics/compute will use VMIDs 1-7
551 * amdkfd will use VMIDs 8-15
552 */
553 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
554 amdgpu_vm_manager_init(adev);
555
556 /* base offset of vram pages */
557 if (adev->flags & AMD_IS_APU) {
558 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
559 tmp <<= 22;
560 adev->vm_manager.vram_base_offset = tmp;
561 } else
562 adev->vm_manager.vram_base_offset = 0;
563
564 return 0;
565}
566
567static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
568{
569}
570
571static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
572 u32 status, u32 addr, u32 mc_client)
573{
574 u32 mc_id;
575 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
576 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
577 PROTECTIONS);
578 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
579 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
580
581 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
582 MEMORY_CLIENT_ID);
583
584 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
585 protections, vmid, addr,
586 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
587 MEMORY_CLIENT_RW) ?
588 "write" : "read", block, mc_client, mc_id);
589}
590
591/*
592static const u32 mc_cg_registers[] = {
593 MC_HUB_MISC_HUB_CG,
594 MC_HUB_MISC_SIP_CG,
595 MC_HUB_MISC_VM_CG,
596 MC_XPB_CLK_GAT,
597 ATC_MISC_CG,
598 MC_CITF_MISC_WR_CG,
599 MC_CITF_MISC_RD_CG,
600 MC_CITF_MISC_VM_CG,
601 VM_L2_CG,
602};
603
604static const u32 mc_cg_ls_en[] = {
605 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
606 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
607 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
608 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
609 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
610 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
611 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
612 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
613 VM_L2_CG__MEM_LS_ENABLE_MASK,
614};
615
616static const u32 mc_cg_en[] = {
617 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
618 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
619 MC_HUB_MISC_VM_CG__ENABLE_MASK,
620 MC_XPB_CLK_GAT__ENABLE_MASK,
621 ATC_MISC_CG__ENABLE_MASK,
622 MC_CITF_MISC_WR_CG__ENABLE_MASK,
623 MC_CITF_MISC_RD_CG__ENABLE_MASK,
624 MC_CITF_MISC_VM_CG__ENABLE_MASK,
625 VM_L2_CG__ENABLE_MASK,
626};
627
628static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
629 bool enable)
630{
631 int i;
632 u32 orig, data;
633
634 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
635 orig = data = RREG32(mc_cg_registers[i]);
636 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
637 data |= mc_cg_ls_en[i];
638 else
639 data &= ~mc_cg_ls_en[i];
640 if (data != orig)
641 WREG32(mc_cg_registers[i], data);
642 }
643}
644
645static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
646 bool enable)
647{
648 int i;
649 u32 orig, data;
650
651 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
652 orig = data = RREG32(mc_cg_registers[i]);
653 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
654 data |= mc_cg_en[i];
655 else
656 data &= ~mc_cg_en[i];
657 if (data != orig)
658 WREG32(mc_cg_registers[i], data);
659 }
660}
661
662static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
663 bool enable)
664{
665 u32 orig, data;
666
667 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
668
669 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
670 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
671 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
672 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
673 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
674 } else {
675 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
676 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
677 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
678 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
679 }
680
681 if (orig != data)
682 WREG32_PCIE(ixPCIE_CNTL2, data);
683}
684
685static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
686 bool enable)
687{
688 u32 orig, data;
689
690 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
691
692 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
693 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
694 else
695 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
696
697 if (orig != data)
698 WREG32(mmHDP_HOST_PATH_CNTL, data);
699}
700
701static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
702 bool enable)
703{
704 u32 orig, data;
705
706 orig = data = RREG32(mmHDP_MEM_POWER_LS);
707
708 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
709 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
710 else
711 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
712
713 if (orig != data)
714 WREG32(mmHDP_MEM_POWER_LS, data);
715}
716*/
717
718static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
719{
720 switch (mc_seq_vram_type) {
721 case MC_SEQ_MISC0__MT__GDDR1:
722 return AMDGPU_VRAM_TYPE_GDDR1;
723 case MC_SEQ_MISC0__MT__DDR2:
724 return AMDGPU_VRAM_TYPE_DDR2;
725 case MC_SEQ_MISC0__MT__GDDR3:
726 return AMDGPU_VRAM_TYPE_GDDR3;
727 case MC_SEQ_MISC0__MT__GDDR4:
728 return AMDGPU_VRAM_TYPE_GDDR4;
729 case MC_SEQ_MISC0__MT__GDDR5:
730 return AMDGPU_VRAM_TYPE_GDDR5;
731 case MC_SEQ_MISC0__MT__DDR3:
732 return AMDGPU_VRAM_TYPE_DDR3;
733 default:
734 return AMDGPU_VRAM_TYPE_UNKNOWN;
735 }
736}
737
738static int gmc_v6_0_early_init(void *handle)
739{
740 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
741
742 gmc_v6_0_set_gart_funcs(adev);
743 gmc_v6_0_set_irq_funcs(adev);
744
745 if (adev->flags & AMD_IS_APU) {
746 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
747 } else {
748 u32 tmp = RREG32(mmMC_SEQ_MISC0);
749 tmp &= MC_SEQ_MISC0__MT__MASK;
750 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
751 }
752
753 return 0;
754}
755
756static int gmc_v6_0_late_init(void *handle)
757{
758 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
759
760 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
761 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
762 else
763 return 0;
764}
765
766static int gmc_v6_0_sw_init(void *handle)
767{
768 int r;
769 int dma_bits;
770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
773 if (r)
774 return r;
775
776 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
777 if (r)
778 return r;
779
780 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
781
782 adev->mc.mc_mask = 0xffffffffffULL;
783
784 adev->need_dma32 = false;
785 dma_bits = adev->need_dma32 ? 32 : 40;
786 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
787 if (r) {
788 adev->need_dma32 = true;
789 dma_bits = 32;
790 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
791 }
792 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
793 if (r) {
794 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
795 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
796 }
797
798 r = gmc_v6_0_init_microcode(adev);
799 if (r) {
800 dev_err(adev->dev, "Failed to load mc firmware!\n");
801 return r;
802 }
803
804 r = gmc_v6_0_mc_init(adev);
805 if (r)
806 return r;
807
808 r = amdgpu_bo_init(adev);
809 if (r)
810 return r;
811
812 r = gmc_v6_0_gart_init(adev);
813 if (r)
814 return r;
815
816 if (!adev->vm_manager.enabled) {
817 r = gmc_v6_0_vm_init(adev);
818 if (r) {
819 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
820 return r;
821 }
822 adev->vm_manager.enabled = true;
823 }
824
825 return r;
826}
827
828static int gmc_v6_0_sw_fini(void *handle)
829{
830 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
831
832 if (adev->vm_manager.enabled) {
833 gmc_v6_0_vm_fini(adev);
834 adev->vm_manager.enabled = false;
835 }
836 gmc_v6_0_gart_fini(adev);
837 amdgpu_gem_force_release(adev);
838 amdgpu_bo_fini(adev);
839
840 return 0;
841}
842
843static int gmc_v6_0_hw_init(void *handle)
844{
845 int r;
846 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
847
848 gmc_v6_0_mc_program(adev);
849
850 if (!(adev->flags & AMD_IS_APU)) {
851 r = gmc_v6_0_mc_load_microcode(adev);
852 if (r) {
853 dev_err(adev->dev, "Failed to load MC firmware!\n");
854 return r;
855 }
856 }
857
858 r = gmc_v6_0_gart_enable(adev);
859 if (r)
860 return r;
861
862 return r;
863}
864
865static int gmc_v6_0_hw_fini(void *handle)
866{
867 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
868
869 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
870 gmc_v6_0_gart_disable(adev);
871
872 return 0;
873}
874
875static int gmc_v6_0_suspend(void *handle)
876{
877 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
878
879 if (adev->vm_manager.enabled) {
880 gmc_v6_0_vm_fini(adev);
881 adev->vm_manager.enabled = false;
882 }
883 gmc_v6_0_hw_fini(adev);
884
885 return 0;
886}
887
888static int gmc_v6_0_resume(void *handle)
889{
890 int r;
891 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
892
893 r = gmc_v6_0_hw_init(adev);
894 if (r)
895 return r;
896
897 if (!adev->vm_manager.enabled) {
898 r = gmc_v6_0_vm_init(adev);
899 if (r) {
900 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
901 return r;
902 }
903 adev->vm_manager.enabled = true;
904 }
905
906 return r;
907}
908
909static bool gmc_v6_0_is_idle(void *handle)
910{
911 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
912 u32 tmp = RREG32(mmSRBM_STATUS);
913
914 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
915 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
916 return false;
917
918 return true;
919}
920
921static int gmc_v6_0_wait_for_idle(void *handle)
922{
923 unsigned i;
924 u32 tmp;
925 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
926
927 for (i = 0; i < adev->usec_timeout; i++) {
928 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
929 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
930 SRBM_STATUS__MCC_BUSY_MASK |
931 SRBM_STATUS__MCD_BUSY_MASK |
932 SRBM_STATUS__VMC_BUSY_MASK);
933 if (!tmp)
934 return 0;
935 udelay(1);
936 }
937 return -ETIMEDOUT;
938
939}
940
941static int gmc_v6_0_soft_reset(void *handle)
942{
943 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
944 struct amdgpu_mode_mc_save save;
945 u32 srbm_soft_reset = 0;
946 u32 tmp = RREG32(mmSRBM_STATUS);
947
948 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
949 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
950 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
951
952 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
953 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
954 if (!(adev->flags & AMD_IS_APU))
955 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
956 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
957 }
958
959 if (srbm_soft_reset) {
960 gmc_v6_0_mc_stop(adev, &save);
961 if (gmc_v6_0_wait_for_idle(adev)) {
962 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
963 }
964
965
966 tmp = RREG32(mmSRBM_SOFT_RESET);
967 tmp |= srbm_soft_reset;
968 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
969 WREG32(mmSRBM_SOFT_RESET, tmp);
970 tmp = RREG32(mmSRBM_SOFT_RESET);
971
972 udelay(50);
973
974 tmp &= ~srbm_soft_reset;
975 WREG32(mmSRBM_SOFT_RESET, tmp);
976 tmp = RREG32(mmSRBM_SOFT_RESET);
977
978 udelay(50);
979
980 gmc_v6_0_mc_resume(adev, &save);
981 udelay(50);
982 }
983
984 return 0;
985}
986
987static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
988 struct amdgpu_irq_src *src,
989 unsigned type,
990 enum amdgpu_interrupt_state state)
991{
992 u32 tmp;
993 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
994 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
995 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
996 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
997 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
998 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
999
1000 switch (state) {
1001 case AMDGPU_IRQ_STATE_DISABLE:
1002 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1003 tmp &= ~bits;
1004 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1005 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1006 tmp &= ~bits;
1007 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1008 break;
1009 case AMDGPU_IRQ_STATE_ENABLE:
1010 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1011 tmp |= bits;
1012 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1013 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1014 tmp |= bits;
1015 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1016 break;
1017 default:
1018 break;
1019 }
1020
1021 return 0;
1022}
1023
1024static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1025 struct amdgpu_irq_src *source,
1026 struct amdgpu_iv_entry *entry)
1027{
1028 u32 addr, status;
1029
1030 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1031 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1032 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1033
1034 if (!addr && !status)
1035 return 0;
1036
1037 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1038 gmc_v6_0_set_fault_enable_default(adev, false);
1039
1040 if (printk_ratelimit()) {
1041 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1042 entry->src_id, entry->src_data);
1043 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1044 addr);
1045 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1046 status);
1047 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1048 }
1049
1050 return 0;
1051}
1052
1053static int gmc_v6_0_set_clockgating_state(void *handle,
1054 enum amd_clockgating_state state)
1055{
1056 return 0;
1057}
1058
1059static int gmc_v6_0_set_powergating_state(void *handle,
1060 enum amd_powergating_state state)
1061{
1062 return 0;
1063}
1064
1065static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1066 .name = "gmc_v6_0",
1067 .early_init = gmc_v6_0_early_init,
1068 .late_init = gmc_v6_0_late_init,
1069 .sw_init = gmc_v6_0_sw_init,
1070 .sw_fini = gmc_v6_0_sw_fini,
1071 .hw_init = gmc_v6_0_hw_init,
1072 .hw_fini = gmc_v6_0_hw_fini,
1073 .suspend = gmc_v6_0_suspend,
1074 .resume = gmc_v6_0_resume,
1075 .is_idle = gmc_v6_0_is_idle,
1076 .wait_for_idle = gmc_v6_0_wait_for_idle,
1077 .soft_reset = gmc_v6_0_soft_reset,
1078 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1079 .set_powergating_state = gmc_v6_0_set_powergating_state,
1080};
1081
1082static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1083 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1084 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1085};
1086
1087static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1088 .set = gmc_v6_0_vm_fault_interrupt_state,
1089 .process = gmc_v6_0_process_interrupt,
1090};
1091
1092static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1093{
1094 if (adev->gart.gart_funcs == NULL)
1095 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1096}
1097
1098static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1099{
1100 adev->mc.vm_fault.num_types = 1;
1101 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1102}
1103
1104const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1105{
1106 .type = AMD_IP_BLOCK_TYPE_GMC,
1107 .major = 6,
1108 .minor = 0,
1109 .rev = 0,
1110 .funcs = &gmc_v6_0_ip_funcs,
1111};