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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27
28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30
31static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32{
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44}
45
46void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47{
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65}
66
67void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68{
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71 const struct smc_firmware_header_v1_0 *v1_0_hdr;
72 const struct smc_firmware_header_v2_0 *v2_0_hdr;
73 const struct smc_firmware_header_v2_1 *v2_1_hdr;
74
75 DRM_DEBUG("SMC\n");
76 amdgpu_ucode_print_common_hdr(hdr);
77
78 if (version_major == 1) {
79 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
80 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
81 } else if (version_major == 2) {
82 switch (version_minor) {
83 case 0:
84 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
85 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
86 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
87 break;
88 case 1:
89 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
90 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
91 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
92 break;
93 default:
94 break;
95 }
96
97 } else {
98 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
99 }
100}
101
102void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
103{
104 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
105 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
106
107 DRM_DEBUG("GFX\n");
108 amdgpu_ucode_print_common_hdr(hdr);
109
110 if (version_major == 1) {
111 const struct gfx_firmware_header_v1_0 *gfx_hdr =
112 container_of(hdr, struct gfx_firmware_header_v1_0, header);
113
114 DRM_DEBUG("ucode_feature_version: %u\n",
115 le32_to_cpu(gfx_hdr->ucode_feature_version));
116 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
117 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
118 } else {
119 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
120 }
121}
122
123void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
124{
125 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
126 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
127
128 DRM_DEBUG("RLC\n");
129 amdgpu_ucode_print_common_hdr(hdr);
130
131 if (version_major == 1) {
132 const struct rlc_firmware_header_v1_0 *rlc_hdr =
133 container_of(hdr, struct rlc_firmware_header_v1_0, header);
134
135 DRM_DEBUG("ucode_feature_version: %u\n",
136 le32_to_cpu(rlc_hdr->ucode_feature_version));
137 DRM_DEBUG("save_and_restore_offset: %u\n",
138 le32_to_cpu(rlc_hdr->save_and_restore_offset));
139 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
140 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
141 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
142 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
143 DRM_DEBUG("master_pkt_description_offset: %u\n",
144 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
145 } else if (version_major == 2) {
146 const struct rlc_firmware_header_v2_0 *rlc_hdr =
147 container_of(hdr, struct rlc_firmware_header_v2_0, header);
148
149 DRM_DEBUG("ucode_feature_version: %u\n",
150 le32_to_cpu(rlc_hdr->ucode_feature_version));
151 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
152 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
153 DRM_DEBUG("save_and_restore_offset: %u\n",
154 le32_to_cpu(rlc_hdr->save_and_restore_offset));
155 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
156 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
157 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
158 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
159 DRM_DEBUG("reg_restore_list_size: %u\n",
160 le32_to_cpu(rlc_hdr->reg_restore_list_size));
161 DRM_DEBUG("reg_list_format_start: %u\n",
162 le32_to_cpu(rlc_hdr->reg_list_format_start));
163 DRM_DEBUG("reg_list_format_separate_start: %u\n",
164 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
165 DRM_DEBUG("starting_offsets_start: %u\n",
166 le32_to_cpu(rlc_hdr->starting_offsets_start));
167 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
168 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
169 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
170 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
171 DRM_DEBUG("reg_list_size_bytes: %u\n",
172 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
173 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
174 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
175 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
176 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
177 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
178 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
179 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
180 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
181 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
182 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
183 if (version_minor == 1) {
184 const struct rlc_firmware_header_v2_1 *v2_1 =
185 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
186 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
187 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
188 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
189 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
190 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
191 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
192 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
193 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
194 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
195 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
196 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
197 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
198 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
199 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
200 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
201 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
202 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
203 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
204 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
205 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
206 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
207 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
208 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
209 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
210 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
211 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
212 }
213 } else {
214 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
215 }
216}
217
218void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
219{
220 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
221 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
222
223 DRM_DEBUG("SDMA\n");
224 amdgpu_ucode_print_common_hdr(hdr);
225
226 if (version_major == 1) {
227 const struct sdma_firmware_header_v1_0 *sdma_hdr =
228 container_of(hdr, struct sdma_firmware_header_v1_0, header);
229
230 DRM_DEBUG("ucode_feature_version: %u\n",
231 le32_to_cpu(sdma_hdr->ucode_feature_version));
232 DRM_DEBUG("ucode_change_version: %u\n",
233 le32_to_cpu(sdma_hdr->ucode_change_version));
234 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
235 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
236 if (version_minor >= 1) {
237 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
238 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
239 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
240 }
241 } else {
242 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
243 version_major, version_minor);
244 }
245}
246
247void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
248{
249 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
250 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
251
252 DRM_DEBUG("PSP\n");
253 amdgpu_ucode_print_common_hdr(hdr);
254
255 if (version_major == 1) {
256 const struct psp_firmware_header_v1_0 *psp_hdr =
257 container_of(hdr, struct psp_firmware_header_v1_0, header);
258
259 DRM_DEBUG("ucode_feature_version: %u\n",
260 le32_to_cpu(psp_hdr->sos.fw_version));
261 DRM_DEBUG("sos_offset_bytes: %u\n",
262 le32_to_cpu(psp_hdr->sos.offset_bytes));
263 DRM_DEBUG("sos_size_bytes: %u\n",
264 le32_to_cpu(psp_hdr->sos.size_bytes));
265 if (version_minor == 1) {
266 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
267 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
268 DRM_DEBUG("toc_header_version: %u\n",
269 le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
270 DRM_DEBUG("toc_offset_bytes: %u\n",
271 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
272 DRM_DEBUG("toc_size_bytes: %u\n",
273 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
274 DRM_DEBUG("kdb_header_version: %u\n",
275 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
276 DRM_DEBUG("kdb_offset_bytes: %u\n",
277 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
278 DRM_DEBUG("kdb_size_bytes: %u\n",
279 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
280 }
281 if (version_minor == 2) {
282 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
283 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
284 DRM_DEBUG("kdb_header_version: %u\n",
285 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
286 DRM_DEBUG("kdb_offset_bytes: %u\n",
287 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
288 DRM_DEBUG("kdb_size_bytes: %u\n",
289 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
290 }
291 if (version_minor == 3) {
292 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
293 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
294 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
295 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
296 DRM_DEBUG("toc_header_version: %u\n",
297 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
298 DRM_DEBUG("toc_offset_bytes: %u\n",
299 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
300 DRM_DEBUG("toc_size_bytes: %u\n",
301 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
302 DRM_DEBUG("kdb_header_version: %u\n",
303 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
304 DRM_DEBUG("kdb_offset_bytes: %u\n",
305 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
306 DRM_DEBUG("kdb_size_bytes: %u\n",
307 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
308 DRM_DEBUG("spl_header_version: %u\n",
309 le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
310 DRM_DEBUG("spl_offset_bytes: %u\n",
311 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
312 DRM_DEBUG("spl_size_bytes: %u\n",
313 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
314 }
315 } else {
316 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
317 version_major, version_minor);
318 }
319}
320
321void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
322{
323 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
324 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
325
326 DRM_DEBUG("GPU_INFO\n");
327 amdgpu_ucode_print_common_hdr(hdr);
328
329 if (version_major == 1) {
330 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
331 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
332
333 DRM_DEBUG("version_major: %u\n",
334 le16_to_cpu(gpu_info_hdr->version_major));
335 DRM_DEBUG("version_minor: %u\n",
336 le16_to_cpu(gpu_info_hdr->version_minor));
337 } else {
338 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
339 }
340}
341
342int amdgpu_ucode_validate(const struct firmware *fw)
343{
344 const struct common_firmware_header *hdr =
345 (const struct common_firmware_header *)fw->data;
346
347 if (fw->size == le32_to_cpu(hdr->size_bytes))
348 return 0;
349
350 return -EINVAL;
351}
352
353bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
354 uint16_t hdr_major, uint16_t hdr_minor)
355{
356 if ((hdr->common.header_version_major == hdr_major) &&
357 (hdr->common.header_version_minor == hdr_minor))
358 return false;
359 return true;
360}
361
362enum amdgpu_firmware_load_type
363amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
364{
365 switch (adev->asic_type) {
366#ifdef CONFIG_DRM_AMDGPU_SI
367 case CHIP_TAHITI:
368 case CHIP_PITCAIRN:
369 case CHIP_VERDE:
370 case CHIP_OLAND:
371 case CHIP_HAINAN:
372 return AMDGPU_FW_LOAD_DIRECT;
373#endif
374#ifdef CONFIG_DRM_AMDGPU_CIK
375 case CHIP_BONAIRE:
376 case CHIP_KAVERI:
377 case CHIP_KABINI:
378 case CHIP_HAWAII:
379 case CHIP_MULLINS:
380 return AMDGPU_FW_LOAD_DIRECT;
381#endif
382 case CHIP_TOPAZ:
383 case CHIP_TONGA:
384 case CHIP_FIJI:
385 case CHIP_CARRIZO:
386 case CHIP_STONEY:
387 case CHIP_POLARIS10:
388 case CHIP_POLARIS11:
389 case CHIP_POLARIS12:
390 case CHIP_VEGAM:
391 return AMDGPU_FW_LOAD_SMU;
392 case CHIP_VEGA10:
393 case CHIP_RAVEN:
394 case CHIP_VEGA12:
395 case CHIP_VEGA20:
396 case CHIP_ARCTURUS:
397 case CHIP_RENOIR:
398 case CHIP_NAVI10:
399 case CHIP_NAVI14:
400 case CHIP_NAVI12:
401 case CHIP_SIENNA_CICHLID:
402 case CHIP_NAVY_FLOUNDER:
403 case CHIP_VANGOGH:
404 case CHIP_DIMGREY_CAVEFISH:
405 case CHIP_ALDEBARAN:
406 case CHIP_BEIGE_GOBY:
407 case CHIP_YELLOW_CARP:
408 if (!load_type)
409 return AMDGPU_FW_LOAD_DIRECT;
410 else
411 return AMDGPU_FW_LOAD_PSP;
412 default:
413 DRM_ERROR("Unknown firmware load type\n");
414 }
415
416 return AMDGPU_FW_LOAD_DIRECT;
417}
418
419#define FW_VERSION_ATTR(name, mode, field) \
420static ssize_t show_##name(struct device *dev, \
421 struct device_attribute *attr, \
422 char *buf) \
423{ \
424 struct drm_device *ddev = dev_get_drvdata(dev); \
425 struct amdgpu_device *adev = drm_to_adev(ddev); \
426 \
427 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \
428} \
429static DEVICE_ATTR(name, mode, show_##name, NULL)
430
431FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
432FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
433FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
434FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
435FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
436FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
437FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
438FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
439FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
440FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
441FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
442FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
443FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version);
444FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version);
445FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_ras_ucode_version);
446FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_xgmi_ucode_version);
447FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
448FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
449FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
450FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
451FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
452
453static struct attribute *fw_attrs[] = {
454 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
455 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
456 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
457 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
458 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
459 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
460 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
461 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
462 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
463 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
464 &dev_attr_dmcu_fw_version.attr, NULL
465};
466
467static const struct attribute_group fw_attr_group = {
468 .name = "fw_version",
469 .attrs = fw_attrs
470};
471
472int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
473{
474 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
475}
476
477void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
478{
479 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
480}
481
482static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
483 struct amdgpu_firmware_info *ucode,
484 uint64_t mc_addr, void *kptr)
485{
486 const struct common_firmware_header *header = NULL;
487 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
488 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
489 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
490 const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
491
492 if (NULL == ucode->fw)
493 return 0;
494
495 ucode->mc_addr = mc_addr;
496 ucode->kaddr = kptr;
497
498 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
499 return 0;
500
501 header = (const struct common_firmware_header *)ucode->fw->data;
502 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
503 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
504 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
505 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
506
507 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
508 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
509 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
510 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
511 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
512 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES &&
513 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA &&
514 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
515 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
516 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
517 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&
518 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&
519 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
520 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
521 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
522 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
523
524 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
525 le32_to_cpu(header->ucode_array_offset_bytes)),
526 ucode->ucode_size);
527 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
528 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
529 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
530 le32_to_cpu(cp_hdr->jt_size) * 4;
531
532 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
533 le32_to_cpu(header->ucode_array_offset_bytes)),
534 ucode->ucode_size);
535 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
536 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
537 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
538
539 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
540 le32_to_cpu(header->ucode_array_offset_bytes) +
541 le32_to_cpu(cp_hdr->jt_offset) * 4),
542 ucode->ucode_size);
543 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
544 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
545 le32_to_cpu(dmcu_hdr->intv_size_bytes);
546
547 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
548 le32_to_cpu(header->ucode_array_offset_bytes)),
549 ucode->ucode_size);
550 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
551 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
552
553 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
554 le32_to_cpu(header->ucode_array_offset_bytes) +
555 le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
556 ucode->ucode_size);
557 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) {
558 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
559 memcpy(ucode->kaddr,
560 (void *)((uint8_t *)ucode->fw->data +
561 le32_to_cpu(header->ucode_array_offset_bytes)),
562 ucode->ucode_size);
563 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
564 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
565 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
566 ucode->ucode_size);
567 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
568 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
569 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
570 ucode->ucode_size);
571 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
572 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
573 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
574 ucode->ucode_size);
575 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {
576 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
577 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,
578 ucode->ucode_size);
579 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {
580 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
581 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,
582 ucode->ucode_size);
583 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {
584 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
585 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
586 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)),
587 ucode->ucode_size);
588 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) {
589 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
590 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
591 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)),
592 ucode->ucode_size);
593 }
594
595 return 0;
596}
597
598static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
599 uint64_t mc_addr, void *kptr)
600{
601 const struct gfx_firmware_header_v1_0 *header = NULL;
602 const struct common_firmware_header *comm_hdr = NULL;
603 uint8_t *src_addr = NULL;
604 uint8_t *dst_addr = NULL;
605
606 if (NULL == ucode->fw)
607 return 0;
608
609 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
610 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
611 dst_addr = ucode->kaddr +
612 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
613 PAGE_SIZE);
614 src_addr = (uint8_t *)ucode->fw->data +
615 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
616 (le32_to_cpu(header->jt_offset) * 4);
617 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
618
619 return 0;
620}
621
622int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
623{
624 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
625 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
626 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
627 &adev->firmware.fw_buf,
628 &adev->firmware.fw_buf_mc,
629 &adev->firmware.fw_buf_ptr);
630 if (!adev->firmware.fw_buf) {
631 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
632 return -ENOMEM;
633 } else if (amdgpu_sriov_vf(adev)) {
634 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
635 }
636 }
637 return 0;
638}
639
640void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
641{
642 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
643 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
644 &adev->firmware.fw_buf_mc,
645 &adev->firmware.fw_buf_ptr);
646}
647
648int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
649{
650 uint64_t fw_offset = 0;
651 int i;
652 struct amdgpu_firmware_info *ucode = NULL;
653
654 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
655 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
656 return 0;
657 /*
658 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
659 * ucode info here
660 */
661 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
662 if (amdgpu_sriov_vf(adev))
663 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
664 else
665 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
666 } else {
667 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
668 }
669
670 for (i = 0; i < adev->firmware.max_ucodes; i++) {
671 ucode = &adev->firmware.ucode[i];
672 if (ucode->fw) {
673 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
674 adev->firmware.fw_buf_ptr + fw_offset);
675 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
676 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
677 const struct gfx_firmware_header_v1_0 *cp_hdr;
678 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
679 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
680 adev->firmware.fw_buf_ptr + fw_offset);
681 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
682 }
683 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
684 }
685 }
686 return 0;
687}
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <drm/drmP.h>
28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30
31static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32{
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44}
45
46void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47{
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65}
66
67void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68{
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71
72 DRM_DEBUG("SMC\n");
73 amdgpu_ucode_print_common_hdr(hdr);
74
75 if (version_major == 1) {
76 const struct smc_firmware_header_v1_0 *smc_hdr =
77 container_of(hdr, struct smc_firmware_header_v1_0, header);
78
79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
80 } else {
81 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
82 }
83}
84
85void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
86{
87 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
88 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
89
90 DRM_DEBUG("GFX\n");
91 amdgpu_ucode_print_common_hdr(hdr);
92
93 if (version_major == 1) {
94 const struct gfx_firmware_header_v1_0 *gfx_hdr =
95 container_of(hdr, struct gfx_firmware_header_v1_0, header);
96
97 DRM_DEBUG("ucode_feature_version: %u\n",
98 le32_to_cpu(gfx_hdr->ucode_feature_version));
99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
100 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
101 } else {
102 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
103 }
104}
105
106void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
107{
108 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
109 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
110
111 DRM_DEBUG("RLC\n");
112 amdgpu_ucode_print_common_hdr(hdr);
113
114 if (version_major == 1) {
115 const struct rlc_firmware_header_v1_0 *rlc_hdr =
116 container_of(hdr, struct rlc_firmware_header_v1_0, header);
117
118 DRM_DEBUG("ucode_feature_version: %u\n",
119 le32_to_cpu(rlc_hdr->ucode_feature_version));
120 DRM_DEBUG("save_and_restore_offset: %u\n",
121 le32_to_cpu(rlc_hdr->save_and_restore_offset));
122 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
124 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
126 DRM_DEBUG("master_pkt_description_offset: %u\n",
127 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
128 } else if (version_major == 2) {
129 const struct rlc_firmware_header_v2_0 *rlc_hdr =
130 container_of(hdr, struct rlc_firmware_header_v2_0, header);
131
132 DRM_DEBUG("ucode_feature_version: %u\n",
133 le32_to_cpu(rlc_hdr->ucode_feature_version));
134 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
135 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
136 DRM_DEBUG("save_and_restore_offset: %u\n",
137 le32_to_cpu(rlc_hdr->save_and_restore_offset));
138 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
139 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
140 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
141 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
142 DRM_DEBUG("reg_restore_list_size: %u\n",
143 le32_to_cpu(rlc_hdr->reg_restore_list_size));
144 DRM_DEBUG("reg_list_format_start: %u\n",
145 le32_to_cpu(rlc_hdr->reg_list_format_start));
146 DRM_DEBUG("reg_list_format_separate_start: %u\n",
147 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
148 DRM_DEBUG("starting_offsets_start: %u\n",
149 le32_to_cpu(rlc_hdr->starting_offsets_start));
150 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
151 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
152 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
153 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
154 DRM_DEBUG("reg_list_size_bytes: %u\n",
155 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
156 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
157 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
158 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
159 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
160 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
161 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
162 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
163 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
164 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
165 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
166 } else {
167 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
168 }
169}
170
171void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
172{
173 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
174 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
175
176 DRM_DEBUG("SDMA\n");
177 amdgpu_ucode_print_common_hdr(hdr);
178
179 if (version_major == 1) {
180 const struct sdma_firmware_header_v1_0 *sdma_hdr =
181 container_of(hdr, struct sdma_firmware_header_v1_0, header);
182
183 DRM_DEBUG("ucode_feature_version: %u\n",
184 le32_to_cpu(sdma_hdr->ucode_feature_version));
185 DRM_DEBUG("ucode_change_version: %u\n",
186 le32_to_cpu(sdma_hdr->ucode_change_version));
187 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
188 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
189 if (version_minor >= 1) {
190 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
191 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
192 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
193 }
194 } else {
195 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
196 version_major, version_minor);
197 }
198}
199
200int amdgpu_ucode_validate(const struct firmware *fw)
201{
202 const struct common_firmware_header *hdr =
203 (const struct common_firmware_header *)fw->data;
204
205 if (fw->size == le32_to_cpu(hdr->size_bytes))
206 return 0;
207
208 return -EINVAL;
209}
210
211bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
212 uint16_t hdr_major, uint16_t hdr_minor)
213{
214 if ((hdr->common.header_version_major == hdr_major) &&
215 (hdr->common.header_version_minor == hdr_minor))
216 return false;
217 return true;
218}
219
220static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
221 uint64_t mc_addr, void *kptr)
222{
223 const struct common_firmware_header *header = NULL;
224
225 if (NULL == ucode->fw)
226 return 0;
227
228 ucode->mc_addr = mc_addr;
229 ucode->kaddr = kptr;
230
231 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
232 return 0;
233
234 header = (const struct common_firmware_header *)ucode->fw->data;
235 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
236 le32_to_cpu(header->ucode_array_offset_bytes)),
237 le32_to_cpu(header->ucode_size_bytes));
238
239 return 0;
240}
241
242static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
243 uint64_t mc_addr, void *kptr)
244{
245 const struct gfx_firmware_header_v1_0 *header = NULL;
246 const struct common_firmware_header *comm_hdr = NULL;
247 uint8_t* src_addr = NULL;
248 uint8_t* dst_addr = NULL;
249
250 if (NULL == ucode->fw)
251 return 0;
252
253 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
254 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
255 dst_addr = ucode->kaddr +
256 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
257 PAGE_SIZE);
258 src_addr = (uint8_t *)ucode->fw->data +
259 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
260 (le32_to_cpu(header->jt_offset) * 4);
261 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
262
263 return 0;
264}
265
266
267int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
268{
269 struct amdgpu_bo **bo = &adev->firmware.fw_buf;
270 uint64_t fw_mc_addr;
271 void *fw_buf_ptr = NULL;
272 uint64_t fw_offset = 0;
273 int i, err;
274 struct amdgpu_firmware_info *ucode = NULL;
275 const struct common_firmware_header *header = NULL;
276
277 err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
278 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
279 0, NULL, NULL, bo);
280 if (err) {
281 dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
282 goto failed;
283 }
284
285 err = amdgpu_bo_reserve(*bo, false);
286 if (err) {
287 dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
288 goto failed_reserve;
289 }
290
291 err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
292 &fw_mc_addr);
293 if (err) {
294 dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
295 goto failed_pin;
296 }
297
298 err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
299 if (err) {
300 dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
301 goto failed_kmap;
302 }
303
304 amdgpu_bo_unreserve(*bo);
305
306 for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
307 ucode = &adev->firmware.ucode[i];
308 if (ucode->fw) {
309 header = (const struct common_firmware_header *)ucode->fw->data;
310 amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset,
311 fw_buf_ptr + fw_offset);
312 if (i == AMDGPU_UCODE_ID_CP_MEC1) {
313 const struct gfx_firmware_header_v1_0 *cp_hdr;
314 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
315 amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
316 fw_buf_ptr + fw_offset);
317 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
318 }
319 fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
320 }
321 }
322 return 0;
323
324failed_kmap:
325 amdgpu_bo_unpin(*bo);
326failed_pin:
327 amdgpu_bo_unreserve(*bo);
328failed_reserve:
329 amdgpu_bo_unref(bo);
330failed:
331 adev->firmware.smu_load = false;
332
333 return err;
334}
335
336int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
337{
338 int i;
339 struct amdgpu_firmware_info *ucode = NULL;
340
341 for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
342 ucode = &adev->firmware.ucode[i];
343 if (ucode->fw) {
344 ucode->mc_addr = 0;
345 ucode->kaddr = NULL;
346 }
347 }
348 amdgpu_bo_unref(&adev->firmware.fw_buf);
349 adev->firmware.fw_buf = NULL;
350
351 return 0;
352}