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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
4 *
5 * Rewrite, cleanup, new allocation schemes, virtual merging:
6 * Copyright (C) 2004 Olof Johansson, IBM Corporation
7 * and Ben. Herrenschmidt, IBM Corporation
8 *
9 * Dynamic DMA mapping support, bus-independent parts.
10 */
11
12
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/slab.h>
16#include <linux/mm.h>
17#include <linux/spinlock.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/bitmap.h>
21#include <linux/iommu-helper.h>
22#include <linux/crash_dump.h>
23#include <linux/hash.h>
24#include <linux/fault-inject.h>
25#include <linux/pci.h>
26#include <linux/iommu.h>
27#include <linux/sched.h>
28#include <linux/debugfs.h>
29#include <asm/io.h>
30#include <asm/prom.h>
31#include <asm/iommu.h>
32#include <asm/pci-bridge.h>
33#include <asm/machdep.h>
34#include <asm/kdump.h>
35#include <asm/fadump.h>
36#include <asm/vio.h>
37#include <asm/tce.h>
38#include <asm/mmu_context.h>
39
40#define DBG(...)
41
42#ifdef CONFIG_IOMMU_DEBUGFS
43static int iommu_debugfs_weight_get(void *data, u64 *val)
44{
45 struct iommu_table *tbl = data;
46 *val = bitmap_weight(tbl->it_map, tbl->it_size);
47 return 0;
48}
49DEFINE_DEBUGFS_ATTRIBUTE(iommu_debugfs_fops_weight, iommu_debugfs_weight_get, NULL, "%llu\n");
50
51static void iommu_debugfs_add(struct iommu_table *tbl)
52{
53 char name[10];
54 struct dentry *liobn_entry;
55
56 sprintf(name, "%08lx", tbl->it_index);
57 liobn_entry = debugfs_create_dir(name, iommu_debugfs_dir);
58
59 debugfs_create_file_unsafe("weight", 0400, liobn_entry, tbl, &iommu_debugfs_fops_weight);
60 debugfs_create_ulong("it_size", 0400, liobn_entry, &tbl->it_size);
61 debugfs_create_ulong("it_page_shift", 0400, liobn_entry, &tbl->it_page_shift);
62 debugfs_create_ulong("it_reserved_start", 0400, liobn_entry, &tbl->it_reserved_start);
63 debugfs_create_ulong("it_reserved_end", 0400, liobn_entry, &tbl->it_reserved_end);
64 debugfs_create_ulong("it_indirect_levels", 0400, liobn_entry, &tbl->it_indirect_levels);
65 debugfs_create_ulong("it_level_size", 0400, liobn_entry, &tbl->it_level_size);
66}
67
68static void iommu_debugfs_del(struct iommu_table *tbl)
69{
70 char name[10];
71 struct dentry *liobn_entry;
72
73 sprintf(name, "%08lx", tbl->it_index);
74 liobn_entry = debugfs_lookup(name, iommu_debugfs_dir);
75 debugfs_remove(liobn_entry);
76}
77#else
78static void iommu_debugfs_add(struct iommu_table *tbl){}
79static void iommu_debugfs_del(struct iommu_table *tbl){}
80#endif
81
82static int novmerge;
83
84static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
85
86static int __init setup_iommu(char *str)
87{
88 if (!strcmp(str, "novmerge"))
89 novmerge = 1;
90 else if (!strcmp(str, "vmerge"))
91 novmerge = 0;
92 return 1;
93}
94
95__setup("iommu=", setup_iommu);
96
97static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
98
99/*
100 * We precalculate the hash to avoid doing it on every allocation.
101 *
102 * The hash is important to spread CPUs across all the pools. For example,
103 * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
104 * with 4 pools all primary threads would map to the same pool.
105 */
106static int __init setup_iommu_pool_hash(void)
107{
108 unsigned int i;
109
110 for_each_possible_cpu(i)
111 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
112
113 return 0;
114}
115subsys_initcall(setup_iommu_pool_hash);
116
117#ifdef CONFIG_FAIL_IOMMU
118
119static DECLARE_FAULT_ATTR(fail_iommu);
120
121static int __init setup_fail_iommu(char *str)
122{
123 return setup_fault_attr(&fail_iommu, str);
124}
125__setup("fail_iommu=", setup_fail_iommu);
126
127static bool should_fail_iommu(struct device *dev)
128{
129 return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
130}
131
132static int __init fail_iommu_debugfs(void)
133{
134 struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
135 NULL, &fail_iommu);
136
137 return PTR_ERR_OR_ZERO(dir);
138}
139late_initcall(fail_iommu_debugfs);
140
141static ssize_t fail_iommu_show(struct device *dev,
142 struct device_attribute *attr, char *buf)
143{
144 return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
145}
146
147static ssize_t fail_iommu_store(struct device *dev,
148 struct device_attribute *attr, const char *buf,
149 size_t count)
150{
151 int i;
152
153 if (count > 0 && sscanf(buf, "%d", &i) > 0)
154 dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
155
156 return count;
157}
158
159static DEVICE_ATTR_RW(fail_iommu);
160
161static int fail_iommu_bus_notify(struct notifier_block *nb,
162 unsigned long action, void *data)
163{
164 struct device *dev = data;
165
166 if (action == BUS_NOTIFY_ADD_DEVICE) {
167 if (device_create_file(dev, &dev_attr_fail_iommu))
168 pr_warn("Unable to create IOMMU fault injection sysfs "
169 "entries\n");
170 } else if (action == BUS_NOTIFY_DEL_DEVICE) {
171 device_remove_file(dev, &dev_attr_fail_iommu);
172 }
173
174 return 0;
175}
176
177static struct notifier_block fail_iommu_bus_notifier = {
178 .notifier_call = fail_iommu_bus_notify
179};
180
181static int __init fail_iommu_setup(void)
182{
183#ifdef CONFIG_PCI
184 bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
185#endif
186#ifdef CONFIG_IBMVIO
187 bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
188#endif
189
190 return 0;
191}
192/*
193 * Must execute after PCI and VIO subsystem have initialised but before
194 * devices are probed.
195 */
196arch_initcall(fail_iommu_setup);
197#else
198static inline bool should_fail_iommu(struct device *dev)
199{
200 return false;
201}
202#endif
203
204static unsigned long iommu_range_alloc(struct device *dev,
205 struct iommu_table *tbl,
206 unsigned long npages,
207 unsigned long *handle,
208 unsigned long mask,
209 unsigned int align_order)
210{
211 unsigned long n, end, start;
212 unsigned long limit;
213 int largealloc = npages > 15;
214 int pass = 0;
215 unsigned long align_mask;
216 unsigned long flags;
217 unsigned int pool_nr;
218 struct iommu_pool *pool;
219
220 align_mask = (1ull << align_order) - 1;
221
222 /* This allocator was derived from x86_64's bit string search */
223
224 /* Sanity check */
225 if (unlikely(npages == 0)) {
226 if (printk_ratelimit())
227 WARN_ON(1);
228 return DMA_MAPPING_ERROR;
229 }
230
231 if (should_fail_iommu(dev))
232 return DMA_MAPPING_ERROR;
233
234 /*
235 * We don't need to disable preemption here because any CPU can
236 * safely use any IOMMU pool.
237 */
238 pool_nr = raw_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1);
239
240 if (largealloc)
241 pool = &(tbl->large_pool);
242 else
243 pool = &(tbl->pools[pool_nr]);
244
245 spin_lock_irqsave(&(pool->lock), flags);
246
247again:
248 if ((pass == 0) && handle && *handle &&
249 (*handle >= pool->start) && (*handle < pool->end))
250 start = *handle;
251 else
252 start = pool->hint;
253
254 limit = pool->end;
255
256 /* The case below can happen if we have a small segment appended
257 * to a large, or when the previous alloc was at the very end of
258 * the available space. If so, go back to the initial start.
259 */
260 if (start >= limit)
261 start = pool->start;
262
263 if (limit + tbl->it_offset > mask) {
264 limit = mask - tbl->it_offset + 1;
265 /* If we're constrained on address range, first try
266 * at the masked hint to avoid O(n) search complexity,
267 * but on second pass, start at 0 in pool 0.
268 */
269 if ((start & mask) >= limit || pass > 0) {
270 spin_unlock(&(pool->lock));
271 pool = &(tbl->pools[0]);
272 spin_lock(&(pool->lock));
273 start = pool->start;
274 } else {
275 start &= mask;
276 }
277 }
278
279 n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
280 dma_get_seg_boundary_nr_pages(dev, tbl->it_page_shift),
281 align_mask);
282 if (n == -1) {
283 if (likely(pass == 0)) {
284 /* First try the pool from the start */
285 pool->hint = pool->start;
286 pass++;
287 goto again;
288
289 } else if (pass <= tbl->nr_pools) {
290 /* Now try scanning all the other pools */
291 spin_unlock(&(pool->lock));
292 pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
293 pool = &tbl->pools[pool_nr];
294 spin_lock(&(pool->lock));
295 pool->hint = pool->start;
296 pass++;
297 goto again;
298
299 } else if (pass == tbl->nr_pools + 1) {
300 /* Last resort: try largepool */
301 spin_unlock(&pool->lock);
302 pool = &tbl->large_pool;
303 spin_lock(&pool->lock);
304 pool->hint = pool->start;
305 pass++;
306 goto again;
307
308 } else {
309 /* Give up */
310 spin_unlock_irqrestore(&(pool->lock), flags);
311 return DMA_MAPPING_ERROR;
312 }
313 }
314
315 end = n + npages;
316
317 /* Bump the hint to a new block for small allocs. */
318 if (largealloc) {
319 /* Don't bump to new block to avoid fragmentation */
320 pool->hint = end;
321 } else {
322 /* Overflow will be taken care of at the next allocation */
323 pool->hint = (end + tbl->it_blocksize - 1) &
324 ~(tbl->it_blocksize - 1);
325 }
326
327 /* Update handle for SG allocations */
328 if (handle)
329 *handle = end;
330
331 spin_unlock_irqrestore(&(pool->lock), flags);
332
333 return n;
334}
335
336static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
337 void *page, unsigned int npages,
338 enum dma_data_direction direction,
339 unsigned long mask, unsigned int align_order,
340 unsigned long attrs)
341{
342 unsigned long entry;
343 dma_addr_t ret = DMA_MAPPING_ERROR;
344 int build_fail;
345
346 entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
347
348 if (unlikely(entry == DMA_MAPPING_ERROR))
349 return DMA_MAPPING_ERROR;
350
351 entry += tbl->it_offset; /* Offset into real TCE table */
352 ret = entry << tbl->it_page_shift; /* Set the return dma address */
353
354 /* Put the TCEs in the HW table */
355 build_fail = tbl->it_ops->set(tbl, entry, npages,
356 (unsigned long)page &
357 IOMMU_PAGE_MASK(tbl), direction, attrs);
358
359 /* tbl->it_ops->set() only returns non-zero for transient errors.
360 * Clean up the table bitmap in this case and return
361 * DMA_MAPPING_ERROR. For all other errors the functionality is
362 * not altered.
363 */
364 if (unlikely(build_fail)) {
365 __iommu_free(tbl, ret, npages);
366 return DMA_MAPPING_ERROR;
367 }
368
369 /* Flush/invalidate TLB caches if necessary */
370 if (tbl->it_ops->flush)
371 tbl->it_ops->flush(tbl);
372
373 /* Make sure updates are seen by hardware */
374 mb();
375
376 return ret;
377}
378
379static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
380 unsigned int npages)
381{
382 unsigned long entry, free_entry;
383
384 entry = dma_addr >> tbl->it_page_shift;
385 free_entry = entry - tbl->it_offset;
386
387 if (((free_entry + npages) > tbl->it_size) ||
388 (entry < tbl->it_offset)) {
389 if (printk_ratelimit()) {
390 printk(KERN_INFO "iommu_free: invalid entry\n");
391 printk(KERN_INFO "\tentry = 0x%lx\n", entry);
392 printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr);
393 printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl);
394 printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno);
395 printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size);
396 printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset);
397 printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index);
398 WARN_ON(1);
399 }
400
401 return false;
402 }
403
404 return true;
405}
406
407static struct iommu_pool *get_pool(struct iommu_table *tbl,
408 unsigned long entry)
409{
410 struct iommu_pool *p;
411 unsigned long largepool_start = tbl->large_pool.start;
412
413 /* The large pool is the last pool at the top of the table */
414 if (entry >= largepool_start) {
415 p = &tbl->large_pool;
416 } else {
417 unsigned int pool_nr = entry / tbl->poolsize;
418
419 BUG_ON(pool_nr > tbl->nr_pools);
420 p = &tbl->pools[pool_nr];
421 }
422
423 return p;
424}
425
426static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
427 unsigned int npages)
428{
429 unsigned long entry, free_entry;
430 unsigned long flags;
431 struct iommu_pool *pool;
432
433 entry = dma_addr >> tbl->it_page_shift;
434 free_entry = entry - tbl->it_offset;
435
436 pool = get_pool(tbl, free_entry);
437
438 if (!iommu_free_check(tbl, dma_addr, npages))
439 return;
440
441 tbl->it_ops->clear(tbl, entry, npages);
442
443 spin_lock_irqsave(&(pool->lock), flags);
444 bitmap_clear(tbl->it_map, free_entry, npages);
445 spin_unlock_irqrestore(&(pool->lock), flags);
446}
447
448static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
449 unsigned int npages)
450{
451 __iommu_free(tbl, dma_addr, npages);
452
453 /* Make sure TLB cache is flushed if the HW needs it. We do
454 * not do an mb() here on purpose, it is not needed on any of
455 * the current platforms.
456 */
457 if (tbl->it_ops->flush)
458 tbl->it_ops->flush(tbl);
459}
460
461int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
462 struct scatterlist *sglist, int nelems,
463 unsigned long mask, enum dma_data_direction direction,
464 unsigned long attrs)
465{
466 dma_addr_t dma_next = 0, dma_addr;
467 struct scatterlist *s, *outs, *segstart;
468 int outcount, incount, i, build_fail = 0;
469 unsigned int align;
470 unsigned long handle;
471 unsigned int max_seg_size;
472
473 BUG_ON(direction == DMA_NONE);
474
475 if ((nelems == 0) || !tbl)
476 return 0;
477
478 outs = s = segstart = &sglist[0];
479 outcount = 1;
480 incount = nelems;
481 handle = 0;
482
483 /* Init first segment length for backout at failure */
484 outs->dma_length = 0;
485
486 DBG("sg mapping %d elements:\n", nelems);
487
488 max_seg_size = dma_get_max_seg_size(dev);
489 for_each_sg(sglist, s, nelems, i) {
490 unsigned long vaddr, npages, entry, slen;
491
492 slen = s->length;
493 /* Sanity check */
494 if (slen == 0) {
495 dma_next = 0;
496 continue;
497 }
498 /* Allocate iommu entries for that segment */
499 vaddr = (unsigned long) sg_virt(s);
500 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
501 align = 0;
502 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
503 (vaddr & ~PAGE_MASK) == 0)
504 align = PAGE_SHIFT - tbl->it_page_shift;
505 entry = iommu_range_alloc(dev, tbl, npages, &handle,
506 mask >> tbl->it_page_shift, align);
507
508 DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
509
510 /* Handle failure */
511 if (unlikely(entry == DMA_MAPPING_ERROR)) {
512 if (!(attrs & DMA_ATTR_NO_WARN) &&
513 printk_ratelimit())
514 dev_info(dev, "iommu_alloc failed, tbl %p "
515 "vaddr %lx npages %lu\n", tbl, vaddr,
516 npages);
517 goto failure;
518 }
519
520 /* Convert entry to a dma_addr_t */
521 entry += tbl->it_offset;
522 dma_addr = entry << tbl->it_page_shift;
523 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
524
525 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
526 npages, entry, dma_addr);
527
528 /* Insert into HW table */
529 build_fail = tbl->it_ops->set(tbl, entry, npages,
530 vaddr & IOMMU_PAGE_MASK(tbl),
531 direction, attrs);
532 if(unlikely(build_fail))
533 goto failure;
534
535 /* If we are in an open segment, try merging */
536 if (segstart != s) {
537 DBG(" - trying merge...\n");
538 /* We cannot merge if:
539 * - allocated dma_addr isn't contiguous to previous allocation
540 */
541 if (novmerge || (dma_addr != dma_next) ||
542 (outs->dma_length + s->length > max_seg_size)) {
543 /* Can't merge: create a new segment */
544 segstart = s;
545 outcount++;
546 outs = sg_next(outs);
547 DBG(" can't merge, new segment.\n");
548 } else {
549 outs->dma_length += s->length;
550 DBG(" merged, new len: %ux\n", outs->dma_length);
551 }
552 }
553
554 if (segstart == s) {
555 /* This is a new segment, fill entries */
556 DBG(" - filling new segment.\n");
557 outs->dma_address = dma_addr;
558 outs->dma_length = slen;
559 }
560
561 /* Calculate next page pointer for contiguous check */
562 dma_next = dma_addr + slen;
563
564 DBG(" - dma next is: %lx\n", dma_next);
565 }
566
567 /* Flush/invalidate TLB caches if necessary */
568 if (tbl->it_ops->flush)
569 tbl->it_ops->flush(tbl);
570
571 DBG("mapped %d elements:\n", outcount);
572
573 /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
574 * next entry of the sglist if we didn't fill the list completely
575 */
576 if (outcount < incount) {
577 outs = sg_next(outs);
578 outs->dma_address = DMA_MAPPING_ERROR;
579 outs->dma_length = 0;
580 }
581
582 /* Make sure updates are seen by hardware */
583 mb();
584
585 return outcount;
586
587 failure:
588 for_each_sg(sglist, s, nelems, i) {
589 if (s->dma_length != 0) {
590 unsigned long vaddr, npages;
591
592 vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
593 npages = iommu_num_pages(s->dma_address, s->dma_length,
594 IOMMU_PAGE_SIZE(tbl));
595 __iommu_free(tbl, vaddr, npages);
596 s->dma_address = DMA_MAPPING_ERROR;
597 s->dma_length = 0;
598 }
599 if (s == outs)
600 break;
601 }
602 return 0;
603}
604
605
606void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
607 int nelems, enum dma_data_direction direction,
608 unsigned long attrs)
609{
610 struct scatterlist *sg;
611
612 BUG_ON(direction == DMA_NONE);
613
614 if (!tbl)
615 return;
616
617 sg = sglist;
618 while (nelems--) {
619 unsigned int npages;
620 dma_addr_t dma_handle = sg->dma_address;
621
622 if (sg->dma_length == 0)
623 break;
624 npages = iommu_num_pages(dma_handle, sg->dma_length,
625 IOMMU_PAGE_SIZE(tbl));
626 __iommu_free(tbl, dma_handle, npages);
627 sg = sg_next(sg);
628 }
629
630 /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
631 * do not do an mb() here, the affected platforms do not need it
632 * when freeing.
633 */
634 if (tbl->it_ops->flush)
635 tbl->it_ops->flush(tbl);
636}
637
638static void iommu_table_clear(struct iommu_table *tbl)
639{
640 /*
641 * In case of firmware assisted dump system goes through clean
642 * reboot process at the time of system crash. Hence it's safe to
643 * clear the TCE entries if firmware assisted dump is active.
644 */
645 if (!is_kdump_kernel() || is_fadump_active()) {
646 /* Clear the table in case firmware left allocations in it */
647 tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
648 return;
649 }
650
651#ifdef CONFIG_CRASH_DUMP
652 if (tbl->it_ops->get) {
653 unsigned long index, tceval, tcecount = 0;
654
655 /* Reserve the existing mappings left by the first kernel. */
656 for (index = 0; index < tbl->it_size; index++) {
657 tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
658 /*
659 * Freed TCE entry contains 0x7fffffffffffffff on JS20
660 */
661 if (tceval && (tceval != 0x7fffffffffffffffUL)) {
662 __set_bit(index, tbl->it_map);
663 tcecount++;
664 }
665 }
666
667 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
668 printk(KERN_WARNING "TCE table is full; freeing ");
669 printk(KERN_WARNING "%d entries for the kdump boot\n",
670 KDUMP_MIN_TCE_ENTRIES);
671 for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
672 index < tbl->it_size; index++)
673 __clear_bit(index, tbl->it_map);
674 }
675 }
676#endif
677}
678
679static void iommu_table_reserve_pages(struct iommu_table *tbl,
680 unsigned long res_start, unsigned long res_end)
681{
682 int i;
683
684 WARN_ON_ONCE(res_end < res_start);
685 /*
686 * Reserve page 0 so it will not be used for any mappings.
687 * This avoids buggy drivers that consider page 0 to be invalid
688 * to crash the machine or even lose data.
689 */
690 if (tbl->it_offset == 0)
691 set_bit(0, tbl->it_map);
692
693 tbl->it_reserved_start = res_start;
694 tbl->it_reserved_end = res_end;
695
696 /* Check if res_start..res_end isn't empty and overlaps the table */
697 if (res_start && res_end &&
698 (tbl->it_offset + tbl->it_size < res_start ||
699 res_end < tbl->it_offset))
700 return;
701
702 for (i = tbl->it_reserved_start; i < tbl->it_reserved_end; ++i)
703 set_bit(i - tbl->it_offset, tbl->it_map);
704}
705
706static void iommu_table_release_pages(struct iommu_table *tbl)
707{
708 int i;
709
710 /*
711 * In case we have reserved the first bit, we should not emit
712 * the warning below.
713 */
714 if (tbl->it_offset == 0)
715 clear_bit(0, tbl->it_map);
716
717 for (i = tbl->it_reserved_start; i < tbl->it_reserved_end; ++i)
718 clear_bit(i - tbl->it_offset, tbl->it_map);
719}
720
721/*
722 * Build a iommu_table structure. This contains a bit map which
723 * is used to manage allocation of the tce space.
724 */
725struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid,
726 unsigned long res_start, unsigned long res_end)
727{
728 unsigned long sz;
729 static int welcomed = 0;
730 unsigned int i;
731 struct iommu_pool *p;
732
733 BUG_ON(!tbl->it_ops);
734
735 /* number of bytes needed for the bitmap */
736 sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
737
738 tbl->it_map = vzalloc_node(sz, nid);
739 if (!tbl->it_map) {
740 pr_err("%s: Can't allocate %ld bytes\n", __func__, sz);
741 return NULL;
742 }
743
744 iommu_table_reserve_pages(tbl, res_start, res_end);
745
746 /* We only split the IOMMU table if we have 1GB or more of space */
747 if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
748 tbl->nr_pools = IOMMU_NR_POOLS;
749 else
750 tbl->nr_pools = 1;
751
752 /* We reserve the top 1/4 of the table for large allocations */
753 tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
754
755 for (i = 0; i < tbl->nr_pools; i++) {
756 p = &tbl->pools[i];
757 spin_lock_init(&(p->lock));
758 p->start = tbl->poolsize * i;
759 p->hint = p->start;
760 p->end = p->start + tbl->poolsize;
761 }
762
763 p = &tbl->large_pool;
764 spin_lock_init(&(p->lock));
765 p->start = tbl->poolsize * i;
766 p->hint = p->start;
767 p->end = tbl->it_size;
768
769 iommu_table_clear(tbl);
770
771 if (!welcomed) {
772 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
773 novmerge ? "disabled" : "enabled");
774 welcomed = 1;
775 }
776
777 iommu_debugfs_add(tbl);
778
779 return tbl;
780}
781
782static void iommu_table_free(struct kref *kref)
783{
784 struct iommu_table *tbl;
785
786 tbl = container_of(kref, struct iommu_table, it_kref);
787
788 if (tbl->it_ops->free)
789 tbl->it_ops->free(tbl);
790
791 if (!tbl->it_map) {
792 kfree(tbl);
793 return;
794 }
795
796 iommu_debugfs_del(tbl);
797
798 iommu_table_release_pages(tbl);
799
800 /* verify that table contains no entries */
801 if (!bitmap_empty(tbl->it_map, tbl->it_size))
802 pr_warn("%s: Unexpected TCEs\n", __func__);
803
804 /* free bitmap */
805 vfree(tbl->it_map);
806
807 /* free table */
808 kfree(tbl);
809}
810
811struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl)
812{
813 if (kref_get_unless_zero(&tbl->it_kref))
814 return tbl;
815
816 return NULL;
817}
818EXPORT_SYMBOL_GPL(iommu_tce_table_get);
819
820int iommu_tce_table_put(struct iommu_table *tbl)
821{
822 if (WARN_ON(!tbl))
823 return 0;
824
825 return kref_put(&tbl->it_kref, iommu_table_free);
826}
827EXPORT_SYMBOL_GPL(iommu_tce_table_put);
828
829/* Creates TCEs for a user provided buffer. The user buffer must be
830 * contiguous real kernel storage (not vmalloc). The address passed here
831 * comprises a page address and offset into that page. The dma_addr_t
832 * returned will point to the same byte within the page as was passed in.
833 */
834dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
835 struct page *page, unsigned long offset, size_t size,
836 unsigned long mask, enum dma_data_direction direction,
837 unsigned long attrs)
838{
839 dma_addr_t dma_handle = DMA_MAPPING_ERROR;
840 void *vaddr;
841 unsigned long uaddr;
842 unsigned int npages, align;
843
844 BUG_ON(direction == DMA_NONE);
845
846 vaddr = page_address(page) + offset;
847 uaddr = (unsigned long)vaddr;
848
849 if (tbl) {
850 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
851 align = 0;
852 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
853 ((unsigned long)vaddr & ~PAGE_MASK) == 0)
854 align = PAGE_SHIFT - tbl->it_page_shift;
855
856 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
857 mask >> tbl->it_page_shift, align,
858 attrs);
859 if (dma_handle == DMA_MAPPING_ERROR) {
860 if (!(attrs & DMA_ATTR_NO_WARN) &&
861 printk_ratelimit()) {
862 dev_info(dev, "iommu_alloc failed, tbl %p "
863 "vaddr %p npages %d\n", tbl, vaddr,
864 npages);
865 }
866 } else
867 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
868 }
869
870 return dma_handle;
871}
872
873void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
874 size_t size, enum dma_data_direction direction,
875 unsigned long attrs)
876{
877 unsigned int npages;
878
879 BUG_ON(direction == DMA_NONE);
880
881 if (tbl) {
882 npages = iommu_num_pages(dma_handle, size,
883 IOMMU_PAGE_SIZE(tbl));
884 iommu_free(tbl, dma_handle, npages);
885 }
886}
887
888/* Allocates a contiguous real buffer and creates mappings over it.
889 * Returns the virtual address of the buffer and sets dma_handle
890 * to the dma address (mapping) of the first page.
891 */
892void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
893 size_t size, dma_addr_t *dma_handle,
894 unsigned long mask, gfp_t flag, int node)
895{
896 void *ret = NULL;
897 dma_addr_t mapping;
898 unsigned int order;
899 unsigned int nio_pages, io_order;
900 struct page *page;
901
902 size = PAGE_ALIGN(size);
903 order = get_order(size);
904
905 /*
906 * Client asked for way too much space. This is checked later
907 * anyway. It is easier to debug here for the drivers than in
908 * the tce tables.
909 */
910 if (order >= IOMAP_MAX_ORDER) {
911 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
912 size);
913 return NULL;
914 }
915
916 if (!tbl)
917 return NULL;
918
919 /* Alloc enough pages (and possibly more) */
920 page = alloc_pages_node(node, flag, order);
921 if (!page)
922 return NULL;
923 ret = page_address(page);
924 memset(ret, 0, size);
925
926 /* Set up tces to cover the allocated range */
927 nio_pages = size >> tbl->it_page_shift;
928 io_order = get_iommu_order(size, tbl);
929 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
930 mask >> tbl->it_page_shift, io_order, 0);
931 if (mapping == DMA_MAPPING_ERROR) {
932 free_pages((unsigned long)ret, order);
933 return NULL;
934 }
935 *dma_handle = mapping;
936 return ret;
937}
938
939void iommu_free_coherent(struct iommu_table *tbl, size_t size,
940 void *vaddr, dma_addr_t dma_handle)
941{
942 if (tbl) {
943 unsigned int nio_pages;
944
945 size = PAGE_ALIGN(size);
946 nio_pages = size >> tbl->it_page_shift;
947 iommu_free(tbl, dma_handle, nio_pages);
948 size = PAGE_ALIGN(size);
949 free_pages((unsigned long)vaddr, get_order(size));
950 }
951}
952
953unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
954{
955 switch (dir) {
956 case DMA_BIDIRECTIONAL:
957 return TCE_PCI_READ | TCE_PCI_WRITE;
958 case DMA_FROM_DEVICE:
959 return TCE_PCI_WRITE;
960 case DMA_TO_DEVICE:
961 return TCE_PCI_READ;
962 default:
963 return 0;
964 }
965}
966EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
967
968#ifdef CONFIG_IOMMU_API
969/*
970 * SPAPR TCE API
971 */
972static void group_release(void *iommu_data)
973{
974 struct iommu_table_group *table_group = iommu_data;
975
976 table_group->group = NULL;
977}
978
979void iommu_register_group(struct iommu_table_group *table_group,
980 int pci_domain_number, unsigned long pe_num)
981{
982 struct iommu_group *grp;
983 char *name;
984
985 grp = iommu_group_alloc();
986 if (IS_ERR(grp)) {
987 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
988 PTR_ERR(grp));
989 return;
990 }
991 table_group->group = grp;
992 iommu_group_set_iommudata(grp, table_group, group_release);
993 name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
994 pci_domain_number, pe_num);
995 if (!name)
996 return;
997 iommu_group_set_name(grp, name);
998 kfree(name);
999}
1000
1001enum dma_data_direction iommu_tce_direction(unsigned long tce)
1002{
1003 if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
1004 return DMA_BIDIRECTIONAL;
1005 else if (tce & TCE_PCI_READ)
1006 return DMA_TO_DEVICE;
1007 else if (tce & TCE_PCI_WRITE)
1008 return DMA_FROM_DEVICE;
1009 else
1010 return DMA_NONE;
1011}
1012EXPORT_SYMBOL_GPL(iommu_tce_direction);
1013
1014void iommu_flush_tce(struct iommu_table *tbl)
1015{
1016 /* Flush/invalidate TLB caches if necessary */
1017 if (tbl->it_ops->flush)
1018 tbl->it_ops->flush(tbl);
1019
1020 /* Make sure updates are seen by hardware */
1021 mb();
1022}
1023EXPORT_SYMBOL_GPL(iommu_flush_tce);
1024
1025int iommu_tce_check_ioba(unsigned long page_shift,
1026 unsigned long offset, unsigned long size,
1027 unsigned long ioba, unsigned long npages)
1028{
1029 unsigned long mask = (1UL << page_shift) - 1;
1030
1031 if (ioba & mask)
1032 return -EINVAL;
1033
1034 ioba >>= page_shift;
1035 if (ioba < offset)
1036 return -EINVAL;
1037
1038 if ((ioba + 1) > (offset + size))
1039 return -EINVAL;
1040
1041 return 0;
1042}
1043EXPORT_SYMBOL_GPL(iommu_tce_check_ioba);
1044
1045int iommu_tce_check_gpa(unsigned long page_shift, unsigned long gpa)
1046{
1047 unsigned long mask = (1UL << page_shift) - 1;
1048
1049 if (gpa & mask)
1050 return -EINVAL;
1051
1052 return 0;
1053}
1054EXPORT_SYMBOL_GPL(iommu_tce_check_gpa);
1055
1056extern long iommu_tce_xchg_no_kill(struct mm_struct *mm,
1057 struct iommu_table *tbl,
1058 unsigned long entry, unsigned long *hpa,
1059 enum dma_data_direction *direction)
1060{
1061 long ret;
1062 unsigned long size = 0;
1063
1064 ret = tbl->it_ops->xchg_no_kill(tbl, entry, hpa, direction, false);
1065 if (!ret && ((*direction == DMA_FROM_DEVICE) ||
1066 (*direction == DMA_BIDIRECTIONAL)) &&
1067 !mm_iommu_is_devmem(mm, *hpa, tbl->it_page_shift,
1068 &size))
1069 SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));
1070
1071 return ret;
1072}
1073EXPORT_SYMBOL_GPL(iommu_tce_xchg_no_kill);
1074
1075void iommu_tce_kill(struct iommu_table *tbl,
1076 unsigned long entry, unsigned long pages)
1077{
1078 if (tbl->it_ops->tce_kill)
1079 tbl->it_ops->tce_kill(tbl, entry, pages, false);
1080}
1081EXPORT_SYMBOL_GPL(iommu_tce_kill);
1082
1083int iommu_take_ownership(struct iommu_table *tbl)
1084{
1085 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1086 int ret = 0;
1087
1088 /*
1089 * VFIO does not control TCE entries allocation and the guest
1090 * can write new TCEs on top of existing ones so iommu_tce_build()
1091 * must be able to release old pages. This functionality
1092 * requires exchange() callback defined so if it is not
1093 * implemented, we disallow taking ownership over the table.
1094 */
1095 if (!tbl->it_ops->xchg_no_kill)
1096 return -EINVAL;
1097
1098 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1099 for (i = 0; i < tbl->nr_pools; i++)
1100 spin_lock_nest_lock(&tbl->pools[i].lock, &tbl->large_pool.lock);
1101
1102 iommu_table_release_pages(tbl);
1103
1104 if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
1105 pr_err("iommu_tce: it_map is not empty");
1106 ret = -EBUSY;
1107 /* Undo iommu_table_release_pages, i.e. restore bit#0, etc */
1108 iommu_table_reserve_pages(tbl, tbl->it_reserved_start,
1109 tbl->it_reserved_end);
1110 } else {
1111 memset(tbl->it_map, 0xff, sz);
1112 }
1113
1114 for (i = 0; i < tbl->nr_pools; i++)
1115 spin_unlock(&tbl->pools[i].lock);
1116 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1117
1118 return ret;
1119}
1120EXPORT_SYMBOL_GPL(iommu_take_ownership);
1121
1122void iommu_release_ownership(struct iommu_table *tbl)
1123{
1124 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1125
1126 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1127 for (i = 0; i < tbl->nr_pools; i++)
1128 spin_lock_nest_lock(&tbl->pools[i].lock, &tbl->large_pool.lock);
1129
1130 memset(tbl->it_map, 0, sz);
1131
1132 iommu_table_reserve_pages(tbl, tbl->it_reserved_start,
1133 tbl->it_reserved_end);
1134
1135 for (i = 0; i < tbl->nr_pools; i++)
1136 spin_unlock(&tbl->pools[i].lock);
1137 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1138}
1139EXPORT_SYMBOL_GPL(iommu_release_ownership);
1140
1141int iommu_add_device(struct iommu_table_group *table_group, struct device *dev)
1142{
1143 /*
1144 * The sysfs entries should be populated before
1145 * binding IOMMU group. If sysfs entries isn't
1146 * ready, we simply bail.
1147 */
1148 if (!device_is_registered(dev))
1149 return -ENOENT;
1150
1151 if (device_iommu_mapped(dev)) {
1152 pr_debug("%s: Skipping device %s with iommu group %d\n",
1153 __func__, dev_name(dev),
1154 iommu_group_id(dev->iommu_group));
1155 return -EBUSY;
1156 }
1157
1158 pr_debug("%s: Adding %s to iommu group %d\n",
1159 __func__, dev_name(dev), iommu_group_id(table_group->group));
1160
1161 return iommu_group_add_device(table_group->group, dev);
1162}
1163EXPORT_SYMBOL_GPL(iommu_add_device);
1164
1165void iommu_del_device(struct device *dev)
1166{
1167 /*
1168 * Some devices might not have IOMMU table and group
1169 * and we needn't detach them from the associated
1170 * IOMMU groups
1171 */
1172 if (!device_iommu_mapped(dev)) {
1173 pr_debug("iommu_tce: skipping device %s with no tbl\n",
1174 dev_name(dev));
1175 return;
1176 }
1177
1178 iommu_group_remove_device(dev);
1179}
1180EXPORT_SYMBOL_GPL(iommu_del_device);
1181#endif /* CONFIG_IOMMU_API */
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 *
4 * Rewrite, cleanup, new allocation schemes, virtual merging:
5 * Copyright (C) 2004 Olof Johansson, IBM Corporation
6 * and Ben. Herrenschmidt, IBM Corporation
7 *
8 * Dynamic DMA mapping support, bus-independent parts.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/slab.h>
29#include <linux/mm.h>
30#include <linux/spinlock.h>
31#include <linux/string.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitmap.h>
34#include <linux/iommu-helper.h>
35#include <linux/crash_dump.h>
36#include <linux/hash.h>
37#include <linux/fault-inject.h>
38#include <linux/pci.h>
39#include <linux/iommu.h>
40#include <linux/sched.h>
41#include <asm/io.h>
42#include <asm/prom.h>
43#include <asm/iommu.h>
44#include <asm/pci-bridge.h>
45#include <asm/machdep.h>
46#include <asm/kdump.h>
47#include <asm/fadump.h>
48#include <asm/vio.h>
49#include <asm/tce.h>
50
51#define DBG(...)
52
53static int novmerge;
54
55static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
56
57static int __init setup_iommu(char *str)
58{
59 if (!strcmp(str, "novmerge"))
60 novmerge = 1;
61 else if (!strcmp(str, "vmerge"))
62 novmerge = 0;
63 return 1;
64}
65
66__setup("iommu=", setup_iommu);
67
68static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
69
70/*
71 * We precalculate the hash to avoid doing it on every allocation.
72 *
73 * The hash is important to spread CPUs across all the pools. For example,
74 * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
75 * with 4 pools all primary threads would map to the same pool.
76 */
77static int __init setup_iommu_pool_hash(void)
78{
79 unsigned int i;
80
81 for_each_possible_cpu(i)
82 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
83
84 return 0;
85}
86subsys_initcall(setup_iommu_pool_hash);
87
88#ifdef CONFIG_FAIL_IOMMU
89
90static DECLARE_FAULT_ATTR(fail_iommu);
91
92static int __init setup_fail_iommu(char *str)
93{
94 return setup_fault_attr(&fail_iommu, str);
95}
96__setup("fail_iommu=", setup_fail_iommu);
97
98static bool should_fail_iommu(struct device *dev)
99{
100 return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
101}
102
103static int __init fail_iommu_debugfs(void)
104{
105 struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
106 NULL, &fail_iommu);
107
108 return PTR_ERR_OR_ZERO(dir);
109}
110late_initcall(fail_iommu_debugfs);
111
112static ssize_t fail_iommu_show(struct device *dev,
113 struct device_attribute *attr, char *buf)
114{
115 return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
116}
117
118static ssize_t fail_iommu_store(struct device *dev,
119 struct device_attribute *attr, const char *buf,
120 size_t count)
121{
122 int i;
123
124 if (count > 0 && sscanf(buf, "%d", &i) > 0)
125 dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
126
127 return count;
128}
129
130static DEVICE_ATTR(fail_iommu, S_IRUGO|S_IWUSR, fail_iommu_show,
131 fail_iommu_store);
132
133static int fail_iommu_bus_notify(struct notifier_block *nb,
134 unsigned long action, void *data)
135{
136 struct device *dev = data;
137
138 if (action == BUS_NOTIFY_ADD_DEVICE) {
139 if (device_create_file(dev, &dev_attr_fail_iommu))
140 pr_warn("Unable to create IOMMU fault injection sysfs "
141 "entries\n");
142 } else if (action == BUS_NOTIFY_DEL_DEVICE) {
143 device_remove_file(dev, &dev_attr_fail_iommu);
144 }
145
146 return 0;
147}
148
149static struct notifier_block fail_iommu_bus_notifier = {
150 .notifier_call = fail_iommu_bus_notify
151};
152
153static int __init fail_iommu_setup(void)
154{
155#ifdef CONFIG_PCI
156 bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
157#endif
158#ifdef CONFIG_IBMVIO
159 bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
160#endif
161
162 return 0;
163}
164/*
165 * Must execute after PCI and VIO subsystem have initialised but before
166 * devices are probed.
167 */
168arch_initcall(fail_iommu_setup);
169#else
170static inline bool should_fail_iommu(struct device *dev)
171{
172 return false;
173}
174#endif
175
176static unsigned long iommu_range_alloc(struct device *dev,
177 struct iommu_table *tbl,
178 unsigned long npages,
179 unsigned long *handle,
180 unsigned long mask,
181 unsigned int align_order)
182{
183 unsigned long n, end, start;
184 unsigned long limit;
185 int largealloc = npages > 15;
186 int pass = 0;
187 unsigned long align_mask;
188 unsigned long boundary_size;
189 unsigned long flags;
190 unsigned int pool_nr;
191 struct iommu_pool *pool;
192
193 align_mask = 0xffffffffffffffffl >> (64 - align_order);
194
195 /* This allocator was derived from x86_64's bit string search */
196
197 /* Sanity check */
198 if (unlikely(npages == 0)) {
199 if (printk_ratelimit())
200 WARN_ON(1);
201 return DMA_ERROR_CODE;
202 }
203
204 if (should_fail_iommu(dev))
205 return DMA_ERROR_CODE;
206
207 /*
208 * We don't need to disable preemption here because any CPU can
209 * safely use any IOMMU pool.
210 */
211 pool_nr = __this_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1);
212
213 if (largealloc)
214 pool = &(tbl->large_pool);
215 else
216 pool = &(tbl->pools[pool_nr]);
217
218 spin_lock_irqsave(&(pool->lock), flags);
219
220again:
221 if ((pass == 0) && handle && *handle &&
222 (*handle >= pool->start) && (*handle < pool->end))
223 start = *handle;
224 else
225 start = pool->hint;
226
227 limit = pool->end;
228
229 /* The case below can happen if we have a small segment appended
230 * to a large, or when the previous alloc was at the very end of
231 * the available space. If so, go back to the initial start.
232 */
233 if (start >= limit)
234 start = pool->start;
235
236 if (limit + tbl->it_offset > mask) {
237 limit = mask - tbl->it_offset + 1;
238 /* If we're constrained on address range, first try
239 * at the masked hint to avoid O(n) search complexity,
240 * but on second pass, start at 0 in pool 0.
241 */
242 if ((start & mask) >= limit || pass > 0) {
243 spin_unlock(&(pool->lock));
244 pool = &(tbl->pools[0]);
245 spin_lock(&(pool->lock));
246 start = pool->start;
247 } else {
248 start &= mask;
249 }
250 }
251
252 if (dev)
253 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
254 1 << tbl->it_page_shift);
255 else
256 boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift);
257 /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
258
259 n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
260 boundary_size >> tbl->it_page_shift, align_mask);
261 if (n == -1) {
262 if (likely(pass == 0)) {
263 /* First try the pool from the start */
264 pool->hint = pool->start;
265 pass++;
266 goto again;
267
268 } else if (pass <= tbl->nr_pools) {
269 /* Now try scanning all the other pools */
270 spin_unlock(&(pool->lock));
271 pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
272 pool = &tbl->pools[pool_nr];
273 spin_lock(&(pool->lock));
274 pool->hint = pool->start;
275 pass++;
276 goto again;
277
278 } else {
279 /* Give up */
280 spin_unlock_irqrestore(&(pool->lock), flags);
281 return DMA_ERROR_CODE;
282 }
283 }
284
285 end = n + npages;
286
287 /* Bump the hint to a new block for small allocs. */
288 if (largealloc) {
289 /* Don't bump to new block to avoid fragmentation */
290 pool->hint = end;
291 } else {
292 /* Overflow will be taken care of at the next allocation */
293 pool->hint = (end + tbl->it_blocksize - 1) &
294 ~(tbl->it_blocksize - 1);
295 }
296
297 /* Update handle for SG allocations */
298 if (handle)
299 *handle = end;
300
301 spin_unlock_irqrestore(&(pool->lock), flags);
302
303 return n;
304}
305
306static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
307 void *page, unsigned int npages,
308 enum dma_data_direction direction,
309 unsigned long mask, unsigned int align_order,
310 unsigned long attrs)
311{
312 unsigned long entry;
313 dma_addr_t ret = DMA_ERROR_CODE;
314 int build_fail;
315
316 entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
317
318 if (unlikely(entry == DMA_ERROR_CODE))
319 return DMA_ERROR_CODE;
320
321 entry += tbl->it_offset; /* Offset into real TCE table */
322 ret = entry << tbl->it_page_shift; /* Set the return dma address */
323
324 /* Put the TCEs in the HW table */
325 build_fail = tbl->it_ops->set(tbl, entry, npages,
326 (unsigned long)page &
327 IOMMU_PAGE_MASK(tbl), direction, attrs);
328
329 /* tbl->it_ops->set() only returns non-zero for transient errors.
330 * Clean up the table bitmap in this case and return
331 * DMA_ERROR_CODE. For all other errors the functionality is
332 * not altered.
333 */
334 if (unlikely(build_fail)) {
335 __iommu_free(tbl, ret, npages);
336 return DMA_ERROR_CODE;
337 }
338
339 /* Flush/invalidate TLB caches if necessary */
340 if (tbl->it_ops->flush)
341 tbl->it_ops->flush(tbl);
342
343 /* Make sure updates are seen by hardware */
344 mb();
345
346 return ret;
347}
348
349static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
350 unsigned int npages)
351{
352 unsigned long entry, free_entry;
353
354 entry = dma_addr >> tbl->it_page_shift;
355 free_entry = entry - tbl->it_offset;
356
357 if (((free_entry + npages) > tbl->it_size) ||
358 (entry < tbl->it_offset)) {
359 if (printk_ratelimit()) {
360 printk(KERN_INFO "iommu_free: invalid entry\n");
361 printk(KERN_INFO "\tentry = 0x%lx\n", entry);
362 printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr);
363 printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl);
364 printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno);
365 printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size);
366 printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset);
367 printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index);
368 WARN_ON(1);
369 }
370
371 return false;
372 }
373
374 return true;
375}
376
377static struct iommu_pool *get_pool(struct iommu_table *tbl,
378 unsigned long entry)
379{
380 struct iommu_pool *p;
381 unsigned long largepool_start = tbl->large_pool.start;
382
383 /* The large pool is the last pool at the top of the table */
384 if (entry >= largepool_start) {
385 p = &tbl->large_pool;
386 } else {
387 unsigned int pool_nr = entry / tbl->poolsize;
388
389 BUG_ON(pool_nr > tbl->nr_pools);
390 p = &tbl->pools[pool_nr];
391 }
392
393 return p;
394}
395
396static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
397 unsigned int npages)
398{
399 unsigned long entry, free_entry;
400 unsigned long flags;
401 struct iommu_pool *pool;
402
403 entry = dma_addr >> tbl->it_page_shift;
404 free_entry = entry - tbl->it_offset;
405
406 pool = get_pool(tbl, free_entry);
407
408 if (!iommu_free_check(tbl, dma_addr, npages))
409 return;
410
411 tbl->it_ops->clear(tbl, entry, npages);
412
413 spin_lock_irqsave(&(pool->lock), flags);
414 bitmap_clear(tbl->it_map, free_entry, npages);
415 spin_unlock_irqrestore(&(pool->lock), flags);
416}
417
418static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
419 unsigned int npages)
420{
421 __iommu_free(tbl, dma_addr, npages);
422
423 /* Make sure TLB cache is flushed if the HW needs it. We do
424 * not do an mb() here on purpose, it is not needed on any of
425 * the current platforms.
426 */
427 if (tbl->it_ops->flush)
428 tbl->it_ops->flush(tbl);
429}
430
431int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
432 struct scatterlist *sglist, int nelems,
433 unsigned long mask, enum dma_data_direction direction,
434 unsigned long attrs)
435{
436 dma_addr_t dma_next = 0, dma_addr;
437 struct scatterlist *s, *outs, *segstart;
438 int outcount, incount, i, build_fail = 0;
439 unsigned int align;
440 unsigned long handle;
441 unsigned int max_seg_size;
442
443 BUG_ON(direction == DMA_NONE);
444
445 if ((nelems == 0) || !tbl)
446 return 0;
447
448 outs = s = segstart = &sglist[0];
449 outcount = 1;
450 incount = nelems;
451 handle = 0;
452
453 /* Init first segment length for backout at failure */
454 outs->dma_length = 0;
455
456 DBG("sg mapping %d elements:\n", nelems);
457
458 max_seg_size = dma_get_max_seg_size(dev);
459 for_each_sg(sglist, s, nelems, i) {
460 unsigned long vaddr, npages, entry, slen;
461
462 slen = s->length;
463 /* Sanity check */
464 if (slen == 0) {
465 dma_next = 0;
466 continue;
467 }
468 /* Allocate iommu entries for that segment */
469 vaddr = (unsigned long) sg_virt(s);
470 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
471 align = 0;
472 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
473 (vaddr & ~PAGE_MASK) == 0)
474 align = PAGE_SHIFT - tbl->it_page_shift;
475 entry = iommu_range_alloc(dev, tbl, npages, &handle,
476 mask >> tbl->it_page_shift, align);
477
478 DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
479
480 /* Handle failure */
481 if (unlikely(entry == DMA_ERROR_CODE)) {
482 if (!(attrs & DMA_ATTR_NO_WARN) &&
483 printk_ratelimit())
484 dev_info(dev, "iommu_alloc failed, tbl %p "
485 "vaddr %lx npages %lu\n", tbl, vaddr,
486 npages);
487 goto failure;
488 }
489
490 /* Convert entry to a dma_addr_t */
491 entry += tbl->it_offset;
492 dma_addr = entry << tbl->it_page_shift;
493 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
494
495 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
496 npages, entry, dma_addr);
497
498 /* Insert into HW table */
499 build_fail = tbl->it_ops->set(tbl, entry, npages,
500 vaddr & IOMMU_PAGE_MASK(tbl),
501 direction, attrs);
502 if(unlikely(build_fail))
503 goto failure;
504
505 /* If we are in an open segment, try merging */
506 if (segstart != s) {
507 DBG(" - trying merge...\n");
508 /* We cannot merge if:
509 * - allocated dma_addr isn't contiguous to previous allocation
510 */
511 if (novmerge || (dma_addr != dma_next) ||
512 (outs->dma_length + s->length > max_seg_size)) {
513 /* Can't merge: create a new segment */
514 segstart = s;
515 outcount++;
516 outs = sg_next(outs);
517 DBG(" can't merge, new segment.\n");
518 } else {
519 outs->dma_length += s->length;
520 DBG(" merged, new len: %ux\n", outs->dma_length);
521 }
522 }
523
524 if (segstart == s) {
525 /* This is a new segment, fill entries */
526 DBG(" - filling new segment.\n");
527 outs->dma_address = dma_addr;
528 outs->dma_length = slen;
529 }
530
531 /* Calculate next page pointer for contiguous check */
532 dma_next = dma_addr + slen;
533
534 DBG(" - dma next is: %lx\n", dma_next);
535 }
536
537 /* Flush/invalidate TLB caches if necessary */
538 if (tbl->it_ops->flush)
539 tbl->it_ops->flush(tbl);
540
541 DBG("mapped %d elements:\n", outcount);
542
543 /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
544 * next entry of the sglist if we didn't fill the list completely
545 */
546 if (outcount < incount) {
547 outs = sg_next(outs);
548 outs->dma_address = DMA_ERROR_CODE;
549 outs->dma_length = 0;
550 }
551
552 /* Make sure updates are seen by hardware */
553 mb();
554
555 return outcount;
556
557 failure:
558 for_each_sg(sglist, s, nelems, i) {
559 if (s->dma_length != 0) {
560 unsigned long vaddr, npages;
561
562 vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
563 npages = iommu_num_pages(s->dma_address, s->dma_length,
564 IOMMU_PAGE_SIZE(tbl));
565 __iommu_free(tbl, vaddr, npages);
566 s->dma_address = DMA_ERROR_CODE;
567 s->dma_length = 0;
568 }
569 if (s == outs)
570 break;
571 }
572 return 0;
573}
574
575
576void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
577 int nelems, enum dma_data_direction direction,
578 unsigned long attrs)
579{
580 struct scatterlist *sg;
581
582 BUG_ON(direction == DMA_NONE);
583
584 if (!tbl)
585 return;
586
587 sg = sglist;
588 while (nelems--) {
589 unsigned int npages;
590 dma_addr_t dma_handle = sg->dma_address;
591
592 if (sg->dma_length == 0)
593 break;
594 npages = iommu_num_pages(dma_handle, sg->dma_length,
595 IOMMU_PAGE_SIZE(tbl));
596 __iommu_free(tbl, dma_handle, npages);
597 sg = sg_next(sg);
598 }
599
600 /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
601 * do not do an mb() here, the affected platforms do not need it
602 * when freeing.
603 */
604 if (tbl->it_ops->flush)
605 tbl->it_ops->flush(tbl);
606}
607
608static void iommu_table_clear(struct iommu_table *tbl)
609{
610 /*
611 * In case of firmware assisted dump system goes through clean
612 * reboot process at the time of system crash. Hence it's safe to
613 * clear the TCE entries if firmware assisted dump is active.
614 */
615 if (!is_kdump_kernel() || is_fadump_active()) {
616 /* Clear the table in case firmware left allocations in it */
617 tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
618 return;
619 }
620
621#ifdef CONFIG_CRASH_DUMP
622 if (tbl->it_ops->get) {
623 unsigned long index, tceval, tcecount = 0;
624
625 /* Reserve the existing mappings left by the first kernel. */
626 for (index = 0; index < tbl->it_size; index++) {
627 tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
628 /*
629 * Freed TCE entry contains 0x7fffffffffffffff on JS20
630 */
631 if (tceval && (tceval != 0x7fffffffffffffffUL)) {
632 __set_bit(index, tbl->it_map);
633 tcecount++;
634 }
635 }
636
637 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
638 printk(KERN_WARNING "TCE table is full; freeing ");
639 printk(KERN_WARNING "%d entries for the kdump boot\n",
640 KDUMP_MIN_TCE_ENTRIES);
641 for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
642 index < tbl->it_size; index++)
643 __clear_bit(index, tbl->it_map);
644 }
645 }
646#endif
647}
648
649/*
650 * Build a iommu_table structure. This contains a bit map which
651 * is used to manage allocation of the tce space.
652 */
653struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
654{
655 unsigned long sz;
656 static int welcomed = 0;
657 struct page *page;
658 unsigned int i;
659 struct iommu_pool *p;
660
661 BUG_ON(!tbl->it_ops);
662
663 /* number of bytes needed for the bitmap */
664 sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
665
666 page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
667 if (!page)
668 panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
669 tbl->it_map = page_address(page);
670 memset(tbl->it_map, 0, sz);
671
672 /*
673 * Reserve page 0 so it will not be used for any mappings.
674 * This avoids buggy drivers that consider page 0 to be invalid
675 * to crash the machine or even lose data.
676 */
677 if (tbl->it_offset == 0)
678 set_bit(0, tbl->it_map);
679
680 /* We only split the IOMMU table if we have 1GB or more of space */
681 if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
682 tbl->nr_pools = IOMMU_NR_POOLS;
683 else
684 tbl->nr_pools = 1;
685
686 /* We reserve the top 1/4 of the table for large allocations */
687 tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
688
689 for (i = 0; i < tbl->nr_pools; i++) {
690 p = &tbl->pools[i];
691 spin_lock_init(&(p->lock));
692 p->start = tbl->poolsize * i;
693 p->hint = p->start;
694 p->end = p->start + tbl->poolsize;
695 }
696
697 p = &tbl->large_pool;
698 spin_lock_init(&(p->lock));
699 p->start = tbl->poolsize * i;
700 p->hint = p->start;
701 p->end = tbl->it_size;
702
703 iommu_table_clear(tbl);
704
705 if (!welcomed) {
706 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
707 novmerge ? "disabled" : "enabled");
708 welcomed = 1;
709 }
710
711 return tbl;
712}
713
714void iommu_free_table(struct iommu_table *tbl, const char *node_name)
715{
716 unsigned long bitmap_sz;
717 unsigned int order;
718
719 if (!tbl)
720 return;
721
722 if (!tbl->it_map) {
723 kfree(tbl);
724 return;
725 }
726
727 /*
728 * In case we have reserved the first bit, we should not emit
729 * the warning below.
730 */
731 if (tbl->it_offset == 0)
732 clear_bit(0, tbl->it_map);
733
734 /* verify that table contains no entries */
735 if (!bitmap_empty(tbl->it_map, tbl->it_size))
736 pr_warn("%s: Unexpected TCEs for %s\n", __func__, node_name);
737
738 /* calculate bitmap size in bytes */
739 bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
740
741 /* free bitmap */
742 order = get_order(bitmap_sz);
743 free_pages((unsigned long) tbl->it_map, order);
744
745 /* free table */
746 kfree(tbl);
747}
748
749/* Creates TCEs for a user provided buffer. The user buffer must be
750 * contiguous real kernel storage (not vmalloc). The address passed here
751 * comprises a page address and offset into that page. The dma_addr_t
752 * returned will point to the same byte within the page as was passed in.
753 */
754dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
755 struct page *page, unsigned long offset, size_t size,
756 unsigned long mask, enum dma_data_direction direction,
757 unsigned long attrs)
758{
759 dma_addr_t dma_handle = DMA_ERROR_CODE;
760 void *vaddr;
761 unsigned long uaddr;
762 unsigned int npages, align;
763
764 BUG_ON(direction == DMA_NONE);
765
766 vaddr = page_address(page) + offset;
767 uaddr = (unsigned long)vaddr;
768 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
769
770 if (tbl) {
771 align = 0;
772 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
773 ((unsigned long)vaddr & ~PAGE_MASK) == 0)
774 align = PAGE_SHIFT - tbl->it_page_shift;
775
776 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
777 mask >> tbl->it_page_shift, align,
778 attrs);
779 if (dma_handle == DMA_ERROR_CODE) {
780 if (!(attrs & DMA_ATTR_NO_WARN) &&
781 printk_ratelimit()) {
782 dev_info(dev, "iommu_alloc failed, tbl %p "
783 "vaddr %p npages %d\n", tbl, vaddr,
784 npages);
785 }
786 } else
787 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
788 }
789
790 return dma_handle;
791}
792
793void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
794 size_t size, enum dma_data_direction direction,
795 unsigned long attrs)
796{
797 unsigned int npages;
798
799 BUG_ON(direction == DMA_NONE);
800
801 if (tbl) {
802 npages = iommu_num_pages(dma_handle, size,
803 IOMMU_PAGE_SIZE(tbl));
804 iommu_free(tbl, dma_handle, npages);
805 }
806}
807
808/* Allocates a contiguous real buffer and creates mappings over it.
809 * Returns the virtual address of the buffer and sets dma_handle
810 * to the dma address (mapping) of the first page.
811 */
812void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
813 size_t size, dma_addr_t *dma_handle,
814 unsigned long mask, gfp_t flag, int node)
815{
816 void *ret = NULL;
817 dma_addr_t mapping;
818 unsigned int order;
819 unsigned int nio_pages, io_order;
820 struct page *page;
821
822 size = PAGE_ALIGN(size);
823 order = get_order(size);
824
825 /*
826 * Client asked for way too much space. This is checked later
827 * anyway. It is easier to debug here for the drivers than in
828 * the tce tables.
829 */
830 if (order >= IOMAP_MAX_ORDER) {
831 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
832 size);
833 return NULL;
834 }
835
836 if (!tbl)
837 return NULL;
838
839 /* Alloc enough pages (and possibly more) */
840 page = alloc_pages_node(node, flag, order);
841 if (!page)
842 return NULL;
843 ret = page_address(page);
844 memset(ret, 0, size);
845
846 /* Set up tces to cover the allocated range */
847 nio_pages = size >> tbl->it_page_shift;
848 io_order = get_iommu_order(size, tbl);
849 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
850 mask >> tbl->it_page_shift, io_order, 0);
851 if (mapping == DMA_ERROR_CODE) {
852 free_pages((unsigned long)ret, order);
853 return NULL;
854 }
855 *dma_handle = mapping;
856 return ret;
857}
858
859void iommu_free_coherent(struct iommu_table *tbl, size_t size,
860 void *vaddr, dma_addr_t dma_handle)
861{
862 if (tbl) {
863 unsigned int nio_pages;
864
865 size = PAGE_ALIGN(size);
866 nio_pages = size >> tbl->it_page_shift;
867 iommu_free(tbl, dma_handle, nio_pages);
868 size = PAGE_ALIGN(size);
869 free_pages((unsigned long)vaddr, get_order(size));
870 }
871}
872
873unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
874{
875 switch (dir) {
876 case DMA_BIDIRECTIONAL:
877 return TCE_PCI_READ | TCE_PCI_WRITE;
878 case DMA_FROM_DEVICE:
879 return TCE_PCI_WRITE;
880 case DMA_TO_DEVICE:
881 return TCE_PCI_READ;
882 default:
883 return 0;
884 }
885}
886EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
887
888#ifdef CONFIG_IOMMU_API
889/*
890 * SPAPR TCE API
891 */
892static void group_release(void *iommu_data)
893{
894 struct iommu_table_group *table_group = iommu_data;
895
896 table_group->group = NULL;
897}
898
899void iommu_register_group(struct iommu_table_group *table_group,
900 int pci_domain_number, unsigned long pe_num)
901{
902 struct iommu_group *grp;
903 char *name;
904
905 grp = iommu_group_alloc();
906 if (IS_ERR(grp)) {
907 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
908 PTR_ERR(grp));
909 return;
910 }
911 table_group->group = grp;
912 iommu_group_set_iommudata(grp, table_group, group_release);
913 name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
914 pci_domain_number, pe_num);
915 if (!name)
916 return;
917 iommu_group_set_name(grp, name);
918 kfree(name);
919}
920
921enum dma_data_direction iommu_tce_direction(unsigned long tce)
922{
923 if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
924 return DMA_BIDIRECTIONAL;
925 else if (tce & TCE_PCI_READ)
926 return DMA_TO_DEVICE;
927 else if (tce & TCE_PCI_WRITE)
928 return DMA_FROM_DEVICE;
929 else
930 return DMA_NONE;
931}
932EXPORT_SYMBOL_GPL(iommu_tce_direction);
933
934void iommu_flush_tce(struct iommu_table *tbl)
935{
936 /* Flush/invalidate TLB caches if necessary */
937 if (tbl->it_ops->flush)
938 tbl->it_ops->flush(tbl);
939
940 /* Make sure updates are seen by hardware */
941 mb();
942}
943EXPORT_SYMBOL_GPL(iommu_flush_tce);
944
945int iommu_tce_clear_param_check(struct iommu_table *tbl,
946 unsigned long ioba, unsigned long tce_value,
947 unsigned long npages)
948{
949 /* tbl->it_ops->clear() does not support any value but 0 */
950 if (tce_value)
951 return -EINVAL;
952
953 if (ioba & ~IOMMU_PAGE_MASK(tbl))
954 return -EINVAL;
955
956 ioba >>= tbl->it_page_shift;
957 if (ioba < tbl->it_offset)
958 return -EINVAL;
959
960 if ((ioba + npages) > (tbl->it_offset + tbl->it_size))
961 return -EINVAL;
962
963 return 0;
964}
965EXPORT_SYMBOL_GPL(iommu_tce_clear_param_check);
966
967int iommu_tce_put_param_check(struct iommu_table *tbl,
968 unsigned long ioba, unsigned long tce)
969{
970 if (tce & ~IOMMU_PAGE_MASK(tbl))
971 return -EINVAL;
972
973 if (ioba & ~IOMMU_PAGE_MASK(tbl))
974 return -EINVAL;
975
976 ioba >>= tbl->it_page_shift;
977 if (ioba < tbl->it_offset)
978 return -EINVAL;
979
980 if ((ioba + 1) > (tbl->it_offset + tbl->it_size))
981 return -EINVAL;
982
983 return 0;
984}
985EXPORT_SYMBOL_GPL(iommu_tce_put_param_check);
986
987long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,
988 unsigned long *hpa, enum dma_data_direction *direction)
989{
990 long ret;
991
992 ret = tbl->it_ops->exchange(tbl, entry, hpa, direction);
993
994 if (!ret && ((*direction == DMA_FROM_DEVICE) ||
995 (*direction == DMA_BIDIRECTIONAL)))
996 SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));
997
998 /* if (unlikely(ret))
999 pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
1000 __func__, hwaddr, entry << tbl->it_page_shift,
1001 hwaddr, ret); */
1002
1003 return ret;
1004}
1005EXPORT_SYMBOL_GPL(iommu_tce_xchg);
1006
1007int iommu_take_ownership(struct iommu_table *tbl)
1008{
1009 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1010 int ret = 0;
1011
1012 /*
1013 * VFIO does not control TCE entries allocation and the guest
1014 * can write new TCEs on top of existing ones so iommu_tce_build()
1015 * must be able to release old pages. This functionality
1016 * requires exchange() callback defined so if it is not
1017 * implemented, we disallow taking ownership over the table.
1018 */
1019 if (!tbl->it_ops->exchange)
1020 return -EINVAL;
1021
1022 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1023 for (i = 0; i < tbl->nr_pools; i++)
1024 spin_lock(&tbl->pools[i].lock);
1025
1026 if (tbl->it_offset == 0)
1027 clear_bit(0, tbl->it_map);
1028
1029 if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
1030 pr_err("iommu_tce: it_map is not empty");
1031 ret = -EBUSY;
1032 /* Restore bit#0 set by iommu_init_table() */
1033 if (tbl->it_offset == 0)
1034 set_bit(0, tbl->it_map);
1035 } else {
1036 memset(tbl->it_map, 0xff, sz);
1037 }
1038
1039 for (i = 0; i < tbl->nr_pools; i++)
1040 spin_unlock(&tbl->pools[i].lock);
1041 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1042
1043 return ret;
1044}
1045EXPORT_SYMBOL_GPL(iommu_take_ownership);
1046
1047void iommu_release_ownership(struct iommu_table *tbl)
1048{
1049 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1050
1051 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1052 for (i = 0; i < tbl->nr_pools; i++)
1053 spin_lock(&tbl->pools[i].lock);
1054
1055 memset(tbl->it_map, 0, sz);
1056
1057 /* Restore bit#0 set by iommu_init_table() */
1058 if (tbl->it_offset == 0)
1059 set_bit(0, tbl->it_map);
1060
1061 for (i = 0; i < tbl->nr_pools; i++)
1062 spin_unlock(&tbl->pools[i].lock);
1063 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1064}
1065EXPORT_SYMBOL_GPL(iommu_release_ownership);
1066
1067int iommu_add_device(struct device *dev)
1068{
1069 struct iommu_table *tbl;
1070 struct iommu_table_group_link *tgl;
1071
1072 /*
1073 * The sysfs entries should be populated before
1074 * binding IOMMU group. If sysfs entries isn't
1075 * ready, we simply bail.
1076 */
1077 if (!device_is_registered(dev))
1078 return -ENOENT;
1079
1080 if (dev->iommu_group) {
1081 pr_debug("%s: Skipping device %s with iommu group %d\n",
1082 __func__, dev_name(dev),
1083 iommu_group_id(dev->iommu_group));
1084 return -EBUSY;
1085 }
1086
1087 tbl = get_iommu_table_base(dev);
1088 if (!tbl) {
1089 pr_debug("%s: Skipping device %s with no tbl\n",
1090 __func__, dev_name(dev));
1091 return 0;
1092 }
1093
1094 tgl = list_first_entry_or_null(&tbl->it_group_list,
1095 struct iommu_table_group_link, next);
1096 if (!tgl) {
1097 pr_debug("%s: Skipping device %s with no group\n",
1098 __func__, dev_name(dev));
1099 return 0;
1100 }
1101 pr_debug("%s: Adding %s to iommu group %d\n",
1102 __func__, dev_name(dev),
1103 iommu_group_id(tgl->table_group->group));
1104
1105 if (PAGE_SIZE < IOMMU_PAGE_SIZE(tbl)) {
1106 pr_err("%s: Invalid IOMMU page size %lx (%lx) on %s\n",
1107 __func__, IOMMU_PAGE_SIZE(tbl),
1108 PAGE_SIZE, dev_name(dev));
1109 return -EINVAL;
1110 }
1111
1112 return iommu_group_add_device(tgl->table_group->group, dev);
1113}
1114EXPORT_SYMBOL_GPL(iommu_add_device);
1115
1116void iommu_del_device(struct device *dev)
1117{
1118 /*
1119 * Some devices might not have IOMMU table and group
1120 * and we needn't detach them from the associated
1121 * IOMMU groups
1122 */
1123 if (!dev->iommu_group) {
1124 pr_debug("iommu_tce: skipping device %s with no tbl\n",
1125 dev_name(dev));
1126 return;
1127 }
1128
1129 iommu_group_remove_device(dev);
1130}
1131EXPORT_SYMBOL_GPL(iommu_del_device);
1132
1133static int tce_iommu_bus_notifier(struct notifier_block *nb,
1134 unsigned long action, void *data)
1135{
1136 struct device *dev = data;
1137
1138 switch (action) {
1139 case BUS_NOTIFY_ADD_DEVICE:
1140 return iommu_add_device(dev);
1141 case BUS_NOTIFY_DEL_DEVICE:
1142 if (dev->iommu_group)
1143 iommu_del_device(dev);
1144 return 0;
1145 default:
1146 return 0;
1147 }
1148}
1149
1150static struct notifier_block tce_iommu_bus_nb = {
1151 .notifier_call = tce_iommu_bus_notifier,
1152};
1153
1154int __init tce_iommu_bus_notifier_init(void)
1155{
1156 bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
1157 return 0;
1158}
1159#endif /* CONFIG_IOMMU_API */