Loading...
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright 2018, IBM Corporation.
4 *
5 * This file contains general idle entry/exit functions to save
6 * and restore stack and NVGPRs which allows C code to call idle
7 * states that lose GPRs, and it will return transparently with
8 * SRR1 wakeup reason return value.
9 *
10 * The platform / CPU caller must ensure SPRs and any other non-GPR
11 * state is saved and restored correctly, handle KVM, interrupts, etc.
12 */
13
14#include <asm/ppc_asm.h>
15#include <asm/asm-offsets.h>
16#include <asm/ppc-opcode.h>
17#include <asm/cpuidle.h>
18#include <asm/thread_info.h> /* TLF_NAPPING */
19
20#ifdef CONFIG_PPC_P7_NAP
21/*
22 * Desired PSSCR in r3
23 *
24 * No state will be lost regardless of wakeup mechanism (interrupt or NIA).
25 *
26 * An EC=0 type wakeup will return with a value of 0. SRESET wakeup (which can
27 * happen with xscom SRESET and possibly MCE) may clobber volatiles except LR,
28 * and must blr, to return to caller with r3 set according to caller's expected
29 * return code (for Book3S/64 that is SRR1).
30 */
31_GLOBAL(isa300_idle_stop_noloss)
32 mtspr SPRN_PSSCR,r3
33 PPC_STOP
34 li r3,0
35 blr
36
37/*
38 * Desired PSSCR in r3
39 *
40 * GPRs may be lost, so they are saved here. Wakeup is by interrupt only.
41 * The SRESET wakeup returns to this function's caller by calling
42 * idle_return_gpr_loss with r3 set to desired return value.
43 *
44 * A wakeup without GPR loss may alteratively be handled as in
45 * isa300_idle_stop_noloss and blr directly, as an optimisation.
46 *
47 * The caller is responsible for saving/restoring SPRs, MSR, timebase,
48 * etc.
49 */
50_GLOBAL(isa300_idle_stop_mayloss)
51 mtspr SPRN_PSSCR,r3
52 std r1,PACAR1(r13)
53 mflr r4
54 mfcr r5
55 /*
56 * Use the stack red zone rather than a new frame for saving regs since
57 * in the case of no GPR loss the wakeup code branches directly back to
58 * the caller without deallocating the stack frame first.
59 */
60 std r2,-8*1(r1)
61 std r14,-8*2(r1)
62 std r15,-8*3(r1)
63 std r16,-8*4(r1)
64 std r17,-8*5(r1)
65 std r18,-8*6(r1)
66 std r19,-8*7(r1)
67 std r20,-8*8(r1)
68 std r21,-8*9(r1)
69 std r22,-8*10(r1)
70 std r23,-8*11(r1)
71 std r24,-8*12(r1)
72 std r25,-8*13(r1)
73 std r26,-8*14(r1)
74 std r27,-8*15(r1)
75 std r28,-8*16(r1)
76 std r29,-8*17(r1)
77 std r30,-8*18(r1)
78 std r31,-8*19(r1)
79 std r4,-8*20(r1)
80 std r5,-8*21(r1)
81 /* 168 bytes */
82 PPC_STOP
83 b . /* catch bugs */
84
85/*
86 * Desired return value in r3
87 *
88 * The idle wakeup SRESET interrupt can call this after calling
89 * to return to the idle sleep function caller with r3 as the return code.
90 *
91 * This must not be used if idle was entered via a _noloss function (use
92 * a simple blr instead).
93 */
94_GLOBAL(idle_return_gpr_loss)
95 ld r1,PACAR1(r13)
96 ld r4,-8*20(r1)
97 ld r5,-8*21(r1)
98 mtlr r4
99 mtcr r5
100 /*
101 * KVM nap requires r2 to be saved, rather than just restoring it
102 * from PACATOC. This could be avoided for that less common case
103 * if KVM saved its r2.
104 */
105 ld r2,-8*1(r1)
106 ld r14,-8*2(r1)
107 ld r15,-8*3(r1)
108 ld r16,-8*4(r1)
109 ld r17,-8*5(r1)
110 ld r18,-8*6(r1)
111 ld r19,-8*7(r1)
112 ld r20,-8*8(r1)
113 ld r21,-8*9(r1)
114 ld r22,-8*10(r1)
115 ld r23,-8*11(r1)
116 ld r24,-8*12(r1)
117 ld r25,-8*13(r1)
118 ld r26,-8*14(r1)
119 ld r27,-8*15(r1)
120 ld r28,-8*16(r1)
121 ld r29,-8*17(r1)
122 ld r30,-8*18(r1)
123 ld r31,-8*19(r1)
124 blr
125
126/*
127 * This is the sequence required to execute idle instructions, as
128 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0.
129 * We have to store a GPR somewhere, ptesync, then reload it, and create
130 * a false dependency on the result of the load. It doesn't matter which
131 * GPR we store, or where we store it. We have already stored r2 to the
132 * stack at -8(r1) in isa206_idle_insn_mayloss, so use that.
133 */
134#define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
135 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
136 std r2,-8(r1); \
137 ptesync; \
138 ld r2,-8(r1); \
139236: cmpd cr0,r2,r2; \
140 bne 236b; \
141 IDLE_INST; \
142 b . /* catch bugs */
143
144/*
145 * Desired instruction type in r3
146 *
147 * GPRs may be lost, so they are saved here. Wakeup is by interrupt only.
148 * The SRESET wakeup returns to this function's caller by calling
149 * idle_return_gpr_loss with r3 set to desired return value.
150 *
151 * A wakeup without GPR loss may alteratively be handled as in
152 * isa300_idle_stop_noloss and blr directly, as an optimisation.
153 *
154 * The caller is responsible for saving/restoring SPRs, MSR, timebase,
155 * etc.
156 *
157 * This must be called in real-mode (MSR_IDLE).
158 */
159_GLOBAL(isa206_idle_insn_mayloss)
160 std r1,PACAR1(r13)
161 mflr r4
162 mfcr r5
163 /*
164 * Use the stack red zone rather than a new frame for saving regs since
165 * in the case of no GPR loss the wakeup code branches directly back to
166 * the caller without deallocating the stack frame first.
167 */
168 std r2,-8*1(r1)
169 std r14,-8*2(r1)
170 std r15,-8*3(r1)
171 std r16,-8*4(r1)
172 std r17,-8*5(r1)
173 std r18,-8*6(r1)
174 std r19,-8*7(r1)
175 std r20,-8*8(r1)
176 std r21,-8*9(r1)
177 std r22,-8*10(r1)
178 std r23,-8*11(r1)
179 std r24,-8*12(r1)
180 std r25,-8*13(r1)
181 std r26,-8*14(r1)
182 std r27,-8*15(r1)
183 std r28,-8*16(r1)
184 std r29,-8*17(r1)
185 std r30,-8*18(r1)
186 std r31,-8*19(r1)
187 std r4,-8*20(r1)
188 std r5,-8*21(r1)
189 cmpwi r3,PNV_THREAD_NAP
190 bne 1f
191 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
1921: cmpwi r3,PNV_THREAD_SLEEP
193 bne 2f
194 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
1952: IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
196#endif
197
198#ifdef CONFIG_PPC_970_NAP
199_GLOBAL(power4_idle_nap)
200 LOAD_REG_IMMEDIATE(r7, MSR_KERNEL|MSR_EE|MSR_POW)
201 ld r9,PACA_THREAD_INFO(r13)
202 ld r8,TI_LOCAL_FLAGS(r9)
203 ori r8,r8,_TLF_NAPPING
204 std r8,TI_LOCAL_FLAGS(r9)
205 /*
206 * NAPPING bit is set, from this point onward power4_fixup_nap
207 * will cause exceptions to return to power4_idle_nap_return.
208 */
2091: sync
210 isync
211 mtmsrd r7
212 isync
213 b 1b
214
215 .globl power4_idle_nap_return
216power4_idle_nap_return:
217 blr
218#endif
1/*
2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <linux/threads.h>
12#include <asm/processor.h>
13#include <asm/page.h>
14#include <asm/cputable.h>
15#include <asm/thread_info.h>
16#include <asm/ppc_asm.h>
17#include <asm/asm-offsets.h>
18#include <asm/ppc-opcode.h>
19#include <asm/hw_irq.h>
20#include <asm/kvm_book3s_asm.h>
21#include <asm/opal.h>
22#include <asm/cpuidle.h>
23#include <asm/book3s/64/mmu-hash.h>
24#include <asm/mmu.h>
25
26#undef DEBUG
27
28/*
29 * Use unused space in the interrupt stack to save and restore
30 * registers for winkle support.
31 */
32#define _SDR1 GPR3
33#define _RPR GPR4
34#define _SPURR GPR5
35#define _PURR GPR6
36#define _TSCR GPR7
37#define _DSCR GPR8
38#define _AMOR GPR9
39#define _WORT GPR10
40#define _WORC GPR11
41#define _PTCR GPR12
42
43#define PSSCR_HV_TEMPLATE PSSCR_ESL | PSSCR_EC | \
44 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
45 PSSCR_MTL_MASK
46
47 .text
48
49/*
50 * Used by threads before entering deep idle states. Saves SPRs
51 * in interrupt stack frame
52 */
53save_sprs_to_stack:
54 /*
55 * Note all register i.e per-core, per-subcore or per-thread is saved
56 * here since any thread in the core might wake up first
57 */
58BEGIN_FTR_SECTION
59 mfspr r3,SPRN_PTCR
60 std r3,_PTCR(r1)
61 /*
62 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
63 * SDR1 here
64 */
65FTR_SECTION_ELSE
66 mfspr r3,SPRN_SDR1
67 std r3,_SDR1(r1)
68ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
69 mfspr r3,SPRN_RPR
70 std r3,_RPR(r1)
71 mfspr r3,SPRN_SPURR
72 std r3,_SPURR(r1)
73 mfspr r3,SPRN_PURR
74 std r3,_PURR(r1)
75 mfspr r3,SPRN_TSCR
76 std r3,_TSCR(r1)
77 mfspr r3,SPRN_DSCR
78 std r3,_DSCR(r1)
79 mfspr r3,SPRN_AMOR
80 std r3,_AMOR(r1)
81 mfspr r3,SPRN_WORT
82 std r3,_WORT(r1)
83 mfspr r3,SPRN_WORC
84 std r3,_WORC(r1)
85
86 blr
87
88/*
89 * Used by threads when the lock bit of core_idle_state is set.
90 * Threads will spin in HMT_LOW until the lock bit is cleared.
91 * r14 - pointer to core_idle_state
92 * r15 - used to load contents of core_idle_state
93 * r9 - used as a temporary variable
94 */
95
96core_idle_lock_held:
97 HMT_LOW
983: lwz r15,0(r14)
99 andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
100 bne 3b
101 HMT_MEDIUM
102 lwarx r15,0,r14
103 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
104 bne core_idle_lock_held
105 blr
106
107/*
108 * Pass requested state in r3:
109 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
110 * - Requested STOP state in POWER9
111 *
112 * To check IRQ_HAPPENED in r4
113 * 0 - don't check
114 * 1 - check
115 *
116 * Address to 'rfid' to in r5
117 */
118_GLOBAL(pnv_powersave_common)
119 /* Use r3 to pass state nap/sleep/winkle */
120 /* NAP is a state loss, we create a regs frame on the
121 * stack, fill it up with the state we care about and
122 * stick a pointer to it in PACAR1. We really only
123 * need to save PC, some CR bits and the NV GPRs,
124 * but for now an interrupt frame will do.
125 */
126 mflr r0
127 std r0,16(r1)
128 stdu r1,-INT_FRAME_SIZE(r1)
129 std r0,_LINK(r1)
130 std r0,_NIP(r1)
131
132 /* Hard disable interrupts */
133 mfmsr r9
134 rldicl r9,r9,48,1
135 rotldi r9,r9,16
136 mtmsrd r9,1 /* hard-disable interrupts */
137
138 /* Check if something happened while soft-disabled */
139 lbz r0,PACAIRQHAPPENED(r13)
140 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
141 beq 1f
142 cmpwi cr0,r4,0
143 beq 1f
144 addi r1,r1,INT_FRAME_SIZE
145 ld r0,16(r1)
146 li r3,0 /* Return 0 (no nap) */
147 mtlr r0
148 blr
149
1501: /* We mark irqs hard disabled as this is the state we'll
151 * be in when returning and we need to tell arch_local_irq_restore()
152 * about it
153 */
154 li r0,PACA_IRQ_HARD_DIS
155 stb r0,PACAIRQHAPPENED(r13)
156
157 /* We haven't lost state ... yet */
158 li r0,0
159 stb r0,PACA_NAPSTATELOST(r13)
160
161 /* Continue saving state */
162 SAVE_GPR(2, r1)
163 SAVE_NVGPRS(r1)
164 mfcr r4
165 std r4,_CCR(r1)
166 std r9,_MSR(r1)
167 std r1,PACAR1(r13)
168
169 /*
170 * Go to real mode to do the nap, as required by the architecture.
171 * Also, we need to be in real mode before setting hwthread_state,
172 * because as soon as we do that, another thread can switch
173 * the MMU context to the guest.
174 */
175 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
176 li r6, MSR_RI
177 andc r6, r9, r6
178 mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
179 mtspr SPRN_SRR0, r5
180 mtspr SPRN_SRR1, r7
181 rfid
182
183 .globl pnv_enter_arch207_idle_mode
184pnv_enter_arch207_idle_mode:
185#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
186 /* Tell KVM we're entering idle */
187 li r4,KVM_HWTHREAD_IN_IDLE
188 /******************************************************/
189 /* N O T E W E L L ! ! ! N O T E W E L L */
190 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
191 /* MUST occur in real mode, i.e. with the MMU off, */
192 /* and the MMU must stay off until we clear this flag */
193 /* and test HSTATE_HWTHREAD_REQ(r13) in the system */
194 /* reset interrupt vector in exceptions-64s.S. */
195 /* The reason is that another thread can switch the */
196 /* MMU to a guest context whenever this flag is set */
197 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
198 /* that would potentially cause this thread to start */
199 /* executing instructions from guest memory in */
200 /* hypervisor mode, leading to a host crash or data */
201 /* corruption, or worse. */
202 /******************************************************/
203 stb r4,HSTATE_HWTHREAD_STATE(r13)
204#endif
205 stb r3,PACA_THREAD_IDLE_STATE(r13)
206 cmpwi cr3,r3,PNV_THREAD_SLEEP
207 bge cr3,2f
208 IDLE_STATE_ENTER_SEQ(PPC_NAP)
209 /* No return */
2102:
211 /* Sleep or winkle */
212 lbz r7,PACA_THREAD_MASK(r13)
213 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
214lwarx_loop1:
215 lwarx r15,0,r14
216
217 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
218 bnel core_idle_lock_held
219
220 andc r15,r15,r7 /* Clear thread bit */
221
222 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
223
224/*
225 * If cr0 = 0, then current thread is the last thread of the core entering
226 * sleep. Last thread needs to execute the hardware bug workaround code if
227 * required by the platform.
228 * Make the workaround call unconditionally here. The below branch call is
229 * patched out when the idle states are discovered if the platform does not
230 * require it.
231 */
232.global pnv_fastsleep_workaround_at_entry
233pnv_fastsleep_workaround_at_entry:
234 beq fastsleep_workaround_at_entry
235
236 stwcx. r15,0,r14
237 bne- lwarx_loop1
238 isync
239
240common_enter: /* common code for all the threads entering sleep or winkle */
241 bgt cr3,enter_winkle
242 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
243
244fastsleep_workaround_at_entry:
245 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
246 stwcx. r15,0,r14
247 bne- lwarx_loop1
248 isync
249
250 /* Fast sleep workaround */
251 li r3,1
252 li r4,1
253 bl opal_rm_config_cpu_idle_state
254
255 /* Clear Lock bit */
256 li r0,0
257 lwsync
258 stw r0,0(r14)
259 b common_enter
260
261enter_winkle:
262 bl save_sprs_to_stack
263
264 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
265
266/*
267 * r3 - requested stop state
268 */
269power_enter_stop:
270#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
271 /* Tell KVM we're entering idle */
272 li r4,KVM_HWTHREAD_IN_IDLE
273 /* DO THIS IN REAL MODE! See comment above. */
274 stb r4,HSTATE_HWTHREAD_STATE(r13)
275#endif
276/*
277 * Check if the requested state is a deep idle state.
278 */
279 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
280 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
281 cmpd r3,r4
282 bge 2f
283 IDLE_STATE_ENTER_SEQ(PPC_STOP)
2842:
285/*
286 * Entering deep idle state.
287 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
288 * stack and enter stop
289 */
290 lbz r7,PACA_THREAD_MASK(r13)
291 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
292
293lwarx_loop_stop:
294 lwarx r15,0,r14
295 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
296 bnel core_idle_lock_held
297 andc r15,r15,r7 /* Clear thread bit */
298
299 stwcx. r15,0,r14
300 bne- lwarx_loop_stop
301 isync
302
303 bl save_sprs_to_stack
304
305 IDLE_STATE_ENTER_SEQ(PPC_STOP)
306
307_GLOBAL(power7_idle)
308 /* Now check if user or arch enabled NAP mode */
309 LOAD_REG_ADDRBASE(r3,powersave_nap)
310 lwz r4,ADDROFF(powersave_nap)(r3)
311 cmpwi 0,r4,0
312 beqlr
313 li r3, 1
314 /* fall through */
315
316_GLOBAL(power7_nap)
317 mr r4,r3
318 li r3,PNV_THREAD_NAP
319 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
320 b pnv_powersave_common
321 /* No return */
322
323_GLOBAL(power7_sleep)
324 li r3,PNV_THREAD_SLEEP
325 li r4,1
326 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
327 b pnv_powersave_common
328 /* No return */
329
330_GLOBAL(power7_winkle)
331 li r3,PNV_THREAD_WINKLE
332 li r4,1
333 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
334 b pnv_powersave_common
335 /* No return */
336
337#define CHECK_HMI_INTERRUPT \
338 mfspr r0,SPRN_SRR1; \
339BEGIN_FTR_SECTION_NESTED(66); \
340 rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
341FTR_SECTION_ELSE_NESTED(66); \
342 rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
343ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
344 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
345 bne 20f; \
346 /* Invoke opal call to handle hmi */ \
347 ld r2,PACATOC(r13); \
348 ld r1,PACAR1(r13); \
349 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
350 li r3,0; /* NULL argument */ \
351 bl hmi_exception_realmode; \
352 nop; \
353 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
35420: nop;
355
356
357/*
358 * r3 - requested stop state
359 */
360_GLOBAL(power9_idle_stop)
361 LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
362 or r4,r4,r3
363 mtspr SPRN_PSSCR, r4
364 li r4, 1
365 LOAD_REG_ADDR(r5,power_enter_stop)
366 b pnv_powersave_common
367 /* No return */
368/*
369 * Called from reset vector. Check whether we have woken up with
370 * hypervisor state loss. If yes, restore hypervisor state and return
371 * back to reset vector.
372 *
373 * r13 - Contents of HSPRG0
374 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
375 */
376_GLOBAL(pnv_restore_hyp_resource)
377BEGIN_FTR_SECTION
378 ld r2,PACATOC(r13);
379 /*
380 * POWER ISA 3. Use PSSCR to determine if we
381 * are waking up from deep idle state
382 */
383 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
384 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
385
386 mfspr r5,SPRN_PSSCR
387 /*
388 * 0-3 bits correspond to Power-Saving Level Status
389 * which indicates the idle state we are waking up from
390 */
391 rldicl r5,r5,4,60
392 cmpd cr4,r5,r4
393 bge cr4,pnv_wakeup_tb_loss
394 /*
395 * Waking up without hypervisor state loss. Return to
396 * reset vector
397 */
398 blr
399
400END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
401
402 /*
403 * POWER ISA 2.07 or less.
404 * Check if last bit of HSPGR0 is set. This indicates whether we are
405 * waking up from winkle.
406 */
407 clrldi r5,r13,63
408 clrrdi r13,r13,1
409
410 /* Now that we are sure r13 is corrected, load TOC */
411 ld r2,PACATOC(r13);
412 cmpwi cr4,r5,1
413 mtspr SPRN_HSPRG0,r13
414
415 lbz r0,PACA_THREAD_IDLE_STATE(r13)
416 cmpwi cr2,r0,PNV_THREAD_NAP
417 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
418
419 /*
420 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
421 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
422 * indicates we are waking with hypervisor state loss from nap.
423 */
424 bgt cr3,.
425
426 blr /* Return back to System Reset vector from where
427 pnv_restore_hyp_resource was invoked */
428
429/*
430 * Called if waking up from idle state which can cause either partial or
431 * complete hyp state loss.
432 * In POWER8, called if waking up from fastsleep or winkle
433 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
434 *
435 * r13 - PACA
436 * cr3 - gt if waking up with partial/complete hypervisor state loss
437 * cr4 - gt or eq if waking up from complete hypervisor state loss.
438 */
439_GLOBAL(pnv_wakeup_tb_loss)
440 ld r1,PACAR1(r13)
441 /*
442 * Before entering any idle state, the NVGPRs are saved in the stack.
443 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
444 * NVGPRs are restored. If we are here, it is likely that state is lost,
445 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
446 * here are the same as the test to restore NVGPRS:
447 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
448 * and SRR1 test for restoring NVGPRs.
449 *
450 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
451 * guarantee they will always be restored. This might be tightened
452 * with careful reading of specs (particularly for ISA300) but this
453 * is already a slow wakeup path and it's simpler to be safe.
454 */
455 li r0,1
456 stb r0,PACA_NAPSTATELOST(r13)
457
458 /*
459 *
460 * Save SRR1 and LR in NVGPRs as they might be clobbered in
461 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
462 * to determine the wakeup reason if we branch to kvm_start_guest. LR
463 * is required to return back to reset vector after hypervisor state
464 * restore is complete.
465 */
466 mflr r17
467 mfspr r16,SPRN_SRR1
468BEGIN_FTR_SECTION
469 CHECK_HMI_INTERRUPT
470END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
471
472 lbz r7,PACA_THREAD_MASK(r13)
473 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
474lwarx_loop2:
475 lwarx r15,0,r14
476 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
477 /*
478 * Lock bit is set in one of the 2 cases-
479 * a. In the sleep/winkle enter path, the last thread is executing
480 * fastsleep workaround code.
481 * b. In the wake up path, another thread is executing fastsleep
482 * workaround undo code or resyncing timebase or restoring context
483 * In either case loop until the lock bit is cleared.
484 */
485 bnel core_idle_lock_held
486
487 cmpwi cr2,r15,0
488
489 /*
490 * At this stage
491 * cr2 - eq if first thread to wakeup in core
492 * cr3- gt if waking up with partial/complete hypervisor state loss
493 * cr4 - gt or eq if waking up from complete hypervisor state loss.
494 */
495
496 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
497 stwcx. r15,0,r14
498 bne- lwarx_loop2
499 isync
500
501BEGIN_FTR_SECTION
502 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
503 and r4,r4,r15
504 cmpwi r4,0 /* Check if first in subcore */
505
506 or r15,r15,r7 /* Set thread bit */
507 beq first_thread_in_subcore
508END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
509
510 or r15,r15,r7 /* Set thread bit */
511 beq cr2,first_thread_in_core
512
513 /* Not first thread in core or subcore to wake up */
514 b clear_lock
515
516first_thread_in_subcore:
517 /*
518 * If waking up from sleep, subcore state is not lost. Hence
519 * skip subcore state restore
520 */
521 blt cr4,subcore_state_restored
522
523 /* Restore per-subcore state */
524 ld r4,_SDR1(r1)
525 mtspr SPRN_SDR1,r4
526
527 ld r4,_RPR(r1)
528 mtspr SPRN_RPR,r4
529 ld r4,_AMOR(r1)
530 mtspr SPRN_AMOR,r4
531
532subcore_state_restored:
533 /*
534 * Check if the thread is also the first thread in the core. If not,
535 * skip to clear_lock.
536 */
537 bne cr2,clear_lock
538
539first_thread_in_core:
540
541 /*
542 * First thread in the core waking up from any state which can cause
543 * partial or complete hypervisor state loss. It needs to
544 * call the fastsleep workaround code if the platform requires it.
545 * Call it unconditionally here. The below branch instruction will
546 * be patched out if the platform does not have fastsleep or does not
547 * require the workaround. Patching will be performed during the
548 * discovery of idle-states.
549 */
550.global pnv_fastsleep_workaround_at_exit
551pnv_fastsleep_workaround_at_exit:
552 b fastsleep_workaround_at_exit
553
554timebase_resync:
555 /*
556 * Use cr3 which indicates that we are waking up with atleast partial
557 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
558 */
559 ble cr3,clear_lock
560 /* Time base re-sync */
561 bl opal_rm_resync_timebase;
562 /*
563 * If waking up from sleep, per core state is not lost, skip to
564 * clear_lock.
565 */
566 blt cr4,clear_lock
567
568 /*
569 * First thread in the core to wake up and its waking up with
570 * complete hypervisor state loss. Restore per core hypervisor
571 * state.
572 */
573BEGIN_FTR_SECTION
574 ld r4,_PTCR(r1)
575 mtspr SPRN_PTCR,r4
576 ld r4,_RPR(r1)
577 mtspr SPRN_RPR,r4
578END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
579
580 ld r4,_TSCR(r1)
581 mtspr SPRN_TSCR,r4
582 ld r4,_WORC(r1)
583 mtspr SPRN_WORC,r4
584
585clear_lock:
586 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
587 lwsync
588 stw r15,0(r14)
589
590common_exit:
591 /*
592 * Common to all threads.
593 *
594 * If waking up from sleep, hypervisor state is not lost. Hence
595 * skip hypervisor state restore.
596 */
597 blt cr4,hypervisor_state_restored
598
599 /* Waking up from winkle */
600
601BEGIN_MMU_FTR_SECTION
602 b no_segments
603END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
604 /* Restore SLB from PACA */
605 ld r8,PACA_SLBSHADOWPTR(r13)
606
607 .rept SLB_NUM_BOLTED
608 li r3, SLBSHADOW_SAVEAREA
609 LDX_BE r5, r8, r3
610 addi r3, r3, 8
611 LDX_BE r6, r8, r3
612 andis. r7,r5,SLB_ESID_V@h
613 beq 1f
614 slbmte r6,r5
6151: addi r8,r8,16
616 .endr
617no_segments:
618
619 /* Restore per thread state */
620
621 ld r4,_SPURR(r1)
622 mtspr SPRN_SPURR,r4
623 ld r4,_PURR(r1)
624 mtspr SPRN_PURR,r4
625 ld r4,_DSCR(r1)
626 mtspr SPRN_DSCR,r4
627 ld r4,_WORT(r1)
628 mtspr SPRN_WORT,r4
629
630 /* Call cur_cpu_spec->cpu_restore() */
631 LOAD_REG_ADDR(r4, cur_cpu_spec)
632 ld r4,0(r4)
633 ld r12,CPU_SPEC_RESTORE(r4)
634#ifdef PPC64_ELF_ABI_v1
635 ld r12,0(r12)
636#endif
637 mtctr r12
638 bctrl
639
640hypervisor_state_restored:
641
642 mtspr SPRN_SRR1,r16
643 mtlr r17
644 blr /* Return back to System Reset vector from where
645 pnv_restore_hyp_resource was invoked */
646
647fastsleep_workaround_at_exit:
648 li r3,1
649 li r4,0
650 bl opal_rm_config_cpu_idle_state
651 b timebase_resync
652
653/*
654 * R3 here contains the value that will be returned to the caller
655 * of power7_nap.
656 */
657_GLOBAL(pnv_wakeup_loss)
658 ld r1,PACAR1(r13)
659BEGIN_FTR_SECTION
660 CHECK_HMI_INTERRUPT
661END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
662 REST_NVGPRS(r1)
663 REST_GPR(2, r1)
664 ld r6,_CCR(r1)
665 ld r4,_MSR(r1)
666 ld r5,_NIP(r1)
667 addi r1,r1,INT_FRAME_SIZE
668 mtcr r6
669 mtspr SPRN_SRR1,r4
670 mtspr SPRN_SRR0,r5
671 rfid
672
673/*
674 * R3 here contains the value that will be returned to the caller
675 * of power7_nap.
676 */
677_GLOBAL(pnv_wakeup_noloss)
678 lbz r0,PACA_NAPSTATELOST(r13)
679 cmpwi r0,0
680 bne pnv_wakeup_loss
681BEGIN_FTR_SECTION
682 CHECK_HMI_INTERRUPT
683END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
684 ld r1,PACAR1(r13)
685 ld r6,_CCR(r1)
686 ld r4,_MSR(r1)
687 ld r5,_NIP(r1)
688 addi r1,r1,INT_FRAME_SIZE
689 mtcr r6
690 mtspr SPRN_SRR1,r4
691 mtspr SPRN_SRR0,r5
692 rfid