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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell OcteonTx2 RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef RVU_STRUCT_H
12#define RVU_STRUCT_H
13
14/* RVU Block revision IDs */
15#define RVU_BLK_RVUM_REVID 0x01
16
17#define RVU_MULTI_BLK_VER 0x7ULL
18
19/* RVU Block Address Enumeration */
20enum rvu_block_addr_e {
21 BLKADDR_RVUM = 0x0ULL,
22 BLKADDR_LMT = 0x1ULL,
23 BLKADDR_MSIX = 0x2ULL,
24 BLKADDR_NPA = 0x3ULL,
25 BLKADDR_NIX0 = 0x4ULL,
26 BLKADDR_NIX1 = 0x5ULL,
27 BLKADDR_NPC = 0x6ULL,
28 BLKADDR_SSO = 0x7ULL,
29 BLKADDR_SSOW = 0x8ULL,
30 BLKADDR_TIM = 0x9ULL,
31 BLKADDR_CPT0 = 0xaULL,
32 BLKADDR_CPT1 = 0xbULL,
33 BLKADDR_NDC_NIX0_RX = 0xcULL,
34 BLKADDR_NDC_NIX0_TX = 0xdULL,
35 BLKADDR_NDC_NPA0 = 0xeULL,
36 BLKADDR_NDC_NIX1_RX = 0x10ULL,
37 BLKADDR_NDC_NIX1_TX = 0x11ULL,
38 BLKADDR_APR = 0x16ULL,
39 BLK_COUNT = 0x17ULL,
40};
41
42/* RVU Block Type Enumeration */
43enum rvu_block_type_e {
44 BLKTYPE_RVUM = 0x0,
45 BLKTYPE_MSIX = 0x1,
46 BLKTYPE_LMT = 0x2,
47 BLKTYPE_NIX = 0x3,
48 BLKTYPE_NPA = 0x4,
49 BLKTYPE_NPC = 0x5,
50 BLKTYPE_SSO = 0x6,
51 BLKTYPE_SSOW = 0x7,
52 BLKTYPE_TIM = 0x8,
53 BLKTYPE_CPT = 0x9,
54 BLKTYPE_NDC = 0xa,
55 BLKTYPE_MAX = 0xa,
56};
57
58/* RVU Admin function Interrupt Vector Enumeration */
59enum rvu_af_int_vec_e {
60 RVU_AF_INT_VEC_POISON = 0x0,
61 RVU_AF_INT_VEC_PFFLR = 0x1,
62 RVU_AF_INT_VEC_PFME = 0x2,
63 RVU_AF_INT_VEC_GEN = 0x3,
64 RVU_AF_INT_VEC_MBOX = 0x4,
65 RVU_AF_INT_VEC_CNT = 0x5,
66};
67
68/* NPA Admin function Interrupt Vector Enumeration */
69enum npa_af_int_vec_e {
70 NPA_AF_INT_VEC_RVU = 0x0,
71 NPA_AF_INT_VEC_GEN = 0x1,
72 NPA_AF_INT_VEC_AQ_DONE = 0x2,
73 NPA_AF_INT_VEC_AF_ERR = 0x3,
74 NPA_AF_INT_VEC_POISON = 0x4,
75 NPA_AF_INT_VEC_CNT = 0x5,
76};
77
78/* NIX Admin function Interrupt Vector Enumeration */
79enum nix_af_int_vec_e {
80 NIX_AF_INT_VEC_RVU = 0x0,
81 NIX_AF_INT_VEC_GEN = 0x1,
82 NIX_AF_INT_VEC_AQ_DONE = 0x2,
83 NIX_AF_INT_VEC_AF_ERR = 0x3,
84 NIX_AF_INT_VEC_POISON = 0x4,
85 NIX_AF_INT_VEC_CNT = 0x5,
86};
87
88/**
89 * RVU PF Interrupt Vector Enumeration
90 */
91enum rvu_pf_int_vec_e {
92 RVU_PF_INT_VEC_VFFLR0 = 0x0,
93 RVU_PF_INT_VEC_VFFLR1 = 0x1,
94 RVU_PF_INT_VEC_VFME0 = 0x2,
95 RVU_PF_INT_VEC_VFME1 = 0x3,
96 RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4,
97 RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5,
98 RVU_PF_INT_VEC_AFPF_MBOX = 0x6,
99 RVU_PF_INT_VEC_CNT = 0x7,
100};
101
102/* NPA admin queue completion enumeration */
103enum npa_aq_comp {
104 NPA_AQ_COMP_NOTDONE = 0x0,
105 NPA_AQ_COMP_GOOD = 0x1,
106 NPA_AQ_COMP_SWERR = 0x2,
107 NPA_AQ_COMP_CTX_POISON = 0x3,
108 NPA_AQ_COMP_CTX_FAULT = 0x4,
109 NPA_AQ_COMP_LOCKERR = 0x5,
110};
111
112/* NPA admin queue context types */
113enum npa_aq_ctype {
114 NPA_AQ_CTYPE_AURA = 0x0,
115 NPA_AQ_CTYPE_POOL = 0x1,
116};
117
118/* NPA admin queue instruction opcodes */
119enum npa_aq_instop {
120 NPA_AQ_INSTOP_NOP = 0x0,
121 NPA_AQ_INSTOP_INIT = 0x1,
122 NPA_AQ_INSTOP_WRITE = 0x2,
123 NPA_AQ_INSTOP_READ = 0x3,
124 NPA_AQ_INSTOP_LOCK = 0x4,
125 NPA_AQ_INSTOP_UNLOCK = 0x5,
126};
127
128/* ALLOC/FREE input queues Enumeration from coprocessors */
129enum npa_inpq {
130 NPA_INPQ_NIX0_RX = 0x0,
131 NPA_INPQ_NIX0_TX = 0x1,
132 NPA_INPQ_NIX1_RX = 0x2,
133 NPA_INPQ_NIX1_TX = 0x3,
134 NPA_INPQ_SSO = 0x4,
135 NPA_INPQ_TIM = 0x5,
136 NPA_INPQ_DPI = 0x6,
137 NPA_INPQ_AURA_OP = 0xe,
138 NPA_INPQ_INTERNAL_RSV = 0xf,
139};
140
141/* NPA admin queue instruction structure */
142struct npa_aq_inst_s {
143 u64 op : 4; /* W0 */
144 u64 ctype : 4;
145 u64 lf : 9;
146 u64 reserved_17_23 : 7;
147 u64 cindex : 20;
148 u64 reserved_44_62 : 19;
149 u64 doneint : 1;
150 u64 res_addr; /* W1 */
151};
152
153/* NPA admin queue result structure */
154struct npa_aq_res_s {
155 u64 op : 4; /* W0 */
156 u64 ctype : 4;
157 u64 compcode : 8;
158 u64 doneint : 1;
159 u64 reserved_17_63 : 47;
160 u64 reserved_64_127; /* W1 */
161};
162
163struct npa_aura_s {
164 u64 pool_addr; /* W0 */
165 u64 ena : 1; /* W1 */
166 u64 reserved_65 : 2;
167 u64 pool_caching : 1;
168 u64 pool_way_mask : 16;
169 u64 avg_con : 9;
170 u64 reserved_93 : 1;
171 u64 pool_drop_ena : 1;
172 u64 aura_drop_ena : 1;
173 u64 bp_ena : 2;
174 u64 reserved_98_103 : 6;
175 u64 aura_drop : 8;
176 u64 shift : 6;
177 u64 reserved_118_119 : 2;
178 u64 avg_level : 8;
179 u64 count : 36; /* W2 */
180 u64 reserved_164_167 : 4;
181 u64 nix0_bpid : 9;
182 u64 reserved_177_179 : 3;
183 u64 nix1_bpid : 9;
184 u64 reserved_189_191 : 3;
185 u64 limit : 36; /* W3 */
186 u64 reserved_228_231 : 4;
187 u64 bp : 8;
188 u64 reserved_241_243 : 3;
189 u64 fc_be : 1;
190 u64 fc_ena : 1;
191 u64 fc_up_crossing : 1;
192 u64 fc_stype : 2;
193 u64 fc_hyst_bits : 4;
194 u64 reserved_252_255 : 4;
195 u64 fc_addr; /* W4 */
196 u64 pool_drop : 8; /* W5 */
197 u64 update_time : 16;
198 u64 err_int : 8;
199 u64 err_int_ena : 8;
200 u64 thresh_int : 1;
201 u64 thresh_int_ena : 1;
202 u64 thresh_up : 1;
203 u64 reserved_363 : 1;
204 u64 thresh_qint_idx : 7;
205 u64 reserved_371 : 1;
206 u64 err_qint_idx : 7;
207 u64 reserved_379_383 : 5;
208 u64 thresh : 36; /* W6*/
209 u64 rsvd_423_420 : 4;
210 u64 fc_msh_dst : 11;
211 u64 reserved_435_447 : 13;
212 u64 reserved_448_511; /* W7 */
213};
214
215struct npa_pool_s {
216 u64 stack_base; /* W0 */
217 u64 ena : 1;
218 u64 nat_align : 1;
219 u64 reserved_66_67 : 2;
220 u64 stack_caching : 1;
221 u64 reserved_70_71 : 3;
222 u64 stack_way_mask : 16;
223 u64 buf_offset : 12;
224 u64 reserved_100_103 : 4;
225 u64 buf_size : 11;
226 u64 reserved_115_127 : 13;
227 u64 stack_max_pages : 32;
228 u64 stack_pages : 32;
229 u64 op_pc : 48;
230 u64 reserved_240_255 : 16;
231 u64 stack_offset : 4;
232 u64 reserved_260_263 : 4;
233 u64 shift : 6;
234 u64 reserved_270_271 : 2;
235 u64 avg_level : 8;
236 u64 avg_con : 9;
237 u64 fc_ena : 1;
238 u64 fc_stype : 2;
239 u64 fc_hyst_bits : 4;
240 u64 fc_up_crossing : 1;
241 u64 fc_be : 1;
242 u64 reserved_298_299 : 2;
243 u64 update_time : 16;
244 u64 reserved_316_319 : 4;
245 u64 fc_addr; /* W5 */
246 u64 ptr_start; /* W6 */
247 u64 ptr_end; /* W7 */
248 u64 reserved_512_535 : 24;
249 u64 err_int : 8;
250 u64 err_int_ena : 8;
251 u64 thresh_int : 1;
252 u64 thresh_int_ena : 1;
253 u64 thresh_up : 1;
254 u64 reserved_555 : 1;
255 u64 thresh_qint_idx : 7;
256 u64 reserved_563 : 1;
257 u64 err_qint_idx : 7;
258 u64 reserved_571_575 : 5;
259 u64 thresh : 36;
260 u64 rsvd_615_612 : 4;
261 u64 fc_msh_dst : 11;
262 u64 reserved_627_639 : 13;
263 u64 reserved_640_703; /* W10 */
264 u64 reserved_704_767; /* W11 */
265 u64 reserved_768_831; /* W12 */
266 u64 reserved_832_895; /* W13 */
267 u64 reserved_896_959; /* W14 */
268 u64 reserved_960_1023; /* W15 */
269};
270
271/* NIX admin queue completion status */
272enum nix_aq_comp {
273 NIX_AQ_COMP_NOTDONE = 0x0,
274 NIX_AQ_COMP_GOOD = 0x1,
275 NIX_AQ_COMP_SWERR = 0x2,
276 NIX_AQ_COMP_CTX_POISON = 0x3,
277 NIX_AQ_COMP_CTX_FAULT = 0x4,
278 NIX_AQ_COMP_LOCKERR = 0x5,
279 NIX_AQ_COMP_SQB_ALLOC_FAIL = 0x6,
280};
281
282/* NIX admin queue context types */
283enum nix_aq_ctype {
284 NIX_AQ_CTYPE_RQ = 0x0,
285 NIX_AQ_CTYPE_SQ = 0x1,
286 NIX_AQ_CTYPE_CQ = 0x2,
287 NIX_AQ_CTYPE_MCE = 0x3,
288 NIX_AQ_CTYPE_RSS = 0x4,
289 NIX_AQ_CTYPE_DYNO = 0x5,
290 NIX_AQ_CTYPE_BANDPROF = 0x6,
291};
292
293/* NIX admin queue instruction opcodes */
294enum nix_aq_instop {
295 NIX_AQ_INSTOP_NOP = 0x0,
296 NIX_AQ_INSTOP_INIT = 0x1,
297 NIX_AQ_INSTOP_WRITE = 0x2,
298 NIX_AQ_INSTOP_READ = 0x3,
299 NIX_AQ_INSTOP_LOCK = 0x4,
300 NIX_AQ_INSTOP_UNLOCK = 0x5,
301};
302
303/* NIX admin queue instruction structure */
304struct nix_aq_inst_s {
305 u64 op : 4;
306 u64 ctype : 4;
307 u64 lf : 9;
308 u64 reserved_17_23 : 7;
309 u64 cindex : 20;
310 u64 reserved_44_62 : 19;
311 u64 doneint : 1;
312 u64 res_addr; /* W1 */
313};
314
315/* NIX admin queue result structure */
316struct nix_aq_res_s {
317 u64 op : 4;
318 u64 ctype : 4;
319 u64 compcode : 8;
320 u64 doneint : 1;
321 u64 reserved_17_63 : 47;
322 u64 reserved_64_127; /* W1 */
323};
324
325/* NIX Completion queue context structure */
326struct nix_cq_ctx_s {
327 u64 base;
328 u64 rsvd_64_67 : 4;
329 u64 bp_ena : 1;
330 u64 rsvd_69_71 : 3;
331 u64 bpid : 9;
332 u64 rsvd_81_83 : 3;
333 u64 qint_idx : 7;
334 u64 cq_err : 1;
335 u64 cint_idx : 7;
336 u64 avg_con : 9;
337 u64 wrptr : 20;
338 u64 tail : 20;
339 u64 head : 20;
340 u64 avg_level : 8;
341 u64 update_time : 16;
342 u64 bp : 8;
343 u64 drop : 8;
344 u64 drop_ena : 1;
345 u64 ena : 1;
346 u64 rsvd_210_211 : 2;
347 u64 substream : 20;
348 u64 caching : 1;
349 u64 rsvd_233_235 : 3;
350 u64 qsize : 4;
351 u64 cq_err_int : 8;
352 u64 cq_err_int_ena : 8;
353};
354
355/* CN10K NIX Receive queue context structure */
356struct nix_cn10k_rq_ctx_s {
357 u64 ena : 1;
358 u64 sso_ena : 1;
359 u64 ipsech_ena : 1;
360 u64 ena_wqwd : 1;
361 u64 cq : 20;
362 u64 rsvd_36_24 : 13;
363 u64 lenerr_dis : 1;
364 u64 csum_il4_dis : 1;
365 u64 csum_ol4_dis : 1;
366 u64 len_il4_dis : 1;
367 u64 len_il3_dis : 1;
368 u64 len_ol4_dis : 1;
369 u64 len_ol3_dis : 1;
370 u64 wqe_aura : 20;
371 u64 spb_aura : 20;
372 u64 lpb_aura : 20;
373 u64 sso_grp : 10;
374 u64 sso_tt : 2;
375 u64 pb_caching : 2;
376 u64 wqe_caching : 1;
377 u64 xqe_drop_ena : 1;
378 u64 spb_drop_ena : 1;
379 u64 lpb_drop_ena : 1;
380 u64 pb_stashing : 1;
381 u64 ipsecd_drop_ena : 1;
382 u64 chi_ena : 1;
383 u64 rsvd_127_125 : 3;
384 u64 band_prof_id : 10; /* W2 */
385 u64 rsvd_138 : 1;
386 u64 policer_ena : 1;
387 u64 spb_sizem1 : 6;
388 u64 wqe_skip : 2;
389 u64 rsvd_150_148 : 3;
390 u64 spb_ena : 1;
391 u64 lpb_sizem1 : 12;
392 u64 first_skip : 7;
393 u64 rsvd_171 : 1;
394 u64 later_skip : 6;
395 u64 xqe_imm_size : 6;
396 u64 rsvd_189_184 : 6;
397 u64 xqe_imm_copy : 1;
398 u64 xqe_hdr_split : 1;
399 u64 xqe_drop : 8; /* W3 */
400 u64 xqe_pass : 8;
401 u64 wqe_pool_drop : 8;
402 u64 wqe_pool_pass : 8;
403 u64 spb_aura_drop : 8;
404 u64 spb_aura_pass : 8;
405 u64 spb_pool_drop : 8;
406 u64 spb_pool_pass : 8;
407 u64 lpb_aura_drop : 8; /* W4 */
408 u64 lpb_aura_pass : 8;
409 u64 lpb_pool_drop : 8;
410 u64 lpb_pool_pass : 8;
411 u64 rsvd_291_288 : 4;
412 u64 rq_int : 8;
413 u64 rq_int_ena : 8;
414 u64 qint_idx : 7;
415 u64 rsvd_319_315 : 5;
416 u64 ltag : 24; /* W5 */
417 u64 good_utag : 8;
418 u64 bad_utag : 8;
419 u64 flow_tagw : 6;
420 u64 ipsec_vwqe : 1;
421 u64 vwqe_ena : 1;
422 u64 vwqe_wait : 8;
423 u64 max_vsize_exp : 4;
424 u64 vwqe_skip : 2;
425 u64 rsvd_383_382 : 2;
426 u64 octs : 48; /* W6 */
427 u64 rsvd_447_432 : 16;
428 u64 pkts : 48; /* W7 */
429 u64 rsvd_511_496 : 16;
430 u64 drop_octs : 48; /* W8 */
431 u64 rsvd_575_560 : 16;
432 u64 drop_pkts : 48; /* W9 */
433 u64 rsvd_639_624 : 16;
434 u64 re_pkts : 48; /* W10 */
435 u64 rsvd_703_688 : 16;
436 u64 rsvd_767_704; /* W11 */
437 u64 rsvd_831_768; /* W12 */
438 u64 rsvd_895_832; /* W13 */
439 u64 rsvd_959_896; /* W14 */
440 u64 rsvd_1023_960; /* W15 */
441};
442
443/* CN10K NIX Send queue context structure */
444struct nix_cn10k_sq_ctx_s {
445 u64 ena : 1;
446 u64 qint_idx : 6;
447 u64 substream : 20;
448 u64 sdp_mcast : 1;
449 u64 cq : 20;
450 u64 sqe_way_mask : 16;
451 u64 smq : 10; /* W1 */
452 u64 cq_ena : 1;
453 u64 xoff : 1;
454 u64 sso_ena : 1;
455 u64 smq_rr_weight : 14;
456 u64 default_chan : 12;
457 u64 sqb_count : 16;
458 u64 rsvd_120_119 : 2;
459 u64 smq_rr_count_lb : 7;
460 u64 smq_rr_count_ub : 25; /* W2 */
461 u64 sqb_aura : 20;
462 u64 sq_int : 8;
463 u64 sq_int_ena : 8;
464 u64 sqe_stype : 2;
465 u64 rsvd_191 : 1;
466 u64 max_sqe_size : 2; /* W3 */
467 u64 cq_limit : 8;
468 u64 lmt_dis : 1;
469 u64 mnq_dis : 1;
470 u64 smq_next_sq : 20;
471 u64 smq_lso_segnum : 8;
472 u64 tail_offset : 6;
473 u64 smenq_offset : 6;
474 u64 head_offset : 6;
475 u64 smenq_next_sqb_vld : 1;
476 u64 smq_pend : 1;
477 u64 smq_next_sq_vld : 1;
478 u64 rsvd_255_253 : 3;
479 u64 next_sqb : 64; /* W4 */
480 u64 tail_sqb : 64; /* W5 */
481 u64 smenq_sqb : 64; /* W6 */
482 u64 smenq_next_sqb : 64; /* W7 */
483 u64 head_sqb : 64; /* W8 */
484 u64 rsvd_583_576 : 8; /* W9 */
485 u64 vfi_lso_total : 18;
486 u64 vfi_lso_sizem1 : 3;
487 u64 vfi_lso_sb : 8;
488 u64 vfi_lso_mps : 14;
489 u64 vfi_lso_vlan0_ins_ena : 1;
490 u64 vfi_lso_vlan1_ins_ena : 1;
491 u64 vfi_lso_vld : 1;
492 u64 rsvd_639_630 : 10;
493 u64 scm_lso_rem : 18; /* W10 */
494 u64 rsvd_703_658 : 46;
495 u64 octs : 48; /* W11 */
496 u64 rsvd_767_752 : 16;
497 u64 pkts : 48; /* W12 */
498 u64 rsvd_831_816 : 16;
499 u64 rsvd_895_832 : 64; /* W13 */
500 u64 dropped_octs : 48;
501 u64 rsvd_959_944 : 16;
502 u64 dropped_pkts : 48;
503 u64 rsvd_1023_1008 : 16;
504};
505
506/* NIX Receive queue context structure */
507struct nix_rq_ctx_s {
508 u64 ena : 1;
509 u64 sso_ena : 1;
510 u64 ipsech_ena : 1;
511 u64 ena_wqwd : 1;
512 u64 cq : 20;
513 u64 substream : 20;
514 u64 wqe_aura : 20;
515 u64 spb_aura : 20;
516 u64 lpb_aura : 20;
517 u64 sso_grp : 10;
518 u64 sso_tt : 2;
519 u64 pb_caching : 2;
520 u64 wqe_caching : 1;
521 u64 xqe_drop_ena : 1;
522 u64 spb_drop_ena : 1;
523 u64 lpb_drop_ena : 1;
524 u64 rsvd_127_122 : 6;
525 u64 rsvd_139_128 : 12; /* W2 */
526 u64 spb_sizem1 : 6;
527 u64 wqe_skip : 2;
528 u64 rsvd_150_148 : 3;
529 u64 spb_ena : 1;
530 u64 lpb_sizem1 : 12;
531 u64 first_skip : 7;
532 u64 rsvd_171 : 1;
533 u64 later_skip : 6;
534 u64 xqe_imm_size : 6;
535 u64 rsvd_189_184 : 6;
536 u64 xqe_imm_copy : 1;
537 u64 xqe_hdr_split : 1;
538 u64 xqe_drop : 8; /* W3*/
539 u64 xqe_pass : 8;
540 u64 wqe_pool_drop : 8;
541 u64 wqe_pool_pass : 8;
542 u64 spb_aura_drop : 8;
543 u64 spb_aura_pass : 8;
544 u64 spb_pool_drop : 8;
545 u64 spb_pool_pass : 8;
546 u64 lpb_aura_drop : 8; /* W4 */
547 u64 lpb_aura_pass : 8;
548 u64 lpb_pool_drop : 8;
549 u64 lpb_pool_pass : 8;
550 u64 rsvd_291_288 : 4;
551 u64 rq_int : 8;
552 u64 rq_int_ena : 8;
553 u64 qint_idx : 7;
554 u64 rsvd_319_315 : 5;
555 u64 ltag : 24; /* W5 */
556 u64 good_utag : 8;
557 u64 bad_utag : 8;
558 u64 flow_tagw : 6;
559 u64 rsvd_383_366 : 18;
560 u64 octs : 48; /* W6 */
561 u64 rsvd_447_432 : 16;
562 u64 pkts : 48; /* W7 */
563 u64 rsvd_511_496 : 16;
564 u64 drop_octs : 48; /* W8 */
565 u64 rsvd_575_560 : 16;
566 u64 drop_pkts : 48; /* W9 */
567 u64 rsvd_639_624 : 16;
568 u64 re_pkts : 48; /* W10 */
569 u64 rsvd_703_688 : 16;
570 u64 rsvd_767_704; /* W11 */
571 u64 rsvd_831_768; /* W12 */
572 u64 rsvd_895_832; /* W13 */
573 u64 rsvd_959_896; /* W14 */
574 u64 rsvd_1023_960; /* W15 */
575};
576
577/* NIX sqe sizes */
578enum nix_maxsqesz {
579 NIX_MAXSQESZ_W16 = 0x0,
580 NIX_MAXSQESZ_W8 = 0x1,
581};
582
583/* NIX SQB caching type */
584enum nix_stype {
585 NIX_STYPE_STF = 0x0,
586 NIX_STYPE_STT = 0x1,
587 NIX_STYPE_STP = 0x2,
588};
589
590/* NIX Send queue context structure */
591struct nix_sq_ctx_s {
592 u64 ena : 1;
593 u64 qint_idx : 6;
594 u64 substream : 20;
595 u64 sdp_mcast : 1;
596 u64 cq : 20;
597 u64 sqe_way_mask : 16;
598 u64 smq : 9;
599 u64 cq_ena : 1;
600 u64 xoff : 1;
601 u64 sso_ena : 1;
602 u64 smq_rr_quantum : 24;
603 u64 default_chan : 12;
604 u64 sqb_count : 16;
605 u64 smq_rr_count : 25;
606 u64 sqb_aura : 20;
607 u64 sq_int : 8;
608 u64 sq_int_ena : 8;
609 u64 sqe_stype : 2;
610 u64 rsvd_191 : 1;
611 u64 max_sqe_size : 2;
612 u64 cq_limit : 8;
613 u64 lmt_dis : 1;
614 u64 mnq_dis : 1;
615 u64 smq_next_sq : 20;
616 u64 smq_lso_segnum : 8;
617 u64 tail_offset : 6;
618 u64 smenq_offset : 6;
619 u64 head_offset : 6;
620 u64 smenq_next_sqb_vld : 1;
621 u64 smq_pend : 1;
622 u64 smq_next_sq_vld : 1;
623 u64 rsvd_255_253 : 3;
624 u64 next_sqb : 64;/* W4 */
625 u64 tail_sqb : 64;/* W5 */
626 u64 smenq_sqb : 64;/* W6 */
627 u64 smenq_next_sqb : 64;/* W7 */
628 u64 head_sqb : 64;/* W8 */
629 u64 rsvd_583_576 : 8;
630 u64 vfi_lso_total : 18;
631 u64 vfi_lso_sizem1 : 3;
632 u64 vfi_lso_sb : 8;
633 u64 vfi_lso_mps : 14;
634 u64 vfi_lso_vlan0_ins_ena : 1;
635 u64 vfi_lso_vlan1_ins_ena : 1;
636 u64 vfi_lso_vld : 1;
637 u64 rsvd_639_630 : 10;
638 u64 scm_lso_rem : 18;
639 u64 rsvd_703_658 : 46;
640 u64 octs : 48;
641 u64 rsvd_767_752 : 16;
642 u64 pkts : 48;
643 u64 rsvd_831_816 : 16;
644 u64 rsvd_895_832 : 64;/* W13 */
645 u64 dropped_octs : 48;
646 u64 rsvd_959_944 : 16;
647 u64 dropped_pkts : 48;
648 u64 rsvd_1023_1008 : 16;
649};
650
651/* NIX Receive side scaling entry structure*/
652struct nix_rsse_s {
653 uint32_t rq : 20;
654 uint32_t reserved_20_31 : 12;
655
656};
657
658/* NIX receive multicast/mirror entry structure */
659struct nix_rx_mce_s {
660 uint64_t op : 2;
661 uint64_t rsvd_2 : 1;
662 uint64_t eol : 1;
663 uint64_t index : 20;
664 uint64_t rsvd_31_24 : 8;
665 uint64_t pf_func : 16;
666 uint64_t next : 16;
667};
668
669enum nix_band_prof_layers {
670 BAND_PROF_LEAF_LAYER = 0,
671 BAND_PROF_INVAL_LAYER = 1,
672 BAND_PROF_MID_LAYER = 2,
673 BAND_PROF_TOP_LAYER = 3,
674 BAND_PROF_NUM_LAYERS = 4,
675};
676
677enum NIX_RX_BAND_PROF_ACTIONRESULT_E {
678 NIX_RX_BAND_PROF_ACTIONRESULT_PASS = 0x0,
679 NIX_RX_BAND_PROF_ACTIONRESULT_DROP = 0x1,
680 NIX_RX_BAND_PROF_ACTIONRESULT_RED = 0x2,
681};
682
683enum nix_band_prof_pc_mode {
684 NIX_RX_PC_MODE_VLAN = 0,
685 NIX_RX_PC_MODE_DSCP = 1,
686 NIX_RX_PC_MODE_GEN = 2,
687 NIX_RX_PC_MODE_RSVD = 3,
688};
689
690/* NIX ingress policer bandwidth profile structure */
691struct nix_bandprof_s {
692 uint64_t pc_mode : 2; /* W0 */
693 uint64_t icolor : 2;
694 uint64_t tnl_ena : 1;
695 uint64_t reserved_5_7 : 3;
696 uint64_t peir_exponent : 5;
697 uint64_t reserved_13_15 : 3;
698 uint64_t pebs_exponent : 5;
699 uint64_t reserved_21_23 : 3;
700 uint64_t cir_exponent : 5;
701 uint64_t reserved_29_31 : 3;
702 uint64_t cbs_exponent : 5;
703 uint64_t reserved_37_39 : 3;
704 uint64_t peir_mantissa : 8;
705 uint64_t pebs_mantissa : 8;
706 uint64_t cir_mantissa : 8;
707 uint64_t cbs_mantissa : 8; /* W1 */
708 uint64_t lmode : 1;
709 uint64_t l_sellect : 3;
710 uint64_t rdiv : 4;
711 uint64_t adjust_exponent : 5;
712 uint64_t reserved_85_86 : 2;
713 uint64_t adjust_mantissa : 9;
714 uint64_t gc_action : 2;
715 uint64_t yc_action : 2;
716 uint64_t rc_action : 2;
717 uint64_t meter_algo : 2;
718 uint64_t band_prof_id : 7;
719 uint64_t reserved_111_118 : 8;
720 uint64_t hl_en : 1;
721 uint64_t reserved_120_127 : 8;
722 uint64_t ts : 48; /* W2 */
723 uint64_t reserved_176_191 : 16;
724 uint64_t pe_accum : 32; /* W3 */
725 uint64_t c_accum : 32;
726 uint64_t green_pkt_pass : 48; /* W4 */
727 uint64_t reserved_304_319 : 16;
728 uint64_t yellow_pkt_pass : 48; /* W5 */
729 uint64_t reserved_368_383 : 16;
730 uint64_t red_pkt_pass : 48; /* W6 */
731 uint64_t reserved_432_447 : 16;
732 uint64_t green_octs_pass : 48; /* W7 */
733 uint64_t reserved_496_511 : 16;
734 uint64_t yellow_octs_pass : 48; /* W8 */
735 uint64_t reserved_560_575 : 16;
736 uint64_t red_octs_pass : 48; /* W9 */
737 uint64_t reserved_624_639 : 16;
738 uint64_t green_pkt_drop : 48; /* W10 */
739 uint64_t reserved_688_703 : 16;
740 uint64_t yellow_pkt_drop : 48; /* W11 */
741 uint64_t reserved_752_767 : 16;
742 uint64_t red_pkt_drop : 48; /* W12 */
743 uint64_t reserved_816_831 : 16;
744 uint64_t green_octs_drop : 48; /* W13 */
745 uint64_t reserved_880_895 : 16;
746 uint64_t yellow_octs_drop : 48; /* W14 */
747 uint64_t reserved_944_959 : 16;
748 uint64_t red_octs_drop : 48; /* W15 */
749 uint64_t reserved_1008_1023 : 16;
750};
751
752enum nix_lsoalg {
753 NIX_LSOALG_NOP,
754 NIX_LSOALG_ADD_SEGNUM,
755 NIX_LSOALG_ADD_PAYLEN,
756 NIX_LSOALG_ADD_OFFSET,
757 NIX_LSOALG_TCP_FLAGS,
758};
759
760enum nix_txlayer {
761 NIX_TXLAYER_OL3,
762 NIX_TXLAYER_OL4,
763 NIX_TXLAYER_IL3,
764 NIX_TXLAYER_IL4,
765};
766
767struct nix_lso_format {
768 u64 offset : 8;
769 u64 layer : 2;
770 u64 rsvd_10_11 : 2;
771 u64 sizem1 : 2;
772 u64 rsvd_14_15 : 2;
773 u64 alg : 3;
774 u64 rsvd_19_63 : 45;
775};
776
777struct nix_rx_flowkey_alg {
778 u64 key_offset :6;
779 u64 ln_mask :1;
780 u64 fn_mask :1;
781 u64 hdr_offset :8;
782 u64 bytesm1 :5;
783 u64 lid :3;
784 u64 reserved_24_24 :1;
785 u64 ena :1;
786 u64 sel_chan :1;
787 u64 ltype_mask :4;
788 u64 ltype_match :4;
789 u64 reserved_35_63 :29;
790};
791
792/* NIX VTAG size */
793enum nix_vtag_size {
794 VTAGSIZE_T4 = 0x0,
795 VTAGSIZE_T8 = 0x1,
796};
797
798enum nix_tx_vtag_op {
799 NOP = 0x0,
800 VTAG_INSERT = 0x1,
801 VTAG_REPLACE = 0x2,
802};
803
804/* NIX RX VTAG actions */
805#define VTAG_STRIP BIT_ULL(4)
806#define VTAG_CAPTURE BIT_ULL(5)
807
808#endif /* RVU_STRUCT_H */