Loading...
Note: File does not exist in v4.10.11.
1/*
2 * Copyright © 2014-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "display/intel_dp.h"
25
26#include "intel_de.h"
27#include "intel_display_types.h"
28#include "intel_dpio_phy.h"
29#include "intel_sideband.h"
30
31/**
32 * DOC: DPIO
33 *
34 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
35 * ports. DPIO is the name given to such a display PHY. These PHYs
36 * don't follow the standard programming model using direct MMIO
37 * registers, and instead their registers must be accessed trough IOSF
38 * sideband. VLV has one such PHY for driving ports B and C, and CHV
39 * adds another PHY for driving port D. Each PHY responds to specific
40 * IOSF-SB port.
41 *
42 * Each display PHY is made up of one or two channels. Each channel
43 * houses a common lane part which contains the PLL and other common
44 * logic. CH0 common lane also contains the IOSF-SB logic for the
45 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
46 * must be running when any DPIO registers are accessed.
47 *
48 * In addition to having their own registers, the PHYs are also
49 * controlled through some dedicated signals from the display
50 * controller. These include PLL reference clock enable, PLL enable,
51 * and CRI clock selection, for example.
52 *
53 * Eeach channel also has two splines (also called data lanes), and
54 * each spline is made up of one Physical Access Coding Sub-Layer
55 * (PCS) block and two TX lanes. So each channel has two PCS blocks
56 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
57 * data/clock pairs depending on the output type.
58 *
59 * Additionally the PHY also contains an AUX lane with AUX blocks
60 * for each channel. This is used for DP AUX communication, but
61 * this fact isn't really relevant for the driver since AUX is
62 * controlled from the display controller side. No DPIO registers
63 * need to be accessed during AUX communication,
64 *
65 * Generally on VLV/CHV the common lane corresponds to the pipe and
66 * the spline (PCS/TX) corresponds to the port.
67 *
68 * For dual channel PHY (VLV/CHV):
69 *
70 * pipe A == CMN/PLL/REF CH0
71 *
72 * pipe B == CMN/PLL/REF CH1
73 *
74 * port B == PCS/TX CH0
75 *
76 * port C == PCS/TX CH1
77 *
78 * This is especially important when we cross the streams
79 * ie. drive port B with pipe B, or port C with pipe A.
80 *
81 * For single channel PHY (CHV):
82 *
83 * pipe C == CMN/PLL/REF CH0
84 *
85 * port D == PCS/TX CH0
86 *
87 * On BXT the entire PHY channel corresponds to the port. That means
88 * the PLL is also now associated with the port rather than the pipe,
89 * and so the clock needs to be routed to the appropriate transcoder.
90 * Port A PLL is directly connected to transcoder EDP and port B/C
91 * PLLs can be routed to any transcoder A/B/C.
92 *
93 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
94 * digital port D (CHV) or port A (BXT). ::
95 *
96 *
97 * Dual channel PHY (VLV/CHV/BXT)
98 * ---------------------------------
99 * | CH0 | CH1 |
100 * | CMN/PLL/REF | CMN/PLL/REF |
101 * |---------------|---------------| Display PHY
102 * | PCS01 | PCS23 | PCS01 | PCS23 |
103 * |-------|-------|-------|-------|
104 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
105 * ---------------------------------
106 * | DDI0 | DDI1 | DP/HDMI ports
107 * ---------------------------------
108 *
109 * Single channel PHY (CHV/BXT)
110 * -----------------
111 * | CH0 |
112 * | CMN/PLL/REF |
113 * |---------------| Display PHY
114 * | PCS01 | PCS23 |
115 * |-------|-------|
116 * |TX0|TX1|TX2|TX3|
117 * -----------------
118 * | DDI2 | DP/HDMI port
119 * -----------------
120 */
121
122/**
123 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
124 */
125struct bxt_ddi_phy_info {
126 /**
127 * @dual_channel: true if this phy has a second channel.
128 */
129 bool dual_channel;
130
131 /**
132 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
133 * Otherwise the GRC value will be copied from the phy indicated by
134 * this field.
135 */
136 enum dpio_phy rcomp_phy;
137
138 /**
139 * @reset_delay: delay in us to wait before setting the common reset
140 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
141 */
142 int reset_delay;
143
144 /**
145 * @pwron_mask: Mask with the appropriate bit set that would cause the
146 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
147 */
148 u32 pwron_mask;
149
150 /**
151 * @channel: struct containing per channel information.
152 */
153 struct {
154 /**
155 * @channel.port: which port maps to this channel.
156 */
157 enum port port;
158 } channel[2];
159};
160
161static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
162 [DPIO_PHY0] = {
163 .dual_channel = true,
164 .rcomp_phy = DPIO_PHY1,
165 .pwron_mask = BIT(0),
166
167 .channel = {
168 [DPIO_CH0] = { .port = PORT_B },
169 [DPIO_CH1] = { .port = PORT_C },
170 }
171 },
172 [DPIO_PHY1] = {
173 .dual_channel = false,
174 .rcomp_phy = -1,
175 .pwron_mask = BIT(1),
176
177 .channel = {
178 [DPIO_CH0] = { .port = PORT_A },
179 }
180 },
181};
182
183static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
184 [DPIO_PHY0] = {
185 .dual_channel = false,
186 .rcomp_phy = DPIO_PHY1,
187 .pwron_mask = BIT(0),
188 .reset_delay = 20,
189
190 .channel = {
191 [DPIO_CH0] = { .port = PORT_B },
192 }
193 },
194 [DPIO_PHY1] = {
195 .dual_channel = false,
196 .rcomp_phy = -1,
197 .pwron_mask = BIT(3),
198 .reset_delay = 20,
199
200 .channel = {
201 [DPIO_CH0] = { .port = PORT_A },
202 }
203 },
204 [DPIO_PHY2] = {
205 .dual_channel = false,
206 .rcomp_phy = DPIO_PHY1,
207 .pwron_mask = BIT(1),
208 .reset_delay = 20,
209
210 .channel = {
211 [DPIO_CH0] = { .port = PORT_C },
212 }
213 },
214};
215
216static const struct bxt_ddi_phy_info *
217bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
218{
219 if (IS_GEMINILAKE(dev_priv)) {
220 *count = ARRAY_SIZE(glk_ddi_phy_info);
221 return glk_ddi_phy_info;
222 } else {
223 *count = ARRAY_SIZE(bxt_ddi_phy_info);
224 return bxt_ddi_phy_info;
225 }
226}
227
228static const struct bxt_ddi_phy_info *
229bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
230{
231 int count;
232 const struct bxt_ddi_phy_info *phy_list =
233 bxt_get_phy_list(dev_priv, &count);
234
235 return &phy_list[phy];
236}
237
238void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
239 enum dpio_phy *phy, enum dpio_channel *ch)
240{
241 const struct bxt_ddi_phy_info *phy_info, *phys;
242 int i, count;
243
244 phys = bxt_get_phy_list(dev_priv, &count);
245
246 for (i = 0; i < count; i++) {
247 phy_info = &phys[i];
248
249 if (port == phy_info->channel[DPIO_CH0].port) {
250 *phy = i;
251 *ch = DPIO_CH0;
252 return;
253 }
254
255 if (phy_info->dual_channel &&
256 port == phy_info->channel[DPIO_CH1].port) {
257 *phy = i;
258 *ch = DPIO_CH1;
259 return;
260 }
261 }
262
263 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
264 port_name(port));
265 *phy = DPIO_PHY0;
266 *ch = DPIO_CH0;
267}
268
269void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
270 enum port port, u32 margin, u32 scale,
271 u32 enable, u32 deemphasis)
272{
273 u32 val;
274 enum dpio_phy phy;
275 enum dpio_channel ch;
276
277 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
278
279 /*
280 * While we write to the group register to program all lanes at once we
281 * can read only lane registers and we pick lanes 0/1 for that.
282 */
283 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
284 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
285 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
286
287 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
288 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
289 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
290 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
291
292 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
293 val &= ~SCALE_DCOMP_METHOD;
294 if (enable)
295 val |= SCALE_DCOMP_METHOD;
296
297 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
298 drm_err(&dev_priv->drm,
299 "Disabled scaling while ouniqetrangenmethod was set");
300
301 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
302
303 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
304 val &= ~DE_EMPHASIS;
305 val |= deemphasis << DEEMPH_SHIFT;
306 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);
307
308 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
309 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
310 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
311}
312
313bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
314 enum dpio_phy phy)
315{
316 const struct bxt_ddi_phy_info *phy_info;
317
318 phy_info = bxt_get_phy_info(dev_priv, phy);
319
320 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
321 return false;
322
323 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
324 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
325 drm_dbg(&dev_priv->drm,
326 "DDI PHY %d powered, but power hasn't settled\n", phy);
327
328 return false;
329 }
330
331 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
332 drm_dbg(&dev_priv->drm,
333 "DDI PHY %d powered, but still in reset\n", phy);
334
335 return false;
336 }
337
338 return true;
339}
340
341static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
342{
343 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
344
345 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
346}
347
348static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
349 enum dpio_phy phy)
350{
351 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
352 GRC_DONE, 10))
353 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
354 phy);
355}
356
357static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
358 enum dpio_phy phy)
359{
360 const struct bxt_ddi_phy_info *phy_info;
361 u32 val;
362
363 phy_info = bxt_get_phy_info(dev_priv, phy);
364
365 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
366 /* Still read out the GRC value for state verification */
367 if (phy_info->rcomp_phy != -1)
368 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
369
370 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
371 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
372 "won't reprogram it\n", phy);
373 return;
374 }
375
376 drm_dbg(&dev_priv->drm,
377 "DDI PHY %d enabled with invalid state, "
378 "force reprogramming it\n", phy);
379 }
380
381 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
382 val |= phy_info->pwron_mask;
383 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val);
384
385 /*
386 * The PHY registers start out inaccessible and respond to reads with
387 * all 1s. Eventually they become accessible as they power up, then
388 * the reserved bit will give the default 0. Poll on the reserved bit
389 * becoming 0 to find when the PHY is accessible.
390 * The flag should get set in 100us according to the HW team, but
391 * use 1ms due to occasional timeouts observed with that.
392 */
393 if (intel_wait_for_register_fw(&dev_priv->uncore,
394 BXT_PORT_CL1CM_DW0(phy),
395 PHY_RESERVED | PHY_POWER_GOOD,
396 PHY_POWER_GOOD,
397 1))
398 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
399 phy);
400
401 /* Program PLL Rcomp code offset */
402 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy));
403 val &= ~IREF0RC_OFFSET_MASK;
404 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
405 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val);
406
407 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy));
408 val &= ~IREF1RC_OFFSET_MASK;
409 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
410 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val);
411
412 /* Program power gating */
413 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy));
414 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
415 SUS_CLK_CONFIG;
416 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val);
417
418 if (phy_info->dual_channel) {
419 val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy));
420 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
421 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val);
422 }
423
424 if (phy_info->rcomp_phy != -1) {
425 u32 grc_code;
426
427 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
428
429 /*
430 * PHY0 isn't connected to an RCOMP resistor so copy over
431 * the corresponding calibrated value from PHY1, and disable
432 * the automatic calibration on PHY0.
433 */
434 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
435 phy_info->rcomp_phy);
436 grc_code = val << GRC_CODE_FAST_SHIFT |
437 val << GRC_CODE_SLOW_SHIFT |
438 val;
439 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
440
441 val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy));
442 val |= GRC_DIS | GRC_RDY_OVRD;
443 intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy), val);
444 }
445
446 if (phy_info->reset_delay)
447 udelay(phy_info->reset_delay);
448
449 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy));
450 val |= COMMON_RESET_DIS;
451 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val);
452}
453
454void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
455{
456 const struct bxt_ddi_phy_info *phy_info;
457 u32 val;
458
459 phy_info = bxt_get_phy_info(dev_priv, phy);
460
461 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy));
462 val &= ~COMMON_RESET_DIS;
463 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val);
464
465 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
466 val &= ~phy_info->pwron_mask;
467 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val);
468}
469
470void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
471{
472 const struct bxt_ddi_phy_info *phy_info =
473 bxt_get_phy_info(dev_priv, phy);
474 enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
475 bool was_enabled;
476
477 lockdep_assert_held(&dev_priv->power_domains.lock);
478
479 was_enabled = true;
480 if (rcomp_phy != -1)
481 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
482
483 /*
484 * We need to copy the GRC calibration value from rcomp_phy,
485 * so make sure it's powered up.
486 */
487 if (!was_enabled)
488 _bxt_ddi_phy_init(dev_priv, rcomp_phy);
489
490 _bxt_ddi_phy_init(dev_priv, phy);
491
492 if (!was_enabled)
493 bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
494}
495
496static bool __printf(6, 7)
497__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
498 i915_reg_t reg, u32 mask, u32 expected,
499 const char *reg_fmt, ...)
500{
501 struct va_format vaf;
502 va_list args;
503 u32 val;
504
505 val = intel_de_read(dev_priv, reg);
506 if ((val & mask) == expected)
507 return true;
508
509 va_start(args, reg_fmt);
510 vaf.fmt = reg_fmt;
511 vaf.va = &args;
512
513 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
514 "current %08x, expected %08x (mask %08x)\n",
515 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
516 mask);
517
518 va_end(args);
519
520 return false;
521}
522
523bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
524 enum dpio_phy phy)
525{
526 const struct bxt_ddi_phy_info *phy_info;
527 u32 mask;
528 bool ok;
529
530 phy_info = bxt_get_phy_info(dev_priv, phy);
531
532#define _CHK(reg, mask, exp, fmt, ...) \
533 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
534 ## __VA_ARGS__)
535
536 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
537 return false;
538
539 ok = true;
540
541 /* PLL Rcomp code offset */
542 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
543 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
544 "BXT_PORT_CL1CM_DW9(%d)", phy);
545 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
546 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
547 "BXT_PORT_CL1CM_DW10(%d)", phy);
548
549 /* Power gating */
550 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
551 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
552 "BXT_PORT_CL1CM_DW28(%d)", phy);
553
554 if (phy_info->dual_channel)
555 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
556 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
557 "BXT_PORT_CL2CM_DW6(%d)", phy);
558
559 if (phy_info->rcomp_phy != -1) {
560 u32 grc_code = dev_priv->bxt_phy_grc;
561
562 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
563 grc_code << GRC_CODE_SLOW_SHIFT |
564 grc_code;
565 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
566 GRC_CODE_NOM_MASK;
567 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
568 "BXT_PORT_REF_DW6(%d)", phy);
569
570 mask = GRC_DIS | GRC_RDY_OVRD;
571 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
572 "BXT_PORT_REF_DW8(%d)", phy);
573 }
574
575 return ok;
576#undef _CHK
577}
578
579u8
580bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
581{
582 switch (lane_count) {
583 case 1:
584 return 0;
585 case 2:
586 return BIT(2) | BIT(0);
587 case 4:
588 return BIT(3) | BIT(2) | BIT(0);
589 default:
590 MISSING_CASE(lane_count);
591
592 return 0;
593 }
594}
595
596void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
597 u8 lane_lat_optim_mask)
598{
599 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
600 enum port port = encoder->port;
601 enum dpio_phy phy;
602 enum dpio_channel ch;
603 int lane;
604
605 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
606
607 for (lane = 0; lane < 4; lane++) {
608 u32 val = intel_de_read(dev_priv,
609 BXT_PORT_TX_DW14_LN(phy, ch, lane));
610
611 /*
612 * Note that on CHV this flag is called UPAR, but has
613 * the same function.
614 */
615 val &= ~LATENCY_OPTIM;
616 if (lane_lat_optim_mask & BIT(lane))
617 val |= LATENCY_OPTIM;
618
619 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
620 val);
621 }
622}
623
624u8
625bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
626{
627 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
628 enum port port = encoder->port;
629 enum dpio_phy phy;
630 enum dpio_channel ch;
631 int lane;
632 u8 mask;
633
634 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
635
636 mask = 0;
637 for (lane = 0; lane < 4; lane++) {
638 u32 val = intel_de_read(dev_priv,
639 BXT_PORT_TX_DW14_LN(phy, ch, lane));
640
641 if (val & LATENCY_OPTIM)
642 mask |= BIT(lane);
643 }
644
645 return mask;
646}
647
648void chv_set_phy_signal_level(struct intel_encoder *encoder,
649 const struct intel_crtc_state *crtc_state,
650 u32 deemph_reg_value, u32 margin_reg_value,
651 bool uniq_trans_scale)
652{
653 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
654 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
655 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
656 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
657 enum pipe pipe = crtc->pipe;
658 u32 val;
659 int i;
660
661 vlv_dpio_get(dev_priv);
662
663 /* Clear calc init */
664 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
665 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
666 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
667 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
668 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
669
670 if (crtc_state->lane_count > 2) {
671 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
672 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
673 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
674 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
675 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
676 }
677
678 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
679 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
680 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
681 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
682
683 if (crtc_state->lane_count > 2) {
684 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
685 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
686 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
687 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
688 }
689
690 /* Program swing deemph */
691 for (i = 0; i < crtc_state->lane_count; i++) {
692 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
693 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
694 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
695 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
696 }
697
698 /* Program swing margin */
699 for (i = 0; i < crtc_state->lane_count; i++) {
700 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
701
702 val &= ~DPIO_SWING_MARGIN000_MASK;
703 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
704
705 /*
706 * Supposedly this value shouldn't matter when unique transition
707 * scale is disabled, but in fact it does matter. Let's just
708 * always program the same value and hope it's OK.
709 */
710 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
711 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
712
713 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
714 }
715
716 /*
717 * The document said it needs to set bit 27 for ch0 and bit 26
718 * for ch1. Might be a typo in the doc.
719 * For now, for this unique transition scale selection, set bit
720 * 27 for ch0 and ch1.
721 */
722 for (i = 0; i < crtc_state->lane_count; i++) {
723 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
724 if (uniq_trans_scale)
725 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
726 else
727 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
728 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
729 }
730
731 /* Start swing calculation */
732 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
733 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
734 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
735
736 if (crtc_state->lane_count > 2) {
737 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
738 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
739 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
740 }
741
742 vlv_dpio_put(dev_priv);
743}
744
745void chv_data_lane_soft_reset(struct intel_encoder *encoder,
746 const struct intel_crtc_state *crtc_state,
747 bool reset)
748{
749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
750 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
752 enum pipe pipe = crtc->pipe;
753 u32 val;
754
755 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
756 if (reset)
757 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
758 else
759 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
760 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
761
762 if (crtc_state->lane_count > 2) {
763 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
764 if (reset)
765 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
766 else
767 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
768 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
769 }
770
771 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
772 val |= CHV_PCS_REQ_SOFTRESET_EN;
773 if (reset)
774 val &= ~DPIO_PCS_CLK_SOFT_RESET;
775 else
776 val |= DPIO_PCS_CLK_SOFT_RESET;
777 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
778
779 if (crtc_state->lane_count > 2) {
780 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
781 val |= CHV_PCS_REQ_SOFTRESET_EN;
782 if (reset)
783 val &= ~DPIO_PCS_CLK_SOFT_RESET;
784 else
785 val |= DPIO_PCS_CLK_SOFT_RESET;
786 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
787 }
788}
789
790void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
791 const struct intel_crtc_state *crtc_state)
792{
793 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
794 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
795 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
796 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
797 enum pipe pipe = crtc->pipe;
798 unsigned int lane_mask =
799 intel_dp_unused_lane_mask(crtc_state->lane_count);
800 u32 val;
801
802 /*
803 * Must trick the second common lane into life.
804 * Otherwise we can't even access the PLL.
805 */
806 if (ch == DPIO_CH0 && pipe == PIPE_B)
807 dig_port->release_cl2_override =
808 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
809
810 chv_phy_powergate_lanes(encoder, true, lane_mask);
811
812 vlv_dpio_get(dev_priv);
813
814 /* Assert data lane reset */
815 chv_data_lane_soft_reset(encoder, crtc_state, true);
816
817 /* program left/right clock distribution */
818 if (pipe != PIPE_B) {
819 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
820 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
821 if (ch == DPIO_CH0)
822 val |= CHV_BUFLEFTENA1_FORCE;
823 if (ch == DPIO_CH1)
824 val |= CHV_BUFRIGHTENA1_FORCE;
825 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
826 } else {
827 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
828 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
829 if (ch == DPIO_CH0)
830 val |= CHV_BUFLEFTENA2_FORCE;
831 if (ch == DPIO_CH1)
832 val |= CHV_BUFRIGHTENA2_FORCE;
833 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
834 }
835
836 /* program clock channel usage */
837 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
838 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
839 if (pipe != PIPE_B)
840 val &= ~CHV_PCS_USEDCLKCHANNEL;
841 else
842 val |= CHV_PCS_USEDCLKCHANNEL;
843 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
844
845 if (crtc_state->lane_count > 2) {
846 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
847 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
848 if (pipe != PIPE_B)
849 val &= ~CHV_PCS_USEDCLKCHANNEL;
850 else
851 val |= CHV_PCS_USEDCLKCHANNEL;
852 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
853 }
854
855 /*
856 * This a a bit weird since generally CL
857 * matches the pipe, but here we need to
858 * pick the CL based on the port.
859 */
860 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
861 if (pipe != PIPE_B)
862 val &= ~CHV_CMN_USEDCLKCHANNEL;
863 else
864 val |= CHV_CMN_USEDCLKCHANNEL;
865 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
866
867 vlv_dpio_put(dev_priv);
868}
869
870void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
871 const struct intel_crtc_state *crtc_state)
872{
873 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
874 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
875 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
876 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
877 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
878 enum pipe pipe = crtc->pipe;
879 int data, i, stagger;
880 u32 val;
881
882 vlv_dpio_get(dev_priv);
883
884 /* allow hardware to manage TX FIFO reset source */
885 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
886 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
887 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
888
889 if (crtc_state->lane_count > 2) {
890 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
891 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
892 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
893 }
894
895 /* Program Tx lane latency optimal setting*/
896 for (i = 0; i < crtc_state->lane_count; i++) {
897 /* Set the upar bit */
898 if (crtc_state->lane_count == 1)
899 data = 0x0;
900 else
901 data = (i == 1) ? 0x0 : 0x1;
902 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
903 data << DPIO_UPAR_SHIFT);
904 }
905
906 /* Data lane stagger programming */
907 if (crtc_state->port_clock > 270000)
908 stagger = 0x18;
909 else if (crtc_state->port_clock > 135000)
910 stagger = 0xd;
911 else if (crtc_state->port_clock > 67500)
912 stagger = 0x7;
913 else if (crtc_state->port_clock > 33750)
914 stagger = 0x4;
915 else
916 stagger = 0x2;
917
918 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
919 val |= DPIO_TX2_STAGGER_MASK(0x1f);
920 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
921
922 if (crtc_state->lane_count > 2) {
923 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
924 val |= DPIO_TX2_STAGGER_MASK(0x1f);
925 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
926 }
927
928 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
929 DPIO_LANESTAGGER_STRAP(stagger) |
930 DPIO_LANESTAGGER_STRAP_OVRD |
931 DPIO_TX1_STAGGER_MASK(0x1f) |
932 DPIO_TX1_STAGGER_MULT(6) |
933 DPIO_TX2_STAGGER_MULT(0));
934
935 if (crtc_state->lane_count > 2) {
936 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
937 DPIO_LANESTAGGER_STRAP(stagger) |
938 DPIO_LANESTAGGER_STRAP_OVRD |
939 DPIO_TX1_STAGGER_MASK(0x1f) |
940 DPIO_TX1_STAGGER_MULT(7) |
941 DPIO_TX2_STAGGER_MULT(5));
942 }
943
944 /* Deassert data lane reset */
945 chv_data_lane_soft_reset(encoder, crtc_state, false);
946
947 vlv_dpio_put(dev_priv);
948}
949
950void chv_phy_release_cl2_override(struct intel_encoder *encoder)
951{
952 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
953 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
954
955 if (dig_port->release_cl2_override) {
956 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
957 dig_port->release_cl2_override = false;
958 }
959}
960
961void chv_phy_post_pll_disable(struct intel_encoder *encoder,
962 const struct intel_crtc_state *old_crtc_state)
963{
964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
965 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
966 u32 val;
967
968 vlv_dpio_get(dev_priv);
969
970 /* disable left/right clock distribution */
971 if (pipe != PIPE_B) {
972 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
973 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
974 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
975 } else {
976 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
977 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
978 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
979 }
980
981 vlv_dpio_put(dev_priv);
982
983 /*
984 * Leave the power down bit cleared for at least one
985 * lane so that chv_powergate_phy_ch() will power
986 * on something when the channel is otherwise unused.
987 * When the port is off and the override is removed
988 * the lanes power down anyway, so otherwise it doesn't
989 * really matter what the state of power down bits is
990 * after this.
991 */
992 chv_phy_powergate_lanes(encoder, false, 0x0);
993}
994
995void vlv_set_phy_signal_level(struct intel_encoder *encoder,
996 const struct intel_crtc_state *crtc_state,
997 u32 demph_reg_value, u32 preemph_reg_value,
998 u32 uniqtranscale_reg_value, u32 tx3_demph)
999{
1000 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1001 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1002 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1003 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1004 enum pipe pipe = crtc->pipe;
1005
1006 vlv_dpio_get(dev_priv);
1007
1008 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
1009 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
1010 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
1011 uniqtranscale_reg_value);
1012 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
1013
1014 if (tx3_demph)
1015 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
1016
1017 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1018 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
1019 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1020
1021 vlv_dpio_put(dev_priv);
1022}
1023
1024void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
1025 const struct intel_crtc_state *crtc_state)
1026{
1027 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1028 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1029 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1030 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1031 enum pipe pipe = crtc->pipe;
1032
1033 /* Program Tx lane resets to default */
1034 vlv_dpio_get(dev_priv);
1035
1036 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1037 DPIO_PCS_TX_LANE2_RESET |
1038 DPIO_PCS_TX_LANE1_RESET);
1039 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1040 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1041 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1042 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1043 DPIO_PCS_CLK_SOFT_RESET);
1044
1045 /* Fix up inter-pair skew failure */
1046 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1047 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1048 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1049
1050 vlv_dpio_put(dev_priv);
1051}
1052
1053void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
1054 const struct intel_crtc_state *crtc_state)
1055{
1056 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1057 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1058 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1059 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1060 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1061 enum pipe pipe = crtc->pipe;
1062 u32 val;
1063
1064 vlv_dpio_get(dev_priv);
1065
1066 /* Enable clock channels for this port */
1067 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1068 val = 0;
1069 if (pipe)
1070 val |= (1<<21);
1071 else
1072 val &= ~(1<<21);
1073 val |= 0x001000c4;
1074 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1075
1076 /* Program lane clock */
1077 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1078 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1079
1080 vlv_dpio_put(dev_priv);
1081}
1082
1083void vlv_phy_reset_lanes(struct intel_encoder *encoder,
1084 const struct intel_crtc_state *old_crtc_state)
1085{
1086 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1087 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1088 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1089 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1090 enum pipe pipe = crtc->pipe;
1091
1092 vlv_dpio_get(dev_priv);
1093 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1094 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1095 vlv_dpio_put(dev_priv);
1096}