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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_fourcc.h>
25#include <drm/drm_vblank.h>
26
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_i2c.h"
30#include "cikd.h"
31#include "atom.h"
32#include "amdgpu_atombios.h"
33#include "atombios_crtc.h"
34#include "atombios_encoders.h"
35#include "amdgpu_pll.h"
36#include "amdgpu_connectors.h"
37#include "amdgpu_display.h"
38#include "dce_v8_0.h"
39
40#include "dce/dce_8_0_d.h"
41#include "dce/dce_8_0_sh_mask.h"
42
43#include "gca/gfx_7_2_enum.h"
44
45#include "gmc/gmc_7_1_d.h"
46#include "gmc/gmc_7_1_sh_mask.h"
47
48#include "oss/oss_2_0_d.h"
49#include "oss/oss_2_0_sh_mask.h"
50
51static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
52static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
53
54static const u32 crtc_offsets[6] =
55{
56 CRTC0_REGISTER_OFFSET,
57 CRTC1_REGISTER_OFFSET,
58 CRTC2_REGISTER_OFFSET,
59 CRTC3_REGISTER_OFFSET,
60 CRTC4_REGISTER_OFFSET,
61 CRTC5_REGISTER_OFFSET
62};
63
64static const u32 hpd_offsets[] =
65{
66 HPD0_REGISTER_OFFSET,
67 HPD1_REGISTER_OFFSET,
68 HPD2_REGISTER_OFFSET,
69 HPD3_REGISTER_OFFSET,
70 HPD4_REGISTER_OFFSET,
71 HPD5_REGISTER_OFFSET
72};
73
74static const uint32_t dig_offsets[] = {
75 CRTC0_REGISTER_OFFSET,
76 CRTC1_REGISTER_OFFSET,
77 CRTC2_REGISTER_OFFSET,
78 CRTC3_REGISTER_OFFSET,
79 CRTC4_REGISTER_OFFSET,
80 CRTC5_REGISTER_OFFSET,
81 (0x13830 - 0x7030) >> 2,
82};
83
84static const struct {
85 uint32_t reg;
86 uint32_t vblank;
87 uint32_t vline;
88 uint32_t hpd;
89
90} interrupt_status_offsets[6] = { {
91 .reg = mmDISP_INTERRUPT_STATUS,
92 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105}, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110}, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115}, {
116 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
117 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
120} };
121
122static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
123 u32 block_offset, u32 reg)
124{
125 unsigned long flags;
126 u32 r;
127
128 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
129 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
130 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
131 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
132
133 return r;
134}
135
136static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
137 u32 block_offset, u32 reg, u32 v)
138{
139 unsigned long flags;
140
141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
144 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
145}
146
147static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
148{
149 if (crtc >= adev->mode_info.num_crtc)
150 return 0;
151 else
152 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
153}
154
155static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
156{
157 unsigned i;
158
159 /* Enable pflip interrupts */
160 for (i = 0; i < adev->mode_info.num_crtc; i++)
161 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
162}
163
164static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
165{
166 unsigned i;
167
168 /* Disable pflip interrupts */
169 for (i = 0; i < adev->mode_info.num_crtc; i++)
170 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
171}
172
173/**
174 * dce_v8_0_page_flip - pageflip callback.
175 *
176 * @adev: amdgpu_device pointer
177 * @crtc_id: crtc to cleanup pageflip on
178 * @crtc_base: new address of the crtc (GPU MC address)
179 * @async: asynchronous flip
180 *
181 * Triggers the actual pageflip by updating the primary
182 * surface base address.
183 */
184static void dce_v8_0_page_flip(struct amdgpu_device *adev,
185 int crtc_id, u64 crtc_base, bool async)
186{
187 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
188 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
189
190 /* flip at hsync for async, default is vsync */
191 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
192 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
193 /* update pitch */
194 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
195 fb->pitches[0] / fb->format->cpp[0]);
196 /* update the primary scanout addresses */
197 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
198 upper_32_bits(crtc_base));
199 /* writing to the low address triggers the update */
200 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
201 lower_32_bits(crtc_base));
202 /* post the write */
203 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
204}
205
206static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
207 u32 *vbl, u32 *position)
208{
209 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
210 return -EINVAL;
211
212 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
213 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
214
215 return 0;
216}
217
218/**
219 * dce_v8_0_hpd_sense - hpd sense callback.
220 *
221 * @adev: amdgpu_device pointer
222 * @hpd: hpd (hotplug detect) pin
223 *
224 * Checks if a digital monitor is connected (evergreen+).
225 * Returns true if connected, false if not connected.
226 */
227static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
228 enum amdgpu_hpd_id hpd)
229{
230 bool connected = false;
231
232 if (hpd >= adev->mode_info.num_hpd)
233 return connected;
234
235 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
236 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
237 connected = true;
238
239 return connected;
240}
241
242/**
243 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
244 *
245 * @adev: amdgpu_device pointer
246 * @hpd: hpd (hotplug detect) pin
247 *
248 * Set the polarity of the hpd pin (evergreen+).
249 */
250static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
251 enum amdgpu_hpd_id hpd)
252{
253 u32 tmp;
254 bool connected = dce_v8_0_hpd_sense(adev, hpd);
255
256 if (hpd >= adev->mode_info.num_hpd)
257 return;
258
259 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
260 if (connected)
261 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
262 else
263 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
264 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
265}
266
267/**
268 * dce_v8_0_hpd_init - hpd setup callback.
269 *
270 * @adev: amdgpu_device pointer
271 *
272 * Setup the hpd pins used by the card (evergreen+).
273 * Enable the pin, set the polarity, and enable the hpd interrupts.
274 */
275static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
276{
277 struct drm_device *dev = adev_to_drm(adev);
278 struct drm_connector *connector;
279 struct drm_connector_list_iter iter;
280 u32 tmp;
281
282 drm_connector_list_iter_begin(dev, &iter);
283 drm_for_each_connector_iter(connector, &iter) {
284 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
285
286 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
287 continue;
288
289 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
290 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
291 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
292
293 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
294 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
295 /* don't try to enable hpd on eDP or LVDS avoid breaking the
296 * aux dp channel on imac and help (but not completely fix)
297 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
298 * also avoid interrupt storms during dpms.
299 */
300 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
301 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
302 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
303 continue;
304 }
305
306 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
307 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
308 }
309 drm_connector_list_iter_end(&iter);
310}
311
312/**
313 * dce_v8_0_hpd_fini - hpd tear down callback.
314 *
315 * @adev: amdgpu_device pointer
316 *
317 * Tear down the hpd pins used by the card (evergreen+).
318 * Disable the hpd interrupts.
319 */
320static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
321{
322 struct drm_device *dev = adev_to_drm(adev);
323 struct drm_connector *connector;
324 struct drm_connector_list_iter iter;
325 u32 tmp;
326
327 drm_connector_list_iter_begin(dev, &iter);
328 drm_for_each_connector_iter(connector, &iter) {
329 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
330
331 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
332 continue;
333
334 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
335 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
336 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
337
338 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
339 }
340 drm_connector_list_iter_end(&iter);
341}
342
343static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
344{
345 return mmDC_GPIO_HPD_A;
346}
347
348static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
349{
350 u32 crtc_hung = 0;
351 u32 crtc_status[6];
352 u32 i, j, tmp;
353
354 for (i = 0; i < adev->mode_info.num_crtc; i++) {
355 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
356 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
357 crtc_hung |= (1 << i);
358 }
359 }
360
361 for (j = 0; j < 10; j++) {
362 for (i = 0; i < adev->mode_info.num_crtc; i++) {
363 if (crtc_hung & (1 << i)) {
364 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
365 if (tmp != crtc_status[i])
366 crtc_hung &= ~(1 << i);
367 }
368 }
369 if (crtc_hung == 0)
370 return false;
371 udelay(100);
372 }
373
374 return true;
375}
376
377static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
378 bool render)
379{
380 u32 tmp;
381
382 /* Lockout access through VGA aperture*/
383 tmp = RREG32(mmVGA_HDP_CONTROL);
384 if (render)
385 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
386 else
387 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
388 WREG32(mmVGA_HDP_CONTROL, tmp);
389
390 /* disable VGA render */
391 tmp = RREG32(mmVGA_RENDER_CONTROL);
392 if (render)
393 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
394 else
395 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
396 WREG32(mmVGA_RENDER_CONTROL, tmp);
397}
398
399static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
400{
401 int num_crtc = 0;
402
403 switch (adev->asic_type) {
404 case CHIP_BONAIRE:
405 case CHIP_HAWAII:
406 num_crtc = 6;
407 break;
408 case CHIP_KAVERI:
409 num_crtc = 4;
410 break;
411 case CHIP_KABINI:
412 case CHIP_MULLINS:
413 num_crtc = 2;
414 break;
415 default:
416 num_crtc = 0;
417 }
418 return num_crtc;
419}
420
421void dce_v8_0_disable_dce(struct amdgpu_device *adev)
422{
423 /*Disable VGA render and enabled crtc, if has DCE engine*/
424 if (amdgpu_atombios_has_dce_engine_info(adev)) {
425 u32 tmp;
426 int crtc_enabled, i;
427
428 dce_v8_0_set_vga_render_state(adev, false);
429
430 /*Disable crtc*/
431 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
432 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
433 CRTC_CONTROL, CRTC_MASTER_EN);
434 if (crtc_enabled) {
435 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
436 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
437 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
438 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
439 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
440 }
441 }
442 }
443}
444
445static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
446{
447 struct drm_device *dev = encoder->dev;
448 struct amdgpu_device *adev = drm_to_adev(dev);
449 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
450 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
451 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
452 int bpc = 0;
453 u32 tmp = 0;
454 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
455
456 if (connector) {
457 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
458 bpc = amdgpu_connector_get_monitor_bpc(connector);
459 dither = amdgpu_connector->dither;
460 }
461
462 /* LVDS/eDP FMT is set up by atom */
463 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
464 return;
465
466 /* not needed for analog */
467 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
468 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
469 return;
470
471 if (bpc == 0)
472 return;
473
474 switch (bpc) {
475 case 6:
476 if (dither == AMDGPU_FMT_DITHER_ENABLE)
477 /* XXX sort out optimal dither settings */
478 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
479 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
480 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
481 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
482 else
483 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
484 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
485 break;
486 case 8:
487 if (dither == AMDGPU_FMT_DITHER_ENABLE)
488 /* XXX sort out optimal dither settings */
489 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
490 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
491 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
492 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
493 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
494 else
495 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
496 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
497 break;
498 case 10:
499 if (dither == AMDGPU_FMT_DITHER_ENABLE)
500 /* XXX sort out optimal dither settings */
501 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
502 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
503 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
504 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
505 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
506 else
507 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
508 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
509 break;
510 default:
511 /* not needed */
512 break;
513 }
514
515 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
516}
517
518
519/* display watermark setup */
520/**
521 * dce_v8_0_line_buffer_adjust - Set up the line buffer
522 *
523 * @adev: amdgpu_device pointer
524 * @amdgpu_crtc: the selected display controller
525 * @mode: the current display mode on the selected display
526 * controller
527 *
528 * Setup up the line buffer allocation for
529 * the selected display controller (CIK).
530 * Returns the line buffer size in pixels.
531 */
532static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
533 struct amdgpu_crtc *amdgpu_crtc,
534 struct drm_display_mode *mode)
535{
536 u32 tmp, buffer_alloc, i;
537 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
538 /*
539 * Line Buffer Setup
540 * There are 6 line buffers, one for each display controllers.
541 * There are 3 partitions per LB. Select the number of partitions
542 * to enable based on the display width. For display widths larger
543 * than 4096, you need use to use 2 display controllers and combine
544 * them using the stereo blender.
545 */
546 if (amdgpu_crtc->base.enabled && mode) {
547 if (mode->crtc_hdisplay < 1920) {
548 tmp = 1;
549 buffer_alloc = 2;
550 } else if (mode->crtc_hdisplay < 2560) {
551 tmp = 2;
552 buffer_alloc = 2;
553 } else if (mode->crtc_hdisplay < 4096) {
554 tmp = 0;
555 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
556 } else {
557 DRM_DEBUG_KMS("Mode too big for LB!\n");
558 tmp = 0;
559 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
560 }
561 } else {
562 tmp = 1;
563 buffer_alloc = 0;
564 }
565
566 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
567 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
568 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
569
570 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
571 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
572 for (i = 0; i < adev->usec_timeout; i++) {
573 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
574 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
575 break;
576 udelay(1);
577 }
578
579 if (amdgpu_crtc->base.enabled && mode) {
580 switch (tmp) {
581 case 0:
582 default:
583 return 4096 * 2;
584 case 1:
585 return 1920 * 2;
586 case 2:
587 return 2560 * 2;
588 }
589 }
590
591 /* controller not enabled, so no lb used */
592 return 0;
593}
594
595/**
596 * cik_get_number_of_dram_channels - get the number of dram channels
597 *
598 * @adev: amdgpu_device pointer
599 *
600 * Look up the number of video ram channels (CIK).
601 * Used for display watermark bandwidth calculations
602 * Returns the number of dram channels
603 */
604static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
605{
606 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
607
608 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
609 case 0:
610 default:
611 return 1;
612 case 1:
613 return 2;
614 case 2:
615 return 4;
616 case 3:
617 return 8;
618 case 4:
619 return 3;
620 case 5:
621 return 6;
622 case 6:
623 return 10;
624 case 7:
625 return 12;
626 case 8:
627 return 16;
628 }
629}
630
631struct dce8_wm_params {
632 u32 dram_channels; /* number of dram channels */
633 u32 yclk; /* bandwidth per dram data pin in kHz */
634 u32 sclk; /* engine clock in kHz */
635 u32 disp_clk; /* display clock in kHz */
636 u32 src_width; /* viewport width */
637 u32 active_time; /* active display time in ns */
638 u32 blank_time; /* blank time in ns */
639 bool interlaced; /* mode is interlaced */
640 fixed20_12 vsc; /* vertical scale ratio */
641 u32 num_heads; /* number of active crtcs */
642 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
643 u32 lb_size; /* line buffer allocated to pipe */
644 u32 vtaps; /* vertical scaler taps */
645};
646
647/**
648 * dce_v8_0_dram_bandwidth - get the dram bandwidth
649 *
650 * @wm: watermark calculation data
651 *
652 * Calculate the raw dram bandwidth (CIK).
653 * Used for display watermark bandwidth calculations
654 * Returns the dram bandwidth in MBytes/s
655 */
656static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
657{
658 /* Calculate raw DRAM Bandwidth */
659 fixed20_12 dram_efficiency; /* 0.7 */
660 fixed20_12 yclk, dram_channels, bandwidth;
661 fixed20_12 a;
662
663 a.full = dfixed_const(1000);
664 yclk.full = dfixed_const(wm->yclk);
665 yclk.full = dfixed_div(yclk, a);
666 dram_channels.full = dfixed_const(wm->dram_channels * 4);
667 a.full = dfixed_const(10);
668 dram_efficiency.full = dfixed_const(7);
669 dram_efficiency.full = dfixed_div(dram_efficiency, a);
670 bandwidth.full = dfixed_mul(dram_channels, yclk);
671 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
672
673 return dfixed_trunc(bandwidth);
674}
675
676/**
677 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
678 *
679 * @wm: watermark calculation data
680 *
681 * Calculate the dram bandwidth used for display (CIK).
682 * Used for display watermark bandwidth calculations
683 * Returns the dram bandwidth for display in MBytes/s
684 */
685static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
686{
687 /* Calculate DRAM Bandwidth and the part allocated to display. */
688 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
689 fixed20_12 yclk, dram_channels, bandwidth;
690 fixed20_12 a;
691
692 a.full = dfixed_const(1000);
693 yclk.full = dfixed_const(wm->yclk);
694 yclk.full = dfixed_div(yclk, a);
695 dram_channels.full = dfixed_const(wm->dram_channels * 4);
696 a.full = dfixed_const(10);
697 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
698 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
699 bandwidth.full = dfixed_mul(dram_channels, yclk);
700 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
701
702 return dfixed_trunc(bandwidth);
703}
704
705/**
706 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
707 *
708 * @wm: watermark calculation data
709 *
710 * Calculate the data return bandwidth used for display (CIK).
711 * Used for display watermark bandwidth calculations
712 * Returns the data return bandwidth in MBytes/s
713 */
714static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
715{
716 /* Calculate the display Data return Bandwidth */
717 fixed20_12 return_efficiency; /* 0.8 */
718 fixed20_12 sclk, bandwidth;
719 fixed20_12 a;
720
721 a.full = dfixed_const(1000);
722 sclk.full = dfixed_const(wm->sclk);
723 sclk.full = dfixed_div(sclk, a);
724 a.full = dfixed_const(10);
725 return_efficiency.full = dfixed_const(8);
726 return_efficiency.full = dfixed_div(return_efficiency, a);
727 a.full = dfixed_const(32);
728 bandwidth.full = dfixed_mul(a, sclk);
729 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
730
731 return dfixed_trunc(bandwidth);
732}
733
734/**
735 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
736 *
737 * @wm: watermark calculation data
738 *
739 * Calculate the dmif bandwidth used for display (CIK).
740 * Used for display watermark bandwidth calculations
741 * Returns the dmif bandwidth in MBytes/s
742 */
743static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
744{
745 /* Calculate the DMIF Request Bandwidth */
746 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
747 fixed20_12 disp_clk, bandwidth;
748 fixed20_12 a, b;
749
750 a.full = dfixed_const(1000);
751 disp_clk.full = dfixed_const(wm->disp_clk);
752 disp_clk.full = dfixed_div(disp_clk, a);
753 a.full = dfixed_const(32);
754 b.full = dfixed_mul(a, disp_clk);
755
756 a.full = dfixed_const(10);
757 disp_clk_request_efficiency.full = dfixed_const(8);
758 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
759
760 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
761
762 return dfixed_trunc(bandwidth);
763}
764
765/**
766 * dce_v8_0_available_bandwidth - get the min available bandwidth
767 *
768 * @wm: watermark calculation data
769 *
770 * Calculate the min available bandwidth used for display (CIK).
771 * Used for display watermark bandwidth calculations
772 * Returns the min available bandwidth in MBytes/s
773 */
774static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
775{
776 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
777 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
778 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
779 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
780
781 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
782}
783
784/**
785 * dce_v8_0_average_bandwidth - get the average available bandwidth
786 *
787 * @wm: watermark calculation data
788 *
789 * Calculate the average available bandwidth used for display (CIK).
790 * Used for display watermark bandwidth calculations
791 * Returns the average available bandwidth in MBytes/s
792 */
793static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
794{
795 /* Calculate the display mode Average Bandwidth
796 * DisplayMode should contain the source and destination dimensions,
797 * timing, etc.
798 */
799 fixed20_12 bpp;
800 fixed20_12 line_time;
801 fixed20_12 src_width;
802 fixed20_12 bandwidth;
803 fixed20_12 a;
804
805 a.full = dfixed_const(1000);
806 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
807 line_time.full = dfixed_div(line_time, a);
808 bpp.full = dfixed_const(wm->bytes_per_pixel);
809 src_width.full = dfixed_const(wm->src_width);
810 bandwidth.full = dfixed_mul(src_width, bpp);
811 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
812 bandwidth.full = dfixed_div(bandwidth, line_time);
813
814 return dfixed_trunc(bandwidth);
815}
816
817/**
818 * dce_v8_0_latency_watermark - get the latency watermark
819 *
820 * @wm: watermark calculation data
821 *
822 * Calculate the latency watermark (CIK).
823 * Used for display watermark bandwidth calculations
824 * Returns the latency watermark in ns
825 */
826static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
827{
828 /* First calculate the latency in ns */
829 u32 mc_latency = 2000; /* 2000 ns. */
830 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
831 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
832 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
833 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
834 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
835 (wm->num_heads * cursor_line_pair_return_time);
836 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
837 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
838 u32 tmp, dmif_size = 12288;
839 fixed20_12 a, b, c;
840
841 if (wm->num_heads == 0)
842 return 0;
843
844 a.full = dfixed_const(2);
845 b.full = dfixed_const(1);
846 if ((wm->vsc.full > a.full) ||
847 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
848 (wm->vtaps >= 5) ||
849 ((wm->vsc.full >= a.full) && wm->interlaced))
850 max_src_lines_per_dst_line = 4;
851 else
852 max_src_lines_per_dst_line = 2;
853
854 a.full = dfixed_const(available_bandwidth);
855 b.full = dfixed_const(wm->num_heads);
856 a.full = dfixed_div(a, b);
857 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
858 tmp = min(dfixed_trunc(a), tmp);
859
860 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
861
862 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
863 b.full = dfixed_const(1000);
864 c.full = dfixed_const(lb_fill_bw);
865 b.full = dfixed_div(c, b);
866 a.full = dfixed_div(a, b);
867 line_fill_time = dfixed_trunc(a);
868
869 if (line_fill_time < wm->active_time)
870 return latency;
871 else
872 return latency + (line_fill_time - wm->active_time);
873
874}
875
876/**
877 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
878 * average and available dram bandwidth
879 *
880 * @wm: watermark calculation data
881 *
882 * Check if the display average bandwidth fits in the display
883 * dram bandwidth (CIK).
884 * Used for display watermark bandwidth calculations
885 * Returns true if the display fits, false if not.
886 */
887static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
888{
889 if (dce_v8_0_average_bandwidth(wm) <=
890 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
891 return true;
892 else
893 return false;
894}
895
896/**
897 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
898 * average and available bandwidth
899 *
900 * @wm: watermark calculation data
901 *
902 * Check if the display average bandwidth fits in the display
903 * available bandwidth (CIK).
904 * Used for display watermark bandwidth calculations
905 * Returns true if the display fits, false if not.
906 */
907static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
908{
909 if (dce_v8_0_average_bandwidth(wm) <=
910 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
911 return true;
912 else
913 return false;
914}
915
916/**
917 * dce_v8_0_check_latency_hiding - check latency hiding
918 *
919 * @wm: watermark calculation data
920 *
921 * Check latency hiding (CIK).
922 * Used for display watermark bandwidth calculations
923 * Returns true if the display fits, false if not.
924 */
925static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
926{
927 u32 lb_partitions = wm->lb_size / wm->src_width;
928 u32 line_time = wm->active_time + wm->blank_time;
929 u32 latency_tolerant_lines;
930 u32 latency_hiding;
931 fixed20_12 a;
932
933 a.full = dfixed_const(1);
934 if (wm->vsc.full > a.full)
935 latency_tolerant_lines = 1;
936 else {
937 if (lb_partitions <= (wm->vtaps + 1))
938 latency_tolerant_lines = 1;
939 else
940 latency_tolerant_lines = 2;
941 }
942
943 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
944
945 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
946 return true;
947 else
948 return false;
949}
950
951/**
952 * dce_v8_0_program_watermarks - program display watermarks
953 *
954 * @adev: amdgpu_device pointer
955 * @amdgpu_crtc: the selected display controller
956 * @lb_size: line buffer size
957 * @num_heads: number of display controllers in use
958 *
959 * Calculate and program the display watermarks for the
960 * selected display controller (CIK).
961 */
962static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
963 struct amdgpu_crtc *amdgpu_crtc,
964 u32 lb_size, u32 num_heads)
965{
966 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
967 struct dce8_wm_params wm_low, wm_high;
968 u32 active_time;
969 u32 line_time = 0;
970 u32 latency_watermark_a = 0, latency_watermark_b = 0;
971 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
972
973 if (amdgpu_crtc->base.enabled && num_heads && mode) {
974 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
975 (u32)mode->clock);
976 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
977 (u32)mode->clock);
978 line_time = min(line_time, (u32)65535);
979
980 /* watermark for high clocks */
981 if (adev->pm.dpm_enabled) {
982 wm_high.yclk =
983 amdgpu_dpm_get_mclk(adev, false) * 10;
984 wm_high.sclk =
985 amdgpu_dpm_get_sclk(adev, false) * 10;
986 } else {
987 wm_high.yclk = adev->pm.current_mclk * 10;
988 wm_high.sclk = adev->pm.current_sclk * 10;
989 }
990
991 wm_high.disp_clk = mode->clock;
992 wm_high.src_width = mode->crtc_hdisplay;
993 wm_high.active_time = active_time;
994 wm_high.blank_time = line_time - wm_high.active_time;
995 wm_high.interlaced = false;
996 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
997 wm_high.interlaced = true;
998 wm_high.vsc = amdgpu_crtc->vsc;
999 wm_high.vtaps = 1;
1000 if (amdgpu_crtc->rmx_type != RMX_OFF)
1001 wm_high.vtaps = 2;
1002 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1003 wm_high.lb_size = lb_size;
1004 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1005 wm_high.num_heads = num_heads;
1006
1007 /* set for high clocks */
1008 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1009
1010 /* possibly force display priority to high */
1011 /* should really do this at mode validation time... */
1012 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1013 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1014 !dce_v8_0_check_latency_hiding(&wm_high) ||
1015 (adev->mode_info.disp_priority == 2)) {
1016 DRM_DEBUG_KMS("force priority to high\n");
1017 }
1018
1019 /* watermark for low clocks */
1020 if (adev->pm.dpm_enabled) {
1021 wm_low.yclk =
1022 amdgpu_dpm_get_mclk(adev, true) * 10;
1023 wm_low.sclk =
1024 amdgpu_dpm_get_sclk(adev, true) * 10;
1025 } else {
1026 wm_low.yclk = adev->pm.current_mclk * 10;
1027 wm_low.sclk = adev->pm.current_sclk * 10;
1028 }
1029
1030 wm_low.disp_clk = mode->clock;
1031 wm_low.src_width = mode->crtc_hdisplay;
1032 wm_low.active_time = active_time;
1033 wm_low.blank_time = line_time - wm_low.active_time;
1034 wm_low.interlaced = false;
1035 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1036 wm_low.interlaced = true;
1037 wm_low.vsc = amdgpu_crtc->vsc;
1038 wm_low.vtaps = 1;
1039 if (amdgpu_crtc->rmx_type != RMX_OFF)
1040 wm_low.vtaps = 2;
1041 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1042 wm_low.lb_size = lb_size;
1043 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1044 wm_low.num_heads = num_heads;
1045
1046 /* set for low clocks */
1047 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1048
1049 /* possibly force display priority to high */
1050 /* should really do this at mode validation time... */
1051 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1052 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1053 !dce_v8_0_check_latency_hiding(&wm_low) ||
1054 (adev->mode_info.disp_priority == 2)) {
1055 DRM_DEBUG_KMS("force priority to high\n");
1056 }
1057 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1058 }
1059
1060 /* select wm A */
1061 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1062 tmp = wm_mask;
1063 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1064 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1065 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1066 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1067 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1068 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1069 /* select wm B */
1070 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1071 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1072 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1073 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1074 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1075 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1076 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1077 /* restore original selection */
1078 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1079
1080 /* save values for DPM */
1081 amdgpu_crtc->line_time = line_time;
1082 amdgpu_crtc->wm_high = latency_watermark_a;
1083 amdgpu_crtc->wm_low = latency_watermark_b;
1084 /* Save number of lines the linebuffer leads before the scanout */
1085 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1086}
1087
1088/**
1089 * dce_v8_0_bandwidth_update - program display watermarks
1090 *
1091 * @adev: amdgpu_device pointer
1092 *
1093 * Calculate and program the display watermarks and line
1094 * buffer allocation (CIK).
1095 */
1096static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1097{
1098 struct drm_display_mode *mode = NULL;
1099 u32 num_heads = 0, lb_size;
1100 int i;
1101
1102 amdgpu_display_update_priority(adev);
1103
1104 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1105 if (adev->mode_info.crtcs[i]->base.enabled)
1106 num_heads++;
1107 }
1108 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1109 mode = &adev->mode_info.crtcs[i]->base.mode;
1110 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1111 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1112 lb_size, num_heads);
1113 }
1114}
1115
1116static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1117{
1118 int i;
1119 u32 offset, tmp;
1120
1121 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1122 offset = adev->mode_info.audio.pin[i].offset;
1123 tmp = RREG32_AUDIO_ENDPT(offset,
1124 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1125 if (((tmp &
1126 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1127 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1128 adev->mode_info.audio.pin[i].connected = false;
1129 else
1130 adev->mode_info.audio.pin[i].connected = true;
1131 }
1132}
1133
1134static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1135{
1136 int i;
1137
1138 dce_v8_0_audio_get_connected_pins(adev);
1139
1140 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1141 if (adev->mode_info.audio.pin[i].connected)
1142 return &adev->mode_info.audio.pin[i];
1143 }
1144 DRM_ERROR("No connected audio pins found!\n");
1145 return NULL;
1146}
1147
1148static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1149{
1150 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1151 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1152 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1153 u32 offset;
1154
1155 if (!dig || !dig->afmt || !dig->afmt->pin)
1156 return;
1157
1158 offset = dig->afmt->offset;
1159
1160 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1161 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1162}
1163
1164static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1165 struct drm_display_mode *mode)
1166{
1167 struct drm_device *dev = encoder->dev;
1168 struct amdgpu_device *adev = drm_to_adev(dev);
1169 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1170 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1171 struct drm_connector *connector;
1172 struct drm_connector_list_iter iter;
1173 struct amdgpu_connector *amdgpu_connector = NULL;
1174 u32 tmp = 0, offset;
1175
1176 if (!dig || !dig->afmt || !dig->afmt->pin)
1177 return;
1178
1179 offset = dig->afmt->pin->offset;
1180
1181 drm_connector_list_iter_begin(dev, &iter);
1182 drm_for_each_connector_iter(connector, &iter) {
1183 if (connector->encoder == encoder) {
1184 amdgpu_connector = to_amdgpu_connector(connector);
1185 break;
1186 }
1187 }
1188 drm_connector_list_iter_end(&iter);
1189
1190 if (!amdgpu_connector) {
1191 DRM_ERROR("Couldn't find encoder's connector\n");
1192 return;
1193 }
1194
1195 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1196 if (connector->latency_present[1])
1197 tmp =
1198 (connector->video_latency[1] <<
1199 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1200 (connector->audio_latency[1] <<
1201 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1202 else
1203 tmp =
1204 (0 <<
1205 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1206 (0 <<
1207 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1208 } else {
1209 if (connector->latency_present[0])
1210 tmp =
1211 (connector->video_latency[0] <<
1212 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1213 (connector->audio_latency[0] <<
1214 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1215 else
1216 tmp =
1217 (0 <<
1218 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1219 (0 <<
1220 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1221
1222 }
1223 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1224}
1225
1226static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1227{
1228 struct drm_device *dev = encoder->dev;
1229 struct amdgpu_device *adev = drm_to_adev(dev);
1230 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1231 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1232 struct drm_connector *connector;
1233 struct drm_connector_list_iter iter;
1234 struct amdgpu_connector *amdgpu_connector = NULL;
1235 u32 offset, tmp;
1236 u8 *sadb = NULL;
1237 int sad_count;
1238
1239 if (!dig || !dig->afmt || !dig->afmt->pin)
1240 return;
1241
1242 offset = dig->afmt->pin->offset;
1243
1244 drm_connector_list_iter_begin(dev, &iter);
1245 drm_for_each_connector_iter(connector, &iter) {
1246 if (connector->encoder == encoder) {
1247 amdgpu_connector = to_amdgpu_connector(connector);
1248 break;
1249 }
1250 }
1251 drm_connector_list_iter_end(&iter);
1252
1253 if (!amdgpu_connector) {
1254 DRM_ERROR("Couldn't find encoder's connector\n");
1255 return;
1256 }
1257
1258 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1259 if (sad_count < 0) {
1260 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1261 sad_count = 0;
1262 }
1263
1264 /* program the speaker allocation */
1265 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1266 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1267 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1268 /* set HDMI mode */
1269 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1270 if (sad_count)
1271 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1272 else
1273 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1274 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1275
1276 kfree(sadb);
1277}
1278
1279static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1280{
1281 struct drm_device *dev = encoder->dev;
1282 struct amdgpu_device *adev = drm_to_adev(dev);
1283 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1284 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1285 u32 offset;
1286 struct drm_connector *connector;
1287 struct drm_connector_list_iter iter;
1288 struct amdgpu_connector *amdgpu_connector = NULL;
1289 struct cea_sad *sads;
1290 int i, sad_count;
1291
1292 static const u16 eld_reg_to_type[][2] = {
1293 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1294 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1295 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1296 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1297 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1298 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1299 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1300 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1301 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1302 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1303 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1304 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1305 };
1306
1307 if (!dig || !dig->afmt || !dig->afmt->pin)
1308 return;
1309
1310 offset = dig->afmt->pin->offset;
1311
1312 drm_connector_list_iter_begin(dev, &iter);
1313 drm_for_each_connector_iter(connector, &iter) {
1314 if (connector->encoder == encoder) {
1315 amdgpu_connector = to_amdgpu_connector(connector);
1316 break;
1317 }
1318 }
1319 drm_connector_list_iter_end(&iter);
1320
1321 if (!amdgpu_connector) {
1322 DRM_ERROR("Couldn't find encoder's connector\n");
1323 return;
1324 }
1325
1326 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1327 if (sad_count < 0)
1328 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1329 if (sad_count <= 0)
1330 return;
1331 BUG_ON(!sads);
1332
1333 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1334 u32 value = 0;
1335 u8 stereo_freqs = 0;
1336 int max_channels = -1;
1337 int j;
1338
1339 for (j = 0; j < sad_count; j++) {
1340 struct cea_sad *sad = &sads[j];
1341
1342 if (sad->format == eld_reg_to_type[i][1]) {
1343 if (sad->channels > max_channels) {
1344 value = (sad->channels <<
1345 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1346 (sad->byte2 <<
1347 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1348 (sad->freq <<
1349 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1350 max_channels = sad->channels;
1351 }
1352
1353 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1354 stereo_freqs |= sad->freq;
1355 else
1356 break;
1357 }
1358 }
1359
1360 value |= (stereo_freqs <<
1361 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1362
1363 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1364 }
1365
1366 kfree(sads);
1367}
1368
1369static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1370 struct amdgpu_audio_pin *pin,
1371 bool enable)
1372{
1373 if (!pin)
1374 return;
1375
1376 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1377 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1378}
1379
1380static const u32 pin_offsets[7] =
1381{
1382 (0x1780 - 0x1780),
1383 (0x1786 - 0x1780),
1384 (0x178c - 0x1780),
1385 (0x1792 - 0x1780),
1386 (0x1798 - 0x1780),
1387 (0x179d - 0x1780),
1388 (0x17a4 - 0x1780),
1389};
1390
1391static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1392{
1393 int i;
1394
1395 if (!amdgpu_audio)
1396 return 0;
1397
1398 adev->mode_info.audio.enabled = true;
1399
1400 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1401 adev->mode_info.audio.num_pins = 7;
1402 else if ((adev->asic_type == CHIP_KABINI) ||
1403 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1404 adev->mode_info.audio.num_pins = 3;
1405 else if ((adev->asic_type == CHIP_BONAIRE) ||
1406 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1407 adev->mode_info.audio.num_pins = 7;
1408 else
1409 adev->mode_info.audio.num_pins = 3;
1410
1411 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1412 adev->mode_info.audio.pin[i].channels = -1;
1413 adev->mode_info.audio.pin[i].rate = -1;
1414 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1415 adev->mode_info.audio.pin[i].status_bits = 0;
1416 adev->mode_info.audio.pin[i].category_code = 0;
1417 adev->mode_info.audio.pin[i].connected = false;
1418 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1419 adev->mode_info.audio.pin[i].id = i;
1420 /* disable audio. it will be set up later */
1421 /* XXX remove once we switch to ip funcs */
1422 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1423 }
1424
1425 return 0;
1426}
1427
1428static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1429{
1430 int i;
1431
1432 if (!amdgpu_audio)
1433 return;
1434
1435 if (!adev->mode_info.audio.enabled)
1436 return;
1437
1438 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1439 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1440
1441 adev->mode_info.audio.enabled = false;
1442}
1443
1444/*
1445 * update the N and CTS parameters for a given pixel clock rate
1446 */
1447static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1448{
1449 struct drm_device *dev = encoder->dev;
1450 struct amdgpu_device *adev = drm_to_adev(dev);
1451 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1452 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1453 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1454 uint32_t offset = dig->afmt->offset;
1455
1456 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1457 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1458
1459 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1460 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1461
1462 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1463 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1464}
1465
1466/*
1467 * build a HDMI Video Info Frame
1468 */
1469static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1470 void *buffer, size_t size)
1471{
1472 struct drm_device *dev = encoder->dev;
1473 struct amdgpu_device *adev = drm_to_adev(dev);
1474 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1475 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1476 uint32_t offset = dig->afmt->offset;
1477 uint8_t *frame = buffer + 3;
1478 uint8_t *header = buffer;
1479
1480 WREG32(mmAFMT_AVI_INFO0 + offset,
1481 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1482 WREG32(mmAFMT_AVI_INFO1 + offset,
1483 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1484 WREG32(mmAFMT_AVI_INFO2 + offset,
1485 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1486 WREG32(mmAFMT_AVI_INFO3 + offset,
1487 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1488}
1489
1490static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1491{
1492 struct drm_device *dev = encoder->dev;
1493 struct amdgpu_device *adev = drm_to_adev(dev);
1494 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1495 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1496 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1497 u32 dto_phase = 24 * 1000;
1498 u32 dto_modulo = clock;
1499
1500 if (!dig || !dig->afmt)
1501 return;
1502
1503 /* XXX two dtos; generally use dto0 for hdmi */
1504 /* Express [24MHz / target pixel clock] as an exact rational
1505 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1506 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1507 */
1508 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1509 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1510 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1511}
1512
1513/*
1514 * update the info frames with the data from the current display mode
1515 */
1516static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1517 struct drm_display_mode *mode)
1518{
1519 struct drm_device *dev = encoder->dev;
1520 struct amdgpu_device *adev = drm_to_adev(dev);
1521 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1522 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1523 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1524 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1525 struct hdmi_avi_infoframe frame;
1526 uint32_t offset, val;
1527 ssize_t err;
1528 int bpc = 8;
1529
1530 if (!dig || !dig->afmt)
1531 return;
1532
1533 /* Silent, r600_hdmi_enable will raise WARN for us */
1534 if (!dig->afmt->enabled)
1535 return;
1536
1537 offset = dig->afmt->offset;
1538
1539 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1540 if (encoder->crtc) {
1541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1542 bpc = amdgpu_crtc->bpc;
1543 }
1544
1545 /* disable audio prior to setting up hw */
1546 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1547 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1548
1549 dce_v8_0_audio_set_dto(encoder, mode->clock);
1550
1551 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1552 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1553
1554 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1555
1556 val = RREG32(mmHDMI_CONTROL + offset);
1557 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1558 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1559
1560 switch (bpc) {
1561 case 0:
1562 case 6:
1563 case 8:
1564 case 16:
1565 default:
1566 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1567 connector->name, bpc);
1568 break;
1569 case 10:
1570 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1571 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1572 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1573 connector->name);
1574 break;
1575 case 12:
1576 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1577 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1578 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1579 connector->name);
1580 break;
1581 }
1582
1583 WREG32(mmHDMI_CONTROL + offset, val);
1584
1585 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1586 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1587 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1588 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1589
1590 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1591 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1592 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1593
1594 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1595 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1596
1597 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1598 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1599
1600 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1601
1602 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1603 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1604 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1605
1606 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1607 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1608
1609 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1610
1611 if (bpc > 8)
1612 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1613 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1614 else
1615 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1616 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1617 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1618
1619 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1620
1621 WREG32(mmAFMT_60958_0 + offset,
1622 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1623
1624 WREG32(mmAFMT_60958_1 + offset,
1625 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1626
1627 WREG32(mmAFMT_60958_2 + offset,
1628 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1629 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1630 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1631 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1632 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1633 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1634
1635 dce_v8_0_audio_write_speaker_allocation(encoder);
1636
1637
1638 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1639 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1640
1641 dce_v8_0_afmt_audio_select_pin(encoder);
1642 dce_v8_0_audio_write_sad_regs(encoder);
1643 dce_v8_0_audio_write_latency_fields(encoder, mode);
1644
1645 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1646 if (err < 0) {
1647 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1648 return;
1649 }
1650
1651 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1652 if (err < 0) {
1653 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1654 return;
1655 }
1656
1657 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1658
1659 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1660 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1661 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1662
1663 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1664 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1665 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1666
1667 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1668 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1669
1670 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1671 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1672 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1673 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1674
1675 /* enable audio after setting up hw */
1676 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1677}
1678
1679static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1680{
1681 struct drm_device *dev = encoder->dev;
1682 struct amdgpu_device *adev = drm_to_adev(dev);
1683 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1684 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1685
1686 if (!dig || !dig->afmt)
1687 return;
1688
1689 /* Silent, r600_hdmi_enable will raise WARN for us */
1690 if (enable && dig->afmt->enabled)
1691 return;
1692 if (!enable && !dig->afmt->enabled)
1693 return;
1694
1695 if (!enable && dig->afmt->pin) {
1696 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1697 dig->afmt->pin = NULL;
1698 }
1699
1700 dig->afmt->enabled = enable;
1701
1702 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1703 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1704}
1705
1706static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1707{
1708 int i;
1709
1710 for (i = 0; i < adev->mode_info.num_dig; i++)
1711 adev->mode_info.afmt[i] = NULL;
1712
1713 /* DCE8 has audio blocks tied to DIG encoders */
1714 for (i = 0; i < adev->mode_info.num_dig; i++) {
1715 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1716 if (adev->mode_info.afmt[i]) {
1717 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1718 adev->mode_info.afmt[i]->id = i;
1719 } else {
1720 int j;
1721 for (j = 0; j < i; j++) {
1722 kfree(adev->mode_info.afmt[j]);
1723 adev->mode_info.afmt[j] = NULL;
1724 }
1725 return -ENOMEM;
1726 }
1727 }
1728 return 0;
1729}
1730
1731static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1732{
1733 int i;
1734
1735 for (i = 0; i < adev->mode_info.num_dig; i++) {
1736 kfree(adev->mode_info.afmt[i]);
1737 adev->mode_info.afmt[i] = NULL;
1738 }
1739}
1740
1741static const u32 vga_control_regs[6] =
1742{
1743 mmD1VGA_CONTROL,
1744 mmD2VGA_CONTROL,
1745 mmD3VGA_CONTROL,
1746 mmD4VGA_CONTROL,
1747 mmD5VGA_CONTROL,
1748 mmD6VGA_CONTROL,
1749};
1750
1751static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1752{
1753 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1754 struct drm_device *dev = crtc->dev;
1755 struct amdgpu_device *adev = drm_to_adev(dev);
1756 u32 vga_control;
1757
1758 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1759 if (enable)
1760 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1761 else
1762 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1763}
1764
1765static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1766{
1767 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1768 struct drm_device *dev = crtc->dev;
1769 struct amdgpu_device *adev = drm_to_adev(dev);
1770
1771 if (enable)
1772 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1773 else
1774 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1775}
1776
1777static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1778 struct drm_framebuffer *fb,
1779 int x, int y, int atomic)
1780{
1781 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1782 struct drm_device *dev = crtc->dev;
1783 struct amdgpu_device *adev = drm_to_adev(dev);
1784 struct drm_framebuffer *target_fb;
1785 struct drm_gem_object *obj;
1786 struct amdgpu_bo *abo;
1787 uint64_t fb_location, tiling_flags;
1788 uint32_t fb_format, fb_pitch_pixels;
1789 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1790 u32 pipe_config;
1791 u32 viewport_w, viewport_h;
1792 int r;
1793 bool bypass_lut = false;
1794
1795 /* no fb bound */
1796 if (!atomic && !crtc->primary->fb) {
1797 DRM_DEBUG_KMS("No FB bound\n");
1798 return 0;
1799 }
1800
1801 if (atomic)
1802 target_fb = fb;
1803 else
1804 target_fb = crtc->primary->fb;
1805
1806 /* If atomic, assume fb object is pinned & idle & fenced and
1807 * just update base pointers
1808 */
1809 obj = target_fb->obj[0];
1810 abo = gem_to_amdgpu_bo(obj);
1811 r = amdgpu_bo_reserve(abo, false);
1812 if (unlikely(r != 0))
1813 return r;
1814
1815 if (!atomic) {
1816 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1817 if (unlikely(r != 0)) {
1818 amdgpu_bo_unreserve(abo);
1819 return -EINVAL;
1820 }
1821 }
1822 fb_location = amdgpu_bo_gpu_offset(abo);
1823
1824 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1825 amdgpu_bo_unreserve(abo);
1826
1827 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1828
1829 switch (target_fb->format->format) {
1830 case DRM_FORMAT_C8:
1831 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1832 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1833 break;
1834 case DRM_FORMAT_XRGB4444:
1835 case DRM_FORMAT_ARGB4444:
1836 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1837 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1838#ifdef __BIG_ENDIAN
1839 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1840#endif
1841 break;
1842 case DRM_FORMAT_XRGB1555:
1843 case DRM_FORMAT_ARGB1555:
1844 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1845 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1846#ifdef __BIG_ENDIAN
1847 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1848#endif
1849 break;
1850 case DRM_FORMAT_BGRX5551:
1851 case DRM_FORMAT_BGRA5551:
1852 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1853 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1854#ifdef __BIG_ENDIAN
1855 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1856#endif
1857 break;
1858 case DRM_FORMAT_RGB565:
1859 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1860 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1861#ifdef __BIG_ENDIAN
1862 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1863#endif
1864 break;
1865 case DRM_FORMAT_XRGB8888:
1866 case DRM_FORMAT_ARGB8888:
1867 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1868 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1869#ifdef __BIG_ENDIAN
1870 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1871#endif
1872 break;
1873 case DRM_FORMAT_XRGB2101010:
1874 case DRM_FORMAT_ARGB2101010:
1875 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1876 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1877#ifdef __BIG_ENDIAN
1878 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1879#endif
1880 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1881 bypass_lut = true;
1882 break;
1883 case DRM_FORMAT_BGRX1010102:
1884 case DRM_FORMAT_BGRA1010102:
1885 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1886 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1887#ifdef __BIG_ENDIAN
1888 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1889#endif
1890 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1891 bypass_lut = true;
1892 break;
1893 case DRM_FORMAT_XBGR8888:
1894 case DRM_FORMAT_ABGR8888:
1895 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1896 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1897 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1898 (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1899#ifdef __BIG_ENDIAN
1900 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1901#endif
1902 break;
1903 default:
1904 DRM_ERROR("Unsupported screen format %p4cc\n",
1905 &target_fb->format->format);
1906 return -EINVAL;
1907 }
1908
1909 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1910 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1911
1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1913 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1915 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1916 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1917
1918 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1919 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1920 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1921 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1922 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1923 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1924 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1925 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1926 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1927 }
1928
1929 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1930
1931 dce_v8_0_vga_enable(crtc, false);
1932
1933 /* Make sure surface address is updated at vertical blank rather than
1934 * horizontal blank
1935 */
1936 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1937
1938 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1939 upper_32_bits(fb_location));
1940 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1941 upper_32_bits(fb_location));
1942 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1943 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1944 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1945 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1946 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1947 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1948
1949 /*
1950 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1951 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1952 * retain the full precision throughout the pipeline.
1953 */
1954 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1955 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1956 ~LUT_10BIT_BYPASS_EN);
1957
1958 if (bypass_lut)
1959 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1960
1961 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1962 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1963 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1964 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1965 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1966 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1967
1968 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1969 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1970
1971 dce_v8_0_grph_enable(crtc, true);
1972
1973 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1974 target_fb->height);
1975
1976 x &= ~3;
1977 y &= ~1;
1978 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1979 (x << 16) | y);
1980 viewport_w = crtc->mode.hdisplay;
1981 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1982 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1983 (viewport_w << 16) | viewport_h);
1984
1985 /* set pageflip to happen anywhere in vblank interval */
1986 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1987
1988 if (!atomic && fb && fb != crtc->primary->fb) {
1989 abo = gem_to_amdgpu_bo(fb->obj[0]);
1990 r = amdgpu_bo_reserve(abo, true);
1991 if (unlikely(r != 0))
1992 return r;
1993 amdgpu_bo_unpin(abo);
1994 amdgpu_bo_unreserve(abo);
1995 }
1996
1997 /* Bytes per pixel may have changed */
1998 dce_v8_0_bandwidth_update(adev);
1999
2000 return 0;
2001}
2002
2003static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2004 struct drm_display_mode *mode)
2005{
2006 struct drm_device *dev = crtc->dev;
2007 struct amdgpu_device *adev = drm_to_adev(dev);
2008 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2009
2010 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2011 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2012 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2013 else
2014 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2015}
2016
2017static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2018{
2019 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2020 struct drm_device *dev = crtc->dev;
2021 struct amdgpu_device *adev = drm_to_adev(dev);
2022 u16 *r, *g, *b;
2023 int i;
2024
2025 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2026
2027 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2028 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2029 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2030 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2031 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2032 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2033 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2034 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2035 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2036 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2037
2038 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2039
2040 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2041 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2042 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2043
2044 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2045 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2046 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2047
2048 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2049 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2050
2051 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2052 r = crtc->gamma_store;
2053 g = r + crtc->gamma_size;
2054 b = g + crtc->gamma_size;
2055 for (i = 0; i < 256; i++) {
2056 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2057 ((*r++ & 0xffc0) << 14) |
2058 ((*g++ & 0xffc0) << 4) |
2059 (*b++ >> 6));
2060 }
2061
2062 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2063 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2064 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2065 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2066 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2067 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2068 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2069 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2070 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2071 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2072 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2073 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2074 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2075 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2076 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2077 /* XXX this only needs to be programmed once per crtc at startup,
2078 * not sure where the best place for it is
2079 */
2080 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2081 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2082}
2083
2084static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2085{
2086 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2087 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2088
2089 switch (amdgpu_encoder->encoder_id) {
2090 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2091 if (dig->linkb)
2092 return 1;
2093 else
2094 return 0;
2095 break;
2096 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2097 if (dig->linkb)
2098 return 3;
2099 else
2100 return 2;
2101 break;
2102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2103 if (dig->linkb)
2104 return 5;
2105 else
2106 return 4;
2107 break;
2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2109 return 6;
2110 break;
2111 default:
2112 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2113 return 0;
2114 }
2115}
2116
2117/**
2118 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2119 *
2120 * @crtc: drm crtc
2121 *
2122 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2123 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2124 * monitors a dedicated PPLL must be used. If a particular board has
2125 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2126 * as there is no need to program the PLL itself. If we are not able to
2127 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2128 * avoid messing up an existing monitor.
2129 *
2130 * Asic specific PLL information
2131 *
2132 * DCE 8.x
2133 * KB/KV
2134 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2135 * CI
2136 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2137 *
2138 */
2139static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2140{
2141 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2142 struct drm_device *dev = crtc->dev;
2143 struct amdgpu_device *adev = drm_to_adev(dev);
2144 u32 pll_in_use;
2145 int pll;
2146
2147 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2148 if (adev->clock.dp_extclk)
2149 /* skip PPLL programming if using ext clock */
2150 return ATOM_PPLL_INVALID;
2151 else {
2152 /* use the same PPLL for all DP monitors */
2153 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2154 if (pll != ATOM_PPLL_INVALID)
2155 return pll;
2156 }
2157 } else {
2158 /* use the same PPLL for all monitors with the same clock */
2159 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2160 if (pll != ATOM_PPLL_INVALID)
2161 return pll;
2162 }
2163 /* otherwise, pick one of the plls */
2164 if ((adev->asic_type == CHIP_KABINI) ||
2165 (adev->asic_type == CHIP_MULLINS)) {
2166 /* KB/ML has PPLL1 and PPLL2 */
2167 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2168 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2169 return ATOM_PPLL2;
2170 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2171 return ATOM_PPLL1;
2172 DRM_ERROR("unable to allocate a PPLL\n");
2173 return ATOM_PPLL_INVALID;
2174 } else {
2175 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2176 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2177 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2178 return ATOM_PPLL2;
2179 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2180 return ATOM_PPLL1;
2181 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2182 return ATOM_PPLL0;
2183 DRM_ERROR("unable to allocate a PPLL\n");
2184 return ATOM_PPLL_INVALID;
2185 }
2186 return ATOM_PPLL_INVALID;
2187}
2188
2189static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2190{
2191 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2192 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2193 uint32_t cur_lock;
2194
2195 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2196 if (lock)
2197 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2198 else
2199 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2200 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2201}
2202
2203static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2204{
2205 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2206 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2207
2208 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2209 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2210 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2211}
2212
2213static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2214{
2215 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2216 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2217
2218 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2219 upper_32_bits(amdgpu_crtc->cursor_addr));
2220 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2221 lower_32_bits(amdgpu_crtc->cursor_addr));
2222
2223 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2224 CUR_CONTROL__CURSOR_EN_MASK |
2225 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2226 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2227}
2228
2229static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2230 int x, int y)
2231{
2232 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2233 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2234 int xorigin = 0, yorigin = 0;
2235
2236 amdgpu_crtc->cursor_x = x;
2237 amdgpu_crtc->cursor_y = y;
2238
2239 /* avivo cursor are offset into the total surface */
2240 x += crtc->x;
2241 y += crtc->y;
2242 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2243
2244 if (x < 0) {
2245 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2246 x = 0;
2247 }
2248 if (y < 0) {
2249 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2250 y = 0;
2251 }
2252
2253 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2254 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2255 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2256 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2257
2258 return 0;
2259}
2260
2261static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2262 int x, int y)
2263{
2264 int ret;
2265
2266 dce_v8_0_lock_cursor(crtc, true);
2267 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2268 dce_v8_0_lock_cursor(crtc, false);
2269
2270 return ret;
2271}
2272
2273static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2274 struct drm_file *file_priv,
2275 uint32_t handle,
2276 uint32_t width,
2277 uint32_t height,
2278 int32_t hot_x,
2279 int32_t hot_y)
2280{
2281 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2282 struct drm_gem_object *obj;
2283 struct amdgpu_bo *aobj;
2284 int ret;
2285
2286 if (!handle) {
2287 /* turn off cursor */
2288 dce_v8_0_hide_cursor(crtc);
2289 obj = NULL;
2290 goto unpin;
2291 }
2292
2293 if ((width > amdgpu_crtc->max_cursor_width) ||
2294 (height > amdgpu_crtc->max_cursor_height)) {
2295 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2296 return -EINVAL;
2297 }
2298
2299 obj = drm_gem_object_lookup(file_priv, handle);
2300 if (!obj) {
2301 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2302 return -ENOENT;
2303 }
2304
2305 aobj = gem_to_amdgpu_bo(obj);
2306 ret = amdgpu_bo_reserve(aobj, false);
2307 if (ret != 0) {
2308 drm_gem_object_put(obj);
2309 return ret;
2310 }
2311
2312 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2313 amdgpu_bo_unreserve(aobj);
2314 if (ret) {
2315 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2316 drm_gem_object_put(obj);
2317 return ret;
2318 }
2319 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2320
2321 dce_v8_0_lock_cursor(crtc, true);
2322
2323 if (width != amdgpu_crtc->cursor_width ||
2324 height != amdgpu_crtc->cursor_height ||
2325 hot_x != amdgpu_crtc->cursor_hot_x ||
2326 hot_y != amdgpu_crtc->cursor_hot_y) {
2327 int x, y;
2328
2329 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2330 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2331
2332 dce_v8_0_cursor_move_locked(crtc, x, y);
2333
2334 amdgpu_crtc->cursor_width = width;
2335 amdgpu_crtc->cursor_height = height;
2336 amdgpu_crtc->cursor_hot_x = hot_x;
2337 amdgpu_crtc->cursor_hot_y = hot_y;
2338 }
2339
2340 dce_v8_0_show_cursor(crtc);
2341 dce_v8_0_lock_cursor(crtc, false);
2342
2343unpin:
2344 if (amdgpu_crtc->cursor_bo) {
2345 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2346 ret = amdgpu_bo_reserve(aobj, true);
2347 if (likely(ret == 0)) {
2348 amdgpu_bo_unpin(aobj);
2349 amdgpu_bo_unreserve(aobj);
2350 }
2351 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2352 }
2353
2354 amdgpu_crtc->cursor_bo = obj;
2355 return 0;
2356}
2357
2358static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2359{
2360 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2361
2362 if (amdgpu_crtc->cursor_bo) {
2363 dce_v8_0_lock_cursor(crtc, true);
2364
2365 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2366 amdgpu_crtc->cursor_y);
2367
2368 dce_v8_0_show_cursor(crtc);
2369
2370 dce_v8_0_lock_cursor(crtc, false);
2371 }
2372}
2373
2374static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2375 u16 *blue, uint32_t size,
2376 struct drm_modeset_acquire_ctx *ctx)
2377{
2378 dce_v8_0_crtc_load_lut(crtc);
2379
2380 return 0;
2381}
2382
2383static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2384{
2385 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2386
2387 drm_crtc_cleanup(crtc);
2388 kfree(amdgpu_crtc);
2389}
2390
2391static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2392 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2393 .cursor_move = dce_v8_0_crtc_cursor_move,
2394 .gamma_set = dce_v8_0_crtc_gamma_set,
2395 .set_config = amdgpu_display_crtc_set_config,
2396 .destroy = dce_v8_0_crtc_destroy,
2397 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2398 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2399 .enable_vblank = amdgpu_enable_vblank_kms,
2400 .disable_vblank = amdgpu_disable_vblank_kms,
2401 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2402};
2403
2404static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct amdgpu_device *adev = drm_to_adev(dev);
2408 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2409 unsigned type;
2410
2411 switch (mode) {
2412 case DRM_MODE_DPMS_ON:
2413 amdgpu_crtc->enabled = true;
2414 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2415 dce_v8_0_vga_enable(crtc, true);
2416 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2417 dce_v8_0_vga_enable(crtc, false);
2418 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2419 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2420 amdgpu_crtc->crtc_id);
2421 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2422 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2423 drm_crtc_vblank_on(crtc);
2424 dce_v8_0_crtc_load_lut(crtc);
2425 break;
2426 case DRM_MODE_DPMS_STANDBY:
2427 case DRM_MODE_DPMS_SUSPEND:
2428 case DRM_MODE_DPMS_OFF:
2429 drm_crtc_vblank_off(crtc);
2430 if (amdgpu_crtc->enabled) {
2431 dce_v8_0_vga_enable(crtc, true);
2432 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2433 dce_v8_0_vga_enable(crtc, false);
2434 }
2435 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2436 amdgpu_crtc->enabled = false;
2437 break;
2438 }
2439 /* adjust pm to dpms */
2440 amdgpu_pm_compute_clocks(adev);
2441}
2442
2443static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2444{
2445 /* disable crtc pair power gating before programming */
2446 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2447 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2448 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2449}
2450
2451static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2452{
2453 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2454 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2455}
2456
2457static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2458{
2459 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2460 struct drm_device *dev = crtc->dev;
2461 struct amdgpu_device *adev = drm_to_adev(dev);
2462 struct amdgpu_atom_ss ss;
2463 int i;
2464
2465 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2466 if (crtc->primary->fb) {
2467 int r;
2468 struct amdgpu_bo *abo;
2469
2470 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2471 r = amdgpu_bo_reserve(abo, true);
2472 if (unlikely(r))
2473 DRM_ERROR("failed to reserve abo before unpin\n");
2474 else {
2475 amdgpu_bo_unpin(abo);
2476 amdgpu_bo_unreserve(abo);
2477 }
2478 }
2479 /* disable the GRPH */
2480 dce_v8_0_grph_enable(crtc, false);
2481
2482 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2483
2484 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2485 if (adev->mode_info.crtcs[i] &&
2486 adev->mode_info.crtcs[i]->enabled &&
2487 i != amdgpu_crtc->crtc_id &&
2488 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2489 /* one other crtc is using this pll don't turn
2490 * off the pll
2491 */
2492 goto done;
2493 }
2494 }
2495
2496 switch (amdgpu_crtc->pll_id) {
2497 case ATOM_PPLL1:
2498 case ATOM_PPLL2:
2499 /* disable the ppll */
2500 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2501 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2502 break;
2503 case ATOM_PPLL0:
2504 /* disable the ppll */
2505 if ((adev->asic_type == CHIP_KAVERI) ||
2506 (adev->asic_type == CHIP_BONAIRE) ||
2507 (adev->asic_type == CHIP_HAWAII))
2508 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2509 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2510 break;
2511 default:
2512 break;
2513 }
2514done:
2515 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2516 amdgpu_crtc->adjusted_clock = 0;
2517 amdgpu_crtc->encoder = NULL;
2518 amdgpu_crtc->connector = NULL;
2519}
2520
2521static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2522 struct drm_display_mode *mode,
2523 struct drm_display_mode *adjusted_mode,
2524 int x, int y, struct drm_framebuffer *old_fb)
2525{
2526 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2527
2528 if (!amdgpu_crtc->adjusted_clock)
2529 return -EINVAL;
2530
2531 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2532 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2533 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2534 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2535 amdgpu_atombios_crtc_scaler_setup(crtc);
2536 dce_v8_0_cursor_reset(crtc);
2537 /* update the hw version fpr dpm */
2538 amdgpu_crtc->hw_mode = *adjusted_mode;
2539
2540 return 0;
2541}
2542
2543static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2544 const struct drm_display_mode *mode,
2545 struct drm_display_mode *adjusted_mode)
2546{
2547 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2548 struct drm_device *dev = crtc->dev;
2549 struct drm_encoder *encoder;
2550
2551 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2552 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2553 if (encoder->crtc == crtc) {
2554 amdgpu_crtc->encoder = encoder;
2555 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2556 break;
2557 }
2558 }
2559 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2560 amdgpu_crtc->encoder = NULL;
2561 amdgpu_crtc->connector = NULL;
2562 return false;
2563 }
2564 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2565 return false;
2566 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2567 return false;
2568 /* pick pll */
2569 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2570 /* if we can't get a PPLL for a non-DP encoder, fail */
2571 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2572 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2573 return false;
2574
2575 return true;
2576}
2577
2578static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2579 struct drm_framebuffer *old_fb)
2580{
2581 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2582}
2583
2584static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2585 struct drm_framebuffer *fb,
2586 int x, int y, enum mode_set_atomic state)
2587{
2588 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2589}
2590
2591static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2592 .dpms = dce_v8_0_crtc_dpms,
2593 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2594 .mode_set = dce_v8_0_crtc_mode_set,
2595 .mode_set_base = dce_v8_0_crtc_set_base,
2596 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2597 .prepare = dce_v8_0_crtc_prepare,
2598 .commit = dce_v8_0_crtc_commit,
2599 .disable = dce_v8_0_crtc_disable,
2600 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2601};
2602
2603static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2604{
2605 struct amdgpu_crtc *amdgpu_crtc;
2606
2607 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2608 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2609 if (amdgpu_crtc == NULL)
2610 return -ENOMEM;
2611
2612 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2613
2614 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2615 amdgpu_crtc->crtc_id = index;
2616 adev->mode_info.crtcs[index] = amdgpu_crtc;
2617
2618 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2619 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2620 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2621 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2622
2623 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2624
2625 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2626 amdgpu_crtc->adjusted_clock = 0;
2627 amdgpu_crtc->encoder = NULL;
2628 amdgpu_crtc->connector = NULL;
2629 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2630
2631 return 0;
2632}
2633
2634static int dce_v8_0_early_init(void *handle)
2635{
2636 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2637
2638 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2639 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2640
2641 dce_v8_0_set_display_funcs(adev);
2642
2643 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2644
2645 switch (adev->asic_type) {
2646 case CHIP_BONAIRE:
2647 case CHIP_HAWAII:
2648 adev->mode_info.num_hpd = 6;
2649 adev->mode_info.num_dig = 6;
2650 break;
2651 case CHIP_KAVERI:
2652 adev->mode_info.num_hpd = 6;
2653 adev->mode_info.num_dig = 7;
2654 break;
2655 case CHIP_KABINI:
2656 case CHIP_MULLINS:
2657 adev->mode_info.num_hpd = 6;
2658 adev->mode_info.num_dig = 6; /* ? */
2659 break;
2660 default:
2661 /* FIXME: not supported yet */
2662 return -EINVAL;
2663 }
2664
2665 dce_v8_0_set_irq_funcs(adev);
2666
2667 return 0;
2668}
2669
2670static int dce_v8_0_sw_init(void *handle)
2671{
2672 int r, i;
2673 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2674
2675 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2676 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2677 if (r)
2678 return r;
2679 }
2680
2681 for (i = 8; i < 20; i += 2) {
2682 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2683 if (r)
2684 return r;
2685 }
2686
2687 /* HPD hotplug */
2688 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2689 if (r)
2690 return r;
2691
2692 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2693
2694 adev_to_drm(adev)->mode_config.async_page_flip = true;
2695
2696 adev_to_drm(adev)->mode_config.max_width = 16384;
2697 adev_to_drm(adev)->mode_config.max_height = 16384;
2698
2699 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2700 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2701
2702 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
2703
2704 r = amdgpu_display_modeset_create_props(adev);
2705 if (r)
2706 return r;
2707
2708 adev_to_drm(adev)->mode_config.max_width = 16384;
2709 adev_to_drm(adev)->mode_config.max_height = 16384;
2710
2711 /* allocate crtcs */
2712 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2713 r = dce_v8_0_crtc_init(adev, i);
2714 if (r)
2715 return r;
2716 }
2717
2718 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2719 amdgpu_display_print_display_setup(adev_to_drm(adev));
2720 else
2721 return -EINVAL;
2722
2723 /* setup afmt */
2724 r = dce_v8_0_afmt_init(adev);
2725 if (r)
2726 return r;
2727
2728 r = dce_v8_0_audio_init(adev);
2729 if (r)
2730 return r;
2731
2732 drm_kms_helper_poll_init(adev_to_drm(adev));
2733
2734 adev->mode_info.mode_config_initialized = true;
2735 return 0;
2736}
2737
2738static int dce_v8_0_sw_fini(void *handle)
2739{
2740 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2741
2742 kfree(adev->mode_info.bios_hardcoded_edid);
2743
2744 drm_kms_helper_poll_fini(adev_to_drm(adev));
2745
2746 dce_v8_0_audio_fini(adev);
2747
2748 dce_v8_0_afmt_fini(adev);
2749
2750 drm_mode_config_cleanup(adev_to_drm(adev));
2751 adev->mode_info.mode_config_initialized = false;
2752
2753 return 0;
2754}
2755
2756static int dce_v8_0_hw_init(void *handle)
2757{
2758 int i;
2759 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2760
2761 /* disable vga render */
2762 dce_v8_0_set_vga_render_state(adev, false);
2763 /* init dig PHYs, disp eng pll */
2764 amdgpu_atombios_encoder_init_dig(adev);
2765 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2766
2767 /* initialize hpd */
2768 dce_v8_0_hpd_init(adev);
2769
2770 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2771 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2772 }
2773
2774 dce_v8_0_pageflip_interrupt_init(adev);
2775
2776 return 0;
2777}
2778
2779static int dce_v8_0_hw_fini(void *handle)
2780{
2781 int i;
2782 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2783
2784 dce_v8_0_hpd_fini(adev);
2785
2786 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2787 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2788 }
2789
2790 dce_v8_0_pageflip_interrupt_fini(adev);
2791
2792 return 0;
2793}
2794
2795static int dce_v8_0_suspend(void *handle)
2796{
2797 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2798 int r;
2799
2800 r = amdgpu_display_suspend_helper(adev);
2801 if (r)
2802 return r;
2803
2804 adev->mode_info.bl_level =
2805 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2806
2807 return dce_v8_0_hw_fini(handle);
2808}
2809
2810static int dce_v8_0_resume(void *handle)
2811{
2812 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2813 int ret;
2814
2815 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2816 adev->mode_info.bl_level);
2817
2818 ret = dce_v8_0_hw_init(handle);
2819
2820 /* turn on the BL */
2821 if (adev->mode_info.bl_encoder) {
2822 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2823 adev->mode_info.bl_encoder);
2824 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2825 bl_level);
2826 }
2827 if (ret)
2828 return ret;
2829
2830 return amdgpu_display_resume_helper(adev);
2831}
2832
2833static bool dce_v8_0_is_idle(void *handle)
2834{
2835 return true;
2836}
2837
2838static int dce_v8_0_wait_for_idle(void *handle)
2839{
2840 return 0;
2841}
2842
2843static int dce_v8_0_soft_reset(void *handle)
2844{
2845 u32 srbm_soft_reset = 0, tmp;
2846 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2847
2848 if (dce_v8_0_is_display_hung(adev))
2849 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2850
2851 if (srbm_soft_reset) {
2852 tmp = RREG32(mmSRBM_SOFT_RESET);
2853 tmp |= srbm_soft_reset;
2854 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2855 WREG32(mmSRBM_SOFT_RESET, tmp);
2856 tmp = RREG32(mmSRBM_SOFT_RESET);
2857
2858 udelay(50);
2859
2860 tmp &= ~srbm_soft_reset;
2861 WREG32(mmSRBM_SOFT_RESET, tmp);
2862 tmp = RREG32(mmSRBM_SOFT_RESET);
2863
2864 /* Wait a little for things to settle down */
2865 udelay(50);
2866 }
2867 return 0;
2868}
2869
2870static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2871 int crtc,
2872 enum amdgpu_interrupt_state state)
2873{
2874 u32 reg_block, lb_interrupt_mask;
2875
2876 if (crtc >= adev->mode_info.num_crtc) {
2877 DRM_DEBUG("invalid crtc %d\n", crtc);
2878 return;
2879 }
2880
2881 switch (crtc) {
2882 case 0:
2883 reg_block = CRTC0_REGISTER_OFFSET;
2884 break;
2885 case 1:
2886 reg_block = CRTC1_REGISTER_OFFSET;
2887 break;
2888 case 2:
2889 reg_block = CRTC2_REGISTER_OFFSET;
2890 break;
2891 case 3:
2892 reg_block = CRTC3_REGISTER_OFFSET;
2893 break;
2894 case 4:
2895 reg_block = CRTC4_REGISTER_OFFSET;
2896 break;
2897 case 5:
2898 reg_block = CRTC5_REGISTER_OFFSET;
2899 break;
2900 default:
2901 DRM_DEBUG("invalid crtc %d\n", crtc);
2902 return;
2903 }
2904
2905 switch (state) {
2906 case AMDGPU_IRQ_STATE_DISABLE:
2907 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2908 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2909 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2910 break;
2911 case AMDGPU_IRQ_STATE_ENABLE:
2912 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2913 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2914 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2915 break;
2916 default:
2917 break;
2918 }
2919}
2920
2921static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2922 int crtc,
2923 enum amdgpu_interrupt_state state)
2924{
2925 u32 reg_block, lb_interrupt_mask;
2926
2927 if (crtc >= adev->mode_info.num_crtc) {
2928 DRM_DEBUG("invalid crtc %d\n", crtc);
2929 return;
2930 }
2931
2932 switch (crtc) {
2933 case 0:
2934 reg_block = CRTC0_REGISTER_OFFSET;
2935 break;
2936 case 1:
2937 reg_block = CRTC1_REGISTER_OFFSET;
2938 break;
2939 case 2:
2940 reg_block = CRTC2_REGISTER_OFFSET;
2941 break;
2942 case 3:
2943 reg_block = CRTC3_REGISTER_OFFSET;
2944 break;
2945 case 4:
2946 reg_block = CRTC4_REGISTER_OFFSET;
2947 break;
2948 case 5:
2949 reg_block = CRTC5_REGISTER_OFFSET;
2950 break;
2951 default:
2952 DRM_DEBUG("invalid crtc %d\n", crtc);
2953 return;
2954 }
2955
2956 switch (state) {
2957 case AMDGPU_IRQ_STATE_DISABLE:
2958 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2959 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2960 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2961 break;
2962 case AMDGPU_IRQ_STATE_ENABLE:
2963 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2964 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2965 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2966 break;
2967 default:
2968 break;
2969 }
2970}
2971
2972static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2973 struct amdgpu_irq_src *src,
2974 unsigned type,
2975 enum amdgpu_interrupt_state state)
2976{
2977 u32 dc_hpd_int_cntl;
2978
2979 if (type >= adev->mode_info.num_hpd) {
2980 DRM_DEBUG("invalid hdp %d\n", type);
2981 return 0;
2982 }
2983
2984 switch (state) {
2985 case AMDGPU_IRQ_STATE_DISABLE:
2986 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2987 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2988 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2989 break;
2990 case AMDGPU_IRQ_STATE_ENABLE:
2991 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2992 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2993 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2994 break;
2995 default:
2996 break;
2997 }
2998
2999 return 0;
3000}
3001
3002static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3003 struct amdgpu_irq_src *src,
3004 unsigned type,
3005 enum amdgpu_interrupt_state state)
3006{
3007 switch (type) {
3008 case AMDGPU_CRTC_IRQ_VBLANK1:
3009 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3010 break;
3011 case AMDGPU_CRTC_IRQ_VBLANK2:
3012 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3013 break;
3014 case AMDGPU_CRTC_IRQ_VBLANK3:
3015 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3016 break;
3017 case AMDGPU_CRTC_IRQ_VBLANK4:
3018 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3019 break;
3020 case AMDGPU_CRTC_IRQ_VBLANK5:
3021 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3022 break;
3023 case AMDGPU_CRTC_IRQ_VBLANK6:
3024 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3025 break;
3026 case AMDGPU_CRTC_IRQ_VLINE1:
3027 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3028 break;
3029 case AMDGPU_CRTC_IRQ_VLINE2:
3030 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3031 break;
3032 case AMDGPU_CRTC_IRQ_VLINE3:
3033 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3034 break;
3035 case AMDGPU_CRTC_IRQ_VLINE4:
3036 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3037 break;
3038 case AMDGPU_CRTC_IRQ_VLINE5:
3039 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3040 break;
3041 case AMDGPU_CRTC_IRQ_VLINE6:
3042 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3043 break;
3044 default:
3045 break;
3046 }
3047 return 0;
3048}
3049
3050static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3051 struct amdgpu_irq_src *source,
3052 struct amdgpu_iv_entry *entry)
3053{
3054 unsigned crtc = entry->src_id - 1;
3055 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3056 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3057 crtc);
3058
3059 switch (entry->src_data[0]) {
3060 case 0: /* vblank */
3061 if (disp_int & interrupt_status_offsets[crtc].vblank)
3062 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3063 else
3064 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3065
3066 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3067 drm_handle_vblank(adev_to_drm(adev), crtc);
3068 }
3069 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3070 break;
3071 case 1: /* vline */
3072 if (disp_int & interrupt_status_offsets[crtc].vline)
3073 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3074 else
3075 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3076
3077 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3078 break;
3079 default:
3080 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3081 break;
3082 }
3083
3084 return 0;
3085}
3086
3087static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3088 struct amdgpu_irq_src *src,
3089 unsigned type,
3090 enum amdgpu_interrupt_state state)
3091{
3092 u32 reg;
3093
3094 if (type >= adev->mode_info.num_crtc) {
3095 DRM_ERROR("invalid pageflip crtc %d\n", type);
3096 return -EINVAL;
3097 }
3098
3099 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3100 if (state == AMDGPU_IRQ_STATE_DISABLE)
3101 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3102 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3103 else
3104 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3105 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3106
3107 return 0;
3108}
3109
3110static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3111 struct amdgpu_irq_src *source,
3112 struct amdgpu_iv_entry *entry)
3113{
3114 unsigned long flags;
3115 unsigned crtc_id;
3116 struct amdgpu_crtc *amdgpu_crtc;
3117 struct amdgpu_flip_work *works;
3118
3119 crtc_id = (entry->src_id - 8) >> 1;
3120 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3121
3122 if (crtc_id >= adev->mode_info.num_crtc) {
3123 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3124 return -EINVAL;
3125 }
3126
3127 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3128 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3129 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3130 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3131
3132 /* IRQ could occur when in initial stage */
3133 if (amdgpu_crtc == NULL)
3134 return 0;
3135
3136 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3137 works = amdgpu_crtc->pflip_works;
3138 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3139 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3140 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3141 amdgpu_crtc->pflip_status,
3142 AMDGPU_FLIP_SUBMITTED);
3143 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3144 return 0;
3145 }
3146
3147 /* page flip completed. clean up */
3148 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3149 amdgpu_crtc->pflip_works = NULL;
3150
3151 /* wakeup usersapce */
3152 if (works->event)
3153 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3154
3155 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3156
3157 drm_crtc_vblank_put(&amdgpu_crtc->base);
3158 schedule_work(&works->unpin_work);
3159
3160 return 0;
3161}
3162
3163static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3164 struct amdgpu_irq_src *source,
3165 struct amdgpu_iv_entry *entry)
3166{
3167 uint32_t disp_int, mask, tmp;
3168 unsigned hpd;
3169
3170 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3171 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3172 return 0;
3173 }
3174
3175 hpd = entry->src_data[0];
3176 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3177 mask = interrupt_status_offsets[hpd].hpd;
3178
3179 if (disp_int & mask) {
3180 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3181 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3182 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3183 schedule_work(&adev->hotplug_work);
3184 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3185 }
3186
3187 return 0;
3188
3189}
3190
3191static int dce_v8_0_set_clockgating_state(void *handle,
3192 enum amd_clockgating_state state)
3193{
3194 return 0;
3195}
3196
3197static int dce_v8_0_set_powergating_state(void *handle,
3198 enum amd_powergating_state state)
3199{
3200 return 0;
3201}
3202
3203static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3204 .name = "dce_v8_0",
3205 .early_init = dce_v8_0_early_init,
3206 .late_init = NULL,
3207 .sw_init = dce_v8_0_sw_init,
3208 .sw_fini = dce_v8_0_sw_fini,
3209 .hw_init = dce_v8_0_hw_init,
3210 .hw_fini = dce_v8_0_hw_fini,
3211 .suspend = dce_v8_0_suspend,
3212 .resume = dce_v8_0_resume,
3213 .is_idle = dce_v8_0_is_idle,
3214 .wait_for_idle = dce_v8_0_wait_for_idle,
3215 .soft_reset = dce_v8_0_soft_reset,
3216 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3217 .set_powergating_state = dce_v8_0_set_powergating_state,
3218};
3219
3220static void
3221dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3222 struct drm_display_mode *mode,
3223 struct drm_display_mode *adjusted_mode)
3224{
3225 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3226
3227 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3228
3229 /* need to call this here rather than in prepare() since we need some crtc info */
3230 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3231
3232 /* set scaler clears this on some chips */
3233 dce_v8_0_set_interleave(encoder->crtc, mode);
3234
3235 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3236 dce_v8_0_afmt_enable(encoder, true);
3237 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3238 }
3239}
3240
3241static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3242{
3243 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3244 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3245 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3246
3247 if ((amdgpu_encoder->active_device &
3248 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3249 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3250 ENCODER_OBJECT_ID_NONE)) {
3251 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3252 if (dig) {
3253 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3254 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3255 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3256 }
3257 }
3258
3259 amdgpu_atombios_scratch_regs_lock(adev, true);
3260
3261 if (connector) {
3262 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3263
3264 /* select the clock/data port if it uses a router */
3265 if (amdgpu_connector->router.cd_valid)
3266 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3267
3268 /* turn eDP panel on for mode set */
3269 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3270 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3271 ATOM_TRANSMITTER_ACTION_POWER_ON);
3272 }
3273
3274 /* this is needed for the pll/ss setup to work correctly in some cases */
3275 amdgpu_atombios_encoder_set_crtc_source(encoder);
3276 /* set up the FMT blocks */
3277 dce_v8_0_program_fmt(encoder);
3278}
3279
3280static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3281{
3282 struct drm_device *dev = encoder->dev;
3283 struct amdgpu_device *adev = drm_to_adev(dev);
3284
3285 /* need to call this here as we need the crtc set up */
3286 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3287 amdgpu_atombios_scratch_regs_lock(adev, false);
3288}
3289
3290static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3291{
3292 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3293 struct amdgpu_encoder_atom_dig *dig;
3294
3295 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3296
3297 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3298 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3299 dce_v8_0_afmt_enable(encoder, false);
3300 dig = amdgpu_encoder->enc_priv;
3301 dig->dig_encoder = -1;
3302 }
3303 amdgpu_encoder->active_device = 0;
3304}
3305
3306/* these are handled by the primary encoders */
3307static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3308{
3309
3310}
3311
3312static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3313{
3314
3315}
3316
3317static void
3318dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3319 struct drm_display_mode *mode,
3320 struct drm_display_mode *adjusted_mode)
3321{
3322
3323}
3324
3325static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3326{
3327
3328}
3329
3330static void
3331dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3332{
3333
3334}
3335
3336static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3337 .dpms = dce_v8_0_ext_dpms,
3338 .prepare = dce_v8_0_ext_prepare,
3339 .mode_set = dce_v8_0_ext_mode_set,
3340 .commit = dce_v8_0_ext_commit,
3341 .disable = dce_v8_0_ext_disable,
3342 /* no detect for TMDS/LVDS yet */
3343};
3344
3345static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3346 .dpms = amdgpu_atombios_encoder_dpms,
3347 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3348 .prepare = dce_v8_0_encoder_prepare,
3349 .mode_set = dce_v8_0_encoder_mode_set,
3350 .commit = dce_v8_0_encoder_commit,
3351 .disable = dce_v8_0_encoder_disable,
3352 .detect = amdgpu_atombios_encoder_dig_detect,
3353};
3354
3355static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3356 .dpms = amdgpu_atombios_encoder_dpms,
3357 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3358 .prepare = dce_v8_0_encoder_prepare,
3359 .mode_set = dce_v8_0_encoder_mode_set,
3360 .commit = dce_v8_0_encoder_commit,
3361 .detect = amdgpu_atombios_encoder_dac_detect,
3362};
3363
3364static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3365{
3366 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3367 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3368 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3369 kfree(amdgpu_encoder->enc_priv);
3370 drm_encoder_cleanup(encoder);
3371 kfree(amdgpu_encoder);
3372}
3373
3374static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3375 .destroy = dce_v8_0_encoder_destroy,
3376};
3377
3378static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3379 uint32_t encoder_enum,
3380 uint32_t supported_device,
3381 u16 caps)
3382{
3383 struct drm_device *dev = adev_to_drm(adev);
3384 struct drm_encoder *encoder;
3385 struct amdgpu_encoder *amdgpu_encoder;
3386
3387 /* see if we already added it */
3388 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3389 amdgpu_encoder = to_amdgpu_encoder(encoder);
3390 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3391 amdgpu_encoder->devices |= supported_device;
3392 return;
3393 }
3394
3395 }
3396
3397 /* add a new one */
3398 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3399 if (!amdgpu_encoder)
3400 return;
3401
3402 encoder = &amdgpu_encoder->base;
3403 switch (adev->mode_info.num_crtc) {
3404 case 1:
3405 encoder->possible_crtcs = 0x1;
3406 break;
3407 case 2:
3408 default:
3409 encoder->possible_crtcs = 0x3;
3410 break;
3411 case 4:
3412 encoder->possible_crtcs = 0xf;
3413 break;
3414 case 6:
3415 encoder->possible_crtcs = 0x3f;
3416 break;
3417 }
3418
3419 amdgpu_encoder->enc_priv = NULL;
3420
3421 amdgpu_encoder->encoder_enum = encoder_enum;
3422 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3423 amdgpu_encoder->devices = supported_device;
3424 amdgpu_encoder->rmx_type = RMX_OFF;
3425 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3426 amdgpu_encoder->is_ext_encoder = false;
3427 amdgpu_encoder->caps = caps;
3428
3429 switch (amdgpu_encoder->encoder_id) {
3430 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3431 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3432 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3433 DRM_MODE_ENCODER_DAC, NULL);
3434 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3435 break;
3436 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3437 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3438 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3439 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3440 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3441 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3442 amdgpu_encoder->rmx_type = RMX_FULL;
3443 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3444 DRM_MODE_ENCODER_LVDS, NULL);
3445 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3446 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3447 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3448 DRM_MODE_ENCODER_DAC, NULL);
3449 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3450 } else {
3451 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3452 DRM_MODE_ENCODER_TMDS, NULL);
3453 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3454 }
3455 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3456 break;
3457 case ENCODER_OBJECT_ID_SI170B:
3458 case ENCODER_OBJECT_ID_CH7303:
3459 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3460 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3461 case ENCODER_OBJECT_ID_TITFP513:
3462 case ENCODER_OBJECT_ID_VT1623:
3463 case ENCODER_OBJECT_ID_HDMI_SI1930:
3464 case ENCODER_OBJECT_ID_TRAVIS:
3465 case ENCODER_OBJECT_ID_NUTMEG:
3466 /* these are handled by the primary encoders */
3467 amdgpu_encoder->is_ext_encoder = true;
3468 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3469 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3470 DRM_MODE_ENCODER_LVDS, NULL);
3471 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3472 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3473 DRM_MODE_ENCODER_DAC, NULL);
3474 else
3475 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3476 DRM_MODE_ENCODER_TMDS, NULL);
3477 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3478 break;
3479 }
3480}
3481
3482static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3483 .bandwidth_update = &dce_v8_0_bandwidth_update,
3484 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3485 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3486 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3487 .hpd_sense = &dce_v8_0_hpd_sense,
3488 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3489 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3490 .page_flip = &dce_v8_0_page_flip,
3491 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3492 .add_encoder = &dce_v8_0_encoder_add,
3493 .add_connector = &amdgpu_connector_add,
3494};
3495
3496static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3497{
3498 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3499}
3500
3501static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3502 .set = dce_v8_0_set_crtc_interrupt_state,
3503 .process = dce_v8_0_crtc_irq,
3504};
3505
3506static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3507 .set = dce_v8_0_set_pageflip_interrupt_state,
3508 .process = dce_v8_0_pageflip_irq,
3509};
3510
3511static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3512 .set = dce_v8_0_set_hpd_interrupt_state,
3513 .process = dce_v8_0_hpd_irq,
3514};
3515
3516static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3517{
3518 if (adev->mode_info.num_crtc > 0)
3519 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3520 else
3521 adev->crtc_irq.num_types = 0;
3522 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3523
3524 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3525 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3526
3527 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3528 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3529}
3530
3531const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3532{
3533 .type = AMD_IP_BLOCK_TYPE_DCE,
3534 .major = 8,
3535 .minor = 0,
3536 .rev = 0,
3537 .funcs = &dce_v8_0_ip_funcs,
3538};
3539
3540const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3541{
3542 .type = AMD_IP_BLOCK_TYPE_DCE,
3543 .major = 8,
3544 .minor = 1,
3545 .rev = 0,
3546 .funcs = &dce_v8_0_ip_funcs,
3547};
3548
3549const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3550{
3551 .type = AMD_IP_BLOCK_TYPE_DCE,
3552 .major = 8,
3553 .minor = 2,
3554 .rev = 0,
3555 .funcs = &dce_v8_0_ip_funcs,
3556};
3557
3558const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3559{
3560 .type = AMD_IP_BLOCK_TYPE_DCE,
3561 .major = 8,
3562 .minor = 3,
3563 .rev = 0,
3564 .funcs = &dce_v8_0_ip_funcs,
3565};
3566
3567const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3568{
3569 .type = AMD_IP_BLOCK_TYPE_DCE,
3570 .major = 8,
3571 .minor = 5,
3572 .rev = 0,
3573 .funcs = &dce_v8_0_ip_funcs,
3574};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "cikd.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34#include "dce_v8_0.h"
35
36#include "dce/dce_8_0_d.h"
37#include "dce/dce_8_0_sh_mask.h"
38
39#include "gca/gfx_7_2_enum.h"
40
41#include "gmc/gmc_7_1_d.h"
42#include "gmc/gmc_7_1_sh_mask.h"
43
44#include "oss/oss_2_0_d.h"
45#include "oss/oss_2_0_sh_mask.h"
46
47static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
48static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
49
50static const u32 crtc_offsets[6] =
51{
52 CRTC0_REGISTER_OFFSET,
53 CRTC1_REGISTER_OFFSET,
54 CRTC2_REGISTER_OFFSET,
55 CRTC3_REGISTER_OFFSET,
56 CRTC4_REGISTER_OFFSET,
57 CRTC5_REGISTER_OFFSET
58};
59
60static const u32 hpd_offsets[] =
61{
62 HPD0_REGISTER_OFFSET,
63 HPD1_REGISTER_OFFSET,
64 HPD2_REGISTER_OFFSET,
65 HPD3_REGISTER_OFFSET,
66 HPD4_REGISTER_OFFSET,
67 HPD5_REGISTER_OFFSET
68};
69
70static const uint32_t dig_offsets[] = {
71 CRTC0_REGISTER_OFFSET,
72 CRTC1_REGISTER_OFFSET,
73 CRTC2_REGISTER_OFFSET,
74 CRTC3_REGISTER_OFFSET,
75 CRTC4_REGISTER_OFFSET,
76 CRTC5_REGISTER_OFFSET,
77 (0x13830 - 0x7030) >> 2,
78};
79
80static const struct {
81 uint32_t reg;
82 uint32_t vblank;
83 uint32_t vline;
84 uint32_t hpd;
85
86} interrupt_status_offsets[6] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91}, {
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
116} };
117
118static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
119 u32 block_offset, u32 reg)
120{
121 unsigned long flags;
122 u32 r;
123
124 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
125 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
126 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
127 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
128
129 return r;
130}
131
132static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
133 u32 block_offset, u32 reg, u32 v)
134{
135 unsigned long flags;
136
137 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
138 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
139 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
140 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
141}
142
143static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
144{
145 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
146 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
147 return true;
148 else
149 return false;
150}
151
152static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
153{
154 u32 pos1, pos2;
155
156 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
157 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
158
159 if (pos1 != pos2)
160 return true;
161 else
162 return false;
163}
164
165/**
166 * dce_v8_0_vblank_wait - vblank wait asic callback.
167 *
168 * @adev: amdgpu_device pointer
169 * @crtc: crtc to wait for vblank on
170 *
171 * Wait for vblank on the requested crtc (evergreen+).
172 */
173static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
174{
175 unsigned i = 100;
176
177 if (crtc >= adev->mode_info.num_crtc)
178 return;
179
180 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
181 return;
182
183 /* depending on when we hit vblank, we may be close to active; if so,
184 * wait for another frame.
185 */
186 while (dce_v8_0_is_in_vblank(adev, crtc)) {
187 if (i++ == 100) {
188 i = 0;
189 if (!dce_v8_0_is_counter_moving(adev, crtc))
190 break;
191 }
192 }
193
194 while (!dce_v8_0_is_in_vblank(adev, crtc)) {
195 if (i++ == 100) {
196 i = 0;
197 if (!dce_v8_0_is_counter_moving(adev, crtc))
198 break;
199 }
200 }
201}
202
203static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
204{
205 if (crtc >= adev->mode_info.num_crtc)
206 return 0;
207 else
208 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
209}
210
211static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
212{
213 unsigned i;
214
215 /* Enable pflip interrupts */
216 for (i = 0; i < adev->mode_info.num_crtc; i++)
217 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
218}
219
220static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
221{
222 unsigned i;
223
224 /* Disable pflip interrupts */
225 for (i = 0; i < adev->mode_info.num_crtc; i++)
226 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
227}
228
229/**
230 * dce_v8_0_page_flip - pageflip callback.
231 *
232 * @adev: amdgpu_device pointer
233 * @crtc_id: crtc to cleanup pageflip on
234 * @crtc_base: new address of the crtc (GPU MC address)
235 *
236 * Triggers the actual pageflip by updating the primary
237 * surface base address.
238 */
239static void dce_v8_0_page_flip(struct amdgpu_device *adev,
240 int crtc_id, u64 crtc_base, bool async)
241{
242 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
243
244 /* flip at hsync for async, default is vsync */
245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
246 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
247 /* update the primary scanout addresses */
248 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
249 upper_32_bits(crtc_base));
250 /* writing to the low address triggers the update */
251 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
252 lower_32_bits(crtc_base));
253 /* post the write */
254 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
255}
256
257static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
258 u32 *vbl, u32 *position)
259{
260 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
261 return -EINVAL;
262
263 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
264 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
265
266 return 0;
267}
268
269/**
270 * dce_v8_0_hpd_sense - hpd sense callback.
271 *
272 * @adev: amdgpu_device pointer
273 * @hpd: hpd (hotplug detect) pin
274 *
275 * Checks if a digital monitor is connected (evergreen+).
276 * Returns true if connected, false if not connected.
277 */
278static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
279 enum amdgpu_hpd_id hpd)
280{
281 bool connected = false;
282
283 if (hpd >= adev->mode_info.num_hpd)
284 return connected;
285
286 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
287 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
288 connected = true;
289
290 return connected;
291}
292
293/**
294 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
295 *
296 * @adev: amdgpu_device pointer
297 * @hpd: hpd (hotplug detect) pin
298 *
299 * Set the polarity of the hpd pin (evergreen+).
300 */
301static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
302 enum amdgpu_hpd_id hpd)
303{
304 u32 tmp;
305 bool connected = dce_v8_0_hpd_sense(adev, hpd);
306
307 if (hpd >= adev->mode_info.num_hpd)
308 return;
309
310 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
311 if (connected)
312 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
313 else
314 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
315 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
316}
317
318/**
319 * dce_v8_0_hpd_init - hpd setup callback.
320 *
321 * @adev: amdgpu_device pointer
322 *
323 * Setup the hpd pins used by the card (evergreen+).
324 * Enable the pin, set the polarity, and enable the hpd interrupts.
325 */
326static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
327{
328 struct drm_device *dev = adev->ddev;
329 struct drm_connector *connector;
330 u32 tmp;
331
332 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
334
335 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
336 continue;
337
338 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
339 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
340 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
341
342 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
343 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
344 /* don't try to enable hpd on eDP or LVDS avoid breaking the
345 * aux dp channel on imac and help (but not completely fix)
346 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
347 * also avoid interrupt storms during dpms.
348 */
349 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
350 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
351 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
352 continue;
353 }
354
355 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
356 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
357 }
358}
359
360/**
361 * dce_v8_0_hpd_fini - hpd tear down callback.
362 *
363 * @adev: amdgpu_device pointer
364 *
365 * Tear down the hpd pins used by the card (evergreen+).
366 * Disable the hpd interrupts.
367 */
368static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
369{
370 struct drm_device *dev = adev->ddev;
371 struct drm_connector *connector;
372 u32 tmp;
373
374 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
375 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
376
377 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
378 continue;
379
380 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
381 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
382 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
383
384 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
385 }
386}
387
388static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
389{
390 return mmDC_GPIO_HPD_A;
391}
392
393static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
394{
395 u32 crtc_hung = 0;
396 u32 crtc_status[6];
397 u32 i, j, tmp;
398
399 for (i = 0; i < adev->mode_info.num_crtc; i++) {
400 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
401 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
402 crtc_hung |= (1 << i);
403 }
404 }
405
406 for (j = 0; j < 10; j++) {
407 for (i = 0; i < adev->mode_info.num_crtc; i++) {
408 if (crtc_hung & (1 << i)) {
409 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
410 if (tmp != crtc_status[i])
411 crtc_hung &= ~(1 << i);
412 }
413 }
414 if (crtc_hung == 0)
415 return false;
416 udelay(100);
417 }
418
419 return true;
420}
421
422static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
423 struct amdgpu_mode_mc_save *save)
424{
425 u32 crtc_enabled, tmp;
426 int i;
427
428 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
429 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
430
431 /* disable VGA render */
432 tmp = RREG32(mmVGA_RENDER_CONTROL);
433 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
434 WREG32(mmVGA_RENDER_CONTROL, tmp);
435
436 /* blank the display controllers */
437 for (i = 0; i < adev->mode_info.num_crtc; i++) {
438 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
439 CRTC_CONTROL, CRTC_MASTER_EN);
440 if (crtc_enabled) {
441#if 1
442 save->crtc_enabled[i] = true;
443 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
444 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
445 /*it is correct only for RGB ; black is 0*/
446 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
447 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
448 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
449 }
450 mdelay(20);
451#else
452 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
453 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
454 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
455 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
456 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
457 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
458 save->crtc_enabled[i] = false;
459 /* ***** */
460#endif
461 } else {
462 save->crtc_enabled[i] = false;
463 }
464 }
465}
466
467static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
468 struct amdgpu_mode_mc_save *save)
469{
470 u32 tmp;
471 int i;
472
473 /* update crtc base addresses */
474 for (i = 0; i < adev->mode_info.num_crtc; i++) {
475 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
476 upper_32_bits(adev->mc.vram_start));
477 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
478 (u32)adev->mc.vram_start);
479
480 if (save->crtc_enabled[i]) {
481 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
482 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
483 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
484 }
485 mdelay(20);
486 }
487
488 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
489 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
490
491 /* Unlock vga access */
492 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
493 mdelay(1);
494 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
495}
496
497static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
498 bool render)
499{
500 u32 tmp;
501
502 /* Lockout access through VGA aperture*/
503 tmp = RREG32(mmVGA_HDP_CONTROL);
504 if (render)
505 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
506 else
507 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
508 WREG32(mmVGA_HDP_CONTROL, tmp);
509
510 /* disable VGA render */
511 tmp = RREG32(mmVGA_RENDER_CONTROL);
512 if (render)
513 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
514 else
515 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
516 WREG32(mmVGA_RENDER_CONTROL, tmp);
517}
518
519static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
520{
521 int num_crtc = 0;
522
523 switch (adev->asic_type) {
524 case CHIP_BONAIRE:
525 case CHIP_HAWAII:
526 num_crtc = 6;
527 break;
528 case CHIP_KAVERI:
529 num_crtc = 4;
530 break;
531 case CHIP_KABINI:
532 case CHIP_MULLINS:
533 num_crtc = 2;
534 break;
535 default:
536 num_crtc = 0;
537 }
538 return num_crtc;
539}
540
541void dce_v8_0_disable_dce(struct amdgpu_device *adev)
542{
543 /*Disable VGA render and enabled crtc, if has DCE engine*/
544 if (amdgpu_atombios_has_dce_engine_info(adev)) {
545 u32 tmp;
546 int crtc_enabled, i;
547
548 dce_v8_0_set_vga_render_state(adev, false);
549
550 /*Disable crtc*/
551 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
552 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
553 CRTC_CONTROL, CRTC_MASTER_EN);
554 if (crtc_enabled) {
555 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
556 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
557 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
558 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
559 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
560 }
561 }
562 }
563}
564
565static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
566{
567 struct drm_device *dev = encoder->dev;
568 struct amdgpu_device *adev = dev->dev_private;
569 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
570 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
571 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
572 int bpc = 0;
573 u32 tmp = 0;
574 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
575
576 if (connector) {
577 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
578 bpc = amdgpu_connector_get_monitor_bpc(connector);
579 dither = amdgpu_connector->dither;
580 }
581
582 /* LVDS/eDP FMT is set up by atom */
583 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
584 return;
585
586 /* not needed for analog */
587 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
588 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
589 return;
590
591 if (bpc == 0)
592 return;
593
594 switch (bpc) {
595 case 6:
596 if (dither == AMDGPU_FMT_DITHER_ENABLE)
597 /* XXX sort out optimal dither settings */
598 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
599 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
600 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
601 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
602 else
603 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
604 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
605 break;
606 case 8:
607 if (dither == AMDGPU_FMT_DITHER_ENABLE)
608 /* XXX sort out optimal dither settings */
609 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
610 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
611 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
612 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
613 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
614 else
615 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
616 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
617 break;
618 case 10:
619 if (dither == AMDGPU_FMT_DITHER_ENABLE)
620 /* XXX sort out optimal dither settings */
621 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
622 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
623 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
624 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
625 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
626 else
627 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
628 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
629 break;
630 default:
631 /* not needed */
632 break;
633 }
634
635 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
636}
637
638
639/* display watermark setup */
640/**
641 * dce_v8_0_line_buffer_adjust - Set up the line buffer
642 *
643 * @adev: amdgpu_device pointer
644 * @amdgpu_crtc: the selected display controller
645 * @mode: the current display mode on the selected display
646 * controller
647 *
648 * Setup up the line buffer allocation for
649 * the selected display controller (CIK).
650 * Returns the line buffer size in pixels.
651 */
652static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
653 struct amdgpu_crtc *amdgpu_crtc,
654 struct drm_display_mode *mode)
655{
656 u32 tmp, buffer_alloc, i;
657 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
658 /*
659 * Line Buffer Setup
660 * There are 6 line buffers, one for each display controllers.
661 * There are 3 partitions per LB. Select the number of partitions
662 * to enable based on the display width. For display widths larger
663 * than 4096, you need use to use 2 display controllers and combine
664 * them using the stereo blender.
665 */
666 if (amdgpu_crtc->base.enabled && mode) {
667 if (mode->crtc_hdisplay < 1920) {
668 tmp = 1;
669 buffer_alloc = 2;
670 } else if (mode->crtc_hdisplay < 2560) {
671 tmp = 2;
672 buffer_alloc = 2;
673 } else if (mode->crtc_hdisplay < 4096) {
674 tmp = 0;
675 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
676 } else {
677 DRM_DEBUG_KMS("Mode too big for LB!\n");
678 tmp = 0;
679 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
680 }
681 } else {
682 tmp = 1;
683 buffer_alloc = 0;
684 }
685
686 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
687 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
688 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
689
690 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
691 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
692 for (i = 0; i < adev->usec_timeout; i++) {
693 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
694 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
695 break;
696 udelay(1);
697 }
698
699 if (amdgpu_crtc->base.enabled && mode) {
700 switch (tmp) {
701 case 0:
702 default:
703 return 4096 * 2;
704 case 1:
705 return 1920 * 2;
706 case 2:
707 return 2560 * 2;
708 }
709 }
710
711 /* controller not enabled, so no lb used */
712 return 0;
713}
714
715/**
716 * cik_get_number_of_dram_channels - get the number of dram channels
717 *
718 * @adev: amdgpu_device pointer
719 *
720 * Look up the number of video ram channels (CIK).
721 * Used for display watermark bandwidth calculations
722 * Returns the number of dram channels
723 */
724static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
725{
726 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
727
728 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
729 case 0:
730 default:
731 return 1;
732 case 1:
733 return 2;
734 case 2:
735 return 4;
736 case 3:
737 return 8;
738 case 4:
739 return 3;
740 case 5:
741 return 6;
742 case 6:
743 return 10;
744 case 7:
745 return 12;
746 case 8:
747 return 16;
748 }
749}
750
751struct dce8_wm_params {
752 u32 dram_channels; /* number of dram channels */
753 u32 yclk; /* bandwidth per dram data pin in kHz */
754 u32 sclk; /* engine clock in kHz */
755 u32 disp_clk; /* display clock in kHz */
756 u32 src_width; /* viewport width */
757 u32 active_time; /* active display time in ns */
758 u32 blank_time; /* blank time in ns */
759 bool interlaced; /* mode is interlaced */
760 fixed20_12 vsc; /* vertical scale ratio */
761 u32 num_heads; /* number of active crtcs */
762 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
763 u32 lb_size; /* line buffer allocated to pipe */
764 u32 vtaps; /* vertical scaler taps */
765};
766
767/**
768 * dce_v8_0_dram_bandwidth - get the dram bandwidth
769 *
770 * @wm: watermark calculation data
771 *
772 * Calculate the raw dram bandwidth (CIK).
773 * Used for display watermark bandwidth calculations
774 * Returns the dram bandwidth in MBytes/s
775 */
776static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
777{
778 /* Calculate raw DRAM Bandwidth */
779 fixed20_12 dram_efficiency; /* 0.7 */
780 fixed20_12 yclk, dram_channels, bandwidth;
781 fixed20_12 a;
782
783 a.full = dfixed_const(1000);
784 yclk.full = dfixed_const(wm->yclk);
785 yclk.full = dfixed_div(yclk, a);
786 dram_channels.full = dfixed_const(wm->dram_channels * 4);
787 a.full = dfixed_const(10);
788 dram_efficiency.full = dfixed_const(7);
789 dram_efficiency.full = dfixed_div(dram_efficiency, a);
790 bandwidth.full = dfixed_mul(dram_channels, yclk);
791 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
792
793 return dfixed_trunc(bandwidth);
794}
795
796/**
797 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
798 *
799 * @wm: watermark calculation data
800 *
801 * Calculate the dram bandwidth used for display (CIK).
802 * Used for display watermark bandwidth calculations
803 * Returns the dram bandwidth for display in MBytes/s
804 */
805static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
806{
807 /* Calculate DRAM Bandwidth and the part allocated to display. */
808 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
809 fixed20_12 yclk, dram_channels, bandwidth;
810 fixed20_12 a;
811
812 a.full = dfixed_const(1000);
813 yclk.full = dfixed_const(wm->yclk);
814 yclk.full = dfixed_div(yclk, a);
815 dram_channels.full = dfixed_const(wm->dram_channels * 4);
816 a.full = dfixed_const(10);
817 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
818 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
819 bandwidth.full = dfixed_mul(dram_channels, yclk);
820 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
821
822 return dfixed_trunc(bandwidth);
823}
824
825/**
826 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
827 *
828 * @wm: watermark calculation data
829 *
830 * Calculate the data return bandwidth used for display (CIK).
831 * Used for display watermark bandwidth calculations
832 * Returns the data return bandwidth in MBytes/s
833 */
834static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
835{
836 /* Calculate the display Data return Bandwidth */
837 fixed20_12 return_efficiency; /* 0.8 */
838 fixed20_12 sclk, bandwidth;
839 fixed20_12 a;
840
841 a.full = dfixed_const(1000);
842 sclk.full = dfixed_const(wm->sclk);
843 sclk.full = dfixed_div(sclk, a);
844 a.full = dfixed_const(10);
845 return_efficiency.full = dfixed_const(8);
846 return_efficiency.full = dfixed_div(return_efficiency, a);
847 a.full = dfixed_const(32);
848 bandwidth.full = dfixed_mul(a, sclk);
849 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
850
851 return dfixed_trunc(bandwidth);
852}
853
854/**
855 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
856 *
857 * @wm: watermark calculation data
858 *
859 * Calculate the dmif bandwidth used for display (CIK).
860 * Used for display watermark bandwidth calculations
861 * Returns the dmif bandwidth in MBytes/s
862 */
863static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
864{
865 /* Calculate the DMIF Request Bandwidth */
866 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
867 fixed20_12 disp_clk, bandwidth;
868 fixed20_12 a, b;
869
870 a.full = dfixed_const(1000);
871 disp_clk.full = dfixed_const(wm->disp_clk);
872 disp_clk.full = dfixed_div(disp_clk, a);
873 a.full = dfixed_const(32);
874 b.full = dfixed_mul(a, disp_clk);
875
876 a.full = dfixed_const(10);
877 disp_clk_request_efficiency.full = dfixed_const(8);
878 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
879
880 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
881
882 return dfixed_trunc(bandwidth);
883}
884
885/**
886 * dce_v8_0_available_bandwidth - get the min available bandwidth
887 *
888 * @wm: watermark calculation data
889 *
890 * Calculate the min available bandwidth used for display (CIK).
891 * Used for display watermark bandwidth calculations
892 * Returns the min available bandwidth in MBytes/s
893 */
894static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
895{
896 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
897 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
898 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
899 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
900
901 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
902}
903
904/**
905 * dce_v8_0_average_bandwidth - get the average available bandwidth
906 *
907 * @wm: watermark calculation data
908 *
909 * Calculate the average available bandwidth used for display (CIK).
910 * Used for display watermark bandwidth calculations
911 * Returns the average available bandwidth in MBytes/s
912 */
913static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
914{
915 /* Calculate the display mode Average Bandwidth
916 * DisplayMode should contain the source and destination dimensions,
917 * timing, etc.
918 */
919 fixed20_12 bpp;
920 fixed20_12 line_time;
921 fixed20_12 src_width;
922 fixed20_12 bandwidth;
923 fixed20_12 a;
924
925 a.full = dfixed_const(1000);
926 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
927 line_time.full = dfixed_div(line_time, a);
928 bpp.full = dfixed_const(wm->bytes_per_pixel);
929 src_width.full = dfixed_const(wm->src_width);
930 bandwidth.full = dfixed_mul(src_width, bpp);
931 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
932 bandwidth.full = dfixed_div(bandwidth, line_time);
933
934 return dfixed_trunc(bandwidth);
935}
936
937/**
938 * dce_v8_0_latency_watermark - get the latency watermark
939 *
940 * @wm: watermark calculation data
941 *
942 * Calculate the latency watermark (CIK).
943 * Used for display watermark bandwidth calculations
944 * Returns the latency watermark in ns
945 */
946static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
947{
948 /* First calculate the latency in ns */
949 u32 mc_latency = 2000; /* 2000 ns. */
950 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
951 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
952 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
953 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
954 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
955 (wm->num_heads * cursor_line_pair_return_time);
956 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
957 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
958 u32 tmp, dmif_size = 12288;
959 fixed20_12 a, b, c;
960
961 if (wm->num_heads == 0)
962 return 0;
963
964 a.full = dfixed_const(2);
965 b.full = dfixed_const(1);
966 if ((wm->vsc.full > a.full) ||
967 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
968 (wm->vtaps >= 5) ||
969 ((wm->vsc.full >= a.full) && wm->interlaced))
970 max_src_lines_per_dst_line = 4;
971 else
972 max_src_lines_per_dst_line = 2;
973
974 a.full = dfixed_const(available_bandwidth);
975 b.full = dfixed_const(wm->num_heads);
976 a.full = dfixed_div(a, b);
977
978 b.full = dfixed_const(mc_latency + 512);
979 c.full = dfixed_const(wm->disp_clk);
980 b.full = dfixed_div(b, c);
981
982 c.full = dfixed_const(dmif_size);
983 b.full = dfixed_div(c, b);
984
985 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
986
987 b.full = dfixed_const(1000);
988 c.full = dfixed_const(wm->disp_clk);
989 b.full = dfixed_div(c, b);
990 c.full = dfixed_const(wm->bytes_per_pixel);
991 b.full = dfixed_mul(b, c);
992
993 lb_fill_bw = min(tmp, dfixed_trunc(b));
994
995 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
996 b.full = dfixed_const(1000);
997 c.full = dfixed_const(lb_fill_bw);
998 b.full = dfixed_div(c, b);
999 a.full = dfixed_div(a, b);
1000 line_fill_time = dfixed_trunc(a);
1001
1002 if (line_fill_time < wm->active_time)
1003 return latency;
1004 else
1005 return latency + (line_fill_time - wm->active_time);
1006
1007}
1008
1009/**
1010 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1011 * average and available dram bandwidth
1012 *
1013 * @wm: watermark calculation data
1014 *
1015 * Check if the display average bandwidth fits in the display
1016 * dram bandwidth (CIK).
1017 * Used for display watermark bandwidth calculations
1018 * Returns true if the display fits, false if not.
1019 */
1020static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1021{
1022 if (dce_v8_0_average_bandwidth(wm) <=
1023 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1024 return true;
1025 else
1026 return false;
1027}
1028
1029/**
1030 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1031 * average and available bandwidth
1032 *
1033 * @wm: watermark calculation data
1034 *
1035 * Check if the display average bandwidth fits in the display
1036 * available bandwidth (CIK).
1037 * Used for display watermark bandwidth calculations
1038 * Returns true if the display fits, false if not.
1039 */
1040static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1041{
1042 if (dce_v8_0_average_bandwidth(wm) <=
1043 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1044 return true;
1045 else
1046 return false;
1047}
1048
1049/**
1050 * dce_v8_0_check_latency_hiding - check latency hiding
1051 *
1052 * @wm: watermark calculation data
1053 *
1054 * Check latency hiding (CIK).
1055 * Used for display watermark bandwidth calculations
1056 * Returns true if the display fits, false if not.
1057 */
1058static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1059{
1060 u32 lb_partitions = wm->lb_size / wm->src_width;
1061 u32 line_time = wm->active_time + wm->blank_time;
1062 u32 latency_tolerant_lines;
1063 u32 latency_hiding;
1064 fixed20_12 a;
1065
1066 a.full = dfixed_const(1);
1067 if (wm->vsc.full > a.full)
1068 latency_tolerant_lines = 1;
1069 else {
1070 if (lb_partitions <= (wm->vtaps + 1))
1071 latency_tolerant_lines = 1;
1072 else
1073 latency_tolerant_lines = 2;
1074 }
1075
1076 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1077
1078 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1079 return true;
1080 else
1081 return false;
1082}
1083
1084/**
1085 * dce_v8_0_program_watermarks - program display watermarks
1086 *
1087 * @adev: amdgpu_device pointer
1088 * @amdgpu_crtc: the selected display controller
1089 * @lb_size: line buffer size
1090 * @num_heads: number of display controllers in use
1091 *
1092 * Calculate and program the display watermarks for the
1093 * selected display controller (CIK).
1094 */
1095static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1096 struct amdgpu_crtc *amdgpu_crtc,
1097 u32 lb_size, u32 num_heads)
1098{
1099 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1100 struct dce8_wm_params wm_low, wm_high;
1101 u32 pixel_period;
1102 u32 line_time = 0;
1103 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1104 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1105
1106 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1107 pixel_period = 1000000 / (u32)mode->clock;
1108 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1109
1110 /* watermark for high clocks */
1111 if (adev->pm.dpm_enabled) {
1112 wm_high.yclk =
1113 amdgpu_dpm_get_mclk(adev, false) * 10;
1114 wm_high.sclk =
1115 amdgpu_dpm_get_sclk(adev, false) * 10;
1116 } else {
1117 wm_high.yclk = adev->pm.current_mclk * 10;
1118 wm_high.sclk = adev->pm.current_sclk * 10;
1119 }
1120
1121 wm_high.disp_clk = mode->clock;
1122 wm_high.src_width = mode->crtc_hdisplay;
1123 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1124 wm_high.blank_time = line_time - wm_high.active_time;
1125 wm_high.interlaced = false;
1126 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1127 wm_high.interlaced = true;
1128 wm_high.vsc = amdgpu_crtc->vsc;
1129 wm_high.vtaps = 1;
1130 if (amdgpu_crtc->rmx_type != RMX_OFF)
1131 wm_high.vtaps = 2;
1132 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1133 wm_high.lb_size = lb_size;
1134 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1135 wm_high.num_heads = num_heads;
1136
1137 /* set for high clocks */
1138 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1139
1140 /* possibly force display priority to high */
1141 /* should really do this at mode validation time... */
1142 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1143 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1144 !dce_v8_0_check_latency_hiding(&wm_high) ||
1145 (adev->mode_info.disp_priority == 2)) {
1146 DRM_DEBUG_KMS("force priority to high\n");
1147 }
1148
1149 /* watermark for low clocks */
1150 if (adev->pm.dpm_enabled) {
1151 wm_low.yclk =
1152 amdgpu_dpm_get_mclk(adev, true) * 10;
1153 wm_low.sclk =
1154 amdgpu_dpm_get_sclk(adev, true) * 10;
1155 } else {
1156 wm_low.yclk = adev->pm.current_mclk * 10;
1157 wm_low.sclk = adev->pm.current_sclk * 10;
1158 }
1159
1160 wm_low.disp_clk = mode->clock;
1161 wm_low.src_width = mode->crtc_hdisplay;
1162 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1163 wm_low.blank_time = line_time - wm_low.active_time;
1164 wm_low.interlaced = false;
1165 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1166 wm_low.interlaced = true;
1167 wm_low.vsc = amdgpu_crtc->vsc;
1168 wm_low.vtaps = 1;
1169 if (amdgpu_crtc->rmx_type != RMX_OFF)
1170 wm_low.vtaps = 2;
1171 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1172 wm_low.lb_size = lb_size;
1173 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1174 wm_low.num_heads = num_heads;
1175
1176 /* set for low clocks */
1177 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1178
1179 /* possibly force display priority to high */
1180 /* should really do this at mode validation time... */
1181 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1182 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1183 !dce_v8_0_check_latency_hiding(&wm_low) ||
1184 (adev->mode_info.disp_priority == 2)) {
1185 DRM_DEBUG_KMS("force priority to high\n");
1186 }
1187 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1188 }
1189
1190 /* select wm A */
1191 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1192 tmp = wm_mask;
1193 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1194 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1195 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1196 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1197 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1198 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1199 /* select wm B */
1200 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1201 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1202 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1203 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1204 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1205 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1206 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1207 /* restore original selection */
1208 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1209
1210 /* save values for DPM */
1211 amdgpu_crtc->line_time = line_time;
1212 amdgpu_crtc->wm_high = latency_watermark_a;
1213 amdgpu_crtc->wm_low = latency_watermark_b;
1214 /* Save number of lines the linebuffer leads before the scanout */
1215 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1216}
1217
1218/**
1219 * dce_v8_0_bandwidth_update - program display watermarks
1220 *
1221 * @adev: amdgpu_device pointer
1222 *
1223 * Calculate and program the display watermarks and line
1224 * buffer allocation (CIK).
1225 */
1226static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1227{
1228 struct drm_display_mode *mode = NULL;
1229 u32 num_heads = 0, lb_size;
1230 int i;
1231
1232 amdgpu_update_display_priority(adev);
1233
1234 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1235 if (adev->mode_info.crtcs[i]->base.enabled)
1236 num_heads++;
1237 }
1238 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1239 mode = &adev->mode_info.crtcs[i]->base.mode;
1240 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1241 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1242 lb_size, num_heads);
1243 }
1244}
1245
1246static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1247{
1248 int i;
1249 u32 offset, tmp;
1250
1251 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1252 offset = adev->mode_info.audio.pin[i].offset;
1253 tmp = RREG32_AUDIO_ENDPT(offset,
1254 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1255 if (((tmp &
1256 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1257 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1258 adev->mode_info.audio.pin[i].connected = false;
1259 else
1260 adev->mode_info.audio.pin[i].connected = true;
1261 }
1262}
1263
1264static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1265{
1266 int i;
1267
1268 dce_v8_0_audio_get_connected_pins(adev);
1269
1270 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1271 if (adev->mode_info.audio.pin[i].connected)
1272 return &adev->mode_info.audio.pin[i];
1273 }
1274 DRM_ERROR("No connected audio pins found!\n");
1275 return NULL;
1276}
1277
1278static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1279{
1280 struct amdgpu_device *adev = encoder->dev->dev_private;
1281 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1282 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1283 u32 offset;
1284
1285 if (!dig || !dig->afmt || !dig->afmt->pin)
1286 return;
1287
1288 offset = dig->afmt->offset;
1289
1290 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1291 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1292}
1293
1294static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1295 struct drm_display_mode *mode)
1296{
1297 struct amdgpu_device *adev = encoder->dev->dev_private;
1298 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1299 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1300 struct drm_connector *connector;
1301 struct amdgpu_connector *amdgpu_connector = NULL;
1302 u32 tmp = 0, offset;
1303
1304 if (!dig || !dig->afmt || !dig->afmt->pin)
1305 return;
1306
1307 offset = dig->afmt->pin->offset;
1308
1309 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1310 if (connector->encoder == encoder) {
1311 amdgpu_connector = to_amdgpu_connector(connector);
1312 break;
1313 }
1314 }
1315
1316 if (!amdgpu_connector) {
1317 DRM_ERROR("Couldn't find encoder's connector\n");
1318 return;
1319 }
1320
1321 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1322 if (connector->latency_present[1])
1323 tmp =
1324 (connector->video_latency[1] <<
1325 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1326 (connector->audio_latency[1] <<
1327 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1328 else
1329 tmp =
1330 (0 <<
1331 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1332 (0 <<
1333 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1334 } else {
1335 if (connector->latency_present[0])
1336 tmp =
1337 (connector->video_latency[0] <<
1338 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1339 (connector->audio_latency[0] <<
1340 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1341 else
1342 tmp =
1343 (0 <<
1344 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1345 (0 <<
1346 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1347
1348 }
1349 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1350}
1351
1352static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1353{
1354 struct amdgpu_device *adev = encoder->dev->dev_private;
1355 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1356 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1357 struct drm_connector *connector;
1358 struct amdgpu_connector *amdgpu_connector = NULL;
1359 u32 offset, tmp;
1360 u8 *sadb = NULL;
1361 int sad_count;
1362
1363 if (!dig || !dig->afmt || !dig->afmt->pin)
1364 return;
1365
1366 offset = dig->afmt->pin->offset;
1367
1368 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1369 if (connector->encoder == encoder) {
1370 amdgpu_connector = to_amdgpu_connector(connector);
1371 break;
1372 }
1373 }
1374
1375 if (!amdgpu_connector) {
1376 DRM_ERROR("Couldn't find encoder's connector\n");
1377 return;
1378 }
1379
1380 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1381 if (sad_count < 0) {
1382 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1383 sad_count = 0;
1384 }
1385
1386 /* program the speaker allocation */
1387 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1388 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1389 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1390 /* set HDMI mode */
1391 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1392 if (sad_count)
1393 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1394 else
1395 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1396 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1397
1398 kfree(sadb);
1399}
1400
1401static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1402{
1403 struct amdgpu_device *adev = encoder->dev->dev_private;
1404 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1405 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1406 u32 offset;
1407 struct drm_connector *connector;
1408 struct amdgpu_connector *amdgpu_connector = NULL;
1409 struct cea_sad *sads;
1410 int i, sad_count;
1411
1412 static const u16 eld_reg_to_type[][2] = {
1413 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1414 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1415 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1416 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1417 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1418 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1419 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1420 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1421 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1422 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1423 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1424 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1425 };
1426
1427 if (!dig || !dig->afmt || !dig->afmt->pin)
1428 return;
1429
1430 offset = dig->afmt->pin->offset;
1431
1432 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1433 if (connector->encoder == encoder) {
1434 amdgpu_connector = to_amdgpu_connector(connector);
1435 break;
1436 }
1437 }
1438
1439 if (!amdgpu_connector) {
1440 DRM_ERROR("Couldn't find encoder's connector\n");
1441 return;
1442 }
1443
1444 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1445 if (sad_count <= 0) {
1446 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1447 return;
1448 }
1449 BUG_ON(!sads);
1450
1451 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1452 u32 value = 0;
1453 u8 stereo_freqs = 0;
1454 int max_channels = -1;
1455 int j;
1456
1457 for (j = 0; j < sad_count; j++) {
1458 struct cea_sad *sad = &sads[j];
1459
1460 if (sad->format == eld_reg_to_type[i][1]) {
1461 if (sad->channels > max_channels) {
1462 value = (sad->channels <<
1463 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1464 (sad->byte2 <<
1465 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1466 (sad->freq <<
1467 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1468 max_channels = sad->channels;
1469 }
1470
1471 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1472 stereo_freqs |= sad->freq;
1473 else
1474 break;
1475 }
1476 }
1477
1478 value |= (stereo_freqs <<
1479 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1480
1481 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1482 }
1483
1484 kfree(sads);
1485}
1486
1487static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1488 struct amdgpu_audio_pin *pin,
1489 bool enable)
1490{
1491 if (!pin)
1492 return;
1493
1494 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1495 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1496}
1497
1498static const u32 pin_offsets[7] =
1499{
1500 (0x1780 - 0x1780),
1501 (0x1786 - 0x1780),
1502 (0x178c - 0x1780),
1503 (0x1792 - 0x1780),
1504 (0x1798 - 0x1780),
1505 (0x179d - 0x1780),
1506 (0x17a4 - 0x1780),
1507};
1508
1509static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1510{
1511 int i;
1512
1513 if (!amdgpu_audio)
1514 return 0;
1515
1516 adev->mode_info.audio.enabled = true;
1517
1518 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1519 adev->mode_info.audio.num_pins = 7;
1520 else if ((adev->asic_type == CHIP_KABINI) ||
1521 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1522 adev->mode_info.audio.num_pins = 3;
1523 else if ((adev->asic_type == CHIP_BONAIRE) ||
1524 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1525 adev->mode_info.audio.num_pins = 7;
1526 else
1527 adev->mode_info.audio.num_pins = 3;
1528
1529 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1530 adev->mode_info.audio.pin[i].channels = -1;
1531 adev->mode_info.audio.pin[i].rate = -1;
1532 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1533 adev->mode_info.audio.pin[i].status_bits = 0;
1534 adev->mode_info.audio.pin[i].category_code = 0;
1535 adev->mode_info.audio.pin[i].connected = false;
1536 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1537 adev->mode_info.audio.pin[i].id = i;
1538 /* disable audio. it will be set up later */
1539 /* XXX remove once we switch to ip funcs */
1540 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1541 }
1542
1543 return 0;
1544}
1545
1546static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1547{
1548 int i;
1549
1550 if (!amdgpu_audio)
1551 return;
1552
1553 if (!adev->mode_info.audio.enabled)
1554 return;
1555
1556 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1557 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1558
1559 adev->mode_info.audio.enabled = false;
1560}
1561
1562/*
1563 * update the N and CTS parameters for a given pixel clock rate
1564 */
1565static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1566{
1567 struct drm_device *dev = encoder->dev;
1568 struct amdgpu_device *adev = dev->dev_private;
1569 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1570 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1571 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1572 uint32_t offset = dig->afmt->offset;
1573
1574 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1575 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1576
1577 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1578 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1579
1580 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1581 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1582}
1583
1584/*
1585 * build a HDMI Video Info Frame
1586 */
1587static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1588 void *buffer, size_t size)
1589{
1590 struct drm_device *dev = encoder->dev;
1591 struct amdgpu_device *adev = dev->dev_private;
1592 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1593 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1594 uint32_t offset = dig->afmt->offset;
1595 uint8_t *frame = buffer + 3;
1596 uint8_t *header = buffer;
1597
1598 WREG32(mmAFMT_AVI_INFO0 + offset,
1599 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1600 WREG32(mmAFMT_AVI_INFO1 + offset,
1601 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1602 WREG32(mmAFMT_AVI_INFO2 + offset,
1603 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1604 WREG32(mmAFMT_AVI_INFO3 + offset,
1605 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1606}
1607
1608static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1609{
1610 struct drm_device *dev = encoder->dev;
1611 struct amdgpu_device *adev = dev->dev_private;
1612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1613 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1614 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1615 u32 dto_phase = 24 * 1000;
1616 u32 dto_modulo = clock;
1617
1618 if (!dig || !dig->afmt)
1619 return;
1620
1621 /* XXX two dtos; generally use dto0 for hdmi */
1622 /* Express [24MHz / target pixel clock] as an exact rational
1623 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1624 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1625 */
1626 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1627 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1628 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1629}
1630
1631/*
1632 * update the info frames with the data from the current display mode
1633 */
1634static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1635 struct drm_display_mode *mode)
1636{
1637 struct drm_device *dev = encoder->dev;
1638 struct amdgpu_device *adev = dev->dev_private;
1639 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1640 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1641 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1642 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1643 struct hdmi_avi_infoframe frame;
1644 uint32_t offset, val;
1645 ssize_t err;
1646 int bpc = 8;
1647
1648 if (!dig || !dig->afmt)
1649 return;
1650
1651 /* Silent, r600_hdmi_enable will raise WARN for us */
1652 if (!dig->afmt->enabled)
1653 return;
1654
1655 offset = dig->afmt->offset;
1656
1657 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1658 if (encoder->crtc) {
1659 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1660 bpc = amdgpu_crtc->bpc;
1661 }
1662
1663 /* disable audio prior to setting up hw */
1664 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1665 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1666
1667 dce_v8_0_audio_set_dto(encoder, mode->clock);
1668
1669 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1670 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1671
1672 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1673
1674 val = RREG32(mmHDMI_CONTROL + offset);
1675 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1676 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1677
1678 switch (bpc) {
1679 case 0:
1680 case 6:
1681 case 8:
1682 case 16:
1683 default:
1684 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1685 connector->name, bpc);
1686 break;
1687 case 10:
1688 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1689 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1690 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1691 connector->name);
1692 break;
1693 case 12:
1694 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1695 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1696 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1697 connector->name);
1698 break;
1699 }
1700
1701 WREG32(mmHDMI_CONTROL + offset, val);
1702
1703 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1704 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1705 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1706 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1707
1708 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1709 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1710 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1711
1712 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1713 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1714
1715 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1716 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1717
1718 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1719
1720 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1721 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1722 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1723
1724 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1725 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1726
1727 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1728
1729 if (bpc > 8)
1730 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1731 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1732 else
1733 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1734 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1735 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1736
1737 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1738
1739 WREG32(mmAFMT_60958_0 + offset,
1740 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1741
1742 WREG32(mmAFMT_60958_1 + offset,
1743 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1744
1745 WREG32(mmAFMT_60958_2 + offset,
1746 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1747 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1748 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1749 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1750 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1751 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1752
1753 dce_v8_0_audio_write_speaker_allocation(encoder);
1754
1755
1756 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1757 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1758
1759 dce_v8_0_afmt_audio_select_pin(encoder);
1760 dce_v8_0_audio_write_sad_regs(encoder);
1761 dce_v8_0_audio_write_latency_fields(encoder, mode);
1762
1763 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1764 if (err < 0) {
1765 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1766 return;
1767 }
1768
1769 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1770 if (err < 0) {
1771 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1772 return;
1773 }
1774
1775 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1776
1777 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1778 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1779 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1780
1781 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1782 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1783 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1784
1785 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1786 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1787
1788 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1789 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1790 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1791 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1792
1793 /* enable audio after setting up hw */
1794 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1795}
1796
1797static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1798{
1799 struct drm_device *dev = encoder->dev;
1800 struct amdgpu_device *adev = dev->dev_private;
1801 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1802 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1803
1804 if (!dig || !dig->afmt)
1805 return;
1806
1807 /* Silent, r600_hdmi_enable will raise WARN for us */
1808 if (enable && dig->afmt->enabled)
1809 return;
1810 if (!enable && !dig->afmt->enabled)
1811 return;
1812
1813 if (!enable && dig->afmt->pin) {
1814 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1815 dig->afmt->pin = NULL;
1816 }
1817
1818 dig->afmt->enabled = enable;
1819
1820 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1821 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1822}
1823
1824static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1825{
1826 int i;
1827
1828 for (i = 0; i < adev->mode_info.num_dig; i++)
1829 adev->mode_info.afmt[i] = NULL;
1830
1831 /* DCE8 has audio blocks tied to DIG encoders */
1832 for (i = 0; i < adev->mode_info.num_dig; i++) {
1833 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1834 if (adev->mode_info.afmt[i]) {
1835 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1836 adev->mode_info.afmt[i]->id = i;
1837 } else {
1838 int j;
1839 for (j = 0; j < i; j++) {
1840 kfree(adev->mode_info.afmt[j]);
1841 adev->mode_info.afmt[j] = NULL;
1842 }
1843 return -ENOMEM;
1844 }
1845 }
1846 return 0;
1847}
1848
1849static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1850{
1851 int i;
1852
1853 for (i = 0; i < adev->mode_info.num_dig; i++) {
1854 kfree(adev->mode_info.afmt[i]);
1855 adev->mode_info.afmt[i] = NULL;
1856 }
1857}
1858
1859static const u32 vga_control_regs[6] =
1860{
1861 mmD1VGA_CONTROL,
1862 mmD2VGA_CONTROL,
1863 mmD3VGA_CONTROL,
1864 mmD4VGA_CONTROL,
1865 mmD5VGA_CONTROL,
1866 mmD6VGA_CONTROL,
1867};
1868
1869static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1870{
1871 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1872 struct drm_device *dev = crtc->dev;
1873 struct amdgpu_device *adev = dev->dev_private;
1874 u32 vga_control;
1875
1876 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1877 if (enable)
1878 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1879 else
1880 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1881}
1882
1883static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1884{
1885 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1886 struct drm_device *dev = crtc->dev;
1887 struct amdgpu_device *adev = dev->dev_private;
1888
1889 if (enable)
1890 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1891 else
1892 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1893}
1894
1895static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1896 struct drm_framebuffer *fb,
1897 int x, int y, int atomic)
1898{
1899 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1900 struct drm_device *dev = crtc->dev;
1901 struct amdgpu_device *adev = dev->dev_private;
1902 struct amdgpu_framebuffer *amdgpu_fb;
1903 struct drm_framebuffer *target_fb;
1904 struct drm_gem_object *obj;
1905 struct amdgpu_bo *abo;
1906 uint64_t fb_location, tiling_flags;
1907 uint32_t fb_format, fb_pitch_pixels;
1908 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1909 u32 pipe_config;
1910 u32 viewport_w, viewport_h;
1911 int r;
1912 bool bypass_lut = false;
1913 struct drm_format_name_buf format_name;
1914
1915 /* no fb bound */
1916 if (!atomic && !crtc->primary->fb) {
1917 DRM_DEBUG_KMS("No FB bound\n");
1918 return 0;
1919 }
1920
1921 if (atomic) {
1922 amdgpu_fb = to_amdgpu_framebuffer(fb);
1923 target_fb = fb;
1924 } else {
1925 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1926 target_fb = crtc->primary->fb;
1927 }
1928
1929 /* If atomic, assume fb object is pinned & idle & fenced and
1930 * just update base pointers
1931 */
1932 obj = amdgpu_fb->obj;
1933 abo = gem_to_amdgpu_bo(obj);
1934 r = amdgpu_bo_reserve(abo, false);
1935 if (unlikely(r != 0))
1936 return r;
1937
1938 if (atomic) {
1939 fb_location = amdgpu_bo_gpu_offset(abo);
1940 } else {
1941 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1942 if (unlikely(r != 0)) {
1943 amdgpu_bo_unreserve(abo);
1944 return -EINVAL;
1945 }
1946 }
1947
1948 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1949 amdgpu_bo_unreserve(abo);
1950
1951 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1952
1953 switch (target_fb->pixel_format) {
1954 case DRM_FORMAT_C8:
1955 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1956 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1957 break;
1958 case DRM_FORMAT_XRGB4444:
1959 case DRM_FORMAT_ARGB4444:
1960 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1961 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1962#ifdef __BIG_ENDIAN
1963 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1964#endif
1965 break;
1966 case DRM_FORMAT_XRGB1555:
1967 case DRM_FORMAT_ARGB1555:
1968 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1969 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1970#ifdef __BIG_ENDIAN
1971 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1972#endif
1973 break;
1974 case DRM_FORMAT_BGRX5551:
1975 case DRM_FORMAT_BGRA5551:
1976 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1977 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1978#ifdef __BIG_ENDIAN
1979 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1980#endif
1981 break;
1982 case DRM_FORMAT_RGB565:
1983 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1984 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1985#ifdef __BIG_ENDIAN
1986 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1987#endif
1988 break;
1989 case DRM_FORMAT_XRGB8888:
1990 case DRM_FORMAT_ARGB8888:
1991 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1992 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1993#ifdef __BIG_ENDIAN
1994 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1995#endif
1996 break;
1997 case DRM_FORMAT_XRGB2101010:
1998 case DRM_FORMAT_ARGB2101010:
1999 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2000 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2001#ifdef __BIG_ENDIAN
2002 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2003#endif
2004 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2005 bypass_lut = true;
2006 break;
2007 case DRM_FORMAT_BGRX1010102:
2008 case DRM_FORMAT_BGRA1010102:
2009 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2010 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2011#ifdef __BIG_ENDIAN
2012 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2013#endif
2014 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2015 bypass_lut = true;
2016 break;
2017 default:
2018 DRM_ERROR("Unsupported screen format %s\n",
2019 drm_get_format_name(target_fb->pixel_format, &format_name));
2020 return -EINVAL;
2021 }
2022
2023 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2024 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2025
2026 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2027 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2028 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2029 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2030 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2031
2032 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2033 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2034 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2035 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2036 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2037 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2038 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
2039 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2040 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2041 }
2042
2043 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2044
2045 dce_v8_0_vga_enable(crtc, false);
2046
2047 /* Make sure surface address is updated at vertical blank rather than
2048 * horizontal blank
2049 */
2050 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2051
2052 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2053 upper_32_bits(fb_location));
2054 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2055 upper_32_bits(fb_location));
2056 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2057 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2058 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2059 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2060 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2061 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2062
2063 /*
2064 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2065 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2066 * retain the full precision throughout the pipeline.
2067 */
2068 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2069 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2070 ~LUT_10BIT_BYPASS_EN);
2071
2072 if (bypass_lut)
2073 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2074
2075 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2076 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2077 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2078 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2079 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2080 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2081
2082 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2083 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2084
2085 dce_v8_0_grph_enable(crtc, true);
2086
2087 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2088 target_fb->height);
2089
2090 x &= ~3;
2091 y &= ~1;
2092 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2093 (x << 16) | y);
2094 viewport_w = crtc->mode.hdisplay;
2095 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2096 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2097 (viewport_w << 16) | viewport_h);
2098
2099 /* set pageflip to happen anywhere in vblank interval */
2100 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2101
2102 if (!atomic && fb && fb != crtc->primary->fb) {
2103 amdgpu_fb = to_amdgpu_framebuffer(fb);
2104 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2105 r = amdgpu_bo_reserve(abo, false);
2106 if (unlikely(r != 0))
2107 return r;
2108 amdgpu_bo_unpin(abo);
2109 amdgpu_bo_unreserve(abo);
2110 }
2111
2112 /* Bytes per pixel may have changed */
2113 dce_v8_0_bandwidth_update(adev);
2114
2115 return 0;
2116}
2117
2118static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2119 struct drm_display_mode *mode)
2120{
2121 struct drm_device *dev = crtc->dev;
2122 struct amdgpu_device *adev = dev->dev_private;
2123 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2124
2125 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2126 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2127 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2128 else
2129 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2130}
2131
2132static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2133{
2134 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2135 struct drm_device *dev = crtc->dev;
2136 struct amdgpu_device *adev = dev->dev_private;
2137 int i;
2138
2139 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2140
2141 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2142 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2143 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2144 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2145 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2146 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2147 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2148 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2149 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2150 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2151
2152 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2153
2154 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2155 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2156 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2157
2158 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2159 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2160 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2161
2162 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2163 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2164
2165 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2166 for (i = 0; i < 256; i++) {
2167 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2168 (amdgpu_crtc->lut_r[i] << 20) |
2169 (amdgpu_crtc->lut_g[i] << 10) |
2170 (amdgpu_crtc->lut_b[i] << 0));
2171 }
2172
2173 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2174 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2175 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2176 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2177 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2178 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2179 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2180 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2181 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2182 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2183 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2184 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2185 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2186 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2187 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2188 /* XXX this only needs to be programmed once per crtc at startup,
2189 * not sure where the best place for it is
2190 */
2191 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2192 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2193}
2194
2195static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2196{
2197 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2198 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2199
2200 switch (amdgpu_encoder->encoder_id) {
2201 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2202 if (dig->linkb)
2203 return 1;
2204 else
2205 return 0;
2206 break;
2207 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2208 if (dig->linkb)
2209 return 3;
2210 else
2211 return 2;
2212 break;
2213 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2214 if (dig->linkb)
2215 return 5;
2216 else
2217 return 4;
2218 break;
2219 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2220 return 6;
2221 break;
2222 default:
2223 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2224 return 0;
2225 }
2226}
2227
2228/**
2229 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2230 *
2231 * @crtc: drm crtc
2232 *
2233 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2234 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2235 * monitors a dedicated PPLL must be used. If a particular board has
2236 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2237 * as there is no need to program the PLL itself. If we are not able to
2238 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2239 * avoid messing up an existing monitor.
2240 *
2241 * Asic specific PLL information
2242 *
2243 * DCE 8.x
2244 * KB/KV
2245 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2246 * CI
2247 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2248 *
2249 */
2250static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2251{
2252 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2253 struct drm_device *dev = crtc->dev;
2254 struct amdgpu_device *adev = dev->dev_private;
2255 u32 pll_in_use;
2256 int pll;
2257
2258 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2259 if (adev->clock.dp_extclk)
2260 /* skip PPLL programming if using ext clock */
2261 return ATOM_PPLL_INVALID;
2262 else {
2263 /* use the same PPLL for all DP monitors */
2264 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2265 if (pll != ATOM_PPLL_INVALID)
2266 return pll;
2267 }
2268 } else {
2269 /* use the same PPLL for all monitors with the same clock */
2270 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2271 if (pll != ATOM_PPLL_INVALID)
2272 return pll;
2273 }
2274 /* otherwise, pick one of the plls */
2275 if ((adev->asic_type == CHIP_KABINI) ||
2276 (adev->asic_type == CHIP_MULLINS)) {
2277 /* KB/ML has PPLL1 and PPLL2 */
2278 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2279 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2280 return ATOM_PPLL2;
2281 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2282 return ATOM_PPLL1;
2283 DRM_ERROR("unable to allocate a PPLL\n");
2284 return ATOM_PPLL_INVALID;
2285 } else {
2286 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2287 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2288 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2289 return ATOM_PPLL2;
2290 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2291 return ATOM_PPLL1;
2292 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2293 return ATOM_PPLL0;
2294 DRM_ERROR("unable to allocate a PPLL\n");
2295 return ATOM_PPLL_INVALID;
2296 }
2297 return ATOM_PPLL_INVALID;
2298}
2299
2300static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2301{
2302 struct amdgpu_device *adev = crtc->dev->dev_private;
2303 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2304 uint32_t cur_lock;
2305
2306 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2307 if (lock)
2308 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2309 else
2310 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2311 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2312}
2313
2314static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2315{
2316 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2317 struct amdgpu_device *adev = crtc->dev->dev_private;
2318
2319 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2320 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2321 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2322}
2323
2324static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2325{
2326 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2327 struct amdgpu_device *adev = crtc->dev->dev_private;
2328
2329 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2330 upper_32_bits(amdgpu_crtc->cursor_addr));
2331 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2332 lower_32_bits(amdgpu_crtc->cursor_addr));
2333
2334 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2335 CUR_CONTROL__CURSOR_EN_MASK |
2336 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2337 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2338}
2339
2340static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2341 int x, int y)
2342{
2343 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2344 struct amdgpu_device *adev = crtc->dev->dev_private;
2345 int xorigin = 0, yorigin = 0;
2346
2347 amdgpu_crtc->cursor_x = x;
2348 amdgpu_crtc->cursor_y = y;
2349
2350 /* avivo cursor are offset into the total surface */
2351 x += crtc->x;
2352 y += crtc->y;
2353 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2354
2355 if (x < 0) {
2356 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2357 x = 0;
2358 }
2359 if (y < 0) {
2360 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2361 y = 0;
2362 }
2363
2364 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2365 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2366 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2367 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2368
2369 return 0;
2370}
2371
2372static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2373 int x, int y)
2374{
2375 int ret;
2376
2377 dce_v8_0_lock_cursor(crtc, true);
2378 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2379 dce_v8_0_lock_cursor(crtc, false);
2380
2381 return ret;
2382}
2383
2384static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2385 struct drm_file *file_priv,
2386 uint32_t handle,
2387 uint32_t width,
2388 uint32_t height,
2389 int32_t hot_x,
2390 int32_t hot_y)
2391{
2392 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2393 struct drm_gem_object *obj;
2394 struct amdgpu_bo *aobj;
2395 int ret;
2396
2397 if (!handle) {
2398 /* turn off cursor */
2399 dce_v8_0_hide_cursor(crtc);
2400 obj = NULL;
2401 goto unpin;
2402 }
2403
2404 if ((width > amdgpu_crtc->max_cursor_width) ||
2405 (height > amdgpu_crtc->max_cursor_height)) {
2406 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2407 return -EINVAL;
2408 }
2409
2410 obj = drm_gem_object_lookup(file_priv, handle);
2411 if (!obj) {
2412 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2413 return -ENOENT;
2414 }
2415
2416 aobj = gem_to_amdgpu_bo(obj);
2417 ret = amdgpu_bo_reserve(aobj, false);
2418 if (ret != 0) {
2419 drm_gem_object_unreference_unlocked(obj);
2420 return ret;
2421 }
2422
2423 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2424 amdgpu_bo_unreserve(aobj);
2425 if (ret) {
2426 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2427 drm_gem_object_unreference_unlocked(obj);
2428 return ret;
2429 }
2430
2431 dce_v8_0_lock_cursor(crtc, true);
2432
2433 if (width != amdgpu_crtc->cursor_width ||
2434 height != amdgpu_crtc->cursor_height ||
2435 hot_x != amdgpu_crtc->cursor_hot_x ||
2436 hot_y != amdgpu_crtc->cursor_hot_y) {
2437 int x, y;
2438
2439 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2440 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2441
2442 dce_v8_0_cursor_move_locked(crtc, x, y);
2443
2444 amdgpu_crtc->cursor_width = width;
2445 amdgpu_crtc->cursor_height = height;
2446 amdgpu_crtc->cursor_hot_x = hot_x;
2447 amdgpu_crtc->cursor_hot_y = hot_y;
2448 }
2449
2450 dce_v8_0_show_cursor(crtc);
2451 dce_v8_0_lock_cursor(crtc, false);
2452
2453unpin:
2454 if (amdgpu_crtc->cursor_bo) {
2455 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2456 ret = amdgpu_bo_reserve(aobj, false);
2457 if (likely(ret == 0)) {
2458 amdgpu_bo_unpin(aobj);
2459 amdgpu_bo_unreserve(aobj);
2460 }
2461 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2462 }
2463
2464 amdgpu_crtc->cursor_bo = obj;
2465 return 0;
2466}
2467
2468static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2469{
2470 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2471
2472 if (amdgpu_crtc->cursor_bo) {
2473 dce_v8_0_lock_cursor(crtc, true);
2474
2475 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2476 amdgpu_crtc->cursor_y);
2477
2478 dce_v8_0_show_cursor(crtc);
2479
2480 dce_v8_0_lock_cursor(crtc, false);
2481 }
2482}
2483
2484static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2485 u16 *blue, uint32_t size)
2486{
2487 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2488 int i;
2489
2490 /* userspace palettes are always correct as is */
2491 for (i = 0; i < size; i++) {
2492 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2493 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2494 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2495 }
2496 dce_v8_0_crtc_load_lut(crtc);
2497
2498 return 0;
2499}
2500
2501static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2502{
2503 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2504
2505 drm_crtc_cleanup(crtc);
2506 kfree(amdgpu_crtc);
2507}
2508
2509static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2510 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2511 .cursor_move = dce_v8_0_crtc_cursor_move,
2512 .gamma_set = dce_v8_0_crtc_gamma_set,
2513 .set_config = amdgpu_crtc_set_config,
2514 .destroy = dce_v8_0_crtc_destroy,
2515 .page_flip_target = amdgpu_crtc_page_flip_target,
2516};
2517
2518static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2519{
2520 struct drm_device *dev = crtc->dev;
2521 struct amdgpu_device *adev = dev->dev_private;
2522 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2523 unsigned type;
2524
2525 switch (mode) {
2526 case DRM_MODE_DPMS_ON:
2527 amdgpu_crtc->enabled = true;
2528 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2529 dce_v8_0_vga_enable(crtc, true);
2530 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2531 dce_v8_0_vga_enable(crtc, false);
2532 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2533 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2534 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2535 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2536 drm_crtc_vblank_on(crtc);
2537 dce_v8_0_crtc_load_lut(crtc);
2538 break;
2539 case DRM_MODE_DPMS_STANDBY:
2540 case DRM_MODE_DPMS_SUSPEND:
2541 case DRM_MODE_DPMS_OFF:
2542 drm_crtc_vblank_off(crtc);
2543 if (amdgpu_crtc->enabled) {
2544 dce_v8_0_vga_enable(crtc, true);
2545 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2546 dce_v8_0_vga_enable(crtc, false);
2547 }
2548 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2549 amdgpu_crtc->enabled = false;
2550 break;
2551 }
2552 /* adjust pm to dpms */
2553 amdgpu_pm_compute_clocks(adev);
2554}
2555
2556static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2557{
2558 /* disable crtc pair power gating before programming */
2559 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2560 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2561 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2562}
2563
2564static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2565{
2566 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2567 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2568}
2569
2570static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2571{
2572 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2573 struct drm_device *dev = crtc->dev;
2574 struct amdgpu_device *adev = dev->dev_private;
2575 struct amdgpu_atom_ss ss;
2576 int i;
2577
2578 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2579 if (crtc->primary->fb) {
2580 int r;
2581 struct amdgpu_framebuffer *amdgpu_fb;
2582 struct amdgpu_bo *abo;
2583
2584 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2585 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2586 r = amdgpu_bo_reserve(abo, false);
2587 if (unlikely(r))
2588 DRM_ERROR("failed to reserve abo before unpin\n");
2589 else {
2590 amdgpu_bo_unpin(abo);
2591 amdgpu_bo_unreserve(abo);
2592 }
2593 }
2594 /* disable the GRPH */
2595 dce_v8_0_grph_enable(crtc, false);
2596
2597 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2598
2599 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2600 if (adev->mode_info.crtcs[i] &&
2601 adev->mode_info.crtcs[i]->enabled &&
2602 i != amdgpu_crtc->crtc_id &&
2603 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2604 /* one other crtc is using this pll don't turn
2605 * off the pll
2606 */
2607 goto done;
2608 }
2609 }
2610
2611 switch (amdgpu_crtc->pll_id) {
2612 case ATOM_PPLL1:
2613 case ATOM_PPLL2:
2614 /* disable the ppll */
2615 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2616 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2617 break;
2618 case ATOM_PPLL0:
2619 /* disable the ppll */
2620 if ((adev->asic_type == CHIP_KAVERI) ||
2621 (adev->asic_type == CHIP_BONAIRE) ||
2622 (adev->asic_type == CHIP_HAWAII))
2623 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2624 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2625 break;
2626 default:
2627 break;
2628 }
2629done:
2630 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2631 amdgpu_crtc->adjusted_clock = 0;
2632 amdgpu_crtc->encoder = NULL;
2633 amdgpu_crtc->connector = NULL;
2634}
2635
2636static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2637 struct drm_display_mode *mode,
2638 struct drm_display_mode *adjusted_mode,
2639 int x, int y, struct drm_framebuffer *old_fb)
2640{
2641 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2642
2643 if (!amdgpu_crtc->adjusted_clock)
2644 return -EINVAL;
2645
2646 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2647 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2648 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2649 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2650 amdgpu_atombios_crtc_scaler_setup(crtc);
2651 dce_v8_0_cursor_reset(crtc);
2652 /* update the hw version fpr dpm */
2653 amdgpu_crtc->hw_mode = *adjusted_mode;
2654
2655 return 0;
2656}
2657
2658static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2659 const struct drm_display_mode *mode,
2660 struct drm_display_mode *adjusted_mode)
2661{
2662 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2663 struct drm_device *dev = crtc->dev;
2664 struct drm_encoder *encoder;
2665
2666 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2667 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2668 if (encoder->crtc == crtc) {
2669 amdgpu_crtc->encoder = encoder;
2670 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2671 break;
2672 }
2673 }
2674 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2675 amdgpu_crtc->encoder = NULL;
2676 amdgpu_crtc->connector = NULL;
2677 return false;
2678 }
2679 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2680 return false;
2681 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2682 return false;
2683 /* pick pll */
2684 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2685 /* if we can't get a PPLL for a non-DP encoder, fail */
2686 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2687 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2688 return false;
2689
2690 return true;
2691}
2692
2693static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2694 struct drm_framebuffer *old_fb)
2695{
2696 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2697}
2698
2699static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2700 struct drm_framebuffer *fb,
2701 int x, int y, enum mode_set_atomic state)
2702{
2703 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2704}
2705
2706static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2707 .dpms = dce_v8_0_crtc_dpms,
2708 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2709 .mode_set = dce_v8_0_crtc_mode_set,
2710 .mode_set_base = dce_v8_0_crtc_set_base,
2711 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2712 .prepare = dce_v8_0_crtc_prepare,
2713 .commit = dce_v8_0_crtc_commit,
2714 .load_lut = dce_v8_0_crtc_load_lut,
2715 .disable = dce_v8_0_crtc_disable,
2716};
2717
2718static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2719{
2720 struct amdgpu_crtc *amdgpu_crtc;
2721 int i;
2722
2723 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2724 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2725 if (amdgpu_crtc == NULL)
2726 return -ENOMEM;
2727
2728 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2729
2730 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2731 amdgpu_crtc->crtc_id = index;
2732 adev->mode_info.crtcs[index] = amdgpu_crtc;
2733
2734 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2735 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2736 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2737 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2738
2739 for (i = 0; i < 256; i++) {
2740 amdgpu_crtc->lut_r[i] = i << 2;
2741 amdgpu_crtc->lut_g[i] = i << 2;
2742 amdgpu_crtc->lut_b[i] = i << 2;
2743 }
2744
2745 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2746
2747 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2748 amdgpu_crtc->adjusted_clock = 0;
2749 amdgpu_crtc->encoder = NULL;
2750 amdgpu_crtc->connector = NULL;
2751 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2752
2753 return 0;
2754}
2755
2756static int dce_v8_0_early_init(void *handle)
2757{
2758 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2759
2760 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2761 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2762
2763 dce_v8_0_set_display_funcs(adev);
2764 dce_v8_0_set_irq_funcs(adev);
2765
2766 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2767
2768 switch (adev->asic_type) {
2769 case CHIP_BONAIRE:
2770 case CHIP_HAWAII:
2771 adev->mode_info.num_hpd = 6;
2772 adev->mode_info.num_dig = 6;
2773 break;
2774 case CHIP_KAVERI:
2775 adev->mode_info.num_hpd = 6;
2776 adev->mode_info.num_dig = 7;
2777 break;
2778 case CHIP_KABINI:
2779 case CHIP_MULLINS:
2780 adev->mode_info.num_hpd = 6;
2781 adev->mode_info.num_dig = 6; /* ? */
2782 break;
2783 default:
2784 /* FIXME: not supported yet */
2785 return -EINVAL;
2786 }
2787
2788 return 0;
2789}
2790
2791static int dce_v8_0_sw_init(void *handle)
2792{
2793 int r, i;
2794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2795
2796 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2797 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2798 if (r)
2799 return r;
2800 }
2801
2802 for (i = 8; i < 20; i += 2) {
2803 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2804 if (r)
2805 return r;
2806 }
2807
2808 /* HPD hotplug */
2809 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2810 if (r)
2811 return r;
2812
2813 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2814
2815 adev->ddev->mode_config.async_page_flip = true;
2816
2817 adev->ddev->mode_config.max_width = 16384;
2818 adev->ddev->mode_config.max_height = 16384;
2819
2820 adev->ddev->mode_config.preferred_depth = 24;
2821 adev->ddev->mode_config.prefer_shadow = 1;
2822
2823 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2824
2825 r = amdgpu_modeset_create_props(adev);
2826 if (r)
2827 return r;
2828
2829 adev->ddev->mode_config.max_width = 16384;
2830 adev->ddev->mode_config.max_height = 16384;
2831
2832 /* allocate crtcs */
2833 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2834 r = dce_v8_0_crtc_init(adev, i);
2835 if (r)
2836 return r;
2837 }
2838
2839 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2840 amdgpu_print_display_setup(adev->ddev);
2841 else
2842 return -EINVAL;
2843
2844 /* setup afmt */
2845 r = dce_v8_0_afmt_init(adev);
2846 if (r)
2847 return r;
2848
2849 r = dce_v8_0_audio_init(adev);
2850 if (r)
2851 return r;
2852
2853 drm_kms_helper_poll_init(adev->ddev);
2854
2855 adev->mode_info.mode_config_initialized = true;
2856 return 0;
2857}
2858
2859static int dce_v8_0_sw_fini(void *handle)
2860{
2861 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2862
2863 kfree(adev->mode_info.bios_hardcoded_edid);
2864
2865 drm_kms_helper_poll_fini(adev->ddev);
2866
2867 dce_v8_0_audio_fini(adev);
2868
2869 dce_v8_0_afmt_fini(adev);
2870
2871 drm_mode_config_cleanup(adev->ddev);
2872 adev->mode_info.mode_config_initialized = false;
2873
2874 return 0;
2875}
2876
2877static int dce_v8_0_hw_init(void *handle)
2878{
2879 int i;
2880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2881
2882 /* init dig PHYs, disp eng pll */
2883 amdgpu_atombios_encoder_init_dig(adev);
2884 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2885
2886 /* initialize hpd */
2887 dce_v8_0_hpd_init(adev);
2888
2889 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2890 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2891 }
2892
2893 dce_v8_0_pageflip_interrupt_init(adev);
2894
2895 return 0;
2896}
2897
2898static int dce_v8_0_hw_fini(void *handle)
2899{
2900 int i;
2901 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2902
2903 dce_v8_0_hpd_fini(adev);
2904
2905 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2906 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2907 }
2908
2909 dce_v8_0_pageflip_interrupt_fini(adev);
2910
2911 return 0;
2912}
2913
2914static int dce_v8_0_suspend(void *handle)
2915{
2916 return dce_v8_0_hw_fini(handle);
2917}
2918
2919static int dce_v8_0_resume(void *handle)
2920{
2921 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2922 int ret;
2923
2924 ret = dce_v8_0_hw_init(handle);
2925
2926 /* turn on the BL */
2927 if (adev->mode_info.bl_encoder) {
2928 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2929 adev->mode_info.bl_encoder);
2930 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2931 bl_level);
2932 }
2933
2934 return ret;
2935}
2936
2937static bool dce_v8_0_is_idle(void *handle)
2938{
2939 return true;
2940}
2941
2942static int dce_v8_0_wait_for_idle(void *handle)
2943{
2944 return 0;
2945}
2946
2947static int dce_v8_0_soft_reset(void *handle)
2948{
2949 u32 srbm_soft_reset = 0, tmp;
2950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2951
2952 if (dce_v8_0_is_display_hung(adev))
2953 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2954
2955 if (srbm_soft_reset) {
2956 tmp = RREG32(mmSRBM_SOFT_RESET);
2957 tmp |= srbm_soft_reset;
2958 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2959 WREG32(mmSRBM_SOFT_RESET, tmp);
2960 tmp = RREG32(mmSRBM_SOFT_RESET);
2961
2962 udelay(50);
2963
2964 tmp &= ~srbm_soft_reset;
2965 WREG32(mmSRBM_SOFT_RESET, tmp);
2966 tmp = RREG32(mmSRBM_SOFT_RESET);
2967
2968 /* Wait a little for things to settle down */
2969 udelay(50);
2970 }
2971 return 0;
2972}
2973
2974static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2975 int crtc,
2976 enum amdgpu_interrupt_state state)
2977{
2978 u32 reg_block, lb_interrupt_mask;
2979
2980 if (crtc >= adev->mode_info.num_crtc) {
2981 DRM_DEBUG("invalid crtc %d\n", crtc);
2982 return;
2983 }
2984
2985 switch (crtc) {
2986 case 0:
2987 reg_block = CRTC0_REGISTER_OFFSET;
2988 break;
2989 case 1:
2990 reg_block = CRTC1_REGISTER_OFFSET;
2991 break;
2992 case 2:
2993 reg_block = CRTC2_REGISTER_OFFSET;
2994 break;
2995 case 3:
2996 reg_block = CRTC3_REGISTER_OFFSET;
2997 break;
2998 case 4:
2999 reg_block = CRTC4_REGISTER_OFFSET;
3000 break;
3001 case 5:
3002 reg_block = CRTC5_REGISTER_OFFSET;
3003 break;
3004 default:
3005 DRM_DEBUG("invalid crtc %d\n", crtc);
3006 return;
3007 }
3008
3009 switch (state) {
3010 case AMDGPU_IRQ_STATE_DISABLE:
3011 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3012 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3013 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3014 break;
3015 case AMDGPU_IRQ_STATE_ENABLE:
3016 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3017 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3018 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3019 break;
3020 default:
3021 break;
3022 }
3023}
3024
3025static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3026 int crtc,
3027 enum amdgpu_interrupt_state state)
3028{
3029 u32 reg_block, lb_interrupt_mask;
3030
3031 if (crtc >= adev->mode_info.num_crtc) {
3032 DRM_DEBUG("invalid crtc %d\n", crtc);
3033 return;
3034 }
3035
3036 switch (crtc) {
3037 case 0:
3038 reg_block = CRTC0_REGISTER_OFFSET;
3039 break;
3040 case 1:
3041 reg_block = CRTC1_REGISTER_OFFSET;
3042 break;
3043 case 2:
3044 reg_block = CRTC2_REGISTER_OFFSET;
3045 break;
3046 case 3:
3047 reg_block = CRTC3_REGISTER_OFFSET;
3048 break;
3049 case 4:
3050 reg_block = CRTC4_REGISTER_OFFSET;
3051 break;
3052 case 5:
3053 reg_block = CRTC5_REGISTER_OFFSET;
3054 break;
3055 default:
3056 DRM_DEBUG("invalid crtc %d\n", crtc);
3057 return;
3058 }
3059
3060 switch (state) {
3061 case AMDGPU_IRQ_STATE_DISABLE:
3062 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3063 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3064 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3065 break;
3066 case AMDGPU_IRQ_STATE_ENABLE:
3067 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3068 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3069 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3070 break;
3071 default:
3072 break;
3073 }
3074}
3075
3076static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3077 struct amdgpu_irq_src *src,
3078 unsigned type,
3079 enum amdgpu_interrupt_state state)
3080{
3081 u32 dc_hpd_int_cntl;
3082
3083 if (type >= adev->mode_info.num_hpd) {
3084 DRM_DEBUG("invalid hdp %d\n", type);
3085 return 0;
3086 }
3087
3088 switch (state) {
3089 case AMDGPU_IRQ_STATE_DISABLE:
3090 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3091 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3092 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3093 break;
3094 case AMDGPU_IRQ_STATE_ENABLE:
3095 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3096 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3097 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3098 break;
3099 default:
3100 break;
3101 }
3102
3103 return 0;
3104}
3105
3106static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3107 struct amdgpu_irq_src *src,
3108 unsigned type,
3109 enum amdgpu_interrupt_state state)
3110{
3111 switch (type) {
3112 case AMDGPU_CRTC_IRQ_VBLANK1:
3113 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3114 break;
3115 case AMDGPU_CRTC_IRQ_VBLANK2:
3116 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3117 break;
3118 case AMDGPU_CRTC_IRQ_VBLANK3:
3119 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3120 break;
3121 case AMDGPU_CRTC_IRQ_VBLANK4:
3122 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3123 break;
3124 case AMDGPU_CRTC_IRQ_VBLANK5:
3125 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3126 break;
3127 case AMDGPU_CRTC_IRQ_VBLANK6:
3128 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3129 break;
3130 case AMDGPU_CRTC_IRQ_VLINE1:
3131 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3132 break;
3133 case AMDGPU_CRTC_IRQ_VLINE2:
3134 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3135 break;
3136 case AMDGPU_CRTC_IRQ_VLINE3:
3137 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3138 break;
3139 case AMDGPU_CRTC_IRQ_VLINE4:
3140 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3141 break;
3142 case AMDGPU_CRTC_IRQ_VLINE5:
3143 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3144 break;
3145 case AMDGPU_CRTC_IRQ_VLINE6:
3146 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3147 break;
3148 default:
3149 break;
3150 }
3151 return 0;
3152}
3153
3154static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3155 struct amdgpu_irq_src *source,
3156 struct amdgpu_iv_entry *entry)
3157{
3158 unsigned crtc = entry->src_id - 1;
3159 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3160 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3161
3162 switch (entry->src_data) {
3163 case 0: /* vblank */
3164 if (disp_int & interrupt_status_offsets[crtc].vblank)
3165 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3166 else
3167 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3168
3169 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3170 drm_handle_vblank(adev->ddev, crtc);
3171 }
3172 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3173 break;
3174 case 1: /* vline */
3175 if (disp_int & interrupt_status_offsets[crtc].vline)
3176 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3177 else
3178 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3179
3180 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3181 break;
3182 default:
3183 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3184 break;
3185 }
3186
3187 return 0;
3188}
3189
3190static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3191 struct amdgpu_irq_src *src,
3192 unsigned type,
3193 enum amdgpu_interrupt_state state)
3194{
3195 u32 reg;
3196
3197 if (type >= adev->mode_info.num_crtc) {
3198 DRM_ERROR("invalid pageflip crtc %d\n", type);
3199 return -EINVAL;
3200 }
3201
3202 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3203 if (state == AMDGPU_IRQ_STATE_DISABLE)
3204 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3205 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3206 else
3207 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3208 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3209
3210 return 0;
3211}
3212
3213static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3214 struct amdgpu_irq_src *source,
3215 struct amdgpu_iv_entry *entry)
3216{
3217 unsigned long flags;
3218 unsigned crtc_id;
3219 struct amdgpu_crtc *amdgpu_crtc;
3220 struct amdgpu_flip_work *works;
3221
3222 crtc_id = (entry->src_id - 8) >> 1;
3223 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3224
3225 if (crtc_id >= adev->mode_info.num_crtc) {
3226 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3227 return -EINVAL;
3228 }
3229
3230 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3231 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3232 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3233 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3234
3235 /* IRQ could occur when in initial stage */
3236 if (amdgpu_crtc == NULL)
3237 return 0;
3238
3239 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3240 works = amdgpu_crtc->pflip_works;
3241 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3242 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3243 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3244 amdgpu_crtc->pflip_status,
3245 AMDGPU_FLIP_SUBMITTED);
3246 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3247 return 0;
3248 }
3249
3250 /* page flip completed. clean up */
3251 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3252 amdgpu_crtc->pflip_works = NULL;
3253
3254 /* wakeup usersapce */
3255 if (works->event)
3256 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3257
3258 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3259
3260 drm_crtc_vblank_put(&amdgpu_crtc->base);
3261 schedule_work(&works->unpin_work);
3262
3263 return 0;
3264}
3265
3266static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3267 struct amdgpu_irq_src *source,
3268 struct amdgpu_iv_entry *entry)
3269{
3270 uint32_t disp_int, mask, tmp;
3271 unsigned hpd;
3272
3273 if (entry->src_data >= adev->mode_info.num_hpd) {
3274 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3275 return 0;
3276 }
3277
3278 hpd = entry->src_data;
3279 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3280 mask = interrupt_status_offsets[hpd].hpd;
3281
3282 if (disp_int & mask) {
3283 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3284 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3285 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3286 schedule_work(&adev->hotplug_work);
3287 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3288 }
3289
3290 return 0;
3291
3292}
3293
3294static int dce_v8_0_set_clockgating_state(void *handle,
3295 enum amd_clockgating_state state)
3296{
3297 return 0;
3298}
3299
3300static int dce_v8_0_set_powergating_state(void *handle,
3301 enum amd_powergating_state state)
3302{
3303 return 0;
3304}
3305
3306static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3307 .name = "dce_v8_0",
3308 .early_init = dce_v8_0_early_init,
3309 .late_init = NULL,
3310 .sw_init = dce_v8_0_sw_init,
3311 .sw_fini = dce_v8_0_sw_fini,
3312 .hw_init = dce_v8_0_hw_init,
3313 .hw_fini = dce_v8_0_hw_fini,
3314 .suspend = dce_v8_0_suspend,
3315 .resume = dce_v8_0_resume,
3316 .is_idle = dce_v8_0_is_idle,
3317 .wait_for_idle = dce_v8_0_wait_for_idle,
3318 .soft_reset = dce_v8_0_soft_reset,
3319 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3320 .set_powergating_state = dce_v8_0_set_powergating_state,
3321};
3322
3323static void
3324dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3325 struct drm_display_mode *mode,
3326 struct drm_display_mode *adjusted_mode)
3327{
3328 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3329
3330 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3331
3332 /* need to call this here rather than in prepare() since we need some crtc info */
3333 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3334
3335 /* set scaler clears this on some chips */
3336 dce_v8_0_set_interleave(encoder->crtc, mode);
3337
3338 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3339 dce_v8_0_afmt_enable(encoder, true);
3340 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3341 }
3342}
3343
3344static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3345{
3346 struct amdgpu_device *adev = encoder->dev->dev_private;
3347 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3348 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3349
3350 if ((amdgpu_encoder->active_device &
3351 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3352 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3353 ENCODER_OBJECT_ID_NONE)) {
3354 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3355 if (dig) {
3356 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3357 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3358 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3359 }
3360 }
3361
3362 amdgpu_atombios_scratch_regs_lock(adev, true);
3363
3364 if (connector) {
3365 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3366
3367 /* select the clock/data port if it uses a router */
3368 if (amdgpu_connector->router.cd_valid)
3369 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3370
3371 /* turn eDP panel on for mode set */
3372 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3373 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3374 ATOM_TRANSMITTER_ACTION_POWER_ON);
3375 }
3376
3377 /* this is needed for the pll/ss setup to work correctly in some cases */
3378 amdgpu_atombios_encoder_set_crtc_source(encoder);
3379 /* set up the FMT blocks */
3380 dce_v8_0_program_fmt(encoder);
3381}
3382
3383static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3384{
3385 struct drm_device *dev = encoder->dev;
3386 struct amdgpu_device *adev = dev->dev_private;
3387
3388 /* need to call this here as we need the crtc set up */
3389 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3390 amdgpu_atombios_scratch_regs_lock(adev, false);
3391}
3392
3393static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3394{
3395 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3396 struct amdgpu_encoder_atom_dig *dig;
3397
3398 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3399
3400 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3401 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3402 dce_v8_0_afmt_enable(encoder, false);
3403 dig = amdgpu_encoder->enc_priv;
3404 dig->dig_encoder = -1;
3405 }
3406 amdgpu_encoder->active_device = 0;
3407}
3408
3409/* these are handled by the primary encoders */
3410static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3411{
3412
3413}
3414
3415static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3416{
3417
3418}
3419
3420static void
3421dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3422 struct drm_display_mode *mode,
3423 struct drm_display_mode *adjusted_mode)
3424{
3425
3426}
3427
3428static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3429{
3430
3431}
3432
3433static void
3434dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3435{
3436
3437}
3438
3439static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3440 .dpms = dce_v8_0_ext_dpms,
3441 .prepare = dce_v8_0_ext_prepare,
3442 .mode_set = dce_v8_0_ext_mode_set,
3443 .commit = dce_v8_0_ext_commit,
3444 .disable = dce_v8_0_ext_disable,
3445 /* no detect for TMDS/LVDS yet */
3446};
3447
3448static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3449 .dpms = amdgpu_atombios_encoder_dpms,
3450 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3451 .prepare = dce_v8_0_encoder_prepare,
3452 .mode_set = dce_v8_0_encoder_mode_set,
3453 .commit = dce_v8_0_encoder_commit,
3454 .disable = dce_v8_0_encoder_disable,
3455 .detect = amdgpu_atombios_encoder_dig_detect,
3456};
3457
3458static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3459 .dpms = amdgpu_atombios_encoder_dpms,
3460 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3461 .prepare = dce_v8_0_encoder_prepare,
3462 .mode_set = dce_v8_0_encoder_mode_set,
3463 .commit = dce_v8_0_encoder_commit,
3464 .detect = amdgpu_atombios_encoder_dac_detect,
3465};
3466
3467static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3468{
3469 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3470 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3471 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3472 kfree(amdgpu_encoder->enc_priv);
3473 drm_encoder_cleanup(encoder);
3474 kfree(amdgpu_encoder);
3475}
3476
3477static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3478 .destroy = dce_v8_0_encoder_destroy,
3479};
3480
3481static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3482 uint32_t encoder_enum,
3483 uint32_t supported_device,
3484 u16 caps)
3485{
3486 struct drm_device *dev = adev->ddev;
3487 struct drm_encoder *encoder;
3488 struct amdgpu_encoder *amdgpu_encoder;
3489
3490 /* see if we already added it */
3491 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3492 amdgpu_encoder = to_amdgpu_encoder(encoder);
3493 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3494 amdgpu_encoder->devices |= supported_device;
3495 return;
3496 }
3497
3498 }
3499
3500 /* add a new one */
3501 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3502 if (!amdgpu_encoder)
3503 return;
3504
3505 encoder = &amdgpu_encoder->base;
3506 switch (adev->mode_info.num_crtc) {
3507 case 1:
3508 encoder->possible_crtcs = 0x1;
3509 break;
3510 case 2:
3511 default:
3512 encoder->possible_crtcs = 0x3;
3513 break;
3514 case 4:
3515 encoder->possible_crtcs = 0xf;
3516 break;
3517 case 6:
3518 encoder->possible_crtcs = 0x3f;
3519 break;
3520 }
3521
3522 amdgpu_encoder->enc_priv = NULL;
3523
3524 amdgpu_encoder->encoder_enum = encoder_enum;
3525 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3526 amdgpu_encoder->devices = supported_device;
3527 amdgpu_encoder->rmx_type = RMX_OFF;
3528 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3529 amdgpu_encoder->is_ext_encoder = false;
3530 amdgpu_encoder->caps = caps;
3531
3532 switch (amdgpu_encoder->encoder_id) {
3533 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3534 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3535 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3536 DRM_MODE_ENCODER_DAC, NULL);
3537 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3538 break;
3539 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3540 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3541 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3542 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3543 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3544 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3545 amdgpu_encoder->rmx_type = RMX_FULL;
3546 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3547 DRM_MODE_ENCODER_LVDS, NULL);
3548 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3549 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3550 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3551 DRM_MODE_ENCODER_DAC, NULL);
3552 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3553 } else {
3554 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3555 DRM_MODE_ENCODER_TMDS, NULL);
3556 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3557 }
3558 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3559 break;
3560 case ENCODER_OBJECT_ID_SI170B:
3561 case ENCODER_OBJECT_ID_CH7303:
3562 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3563 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3564 case ENCODER_OBJECT_ID_TITFP513:
3565 case ENCODER_OBJECT_ID_VT1623:
3566 case ENCODER_OBJECT_ID_HDMI_SI1930:
3567 case ENCODER_OBJECT_ID_TRAVIS:
3568 case ENCODER_OBJECT_ID_NUTMEG:
3569 /* these are handled by the primary encoders */
3570 amdgpu_encoder->is_ext_encoder = true;
3571 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3572 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3573 DRM_MODE_ENCODER_LVDS, NULL);
3574 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3575 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3576 DRM_MODE_ENCODER_DAC, NULL);
3577 else
3578 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3579 DRM_MODE_ENCODER_TMDS, NULL);
3580 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3581 break;
3582 }
3583}
3584
3585static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3586 .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3587 .bandwidth_update = &dce_v8_0_bandwidth_update,
3588 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3589 .vblank_wait = &dce_v8_0_vblank_wait,
3590 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3591 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3592 .hpd_sense = &dce_v8_0_hpd_sense,
3593 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3594 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3595 .page_flip = &dce_v8_0_page_flip,
3596 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3597 .add_encoder = &dce_v8_0_encoder_add,
3598 .add_connector = &amdgpu_connector_add,
3599 .stop_mc_access = &dce_v8_0_stop_mc_access,
3600 .resume_mc_access = &dce_v8_0_resume_mc_access,
3601};
3602
3603static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3604{
3605 if (adev->mode_info.funcs == NULL)
3606 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3607}
3608
3609static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3610 .set = dce_v8_0_set_crtc_interrupt_state,
3611 .process = dce_v8_0_crtc_irq,
3612};
3613
3614static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3615 .set = dce_v8_0_set_pageflip_interrupt_state,
3616 .process = dce_v8_0_pageflip_irq,
3617};
3618
3619static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3620 .set = dce_v8_0_set_hpd_interrupt_state,
3621 .process = dce_v8_0_hpd_irq,
3622};
3623
3624static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3625{
3626 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3627 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3628
3629 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3630 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3631
3632 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3633 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3634}
3635
3636const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3637{
3638 .type = AMD_IP_BLOCK_TYPE_DCE,
3639 .major = 8,
3640 .minor = 0,
3641 .rev = 0,
3642 .funcs = &dce_v8_0_ip_funcs,
3643};
3644
3645const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3646{
3647 .type = AMD_IP_BLOCK_TYPE_DCE,
3648 .major = 8,
3649 .minor = 1,
3650 .rev = 0,
3651 .funcs = &dce_v8_0_ip_funcs,
3652};
3653
3654const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3655{
3656 .type = AMD_IP_BLOCK_TYPE_DCE,
3657 .major = 8,
3658 .minor = 2,
3659 .rev = 0,
3660 .funcs = &dce_v8_0_ip_funcs,
3661};
3662
3663const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3664{
3665 .type = AMD_IP_BLOCK_TYPE_DCE,
3666 .major = 8,
3667 .minor = 3,
3668 .rev = 0,
3669 .funcs = &dce_v8_0_ip_funcs,
3670};
3671
3672const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3673{
3674 .type = AMD_IP_BLOCK_TYPE_DCE,
3675 .major = 8,
3676 .minor = 5,
3677 .rev = 0,
3678 .funcs = &dce_v8_0_ip_funcs,
3679};