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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree for the ARM Integrator/AP platform
4 */
5
6/dts-v1/;
7#include "integrator.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12 model = "ARM Integrator/AP";
13 compatible = "arm,integrator-ap";
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 /*
22 * Since the board has pluggable CPU modules, we
23 * cannot define a proper compatible here. Let the
24 * boot loader fill in the apropriate compatible
25 * string if necessary.
26 */
27 /* compatible = "arm,arm926ej-s"; */
28 reg = <0>;
29 /*
30 * The documentation in ARM DUI 0138E page 3-12 states
31 * that the maximum frequency for this clock is 200 MHz
32 * but painful trial-and-error has proved to me that it
33 * is actually just hanging the system above 71 MHz.
34 * Sad but true.
35 */
36 /* kHz uV */
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
44 clocks = <&cmosc>;
45 clock-names = "cpu";
46 clock-latency = <1000000>; /* 1 ms */
47 };
48 };
49
50 aliases {
51 arm,timer-primary = &timer2;
52 arm,timer-secondary = &timer1;
53 };
54
55 chosen {
56 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
57 };
58
59 /* 24 MHz chrystal on the Integrator/AP development board */
60 xtal24mhz: xtal24mhz@24M {
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 };
65
66 pclk: pclk@0 {
67 #clock-cells = <0>;
68 compatible = "fixed-factor-clock";
69 clock-div = <1>;
70 clock-mult = <1>;
71 clocks = <&xtal24mhz>;
72 };
73
74 /* The UART clock is 14.74 MHz divided by an ICS525 */
75 uartclk: uartclk@14.74M {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <14745600>;
79 clocks = <&xtal24mhz>;
80 };
81
82 core-module@10000000 {
83 /* 24 MHz chrystal on the core module */
84 cm24mhz: cm24mhz@24M {
85 #clock-cells = <0>;
86 compatible = "fixed-clock";
87 clock-frequency = <24000000>;
88 };
89
90 /* Oscillator on the core module, clocks the CPU core */
91 cmosc: cmosc@24M {
92 compatible = "arm,syscon-icst525-integratorap-cm";
93 #clock-cells = <0>;
94 lock-offset = <0x14>;
95 vco-offset = <0x08>;
96 clocks = <&cm24mhz>;
97 };
98
99 /* Auxilary oscillator on the core module, 32.369MHz at boot */
100 auxosc: auxosc@24M {
101 compatible = "arm,syscon-icst525";
102 #clock-cells = <0>;
103 lock-offset = <0x14>;
104 vco-offset = <0x1c>;
105 clocks = <&cm24mhz>;
106 };
107 };
108
109 syscon {
110 compatible = "arm,integrator-ap-syscon", "syscon";
111 reg = <0x11000000 0x100>;
112
113 /*
114 * SYSCLK clocks PCIv3 bridge, system controller and the
115 * logic modules.
116 */
117 sysclk: apsys@24M {
118 compatible = "arm,syscon-icst525-integratorap-sys";
119 #clock-cells = <0>;
120 lock-offset = <0x1c>;
121 vco-offset = <0x04>;
122 clocks = <&xtal24mhz>;
123 };
124
125 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
126 pciclk: pciclk@24M {
127 compatible = "arm,syscon-icst525-integratorap-pci";
128 #clock-cells = <0>;
129 lock-offset = <0x1c>;
130 vco-offset = <0x04>;
131 clocks = <&xtal24mhz>;
132 };
133 };
134
135 timer0: timer@13000000 {
136 compatible = "arm,integrator-timer";
137 clocks = <&xtal24mhz>;
138 };
139
140 timer1: timer@13000100 {
141 compatible = "arm,integrator-timer";
142 clocks = <&xtal24mhz>;
143 };
144
145 timer2: timer@13000200 {
146 compatible = "arm,integrator-timer";
147 clocks = <&xtal24mhz>;
148 };
149
150 pic: pic@14000000 {
151 valid-mask = <0x003fffff>;
152 };
153
154 pci: pciv3@62000000 {
155 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
156 #interrupt-cells = <1>;
157 #size-cells = <2>;
158 #address-cells = <3>;
159 /* Bridge registers and config access space */
160 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
161 interrupt-parent = <&pic>;
162 interrupts = <17>; /* Bus error IRQ */
163 clocks = <&pciclk>;
164 bus-range = <0x00 0xff>;
165 ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
166 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
167 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
168 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
169 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
170 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
171 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
172 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
173 0x02000000 0 0x80000000 /* Core module alias memory */
174 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
175 interrupt-map-mask = <0xf800 0 0 0x7>;
176 interrupt-map = <
177 /* IDSEL 9 */
178 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
179 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
180 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
181 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
182 /* IDSEL 10 */
183 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
184 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
185 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
186 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
187 /* IDSEL 11 */
188 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
189 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
190 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
191 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
192 /* IDSEL 12 */
193 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
194 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
195 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
196 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
197 >;
198 };
199
200 fpga {
201 /*
202 * The Integator/AP predates the idea to have magic numbers
203 * identifying the PrimeCell in hardware, thus we have to
204 * supply these from the device tree.
205 */
206 rtc: rtc@15000000 {
207 compatible = "arm,pl030", "arm,primecell";
208 arm,primecell-periphid = <0x00041030>;
209 clocks = <&pclk>;
210 clock-names = "apb_pclk";
211 };
212
213 uart0: uart@16000000 {
214 compatible = "arm,pl010", "arm,primecell";
215 arm,primecell-periphid = <0x00041010>;
216 clocks = <&uartclk>, <&pclk>;
217 clock-names = "uartclk", "apb_pclk";
218 };
219
220 uart1: uart@17000000 {
221 compatible = "arm,pl010", "arm,primecell";
222 arm,primecell-periphid = <0x00041010>;
223 clocks = <&uartclk>, <&pclk>;
224 clock-names = "uartclk", "apb_pclk";
225 };
226
227 kmi0: kmi@18000000 {
228 compatible = "arm,pl050", "arm,primecell";
229 arm,primecell-periphid = <0x00041050>;
230 clocks = <&xtal24mhz>, <&pclk>;
231 clock-names = "KMIREFCLK", "apb_pclk";
232 };
233
234 kmi1: kmi@19000000 {
235 compatible = "arm,pl050", "arm,primecell";
236 arm,primecell-periphid = <0x00041050>;
237 clocks = <&xtal24mhz>, <&pclk>;
238 clock-names = "KMIREFCLK", "apb_pclk";
239 };
240 };
241
242 /*
243 * Logic module bus, we support up to 4 logical modules
244 * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
245 * and use interrupts 9, 10, 11 and 12 respectively.
246 */
247 bus@c0000000 {
248 compatible = "arm,integrator-ap-lm";
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges = <0xc0000000 0xc0000000 0x40000000>;
252 dma-ranges;
253
254 lm0: bus@c0000000 {
255 compatible = "simple-bus";
256 ranges = <0x00000000 0xc0000000 0x10000000>;
257 dma-ranges = <0x00000000 0x80000000 0x10000000>;
258 reg = <0xc0000000 0x10000000>;
259 #address-cells = <1>;
260 #size-cells = <1>;
261 };
262 lm1: bus@d0000000 {
263 compatible = "simple-bus";
264 ranges = <0x00000000 0xd0000000 0x10000000>;
265 dma-ranges = <0x00000000 0x80000000 0x10000000>;
266 reg = <0xd0000000 0x10000000>;
267 #address-cells = <1>;
268 #size-cells = <1>;
269 };
270 lm2: bus@e0000000 {
271 compatible = "simple-bus";
272 ranges = <0x00000000 0xe0000000 0x10000000>;
273 dma-ranges = <0x00000000 0x80000000 0x10000000>;
274 reg = <0xe0000000 0x10000000>;
275 #address-cells = <1>;
276 #size-cells = <1>;
277 };
278 lm3: bus@f0000000 {
279 compatible = "simple-bus";
280 ranges = <0x00000000 0xf0000000 0x10000000>;
281 dma-ranges = <0x00000000 0x80000000 0x10000000>;
282 reg = <0xf0000000 0x10000000>;
283 #address-cells = <1>;
284 #size-cells = <1>;
285 };
286 };
287};
1/*
2 * Device Tree for the ARM Integrator/AP platform
3 */
4
5/dts-v1/;
6/include/ "integrator.dtsi"
7
8/ {
9 model = "ARM Integrator/AP";
10 compatible = "arm,integrator-ap";
11 dma-ranges = <0x80000000 0x0 0x80000000>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 device_type = "cpu";
19 /*
20 * Since the board has pluggable CPU modules, we
21 * cannot define a proper compatible here. Let the
22 * boot loader fill in the apropriate compatible
23 * string if necessary.
24 */
25 /* compatible = "arm,arm926ej-s"; */
26 reg = <0>;
27 /*
28 * The documentation in ARM DUI 0138E page 3-12 states
29 * that the maximum frequency for this clock is 200 MHz
30 * but painful trial-and-error has proved to me that it
31 * is actually just hanging the system above 71 MHz.
32 * Sad but true.
33 */
34 /* kHz uV */
35 operating-points = <71000 0
36 66000 0
37 60000 0
38 48000 0
39 36000 0
40 24000 0
41 12000 0>;
42 clocks = <&cmosc>;
43 clock-names = "cpu";
44 clock-latency = <1000000>; /* 1 ms */
45 };
46 };
47
48 aliases {
49 arm,timer-primary = &timer2;
50 arm,timer-secondary = &timer1;
51 };
52
53 chosen {
54 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
55 };
56
57 /* 24 MHz chrystal on the Integrator/AP development board */
58 xtal24mhz: xtal24mhz@24M {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
62 };
63
64 pclk: pclk@0 {
65 #clock-cells = <0>;
66 compatible = "fixed-factor-clock";
67 clock-div = <1>;
68 clock-mult = <1>;
69 clocks = <&xtal24mhz>;
70 };
71
72 /* The UART clock is 14.74 MHz divided by an ICS525 */
73 uartclk: uartclk@14.74M {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <14745600>;
77 clocks = <&xtal24mhz>;
78 };
79
80 core-module@10000000 {
81 /* 24 MHz chrystal on the core module */
82 cm24mhz: cm24mhz@24M {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <24000000>;
86 };
87
88 /* Oscillator on the core module, clocks the CPU core */
89 cmosc: cmosc@24M {
90 compatible = "arm,syscon-icst525-integratorap-cm";
91 #clock-cells = <0>;
92 lock-offset = <0x14>;
93 vco-offset = <0x08>;
94 clocks = <&cm24mhz>;
95 };
96
97 /* Auxilary oscillator on the core module, 32.369MHz at boot */
98 auxosc: auxosc@24M {
99 compatible = "arm,syscon-icst525";
100 #clock-cells = <0>;
101 lock-offset = <0x14>;
102 vco-offset = <0x1c>;
103 clocks = <&cm24mhz>;
104 };
105 };
106
107 syscon {
108 compatible = "arm,integrator-ap-syscon", "syscon";
109 reg = <0x11000000 0x100>;
110 interrupt-parent = <&pic>;
111 /* These are the logical module IRQs */
112 interrupts = <9>, <10>, <11>, <12>;
113
114 /*
115 * SYSCLK clocks PCIv3 bridge, system controller and the
116 * logic modules.
117 */
118 sysclk: apsys@24M {
119 compatible = "arm,syscon-icst525-integratorap-sys";
120 #clock-cells = <0>;
121 lock-offset = <0x1c>;
122 vco-offset = <0x04>;
123 clocks = <&xtal24mhz>;
124 };
125
126 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
127 pciclk: pciclk@24M {
128 compatible = "arm,syscon-icst525-integratorap-pci";
129 #clock-cells = <0>;
130 lock-offset = <0x1c>;
131 vco-offset = <0x04>;
132 clocks = <&xtal24mhz>;
133 };
134 };
135
136 timer0: timer@13000000 {
137 compatible = "arm,integrator-timer";
138 clocks = <&xtal24mhz>;
139 };
140
141 timer1: timer@13000100 {
142 compatible = "arm,integrator-timer";
143 clocks = <&xtal24mhz>;
144 };
145
146 timer2: timer@13000200 {
147 compatible = "arm,integrator-timer";
148 clocks = <&xtal24mhz>;
149 };
150
151 pic: pic@14000000 {
152 valid-mask = <0x003fffff>;
153 };
154
155 pci: pciv3@62000000 {
156 compatible = "v3,v360epc-pci";
157 #interrupt-cells = <1>;
158 #size-cells = <2>;
159 #address-cells = <3>;
160 reg = <0x62000000 0x10000>;
161 interrupt-parent = <&pic>;
162 interrupts = <17>; /* Bus error IRQ */
163 ranges = <0x00000000 0 0x61000000 /* config space */
164 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
165 0x01000000 0 0x0 /* I/O space */
166 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
167 0x02000000 0 0x00000000 /* non-prefectable memory */
168 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
169 0x42000000 0 0x10000000 /* prefetchable memory */
170 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
171 interrupt-map-mask = <0xf800 0 0 0x7>;
172 interrupt-map = <
173 /* IDSEL 9 */
174 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
175 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
176 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
177 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
178 /* IDSEL 10 */
179 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
180 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
181 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
182 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
183 /* IDSEL 11 */
184 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
185 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
186 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
187 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
188 /* IDSEL 12 */
189 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
190 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
191 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
192 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
193 >;
194 };
195
196 fpga {
197 /*
198 * The Integator/AP predates the idea to have magic numbers
199 * identifying the PrimeCell in hardware, thus we have to
200 * supply these from the device tree.
201 */
202 rtc: rtc@15000000 {
203 compatible = "arm,pl030", "arm,primecell";
204 arm,primecell-periphid = <0x00041030>;
205 clocks = <&pclk>;
206 clock-names = "apb_pclk";
207 };
208
209 uart0: uart@16000000 {
210 compatible = "arm,pl010", "arm,primecell";
211 arm,primecell-periphid = <0x00041010>;
212 clocks = <&uartclk>, <&pclk>;
213 clock-names = "uartclk", "apb_pclk";
214 };
215
216 uart1: uart@17000000 {
217 compatible = "arm,pl010", "arm,primecell";
218 arm,primecell-periphid = <0x00041010>;
219 clocks = <&uartclk>, <&pclk>;
220 clock-names = "uartclk", "apb_pclk";
221 };
222
223 kmi0: kmi@18000000 {
224 compatible = "arm,pl050", "arm,primecell";
225 arm,primecell-periphid = <0x00041050>;
226 clocks = <&xtal24mhz>, <&pclk>;
227 clock-names = "KMIREFCLK", "apb_pclk";
228 };
229
230 kmi1: kmi@19000000 {
231 compatible = "arm,pl050", "arm,primecell";
232 arm,primecell-periphid = <0x00041050>;
233 clocks = <&xtal24mhz>, <&pclk>;
234 clock-names = "KMIREFCLK", "apb_pclk";
235 };
236 };
237};