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v5.14.15
  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Device Tree file for Marvell Armada 390 Development Board
  4 * (DB-88F6920)
  5 *
  6 * Copyright (C) 2016 Marvell
  7 *
  8 * Grzegorz Jaszczyk <jaz@semihalf.com>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  9 */
 10
 11/dts-v1/;
 12#include "armada-390.dtsi"
 13
 14/ {
 15	model = "Marvell Armada 390 Development Board";
 16	compatible = "marvell,a390-db", "marvell,armada390";
 17
 18	chosen {
 19		stdout-path = "serial0:115200n8";
 20	};
 21
 22	memory {
 23		device_type = "memory";
 24		reg = <0x00000000 0x80000000>; /* 2 GB */
 25	};
 26
 27	soc {
 28		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 29			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
 30
 31		internal-regs {
 32			i2c@11000 {
 33				status = "okay";
 34				clock-frequency = <100000>;
 35
 36				eeprom@50 {
 37					compatible = "atmel,24c64";
 38					reg = <0x50>;
 39				};
 40			};
 41
 42			/* CON104 */
 43			serial@12000 {
 44				status = "okay";
 45			};
 46
 47			/* CON97 */
 48			usb@58000 {
 49				status = "okay";
 50			};
 51
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 52			/* CON98 */
 53			usb3@f8000 {
 54				status = "okay";
 55			};
 56		};
 57
 58		pcie {
 59			status = "okay";
 60
 61			/* CON30 */
 62			pcie@1,0 {
 63				status = "okay";
 64			};
 65
 66			/* CON44 */
 67			pcie@2,0 {
 68				status = "okay";
 69			};
 70
 71			/* CON61 */
 72			pcie@3,0 {
 73				status = "okay";
 74			};
 75		};
 76	};
 77};
 78
 79&spi1 {
 80	status = "okay";
 81	pinctrl-0 = <&spi1_pins>;
 82	pinctrl-names = "default";
 83
 84	spi-flash@1 {
 85		#address-cells = <1>;
 86		#size-cells = <1>;
 87		compatible = "n25q128a13",
 88			     "jedec,spi-nor";
 89		reg = <0>; /* Chip select 0 */
 90		spi-max-frequency = <108000000>;
 91
 92		partitions {
 93			compatible = "fixed-partitions";
 94			#address-cells = <1>;
 95			#size-cells = <1>;
 96
 97			partition@0 {
 98				label = "U-Boot";
 99				reg = <0 0x400000>;
100			};
101			partition@400000 {
102				label = "Filesystem";
103				reg = <0x400000 0xc00000>;
104			};
105		};
106	};
107};
108
109&nand_controller {
110	status = "okay";
111	pinctrl-0 = <&nand_pins>;
112	pinctrl-names = "default";
113
114	nand@0 {
115		reg = <0>;
116		label = "pxa3xx_nand-0";
117		nand-rb = <0>;
118		marvell,nand-keep-config;
119		nand-on-flash-bbt;
120		nand-ecc-strength = <8>;
121		nand-ecc-step-size = <512>;
122
123		partitions {
124			compatible = "fixed-partitions";
125			#address-cells = <1>;
126			#size-cells = <1>;
127
128			partition@0 {
129				label = "U-Boot";
130				reg = <0 0x800000>;
131			};
132			partition@800000 {
133				label = "Linux";
134				reg = <0x800000 0x800000>;
135			};
136			partition@1000000 {
137				label = "Filesystem";
138				reg = <0x1000000 0x3f000000>;
139			};
140		};
141	};
142};
v4.10.11
 
  1/*
  2 * Device Tree file for Marvell Armada 390 Development Board
  3 * (DB-88F6920)
  4 *
  5 * Copyright (C) 2016 Marvell
  6 *
  7 * Grzegorz Jaszczyk <jaz@semihalf.com>
  8 *
  9 * This file is dual-licensed: you can use it either under the terms
 10 * of the GPL or the X11 license, at your option. Note that this dual
 11 * licensing only applies to this file, and not this project as a
 12 * whole.
 13 *
 14 *  a) This file is free software; you can redistribute it and/or
 15 *     modify it under the terms of the GNU General Public License as
 16 *     published by the Free Software Foundation; either version 2 of the
 17 *     License, or (at your option) any later version.
 18 *
 19 *     This file is distributed in the hope that it will be useful
 20 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 21 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 22 *     GNU General Public License for more details.
 23 *
 24 * Or, alternatively
 25 *
 26 *  b) Permission is hereby granted, free of charge, to any person
 27 *     obtaining a copy of this software and associated documentation
 28 *     files (the "Software"), to deal in the Software without
 29 *     restriction, including without limitation the rights to use
 30 *     copy, modify, merge, publish, distribute, sublicense, and/or
 31 *     sell copies of the Software, and to permit persons to whom the
 32 *     Software is furnished to do so, subject to the following
 33 *     conditions:
 34 *
 35 *     The above copyright notice and this permission notice shall be
 36 *     included in all copies or substantial portions of the Software.
 37 *
 38 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 45 *     OTHER DEALINGS IN THE SOFTWARE.
 46 */
 47
 48/dts-v1/;
 49#include "armada-390.dtsi"
 50
 51/ {
 52	model = "Marvell Armada 390 Development Board";
 53	compatible = "marvell,a390-db", "marvell,armada390";
 54
 55	chosen {
 56		stdout-path = "serial0:115200n8";
 57	};
 58
 59	memory {
 60		device_type = "memory";
 61		reg = <0x00000000 0x80000000>; /* 2 GB */
 62	};
 63
 64	soc {
 65		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 66			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
 67
 68		internal-regs {
 69			i2c@11000 {
 70				status = "okay";
 71				clock-frequency = <100000>;
 72
 73				eeprom@50 {
 74					compatible = "atmel,24c64";
 75					reg = <0x50>;
 76				};
 77			};
 78
 79			/* CON104 */
 80			serial@12000 {
 81				status = "okay";
 82			};
 83
 84			/* CON97 */
 85			usb@58000 {
 86				status = "okay";
 87			};
 88
 89			flash@d0000 {
 90				status = "okay";
 91				pinctrl-0 = <&nand_pins>;
 92				pinctrl-names = "default";
 93				num-cs = <1>;
 94				marvell,nand-keep-config;
 95				marvell,nand-enable-arbiter;
 96				nand-on-flash-bbt;
 97				nand-ecc-strength = <8>;
 98				nand-ecc-step-size = <512>;
 99
100				partitions {
101					compatible = "fixed-partitions";
102					#address-cells = <1>;
103					#size-cells = <1>;
104
105					partition@0 {
106						label = "U-Boot";
107						reg = <0 0x800000>;
108					};
109					partition@800000 {
110						label = "Linux";
111						reg = <0x800000 0x800000>;
112					};
113					partition@1000000 {
114						label = "Filesystem";
115						reg = <0x1000000 0x3f000000>;
116					};
117				};
118			};
119
120			/* CON98 */
121			usb3@f8000 {
122				status = "okay";
123			};
124		};
125
126		pcie-controller {
127			status = "okay";
128
129			/* CON30 */
130			pcie@1,0 {
131				status = "okay";
132			};
133
134			/* CON44 */
135			pcie@2,0 {
136				status = "okay";
137			};
138
139			/* CON61 */
140			pcie@3,0 {
141				status = "okay";
142			};
143		};
144	};
145};
146
147&spi1 {
148	status = "okay";
149	pinctrl-0 = <&spi1_pins>;
150	pinctrl-names = "default";
151
152	spi-flash@1 {
153		#address-cells = <1>;
154		#size-cells = <1>;
155		compatible = "n25q128a13",
156			     "jedec,spi-nor";
157		reg = <0>; /* Chip select 0 */
158		spi-max-frequency = <108000000>;
159
160		partitions {
161			compatible = "fixed-partitions";
162			#address-cells = <1>;
163			#size-cells = <1>;
164
165			partition@0 {
166				label = "U-Boot";
167				reg = <0 0x400000>;
168			};
169			partition@400000 {
170				label = "Filesystem";
171				reg = <0x400000 0xc00000>;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
172			};
173		};
174	};
175};