1/*
  2 * Copyright © 2013 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21 * DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors:
 24 *	Shobhit Kumar <shobhit.kumar@intel.com>
 25 *	Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
 26 */
 27
 28#include <linux/kernel.h>
 29
 30#include "i915_drv.h"
 31#include "intel_de.h"
 32#include "intel_display_types.h"
 33#include "intel_dsi.h"
 34#include "intel_sideband.h"
 35
 36static const u16 lfsr_converts[] = {
 37	426, 469, 234, 373, 442, 221, 110, 311, 411,		/* 62 - 70 */
 38	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
 39	106, 53, 282, 397, 454, 227, 113, 56, 284, 142,		/* 81 - 90 */
 40	71, 35, 273, 136, 324, 418, 465, 488, 500, 506		/* 91 - 100 */
 41};
 42
 43/* Get DSI clock from pixel clock */
 44static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
 45			     int lane_count)
 46{
 47	u32 dsi_clk_khz;
 48	u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
 49
 50	/* DSI data rate = pixel clock * bits per pixel / lane count
 51	   pixel clock is converted from KHz to Hz */
 52	dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
 53
 54	return dsi_clk_khz;
 55}
 56
 57static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
 58			struct intel_crtc_state *config,
 59			int target_dsi_clk)
 60{
 61	unsigned int m_min, m_max, p_min = 2, p_max = 6;
 62	unsigned int m, n, p;
 63	unsigned int calc_m, calc_p;
 64	int delta, ref_clk;
 65
 66	/* target_dsi_clk is expected in kHz */
 67	if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
 68		drm_err(&dev_priv->drm, "DSI CLK Out of Range\n");
 69		return -ECHRNG;
 70	}
 71
 72	if (IS_CHERRYVIEW(dev_priv)) {
 73		ref_clk = 100000;
 74		n = 4;
 75		m_min = 70;
 76		m_max = 96;
 77	} else {
 78		ref_clk = 25000;
 79		n = 1;
 80		m_min = 62;
 81		m_max = 92;
 82	}
 83
 84	calc_p = p_min;
 85	calc_m = m_min;
 86	delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
 87
 88	for (m = m_min; m <= m_max && delta; m++) {
 89		for (p = p_min; p <= p_max && delta; p++) {
 90			/*
 91			 * Find the optimal m and p divisors with minimal delta
 92			 * +/- the required clock
 93			 */
 94			int calc_dsi_clk = (m * ref_clk) / (p * n);
 95			int d = abs(target_dsi_clk - calc_dsi_clk);
 96			if (d < delta) {
 97				delta = d;
 98				calc_m = m;
 99				calc_p = p;
100			}
101		}
102	}
103
104	/* register has log2(N1), this works fine for powers of two */
105	config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
106	config->dsi_pll.div =
107		(ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
108		(u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
109
110	return 0;
111}
112
113/*
114 * XXX: The muxing and gating is hard coded for now. Need to add support for
115 * sharing PLLs with two DSI outputs.
116 */
117int vlv_dsi_pll_compute(struct intel_encoder *encoder,
118			struct intel_crtc_state *config)
119{
120	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
121	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
122	int ret;
123	u32 dsi_clk;
124
125	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
126				    intel_dsi->lane_count);
127
128	ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
129	if (ret) {
130		drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n");
131		return ret;
132	}
133
134	if (intel_dsi->ports & (1 << PORT_A))
135		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
136
137	if (intel_dsi->ports & (1 << PORT_C))
138		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
139
140	config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
141
142	drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n",
143		    config->dsi_pll.div, config->dsi_pll.ctrl);
144
145	return 0;
146}
147
148void vlv_dsi_pll_enable(struct intel_encoder *encoder,
149			const struct intel_crtc_state *config)
150{
151	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
152
153	drm_dbg_kms(&dev_priv->drm, "\n");
154
155	vlv_cck_get(dev_priv);
156
157	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
158	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
159	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
160		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
161
162	/* wait at least 0.5 us after ungating before enabling VCO,
163	 * allow hrtimer subsystem optimization by relaxing timing
164	 */
165	usleep_range(10, 50);
166
167	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
168
169	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
170						DSI_PLL_LOCK, 20)) {
171
172		vlv_cck_put(dev_priv);
173		drm_err(&dev_priv->drm, "DSI PLL lock failed\n");
174		return;
175	}
176	vlv_cck_put(dev_priv);
177
178	drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");
179}
180
181void vlv_dsi_pll_disable(struct intel_encoder *encoder)
182{
183	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
184	u32 tmp;
185
186	drm_dbg_kms(&dev_priv->drm, "\n");
187
188	vlv_cck_get(dev_priv);
189
190	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
191	tmp &= ~DSI_PLL_VCO_EN;
192	tmp |= DSI_PLL_LDO_GATE;
193	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
194
195	vlv_cck_put(dev_priv);
196}
197
198bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
199{
200	bool enabled;
201	u32 val;
202	u32 mask;
203
204	mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
205	val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
206	enabled = (val & mask) == mask;
207
208	if (!enabled)
209		return false;
210
211	/*
212	 * Dividers must be programmed with valid values. As per BSEPC, for
213	 * GEMINLAKE only PORT A divider values are checked while for BXT
214	 * both divider values are validated. Check this here for
215	 * paranoia, since BIOS is known to misconfigure PLLs in this way at
216	 * times, and since accessing DSI registers with invalid dividers
217	 * causes a system hang.
218	 */
219	val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);
220	if (IS_GEMINILAKE(dev_priv)) {
221		if (!(val & BXT_DSIA_16X_MASK)) {
222			drm_dbg(&dev_priv->drm,
223				"Invalid PLL divider (%08x)\n", val);
224			enabled = false;
225		}
226	} else {
227		if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
228			drm_dbg(&dev_priv->drm,
229				"Invalid PLL divider (%08x)\n", val);
230			enabled = false;
231		}
232	}
233
234	return enabled;
235}
236
237void bxt_dsi_pll_disable(struct intel_encoder *encoder)
238{
239	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
240	u32 val;
241
242	drm_dbg_kms(&dev_priv->drm, "\n");
243
244	val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
245	val &= ~BXT_DSI_PLL_DO_ENABLE;
246	intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val);
247
248	/*
249	 * PLL lock should deassert within 200us.
250	 * Wait up to 1ms before timing out.
251	 */
252	if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE,
253				    BXT_DSI_PLL_LOCKED, 1))
254		drm_err(&dev_priv->drm,
255			"Timeout waiting for PLL lock deassertion\n");
256}
257
258u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
259		     struct intel_crtc_state *config)
260{
261	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
262	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
263	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
264	u32 dsi_clock, pclk;
265	u32 pll_ctl, pll_div;
266	u32 m = 0, p = 0, n;
267	int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
268	int i;
269
270	drm_dbg_kms(&dev_priv->drm, "\n");
271
272	vlv_cck_get(dev_priv);
273	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
274	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
275	vlv_cck_put(dev_priv);
276
277	config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
278	config->dsi_pll.div = pll_div;
279
280	/* mask out other bits and extract the P1 divisor */
281	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
282	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
283
284	/* N1 divisor */
285	n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
286	n = 1 << n; /* register has log2(N1) */
287
288	/* mask out the other bits and extract the M1 divisor */
289	pll_div &= DSI_PLL_M1_DIV_MASK;
290	pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
291
292	while (pll_ctl) {
293		pll_ctl = pll_ctl >> 1;
294		p++;
295	}
296	p--;
297
298	if (!p) {
299		drm_err(&dev_priv->drm, "wrong P1 divisor\n");
300		return 0;
301	}
302
303	for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
304		if (lfsr_converts[i] == pll_div)
305			break;
306	}
307
308	if (i == ARRAY_SIZE(lfsr_converts)) {
309		drm_err(&dev_priv->drm, "wrong m_seed programmed\n");
310		return 0;
311	}
312
313	m = i + 62;
314
315	dsi_clock = (m * refclk) / (p * n);
316
317	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
318
319	return pclk;
320}
321
322u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
323		     struct intel_crtc_state *config)
324{
325	u32 pclk;
326	u32 dsi_clk;
327	u32 dsi_ratio;
328	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
329	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
330	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
331
332	config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);
333
334	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
335
336	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
337
338	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
339
340	drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk);
341	return pclk;
342}
343
344void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
345{
346	u32 temp;
347	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
348	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
349
350	temp = intel_de_read(dev_priv, MIPI_CTRL(port));
351	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
352	intel_de_write(dev_priv, MIPI_CTRL(port),
353		       temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT);
354}
355
356static void glk_dsi_program_esc_clock(struct drm_device *dev,
357				   const struct intel_crtc_state *config)
358{
359	struct drm_i915_private *dev_priv = to_i915(dev);
360	u32 dsi_rate = 0;
361	u32 pll_ratio = 0;
362	u32 ddr_clk = 0;
363	u32 div1_value = 0;
364	u32 div2_value = 0;
365	u32 txesc1_div = 0;
366	u32 txesc2_div = 0;
367
368	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
369
370	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
371
372	ddr_clk = dsi_rate / 2;
373
374	/* Variable divider value */
375	div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
376
377	/* Calculate TXESC1 divider */
378	if (div1_value <= 10)
379		txesc1_div = div1_value;
380	else if ((div1_value > 10) && (div1_value <= 20))
381		txesc1_div = DIV_ROUND_UP(div1_value, 2);
382	else if ((div1_value > 20) && (div1_value <= 30))
383		txesc1_div = DIV_ROUND_UP(div1_value, 4);
384	else if ((div1_value > 30) && (div1_value <= 40))
385		txesc1_div = DIV_ROUND_UP(div1_value, 6);
386	else if ((div1_value > 40) && (div1_value <= 50))
387		txesc1_div = DIV_ROUND_UP(div1_value, 8);
388	else
389		txesc1_div = 10;
390
391	/* Calculate TXESC2 divider */
392	div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
393
394	if (div2_value < 10)
395		txesc2_div = div2_value;
396	else
397		txesc2_div = 10;
398
399	intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1,
400		       (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
401	intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2,
402		       (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
403}
404
405/* Program BXT Mipi clocks and dividers */
406static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
407				   const struct intel_crtc_state *config)
408{
409	struct drm_i915_private *dev_priv = to_i915(dev);
410	u32 tmp;
411	u32 dsi_rate = 0;
412	u32 pll_ratio = 0;
413	u32 rx_div;
414	u32 tx_div;
415	u32 rx_div_upper;
416	u32 rx_div_lower;
417	u32 mipi_8by3_divider;
418
419	/* Clear old configurations */
420	tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL);
421	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
422	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
423	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
424	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
425
426	/* Get the current DSI rate(actual) */
427	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
428	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
429
430	/*
431	 * tx clock should be <= 20MHz and the div value must be
432	 * subtracted by 1 as per bspec
433	 */
434	tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
435	/*
436	 * rx clock should be <= 150MHz and the div value must be
437	 * subtracted by 1 as per bspec
438	 */
439	rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
440
441	/*
442	 * rx divider value needs to be updated in the
443	 * two differnt bit fields in the register hence splitting the
444	 * rx divider value accordingly
445	 */
446	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
447	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
448
449	mipi_8by3_divider = 0x2;
450
451	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
452	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
453	tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
454	tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
455
456	intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp);
457}
458
459int bxt_dsi_pll_compute(struct intel_encoder *encoder,
460			struct intel_crtc_state *config)
461{
462	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
463	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
464	u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
465	u32 dsi_clk;
466
467	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
468				    intel_dsi->lane_count);
469
470	/*
471	 * From clock diagram, to get PLL ratio divider, divide double of DSI
472	 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
473	 * round 'up' the result
474	 */
475	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
476
477	if (IS_BROXTON(dev_priv)) {
478		dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
479		dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
480	} else {
481		dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
482		dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
483	}
484
485	if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
486		drm_err(&dev_priv->drm,
487			"Can't get a suitable ratio from DSI PLL ratios\n");
488		return -ECHRNG;
489	} else
490		drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n");
491
492	/*
493	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
494	 * Spec says both have to be programmed, even if one is not getting
495	 * used. Configure MIPI_CLOCK_CTL dividers in modeset
496	 */
497	config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
498
499	/* As per recommendation from hardware team,
500	 * Prog PVD ratio =1 if dsi ratio <= 50
501	 */
502	if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
503		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
504
505	return 0;
506}
507
508void bxt_dsi_pll_enable(struct intel_encoder *encoder,
509			const struct intel_crtc_state *config)
510{
511	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
512	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
513	enum port port;
514	u32 val;
515
516	drm_dbg_kms(&dev_priv->drm, "\n");
517
518	/* Configure PLL vales */
519	intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
520	intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL);
521
522	/* Program TX, RX, Dphy clocks */
523	if (IS_BROXTON(dev_priv)) {
524		for_each_dsi_port(port, intel_dsi->ports)
525			bxt_dsi_program_clocks(encoder->base.dev, port, config);
526	} else {
527		glk_dsi_program_esc_clock(encoder->base.dev, config);
528	}
529
530	/* Enable DSI PLL */
531	val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
532	val |= BXT_DSI_PLL_DO_ENABLE;
533	intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val);
534
535	/* Timeout and fail if PLL not locked */
536	if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE,
537				  BXT_DSI_PLL_LOCKED, 1)) {
538		drm_err(&dev_priv->drm,
539			"Timed out waiting for DSI PLL to lock\n");
540		return;
541	}
542
543	drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");
544}
545
546void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
547{
548	u32 tmp;
549	struct drm_device *dev = encoder->base.dev;
550	struct drm_i915_private *dev_priv = to_i915(dev);
551
552	/* Clear old configurations */
553	if (IS_BROXTON(dev_priv)) {
554		tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL);
555		tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
556		tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
557		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
558		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
559		intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp);
560	} else {
561		tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1);
562		tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
563		intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp);
564
565		tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2);
566		tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
567		intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp);
568	}
569	intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
570}