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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TQM 8555 Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 */
7
8/dts-v1/;
9
10/ {
11 model = "tqc,tqm8555";
12 compatible = "tqc,tqm8555";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 pci0 = &pci0;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,8555@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <32768>;
34 i-cache-size = <32768>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
38 next-level-cache = <&L2>;
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 reg = <0x00000000 0x10000000>;
45 };
46
47 soc@e0000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 device_type = "soc";
51 ranges = <0x0 0xe0000000 0x100000>;
52 bus-frequency = <0>;
53 compatible = "fsl,mpc8555-immr", "simple-bus";
54
55 ecm-law@0 {
56 compatible = "fsl,ecm-law";
57 reg = <0x0 0x1000>;
58 fsl,num-laws = <8>;
59 };
60
61 ecm@1000 {
62 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
63 reg = <0x1000 0x1000>;
64 interrupts = <17 2>;
65 interrupt-parent = <&mpic>;
66 };
67
68 memory-controller@2000 {
69 compatible = "fsl,mpc8540-memory-controller";
70 reg = <0x2000 0x1000>;
71 interrupt-parent = <&mpic>;
72 interrupts = <18 2>;
73 };
74
75 L2: l2-cache-controller@20000 {
76 compatible = "fsl,mpc8540-l2-cache-controller";
77 reg = <0x20000 0x1000>;
78 cache-line-size = <32>;
79 cache-size = <0x40000>; // L2, 256K
80 interrupt-parent = <&mpic>;
81 interrupts = <16 2>;
82 };
83
84 i2c@3000 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 cell-index = <0>;
88 compatible = "fsl-i2c";
89 reg = <0x3000 0x100>;
90 interrupts = <43 2>;
91 interrupt-parent = <&mpic>;
92 dfsrr;
93
94 dtt@48 {
95 compatible = "national,lm75";
96 reg = <0x48>;
97 };
98
99 rtc@68 {
100 compatible = "dallas,ds1337";
101 reg = <0x68>;
102 };
103 };
104
105 dma@21300 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
109 reg = <0x21300 0x4>;
110 ranges = <0x0 0x21100 0x200>;
111 cell-index = <0>;
112 dma-channel@0 {
113 compatible = "fsl,mpc8555-dma-channel",
114 "fsl,eloplus-dma-channel";
115 reg = <0x0 0x80>;
116 cell-index = <0>;
117 interrupt-parent = <&mpic>;
118 interrupts = <20 2>;
119 };
120 dma-channel@80 {
121 compatible = "fsl,mpc8555-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x80 0x80>;
124 cell-index = <1>;
125 interrupt-parent = <&mpic>;
126 interrupts = <21 2>;
127 };
128 dma-channel@100 {
129 compatible = "fsl,mpc8555-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x100 0x80>;
132 cell-index = <2>;
133 interrupt-parent = <&mpic>;
134 interrupts = <22 2>;
135 };
136 dma-channel@180 {
137 compatible = "fsl,mpc8555-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x180 0x80>;
140 cell-index = <3>;
141 interrupt-parent = <&mpic>;
142 interrupts = <23 2>;
143 };
144 };
145
146 enet0: ethernet@24000 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 cell-index = <0>;
150 device_type = "network";
151 model = "TSEC";
152 compatible = "gianfar";
153 reg = <0x24000 0x1000>;
154 ranges = <0x0 0x24000 0x1000>;
155 local-mac-address = [ 00 00 00 00 00 00 ];
156 interrupts = <29 2 30 2 34 2>;
157 interrupt-parent = <&mpic>;
158 tbi-handle = <&tbi0>;
159 phy-handle = <&phy2>;
160
161 mdio@520 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "fsl,gianfar-mdio";
165 reg = <0x520 0x20>;
166
167 phy1: ethernet-phy@1 {
168 interrupt-parent = <&mpic>;
169 interrupts = <8 1>;
170 reg = <1>;
171 };
172 phy2: ethernet-phy@2 {
173 interrupt-parent = <&mpic>;
174 interrupts = <8 1>;
175 reg = <2>;
176 };
177 phy3: ethernet-phy@3 {
178 interrupt-parent = <&mpic>;
179 interrupts = <8 1>;
180 reg = <3>;
181 };
182 tbi0: tbi-phy@11 {
183 reg = <0x11>;
184 device_type = "tbi-phy";
185 };
186 };
187 };
188
189 enet1: ethernet@25000 {
190 #address-cells = <1>;
191 #size-cells = <1>;
192 cell-index = <1>;
193 device_type = "network";
194 model = "TSEC";
195 compatible = "gianfar";
196 reg = <0x25000 0x1000>;
197 ranges = <0x0 0x25000 0x1000>;
198 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <35 2 36 2 40 2>;
200 interrupt-parent = <&mpic>;
201 tbi-handle = <&tbi1>;
202 phy-handle = <&phy1>;
203
204 mdio@520 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,gianfar-tbi";
208 reg = <0x520 0x20>;
209
210 tbi1: tbi-phy@11 {
211 reg = <0x11>;
212 device_type = "tbi-phy";
213 };
214 };
215 };
216
217 serial0: serial@4500 {
218 cell-index = <0>;
219 device_type = "serial";
220 compatible = "fsl,ns16550", "ns16550";
221 reg = <0x4500 0x100>; // reg base, size
222 clock-frequency = <0>; // should we fill in in uboot?
223 interrupts = <42 2>;
224 interrupt-parent = <&mpic>;
225 };
226
227 serial1: serial@4600 {
228 cell-index = <1>;
229 device_type = "serial";
230 compatible = "fsl,ns16550", "ns16550";
231 reg = <0x4600 0x100>; // reg base, size
232 clock-frequency = <0>; // should we fill in in uboot?
233 interrupts = <42 2>;
234 interrupt-parent = <&mpic>;
235 };
236
237 crypto@30000 {
238 compatible = "fsl,sec2.0";
239 reg = <0x30000 0x10000>;
240 interrupts = <45 2>;
241 interrupt-parent = <&mpic>;
242 fsl,num-channels = <4>;
243 fsl,channel-fifo-len = <24>;
244 fsl,exec-units-mask = <0x7e>;
245 fsl,descriptor-types-mask = <0x01010ebf>;
246 };
247
248 mpic: pic@40000 {
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <2>;
252 reg = <0x40000 0x40000>;
253 device_type = "open-pic";
254 compatible = "chrp,open-pic";
255 };
256
257 cpm@919c0 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus";
261 reg = <0x919c0 0x30>;
262 ranges;
263
264 muram@80000 {
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges = <0 0x80000 0x10000>;
268
269 data@0 {
270 compatible = "fsl,cpm-muram-data";
271 reg = <0 0x2000 0x9000 0x1000>;
272 };
273 };
274
275 brg@919f0 {
276 compatible = "fsl,mpc8555-brg",
277 "fsl,cpm2-brg",
278 "fsl,cpm-brg";
279 reg = <0x919f0 0x10 0x915f0 0x10>;
280 clock-frequency = <0>;
281 };
282
283 cpmpic: pic@90c00 {
284 interrupt-controller;
285 #address-cells = <0>;
286 #interrupt-cells = <2>;
287 interrupts = <46 2>;
288 interrupt-parent = <&mpic>;
289 reg = <0x90c00 0x80>;
290 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
291 };
292 };
293 };
294
295 pci0: pci@e0008000 {
296 #interrupt-cells = <1>;
297 #size-cells = <2>;
298 #address-cells = <3>;
299 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
300 device_type = "pci";
301 reg = <0xe0008000 0x1000>;
302 clock-frequency = <66666666>;
303 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
304 interrupt-map = <
305 /* IDSEL 28 */
306 0xe000 0 0 1 &mpic 2 1
307 0xe000 0 0 2 &mpic 3 1
308 0xe000 0 0 3 &mpic 6 1
309 0xe000 0 0 4 &mpic 5 1
310
311 /* IDSEL 11 */
312 0x5800 0 0 1 &mpic 6 1
313 0x5800 0 0 2 &mpic 5 1
314 >;
315
316 interrupt-parent = <&mpic>;
317 interrupts = <24 2>;
318 bus-range = <0 0>;
319 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
320 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
321 };
322};
1/*
2 * TQM 8555 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "tqc,tqm8555";
16 compatible = "tqc,tqm8555";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8555@0 {
33 device_type = "cpu";
34 reg = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
49 };
50
51 soc@e0000000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
57 compatible = "fsl,mpc8555-immr", "simple-bus";
58
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
61 reg = <0x0 0x1000>;
62 fsl,num-laws = <8>;
63 };
64
65 ecm@1000 {
66 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>;
69 interrupt-parent = <&mpic>;
70 };
71
72 memory-controller@2000 {
73 compatible = "fsl,mpc8540-memory-controller";
74 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>;
76 interrupts = <18 2>;
77 };
78
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8540-l2-cache-controller";
81 reg = <0x20000 0x1000>;
82 cache-line-size = <32>;
83 cache-size = <0x40000>; // L2, 256K
84 interrupt-parent = <&mpic>;
85 interrupts = <16 2>;
86 };
87
88 i2c@3000 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <0>;
92 compatible = "fsl-i2c";
93 reg = <0x3000 0x100>;
94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>;
96 dfsrr;
97
98 dtt@48 {
99 compatible = "national,lm75";
100 reg = <0x48>;
101 };
102
103 rtc@68 {
104 compatible = "dallas,ds1337";
105 reg = <0x68>;
106 };
107 };
108
109 dma@21300 {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
113 reg = <0x21300 0x4>;
114 ranges = <0x0 0x21100 0x200>;
115 cell-index = <0>;
116 dma-channel@0 {
117 compatible = "fsl,mpc8555-dma-channel",
118 "fsl,eloplus-dma-channel";
119 reg = <0x0 0x80>;
120 cell-index = <0>;
121 interrupt-parent = <&mpic>;
122 interrupts = <20 2>;
123 };
124 dma-channel@80 {
125 compatible = "fsl,mpc8555-dma-channel",
126 "fsl,eloplus-dma-channel";
127 reg = <0x80 0x80>;
128 cell-index = <1>;
129 interrupt-parent = <&mpic>;
130 interrupts = <21 2>;
131 };
132 dma-channel@100 {
133 compatible = "fsl,mpc8555-dma-channel",
134 "fsl,eloplus-dma-channel";
135 reg = <0x100 0x80>;
136 cell-index = <2>;
137 interrupt-parent = <&mpic>;
138 interrupts = <22 2>;
139 };
140 dma-channel@180 {
141 compatible = "fsl,mpc8555-dma-channel",
142 "fsl,eloplus-dma-channel";
143 reg = <0x180 0x80>;
144 cell-index = <3>;
145 interrupt-parent = <&mpic>;
146 interrupts = <23 2>;
147 };
148 };
149
150 enet0: ethernet@24000 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 cell-index = <0>;
154 device_type = "network";
155 model = "TSEC";
156 compatible = "gianfar";
157 reg = <0x24000 0x1000>;
158 ranges = <0x0 0x24000 0x1000>;
159 local-mac-address = [ 00 00 00 00 00 00 ];
160 interrupts = <29 2 30 2 34 2>;
161 interrupt-parent = <&mpic>;
162 tbi-handle = <&tbi0>;
163 phy-handle = <&phy2>;
164
165 mdio@520 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,gianfar-mdio";
169 reg = <0x520 0x20>;
170
171 phy1: ethernet-phy@1 {
172 interrupt-parent = <&mpic>;
173 interrupts = <8 1>;
174 reg = <1>;
175 device_type = "ethernet-phy";
176 };
177 phy2: ethernet-phy@2 {
178 interrupt-parent = <&mpic>;
179 interrupts = <8 1>;
180 reg = <2>;
181 device_type = "ethernet-phy";
182 };
183 phy3: ethernet-phy@3 {
184 interrupt-parent = <&mpic>;
185 interrupts = <8 1>;
186 reg = <3>;
187 device_type = "ethernet-phy";
188 };
189 tbi0: tbi-phy@11 {
190 reg = <0x11>;
191 device_type = "tbi-phy";
192 };
193 };
194 };
195
196 enet1: ethernet@25000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 cell-index = <1>;
200 device_type = "network";
201 model = "TSEC";
202 compatible = "gianfar";
203 reg = <0x25000 0x1000>;
204 ranges = <0x0 0x25000 0x1000>;
205 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupts = <35 2 36 2 40 2>;
207 interrupt-parent = <&mpic>;
208 tbi-handle = <&tbi1>;
209 phy-handle = <&phy1>;
210
211 mdio@520 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,gianfar-tbi";
215 reg = <0x520 0x20>;
216
217 tbi1: tbi-phy@11 {
218 reg = <0x11>;
219 device_type = "tbi-phy";
220 };
221 };
222 };
223
224 serial0: serial@4500 {
225 cell-index = <0>;
226 device_type = "serial";
227 compatible = "fsl,ns16550", "ns16550";
228 reg = <0x4500 0x100>; // reg base, size
229 clock-frequency = <0>; // should we fill in in uboot?
230 interrupts = <42 2>;
231 interrupt-parent = <&mpic>;
232 };
233
234 serial1: serial@4600 {
235 cell-index = <1>;
236 device_type = "serial";
237 compatible = "fsl,ns16550", "ns16550";
238 reg = <0x4600 0x100>; // reg base, size
239 clock-frequency = <0>; // should we fill in in uboot?
240 interrupts = <42 2>;
241 interrupt-parent = <&mpic>;
242 };
243
244 crypto@30000 {
245 compatible = "fsl,sec2.0";
246 reg = <0x30000 0x10000>;
247 interrupts = <45 2>;
248 interrupt-parent = <&mpic>;
249 fsl,num-channels = <4>;
250 fsl,channel-fifo-len = <24>;
251 fsl,exec-units-mask = <0x7e>;
252 fsl,descriptor-types-mask = <0x01010ebf>;
253 };
254
255 mpic: pic@40000 {
256 interrupt-controller;
257 #address-cells = <0>;
258 #interrupt-cells = <2>;
259 reg = <0x40000 0x40000>;
260 device_type = "open-pic";
261 compatible = "chrp,open-pic";
262 };
263
264 cpm@919c0 {
265 #address-cells = <1>;
266 #size-cells = <1>;
267 compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus";
268 reg = <0x919c0 0x30>;
269 ranges;
270
271 muram@80000 {
272 #address-cells = <1>;
273 #size-cells = <1>;
274 ranges = <0 0x80000 0x10000>;
275
276 data@0 {
277 compatible = "fsl,cpm-muram-data";
278 reg = <0 0x2000 0x9000 0x1000>;
279 };
280 };
281
282 brg@919f0 {
283 compatible = "fsl,mpc8555-brg",
284 "fsl,cpm2-brg",
285 "fsl,cpm-brg";
286 reg = <0x919f0 0x10 0x915f0 0x10>;
287 clock-frequency = <0>;
288 };
289
290 cpmpic: pic@90c00 {
291 interrupt-controller;
292 #address-cells = <0>;
293 #interrupt-cells = <2>;
294 interrupts = <46 2>;
295 interrupt-parent = <&mpic>;
296 reg = <0x90c00 0x80>;
297 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
298 };
299 };
300 };
301
302 pci0: pci@e0008000 {
303 #interrupt-cells = <1>;
304 #size-cells = <2>;
305 #address-cells = <3>;
306 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
307 device_type = "pci";
308 reg = <0xe0008000 0x1000>;
309 clock-frequency = <66666666>;
310 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
311 interrupt-map = <
312 /* IDSEL 28 */
313 0xe000 0 0 1 &mpic 2 1
314 0xe000 0 0 2 &mpic 3 1
315 0xe000 0 0 3 &mpic 6 1
316 0xe000 0 0 4 &mpic 5 1
317
318 /* IDSEL 11 */
319 0x5800 0 0 1 &mpic 6 1
320 0x5800 0 0 2 &mpic 5 1
321 >;
322
323 interrupt-parent = <&mpic>;
324 interrupts = <24 2>;
325 bus-range = <0 0>;
326 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
327 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
328 };
329};