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1/*
2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 reg = <0x0 0x03000000>;
46 label = "ramdisk-nor";
47 };
48
49 partition@3000000 {
50 reg = <0x03000000 0x00e00000>;
51 label = "diagnostic-nor";
52 read-only;
53 };
54
55 partition@3e00000 {
56 reg = <0x03e00000 0x00200000>;
57 label = "dink-nor";
58 read-only;
59 };
60
61 partition@4000000 {
62 reg = <0x04000000 0x00400000>;
63 label = "kernel-nor";
64 };
65
66 partition@4400000 {
67 reg = <0x04400000 0x03b00000>;
68 label = "fs-nor";
69 };
70
71 partition@7f00000 {
72 reg = <0x07f00000 0x00060000>;
73 label = "dtb-nor";
74 };
75
76 partition@7f60000 {
77 reg = <0x07f60000 0x00020000>;
78 label = "env-nor";
79 read-only;
80 };
81
82 partition@7f80000 {
83 reg = <0x07f80000 0x00080000>;
84 label = "u-boot-nor";
85 read-only;
86 };
87 };
88
89 nand@2,0 {
90 #address-cells = <1>;
91 #size-cells = <1>;
92 compatible = "fsl,mpc8572-fcm-nand",
93 "fsl,elbc-fcm-nand";
94 reg = <0x2 0x0 0x40000>;
95
96 partition@0 {
97 reg = <0x0 0x02000000>;
98 label = "u-boot-nand";
99 read-only;
100 };
101
102 partition@2000000 {
103 reg = <0x02000000 0x10000000>;
104 label = "fs-nand";
105 };
106
107 partition@12000000 {
108 reg = <0x12000000 0x08000000>;
109 label = "ramdisk-nand";
110 };
111
112 partition@1a000000 {
113 reg = <0x1a000000 0x04000000>;
114 label = "kernel-nand";
115 };
116
117 partition@1e000000 {
118 reg = <0x1e000000 0x01000000>;
119 label = "dtb-nand";
120 };
121
122 partition@1f000000 {
123 reg = <0x1f000000 0x21000000>;
124 label = "empty-nand";
125 };
126 };
127
128 nand@4,0 {
129 compatible = "fsl,mpc8572-fcm-nand",
130 "fsl,elbc-fcm-nand";
131 reg = <0x4 0x0 0x40000>;
132 };
133
134 nand@5,0 {
135 compatible = "fsl,mpc8572-fcm-nand",
136 "fsl,elbc-fcm-nand";
137 reg = <0x5 0x0 0x40000>;
138 };
139
140 nand@6,0 {
141 compatible = "fsl,mpc8572-fcm-nand",
142 "fsl,elbc-fcm-nand";
143 reg = <0x6 0x0 0x40000>;
144 };
145};
146
147&board_soc {
148 enet0: ethernet@24000 {
149 tbi-handle = <&tbi0>;
150 phy-handle = <&phy0>;
151 phy-connection-type = "rgmii-id";
152 };
153
154 mdio@24520 {
155 phy0: ethernet-phy@0 {
156 interrupts = <10 1 0 0>;
157 reg = <0x0>;
158 };
159 phy1: ethernet-phy@1 {
160 interrupts = <10 1 0 0>;
161 reg = <0x1>;
162 };
163 phy2: ethernet-phy@2 {
164 interrupts = <10 1 0 0>;
165 reg = <0x2>;
166 };
167 phy3: ethernet-phy@3 {
168 interrupts = <10 1 0 0>;
169 reg = <0x3>;
170 };
171
172 tbi0: tbi-phy@11 {
173 reg = <0x11>;
174 device_type = "tbi-phy";
175 };
176 };
177
178 ptp_clock@24e00 {
179 fsl,tclk-period = <5>;
180 fsl,tmr-prsc = <200>;
181 fsl,tmr-add = <0xAAAAAAAB>;
182 fsl,tmr-fiper1 = <0x3B9AC9FB>;
183 fsl,tmr-fiper2 = <0x3B9AC9FB>;
184 fsl,max-adj = <499999999>;
185 };
186
187 enet1: ethernet@25000 {
188 tbi-handle = <&tbi1>;
189 phy-handle = <&phy1>;
190 phy-connection-type = "rgmii-id";
191
192 };
193
194 mdio@25520 {
195 tbi1: tbi-phy@11 {
196 reg = <0x11>;
197 device_type = "tbi-phy";
198 };
199 };
200
201 enet2: ethernet@26000 {
202 tbi-handle = <&tbi2>;
203 phy-handle = <&phy2>;
204 phy-connection-type = "rgmii-id";
205
206 };
207 mdio@26520 {
208 tbi2: tbi-phy@11 {
209 reg = <0x11>;
210 device_type = "tbi-phy";
211 };
212 };
213
214 enet3: ethernet@27000 {
215 tbi-handle = <&tbi3>;
216 phy-handle = <&phy3>;
217 phy-connection-type = "rgmii-id";
218 };
219
220 mdio@27520 {
221 tbi3: tbi-phy@11 {
222 reg = <0x11>;
223 device_type = "tbi-phy";
224 };
225 };
226};
227
228&board_pci0 {
229 pcie@0 {
230 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
231 interrupt-map = <
232 /* IDSEL 0x11 func 0 - PCI slot 1 */
233 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
234 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
235 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
236 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
237
238 /* IDSEL 0x11 func 1 - PCI slot 1 */
239 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
240 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
241 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
242 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
243
244 /* IDSEL 0x11 func 2 - PCI slot 1 */
245 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
246 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
247 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
248 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
249
250 /* IDSEL 0x11 func 3 - PCI slot 1 */
251 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
252 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
253 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
254 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
255
256 /* IDSEL 0x11 func 4 - PCI slot 1 */
257 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
258 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
259 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
260 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
261
262 /* IDSEL 0x11 func 5 - PCI slot 1 */
263 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
264 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
265 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
266 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
267
268 /* IDSEL 0x11 func 6 - PCI slot 1 */
269 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
270 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
271 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
272 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
273
274 /* IDSEL 0x11 func 7 - PCI slot 1 */
275 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
276 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
277 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
278 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
279
280 /* IDSEL 0x12 func 0 - PCI slot 2 */
281 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
282 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
283 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
284 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
285
286 /* IDSEL 0x12 func 1 - PCI slot 2 */
287 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
288 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
289 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
290 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
291
292 /* IDSEL 0x12 func 2 - PCI slot 2 */
293 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
294 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
295 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
296 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
297
298 /* IDSEL 0x12 func 3 - PCI slot 2 */
299 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
300 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
301 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
302 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
303
304 /* IDSEL 0x12 func 4 - PCI slot 2 */
305 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
306 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
307 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
308 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
309
310 /* IDSEL 0x12 func 5 - PCI slot 2 */
311 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
312 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
313 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
314 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
315
316 /* IDSEL 0x12 func 6 - PCI slot 2 */
317 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
318 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
319 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
320 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
321
322 /* IDSEL 0x12 func 7 - PCI slot 2 */
323 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
324 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
325 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
326 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
327
328 // IDSEL 0x1c USB
329 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
330 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
331 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
332 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
333
334 // IDSEL 0x1d Audio
335 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
336
337 // IDSEL 0x1e Legacy
338 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
339 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
340
341 // IDSEL 0x1f IDE/SATA
342 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
343 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
344 >;
345
346
347 uli1575@0 {
348 reg = <0x0 0x0 0x0 0x0 0x0>;
349 #size-cells = <2>;
350 #address-cells = <3>;
351 ranges = <0x2000000 0x0 0x80000000
352 0x2000000 0x0 0x80000000
353 0x0 0x20000000
354
355 0x1000000 0x0 0x0
356 0x1000000 0x0 0x0
357 0x0 0x10000>;
358 isa@1e {
359 device_type = "isa";
360 #interrupt-cells = <2>;
361 #size-cells = <1>;
362 #address-cells = <2>;
363 reg = <0xf000 0x0 0x0 0x0 0x0>;
364 ranges = <0x1 0x0 0x1000000 0x0 0x0
365 0x1000>;
366 interrupt-parent = <&i8259>;
367
368 i8259: interrupt-controller@20 {
369 reg = <0x1 0x20 0x2
370 0x1 0xa0 0x2
371 0x1 0x4d0 0x2>;
372 interrupt-controller;
373 device_type = "interrupt-controller";
374 #address-cells = <0>;
375 #interrupt-cells = <2>;
376 compatible = "chrp,iic";
377 interrupts = <9 2 0 0>;
378 interrupt-parent = <&mpic>;
379 };
380
381 i8042@60 {
382 #size-cells = <0>;
383 #address-cells = <1>;
384 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
385 interrupts = <1 3 12 3>;
386 interrupt-parent =
387 <&i8259>;
388
389 keyboard@0 {
390 reg = <0x0>;
391 compatible = "pnpPNP,303";
392 };
393
394 mouse@1 {
395 reg = <0x1>;
396 compatible = "pnpPNP,f03";
397 };
398 };
399
400 rtc@70 {
401 compatible = "pnpPNP,b00";
402 reg = <0x1 0x70 0x2>;
403 };
404
405 gpio@400 {
406 reg = <0x1 0x400 0x80>;
407 };
408 };
409 };
410 };
411};