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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
13 *
14 * ... and the days got worse and worse and now you see
15 * I've gone completely out of my mind.
16 *
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
20 *
21 * (Condolences to Napoleon XIV)
22 */
23
24#include <linux/bug.h>
25#include <linux/export.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/smp.h>
29#include <linux/string.h>
30#include <linux/cache.h>
31#include <linux/pgtable.h>
32
33#include <asm/cacheflush.h>
34#include <asm/cpu-type.h>
35#include <asm/mmu_context.h>
36#include <asm/war.h>
37#include <asm/uasm.h>
38#include <asm/setup.h>
39#include <asm/tlbex.h>
40
41static int mips_xpa_disabled;
42
43static int __init xpa_disable(char *s)
44{
45 mips_xpa_disabled = 1;
46
47 return 1;
48}
49
50__setup("noxpa", xpa_disable);
51
52/*
53 * TLB load/store/modify handlers.
54 *
55 * Only the fastpath gets synthesized at runtime, the slowpath for
56 * do_page_fault remains normal asm.
57 */
58extern void tlb_do_page_fault_0(void);
59extern void tlb_do_page_fault_1(void);
60
61struct work_registers {
62 int r1;
63 int r2;
64 int r3;
65};
66
67struct tlb_reg_save {
68 unsigned long a;
69 unsigned long b;
70} ____cacheline_aligned_in_smp;
71
72static struct tlb_reg_save handler_reg_save[NR_CPUS];
73
74static inline int r45k_bvahwbug(void)
75{
76 /* XXX: We should probe for the presence of this bug, but we don't. */
77 return 0;
78}
79
80static inline int r4k_250MHZhwbug(void)
81{
82 /* XXX: We should probe for the presence of this bug, but we don't. */
83 return 0;
84}
85
86extern int sb1250_m3_workaround_needed(void);
87
88static inline int __maybe_unused bcm1250_m3_war(void)
89{
90 if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
91 return sb1250_m3_workaround_needed();
92 return 0;
93}
94
95static inline int __maybe_unused r10000_llsc_war(void)
96{
97 return IS_ENABLED(CONFIG_WAR_R10000_LLSC);
98}
99
100static int use_bbit_insns(void)
101{
102 switch (current_cpu_type()) {
103 case CPU_CAVIUM_OCTEON:
104 case CPU_CAVIUM_OCTEON_PLUS:
105 case CPU_CAVIUM_OCTEON2:
106 case CPU_CAVIUM_OCTEON3:
107 return 1;
108 default:
109 return 0;
110 }
111}
112
113static int use_lwx_insns(void)
114{
115 switch (current_cpu_type()) {
116 case CPU_CAVIUM_OCTEON2:
117 case CPU_CAVIUM_OCTEON3:
118 return 1;
119 default:
120 return 0;
121 }
122}
123#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
124 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
125static bool scratchpad_available(void)
126{
127 return true;
128}
129static int scratchpad_offset(int i)
130{
131 /*
132 * CVMSEG starts at address -32768 and extends for
133 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
134 */
135 i += 1; /* Kernel use starts at the top and works down. */
136 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
137}
138#else
139static bool scratchpad_available(void)
140{
141 return false;
142}
143static int scratchpad_offset(int i)
144{
145 BUG();
146 /* Really unreachable, but evidently some GCC want this. */
147 return 0;
148}
149#endif
150/*
151 * Found by experiment: At least some revisions of the 4kc throw under
152 * some circumstances a machine check exception, triggered by invalid
153 * values in the index register. Delaying the tlbp instruction until
154 * after the next branch, plus adding an additional nop in front of
155 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
156 * why; it's not an issue caused by the core RTL.
157 *
158 */
159static int m4kc_tlbp_war(void)
160{
161 return current_cpu_type() == CPU_4KC;
162}
163
164/* Handle labels (which must be positive integers). */
165enum label_id {
166 label_second_part = 1,
167 label_leave,
168 label_vmalloc,
169 label_vmalloc_done,
170 label_tlbw_hazard_0,
171 label_split = label_tlbw_hazard_0 + 8,
172 label_tlbl_goaround1,
173 label_tlbl_goaround2,
174 label_nopage_tlbl,
175 label_nopage_tlbs,
176 label_nopage_tlbm,
177 label_smp_pgtable_change,
178 label_r3000_write_probe_fail,
179 label_large_segbits_fault,
180#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
181 label_tlb_huge_update,
182#endif
183};
184
185UASM_L_LA(_second_part)
186UASM_L_LA(_leave)
187UASM_L_LA(_vmalloc)
188UASM_L_LA(_vmalloc_done)
189/* _tlbw_hazard_x is handled differently. */
190UASM_L_LA(_split)
191UASM_L_LA(_tlbl_goaround1)
192UASM_L_LA(_tlbl_goaround2)
193UASM_L_LA(_nopage_tlbl)
194UASM_L_LA(_nopage_tlbs)
195UASM_L_LA(_nopage_tlbm)
196UASM_L_LA(_smp_pgtable_change)
197UASM_L_LA(_r3000_write_probe_fail)
198UASM_L_LA(_large_segbits_fault)
199#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
200UASM_L_LA(_tlb_huge_update)
201#endif
202
203static int hazard_instance;
204
205static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
206{
207 switch (instance) {
208 case 0 ... 7:
209 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
210 return;
211 default:
212 BUG();
213 }
214}
215
216static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
217{
218 switch (instance) {
219 case 0 ... 7:
220 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
221 break;
222 default:
223 BUG();
224 }
225}
226
227/*
228 * pgtable bits are assigned dynamically depending on processor feature
229 * and statically based on kernel configuration. This spits out the actual
230 * values the kernel is using. Required to make sense from disassembled
231 * TLB exception handlers.
232 */
233static void output_pgtable_bits_defines(void)
234{
235#define pr_define(fmt, ...) \
236 pr_debug("#define " fmt, ##__VA_ARGS__)
237
238 pr_debug("#include <asm/asm.h>\n");
239 pr_debug("#include <asm/regdef.h>\n");
240 pr_debug("\n");
241
242 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
243 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
244 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
245 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
246 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
247#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
248 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
249#endif
250#ifdef _PAGE_NO_EXEC_SHIFT
251 if (cpu_has_rixi)
252 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
253#endif
254 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
255 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
256 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
257 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
258 pr_debug("\n");
259}
260
261static inline void dump_handler(const char *symbol, const void *start, const void *end)
262{
263 unsigned int count = (end - start) / sizeof(u32);
264 const u32 *handler = start;
265 int i;
266
267 pr_debug("LEAF(%s)\n", symbol);
268
269 pr_debug("\t.set push\n");
270 pr_debug("\t.set noreorder\n");
271
272 for (i = 0; i < count; i++)
273 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
274
275 pr_debug("\t.set\tpop\n");
276
277 pr_debug("\tEND(%s)\n", symbol);
278}
279
280/* The only general purpose registers allowed in TLB handlers. */
281#define K0 26
282#define K1 27
283
284/* Some CP0 registers */
285#define C0_INDEX 0, 0
286#define C0_ENTRYLO0 2, 0
287#define C0_TCBIND 2, 2
288#define C0_ENTRYLO1 3, 0
289#define C0_CONTEXT 4, 0
290#define C0_PAGEMASK 5, 0
291#define C0_PWBASE 5, 5
292#define C0_PWFIELD 5, 6
293#define C0_PWSIZE 5, 7
294#define C0_PWCTL 6, 6
295#define C0_BADVADDR 8, 0
296#define C0_PGD 9, 7
297#define C0_ENTRYHI 10, 0
298#define C0_EPC 14, 0
299#define C0_XCONTEXT 20, 0
300
301#ifdef CONFIG_64BIT
302# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
303#else
304# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
305#endif
306
307/* The worst case length of the handler is around 18 instructions for
308 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
309 * Maximum space available is 32 instructions for R3000 and 64
310 * instructions for R4000.
311 *
312 * We deliberately chose a buffer size of 128, so we won't scribble
313 * over anything important on overflow before we panic.
314 */
315static u32 tlb_handler[128];
316
317/* simply assume worst case size for labels and relocs */
318static struct uasm_label labels[128];
319static struct uasm_reloc relocs[128];
320
321static int check_for_high_segbits;
322static bool fill_includes_sw_bits;
323
324static unsigned int kscratch_used_mask;
325
326static inline int __maybe_unused c0_kscratch(void)
327{
328 switch (current_cpu_type()) {
329 case CPU_XLP:
330 case CPU_XLR:
331 return 22;
332 default:
333 return 31;
334 }
335}
336
337static int allocate_kscratch(void)
338{
339 int r;
340 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
341
342 r = ffs(a);
343
344 if (r == 0)
345 return -1;
346
347 r--; /* make it zero based */
348
349 kscratch_used_mask |= (1 << r);
350
351 return r;
352}
353
354static int scratch_reg;
355int pgd_reg;
356EXPORT_SYMBOL_GPL(pgd_reg);
357enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
358
359static struct work_registers build_get_work_registers(u32 **p)
360{
361 struct work_registers r;
362
363 if (scratch_reg >= 0) {
364 /* Save in CPU local C0_KScratch? */
365 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
366 r.r1 = K0;
367 r.r2 = K1;
368 r.r3 = 1;
369 return r;
370 }
371
372 if (num_possible_cpus() > 1) {
373 /* Get smp_processor_id */
374 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
375 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
376
377 /* handler_reg_save index in K0 */
378 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
379
380 UASM_i_LA(p, K1, (long)&handler_reg_save);
381 UASM_i_ADDU(p, K0, K0, K1);
382 } else {
383 UASM_i_LA(p, K0, (long)&handler_reg_save);
384 }
385 /* K0 now points to save area, save $1 and $2 */
386 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
387 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
388
389 r.r1 = K1;
390 r.r2 = 1;
391 r.r3 = 2;
392 return r;
393}
394
395static void build_restore_work_registers(u32 **p)
396{
397 if (scratch_reg >= 0) {
398 uasm_i_ehb(p);
399 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
400 return;
401 }
402 /* K0 already points to save area, restore $1 and $2 */
403 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
404 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
405}
406
407#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
408
409/*
410 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
411 * we cannot do r3000 under these circumstances.
412 *
413 * The R3000 TLB handler is simple.
414 */
415static void build_r3000_tlb_refill_handler(void)
416{
417 long pgdc = (long)pgd_current;
418 u32 *p;
419
420 memset(tlb_handler, 0, sizeof(tlb_handler));
421 p = tlb_handler;
422
423 uasm_i_mfc0(&p, K0, C0_BADVADDR);
424 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
425 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
426 uasm_i_srl(&p, K0, K0, 22); /* load delay */
427 uasm_i_sll(&p, K0, K0, 2);
428 uasm_i_addu(&p, K1, K1, K0);
429 uasm_i_mfc0(&p, K0, C0_CONTEXT);
430 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
431 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
432 uasm_i_addu(&p, K1, K1, K0);
433 uasm_i_lw(&p, K0, 0, K1);
434 uasm_i_nop(&p); /* load delay */
435 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
436 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
437 uasm_i_tlbwr(&p); /* cp0 delay */
438 uasm_i_jr(&p, K1);
439 uasm_i_rfe(&p); /* branch delay */
440
441 if (p > tlb_handler + 32)
442 panic("TLB refill handler space exceeded");
443
444 pr_debug("Wrote TLB refill handler (%u instructions).\n",
445 (unsigned int)(p - tlb_handler));
446
447 memcpy((void *)ebase, tlb_handler, 0x80);
448 local_flush_icache_range(ebase, ebase + 0x80);
449 dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80));
450}
451#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
452
453/*
454 * The R4000 TLB handler is much more complicated. We have two
455 * consecutive handler areas with 32 instructions space each.
456 * Since they aren't used at the same time, we can overflow in the
457 * other one.To keep things simple, we first assume linear space,
458 * then we relocate it to the final handler layout as needed.
459 */
460static u32 final_handler[64];
461
462/*
463 * Hazards
464 *
465 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
466 * 2. A timing hazard exists for the TLBP instruction.
467 *
468 * stalling_instruction
469 * TLBP
470 *
471 * The JTLB is being read for the TLBP throughout the stall generated by the
472 * previous instruction. This is not really correct as the stalling instruction
473 * can modify the address used to access the JTLB. The failure symptom is that
474 * the TLBP instruction will use an address created for the stalling instruction
475 * and not the address held in C0_ENHI and thus report the wrong results.
476 *
477 * The software work-around is to not allow the instruction preceding the TLBP
478 * to stall - make it an NOP or some other instruction guaranteed not to stall.
479 *
480 * Errata 2 will not be fixed. This errata is also on the R5000.
481 *
482 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
483 */
484static void __maybe_unused build_tlb_probe_entry(u32 **p)
485{
486 switch (current_cpu_type()) {
487 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
488 case CPU_R4600:
489 case CPU_R4700:
490 case CPU_R5000:
491 case CPU_NEVADA:
492 uasm_i_nop(p);
493 uasm_i_tlbp(p);
494 break;
495
496 default:
497 uasm_i_tlbp(p);
498 break;
499 }
500}
501
502void build_tlb_write_entry(u32 **p, struct uasm_label **l,
503 struct uasm_reloc **r,
504 enum tlb_write_entry wmode)
505{
506 void(*tlbw)(u32 **) = NULL;
507
508 switch (wmode) {
509 case tlb_random: tlbw = uasm_i_tlbwr; break;
510 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
511 }
512
513 if (cpu_has_mips_r2_r6) {
514 if (cpu_has_mips_r2_exec_hazard)
515 uasm_i_ehb(p);
516 tlbw(p);
517 return;
518 }
519
520 switch (current_cpu_type()) {
521 case CPU_R4000PC:
522 case CPU_R4000SC:
523 case CPU_R4000MC:
524 case CPU_R4400PC:
525 case CPU_R4400SC:
526 case CPU_R4400MC:
527 /*
528 * This branch uses up a mtc0 hazard nop slot and saves
529 * two nops after the tlbw instruction.
530 */
531 uasm_bgezl_hazard(p, r, hazard_instance);
532 tlbw(p);
533 uasm_bgezl_label(l, p, hazard_instance);
534 hazard_instance++;
535 uasm_i_nop(p);
536 break;
537
538 case CPU_R4600:
539 case CPU_R4700:
540 uasm_i_nop(p);
541 tlbw(p);
542 uasm_i_nop(p);
543 break;
544
545 case CPU_R5000:
546 case CPU_NEVADA:
547 uasm_i_nop(p); /* QED specifies 2 nops hazard */
548 uasm_i_nop(p); /* QED specifies 2 nops hazard */
549 tlbw(p);
550 break;
551
552 case CPU_R4300:
553 case CPU_5KC:
554 case CPU_TX49XX:
555 case CPU_PR4450:
556 case CPU_XLR:
557 uasm_i_nop(p);
558 tlbw(p);
559 break;
560
561 case CPU_R10000:
562 case CPU_R12000:
563 case CPU_R14000:
564 case CPU_R16000:
565 case CPU_4KC:
566 case CPU_4KEC:
567 case CPU_M14KC:
568 case CPU_M14KEC:
569 case CPU_SB1:
570 case CPU_SB1A:
571 case CPU_4KSC:
572 case CPU_20KC:
573 case CPU_25KF:
574 case CPU_BMIPS32:
575 case CPU_BMIPS3300:
576 case CPU_BMIPS4350:
577 case CPU_BMIPS4380:
578 case CPU_BMIPS5000:
579 case CPU_LOONGSON2EF:
580 case CPU_LOONGSON64:
581 case CPU_R5500:
582 if (m4kc_tlbp_war())
583 uasm_i_nop(p);
584 fallthrough;
585 case CPU_ALCHEMY:
586 tlbw(p);
587 break;
588
589 case CPU_RM7000:
590 uasm_i_nop(p);
591 uasm_i_nop(p);
592 uasm_i_nop(p);
593 uasm_i_nop(p);
594 tlbw(p);
595 break;
596
597 case CPU_VR4111:
598 case CPU_VR4121:
599 case CPU_VR4122:
600 case CPU_VR4181:
601 case CPU_VR4181A:
602 uasm_i_nop(p);
603 uasm_i_nop(p);
604 tlbw(p);
605 uasm_i_nop(p);
606 uasm_i_nop(p);
607 break;
608
609 case CPU_VR4131:
610 case CPU_VR4133:
611 uasm_i_nop(p);
612 uasm_i_nop(p);
613 tlbw(p);
614 break;
615
616 case CPU_XBURST:
617 tlbw(p);
618 uasm_i_nop(p);
619 break;
620
621 default:
622 panic("No TLB refill handler yet (CPU type: %d)",
623 current_cpu_type());
624 break;
625 }
626}
627EXPORT_SYMBOL_GPL(build_tlb_write_entry);
628
629static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
630 unsigned int reg)
631{
632 if (_PAGE_GLOBAL_SHIFT == 0) {
633 /* pte_t is already in EntryLo format */
634 return;
635 }
636
637 if (cpu_has_rixi && !!_PAGE_NO_EXEC) {
638 if (fill_includes_sw_bits) {
639 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
640 } else {
641 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
642 UASM_i_ROTR(p, reg, reg,
643 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
644 }
645 } else {
646#ifdef CONFIG_PHYS_ADDR_T_64BIT
647 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
648#else
649 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
650#endif
651 }
652}
653
654#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
655
656static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
657 unsigned int tmp, enum label_id lid,
658 int restore_scratch)
659{
660 if (restore_scratch) {
661 /*
662 * Ensure the MFC0 below observes the value written to the
663 * KScratch register by the prior MTC0.
664 */
665 if (scratch_reg >= 0)
666 uasm_i_ehb(p);
667
668 /* Reset default page size */
669 if (PM_DEFAULT_MASK >> 16) {
670 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
671 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
672 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
673 uasm_il_b(p, r, lid);
674 } else if (PM_DEFAULT_MASK) {
675 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
676 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
677 uasm_il_b(p, r, lid);
678 } else {
679 uasm_i_mtc0(p, 0, C0_PAGEMASK);
680 uasm_il_b(p, r, lid);
681 }
682 if (scratch_reg >= 0)
683 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
684 else
685 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
686 } else {
687 /* Reset default page size */
688 if (PM_DEFAULT_MASK >> 16) {
689 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
690 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
691 uasm_il_b(p, r, lid);
692 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
693 } else if (PM_DEFAULT_MASK) {
694 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
695 uasm_il_b(p, r, lid);
696 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
697 } else {
698 uasm_il_b(p, r, lid);
699 uasm_i_mtc0(p, 0, C0_PAGEMASK);
700 }
701 }
702}
703
704static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
705 struct uasm_reloc **r,
706 unsigned int tmp,
707 enum tlb_write_entry wmode,
708 int restore_scratch)
709{
710 /* Set huge page tlb entry size */
711 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
712 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
713 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
714
715 build_tlb_write_entry(p, l, r, wmode);
716
717 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
718}
719
720/*
721 * Check if Huge PTE is present, if so then jump to LABEL.
722 */
723static void
724build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
725 unsigned int pmd, int lid)
726{
727 UASM_i_LW(p, tmp, 0, pmd);
728 if (use_bbit_insns()) {
729 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
730 } else {
731 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
732 uasm_il_bnez(p, r, tmp, lid);
733 }
734}
735
736static void build_huge_update_entries(u32 **p, unsigned int pte,
737 unsigned int tmp)
738{
739 int small_sequence;
740
741 /*
742 * A huge PTE describes an area the size of the
743 * configured huge page size. This is twice the
744 * of the large TLB entry size we intend to use.
745 * A TLB entry half the size of the configured
746 * huge page size is configured into entrylo0
747 * and entrylo1 to cover the contiguous huge PTE
748 * address space.
749 */
750 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
751
752 /* We can clobber tmp. It isn't used after this.*/
753 if (!small_sequence)
754 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
755
756 build_convert_pte_to_entrylo(p, pte);
757 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
758 /* convert to entrylo1 */
759 if (small_sequence)
760 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
761 else
762 UASM_i_ADDU(p, pte, pte, tmp);
763
764 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
765}
766
767static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
768 struct uasm_label **l,
769 unsigned int pte,
770 unsigned int ptr,
771 unsigned int flush)
772{
773#ifdef CONFIG_SMP
774 UASM_i_SC(p, pte, 0, ptr);
775 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
776 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
777#else
778 UASM_i_SW(p, pte, 0, ptr);
779#endif
780 if (cpu_has_ftlb && flush) {
781 BUG_ON(!cpu_has_tlbinv);
782
783 UASM_i_MFC0(p, ptr, C0_ENTRYHI);
784 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
785 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
786 build_tlb_write_entry(p, l, r, tlb_indexed);
787
788 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
789 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
790 build_huge_update_entries(p, pte, ptr);
791 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
792
793 return;
794 }
795
796 build_huge_update_entries(p, pte, ptr);
797 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
798}
799#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
800
801#ifdef CONFIG_64BIT
802/*
803 * TMP and PTR are scratch.
804 * TMP will be clobbered, PTR will hold the pmd entry.
805 */
806void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
807 unsigned int tmp, unsigned int ptr)
808{
809#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
810 long pgdc = (long)pgd_current;
811#endif
812 /*
813 * The vmalloc handling is not in the hotpath.
814 */
815 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
816
817 if (check_for_high_segbits) {
818 /*
819 * The kernel currently implicitely assumes that the
820 * MIPS SEGBITS parameter for the processor is
821 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
822 * allocate virtual addresses outside the maximum
823 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
824 * that doesn't prevent user code from accessing the
825 * higher xuseg addresses. Here, we make sure that
826 * everything but the lower xuseg addresses goes down
827 * the module_alloc/vmalloc path.
828 */
829 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
830 uasm_il_bnez(p, r, ptr, label_vmalloc);
831 } else {
832 uasm_il_bltz(p, r, tmp, label_vmalloc);
833 }
834 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
835
836 if (pgd_reg != -1) {
837 /* pgd is in pgd_reg */
838 if (cpu_has_ldpte)
839 UASM_i_MFC0(p, ptr, C0_PWBASE);
840 else
841 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
842 } else {
843#if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
844 /*
845 * &pgd << 11 stored in CONTEXT [23..63].
846 */
847 UASM_i_MFC0(p, ptr, C0_CONTEXT);
848
849 /* Clear lower 23 bits of context. */
850 uasm_i_dins(p, ptr, 0, 0, 23);
851
852 /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */
853 uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53));
854 uasm_i_drotr(p, ptr, ptr, 11);
855#elif defined(CONFIG_SMP)
856 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
857 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
858 UASM_i_LA_mostly(p, tmp, pgdc);
859 uasm_i_daddu(p, ptr, ptr, tmp);
860 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
861 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
862#else
863 UASM_i_LA_mostly(p, ptr, pgdc);
864 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
865#endif
866 }
867
868 uasm_l_vmalloc_done(l, *p);
869
870 /* get pgd offset in bytes */
871 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
872
873 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
874 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
875#ifndef __PAGETABLE_PUD_FOLDED
876 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
877 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */
878 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */
879 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3);
880 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */
881#endif
882#ifndef __PAGETABLE_PMD_FOLDED
883 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
884 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
885 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
886 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
887 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
888#endif
889}
890EXPORT_SYMBOL_GPL(build_get_pmde64);
891
892/*
893 * BVADDR is the faulting address, PTR is scratch.
894 * PTR will hold the pgd for vmalloc.
895 */
896static void
897build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
898 unsigned int bvaddr, unsigned int ptr,
899 enum vmalloc64_mode mode)
900{
901 long swpd = (long)swapper_pg_dir;
902 int single_insn_swpd;
903 int did_vmalloc_branch = 0;
904
905 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
906
907 uasm_l_vmalloc(l, *p);
908
909 if (mode != not_refill && check_for_high_segbits) {
910 if (single_insn_swpd) {
911 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
912 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
913 did_vmalloc_branch = 1;
914 /* fall through */
915 } else {
916 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
917 }
918 }
919 if (!did_vmalloc_branch) {
920 if (single_insn_swpd) {
921 uasm_il_b(p, r, label_vmalloc_done);
922 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
923 } else {
924 UASM_i_LA_mostly(p, ptr, swpd);
925 uasm_il_b(p, r, label_vmalloc_done);
926 if (uasm_in_compat_space_p(swpd))
927 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
928 else
929 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
930 }
931 }
932 if (mode != not_refill && check_for_high_segbits) {
933 uasm_l_large_segbits_fault(l, *p);
934
935 if (mode == refill_scratch && scratch_reg >= 0)
936 uasm_i_ehb(p);
937
938 /*
939 * We get here if we are an xsseg address, or if we are
940 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
941 *
942 * Ignoring xsseg (assume disabled so would generate
943 * (address errors?), the only remaining possibility
944 * is the upper xuseg addresses. On processors with
945 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
946 * addresses would have taken an address error. We try
947 * to mimic that here by taking a load/istream page
948 * fault.
949 */
950 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
951 uasm_i_sync(p, 0);
952 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
953 uasm_i_jr(p, ptr);
954
955 if (mode == refill_scratch) {
956 if (scratch_reg >= 0)
957 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
958 else
959 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
960 } else {
961 uasm_i_nop(p);
962 }
963 }
964}
965
966#else /* !CONFIG_64BIT */
967
968/*
969 * TMP and PTR are scratch.
970 * TMP will be clobbered, PTR will hold the pgd entry.
971 */
972void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
973{
974 if (pgd_reg != -1) {
975 /* pgd is in pgd_reg */
976 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
977 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
978 } else {
979 long pgdc = (long)pgd_current;
980
981 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
982#ifdef CONFIG_SMP
983 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
984 UASM_i_LA_mostly(p, tmp, pgdc);
985 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
986 uasm_i_addu(p, ptr, tmp, ptr);
987#else
988 UASM_i_LA_mostly(p, ptr, pgdc);
989#endif
990 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
991 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
992 }
993 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
994 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
995 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
996}
997EXPORT_SYMBOL_GPL(build_get_pgde32);
998
999#endif /* !CONFIG_64BIT */
1000
1001static void build_adjust_context(u32 **p, unsigned int ctx)
1002{
1003 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1004 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1005
1006 switch (current_cpu_type()) {
1007 case CPU_VR41XX:
1008 case CPU_VR4111:
1009 case CPU_VR4121:
1010 case CPU_VR4122:
1011 case CPU_VR4131:
1012 case CPU_VR4181:
1013 case CPU_VR4181A:
1014 case CPU_VR4133:
1015 shift += 2;
1016 break;
1017
1018 default:
1019 break;
1020 }
1021
1022 if (shift)
1023 UASM_i_SRL(p, ctx, ctx, shift);
1024 uasm_i_andi(p, ctx, ctx, mask);
1025}
1026
1027void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1028{
1029 /*
1030 * Bug workaround for the Nevada. It seems as if under certain
1031 * circumstances the move from cp0_context might produce a
1032 * bogus result when the mfc0 instruction and its consumer are
1033 * in a different cacheline or a load instruction, probably any
1034 * memory reference, is between them.
1035 */
1036 switch (current_cpu_type()) {
1037 case CPU_NEVADA:
1038 UASM_i_LW(p, ptr, 0, ptr);
1039 GET_CONTEXT(p, tmp); /* get context reg */
1040 break;
1041
1042 default:
1043 GET_CONTEXT(p, tmp); /* get context reg */
1044 UASM_i_LW(p, ptr, 0, ptr);
1045 break;
1046 }
1047
1048 build_adjust_context(p, tmp);
1049 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1050}
1051EXPORT_SYMBOL_GPL(build_get_ptep);
1052
1053void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1054{
1055 int pte_off_even = 0;
1056 int pte_off_odd = sizeof(pte_t);
1057
1058#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
1059 /* The low 32 bits of EntryLo is stored in pte_high */
1060 pte_off_even += offsetof(pte_t, pte_high);
1061 pte_off_odd += offsetof(pte_t, pte_high);
1062#endif
1063
1064 if (IS_ENABLED(CONFIG_XPA)) {
1065 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
1066 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1067 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
1068
1069 if (cpu_has_xpa && !mips_xpa_disabled) {
1070 uasm_i_lw(p, tmp, 0, ptep);
1071 uasm_i_ext(p, tmp, tmp, 0, 24);
1072 uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1073 }
1074
1075 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
1076 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1077 UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
1078
1079 if (cpu_has_xpa && !mips_xpa_disabled) {
1080 uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
1081 uasm_i_ext(p, tmp, tmp, 0, 24);
1082 uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
1083 }
1084 return;
1085 }
1086
1087 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
1088 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
1089 if (r45k_bvahwbug())
1090 build_tlb_probe_entry(p);
1091 build_convert_pte_to_entrylo(p, tmp);
1092 if (r4k_250MHZhwbug())
1093 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1094 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1095 build_convert_pte_to_entrylo(p, ptep);
1096 if (r45k_bvahwbug())
1097 uasm_i_mfc0(p, tmp, C0_INDEX);
1098 if (r4k_250MHZhwbug())
1099 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1100 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1101}
1102EXPORT_SYMBOL_GPL(build_update_entries);
1103
1104struct mips_huge_tlb_info {
1105 int huge_pte;
1106 int restore_scratch;
1107 bool need_reload_pte;
1108};
1109
1110static struct mips_huge_tlb_info
1111build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1112 struct uasm_reloc **r, unsigned int tmp,
1113 unsigned int ptr, int c0_scratch_reg)
1114{
1115 struct mips_huge_tlb_info rv;
1116 unsigned int even, odd;
1117 int vmalloc_branch_delay_filled = 0;
1118 const int scratch = 1; /* Our extra working register */
1119
1120 rv.huge_pte = scratch;
1121 rv.restore_scratch = 0;
1122 rv.need_reload_pte = false;
1123
1124 if (check_for_high_segbits) {
1125 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1126
1127 if (pgd_reg != -1)
1128 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1129 else
1130 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1131
1132 if (c0_scratch_reg >= 0)
1133 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1134 else
1135 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1136
1137 uasm_i_dsrl_safe(p, scratch, tmp,
1138 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1139 uasm_il_bnez(p, r, scratch, label_vmalloc);
1140
1141 if (pgd_reg == -1) {
1142 vmalloc_branch_delay_filled = 1;
1143 /* Clear lower 23 bits of context. */
1144 uasm_i_dins(p, ptr, 0, 0, 23);
1145 }
1146 } else {
1147 if (pgd_reg != -1)
1148 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1149 else
1150 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1151
1152 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1153
1154 if (c0_scratch_reg >= 0)
1155 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1156 else
1157 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1158
1159 if (pgd_reg == -1)
1160 /* Clear lower 23 bits of context. */
1161 uasm_i_dins(p, ptr, 0, 0, 23);
1162
1163 uasm_il_bltz(p, r, tmp, label_vmalloc);
1164 }
1165
1166 if (pgd_reg == -1) {
1167 vmalloc_branch_delay_filled = 1;
1168 /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */
1169 uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53));
1170
1171 uasm_i_drotr(p, ptr, ptr, 11);
1172 }
1173
1174#ifdef __PAGETABLE_PMD_FOLDED
1175#define LOC_PTEP scratch
1176#else
1177#define LOC_PTEP ptr
1178#endif
1179
1180 if (!vmalloc_branch_delay_filled)
1181 /* get pgd offset in bytes */
1182 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1183
1184 uasm_l_vmalloc_done(l, *p);
1185
1186 /*
1187 * tmp ptr
1188 * fall-through case = badvaddr *pgd_current
1189 * vmalloc case = badvaddr swapper_pg_dir
1190 */
1191
1192 if (vmalloc_branch_delay_filled)
1193 /* get pgd offset in bytes */
1194 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1195
1196#ifdef __PAGETABLE_PMD_FOLDED
1197 GET_CONTEXT(p, tmp); /* get context reg */
1198#endif
1199 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1200
1201 if (use_lwx_insns()) {
1202 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1203 } else {
1204 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1205 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1206 }
1207
1208#ifndef __PAGETABLE_PUD_FOLDED
1209 /* get pud offset in bytes */
1210 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3);
1211 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3);
1212
1213 if (use_lwx_insns()) {
1214 UASM_i_LWX(p, ptr, scratch, ptr);
1215 } else {
1216 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1217 UASM_i_LW(p, ptr, 0, ptr);
1218 }
1219 /* ptr contains a pointer to PMD entry */
1220 /* tmp contains the address */
1221#endif
1222
1223#ifndef __PAGETABLE_PMD_FOLDED
1224 /* get pmd offset in bytes */
1225 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1226 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1227 GET_CONTEXT(p, tmp); /* get context reg */
1228
1229 if (use_lwx_insns()) {
1230 UASM_i_LWX(p, scratch, scratch, ptr);
1231 } else {
1232 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1233 UASM_i_LW(p, scratch, 0, ptr);
1234 }
1235#endif
1236 /* Adjust the context during the load latency. */
1237 build_adjust_context(p, tmp);
1238
1239#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1240 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1241 /*
1242 * The in the LWX case we don't want to do the load in the
1243 * delay slot. It cannot issue in the same cycle and may be
1244 * speculative and unneeded.
1245 */
1246 if (use_lwx_insns())
1247 uasm_i_nop(p);
1248#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1249
1250
1251 /* build_update_entries */
1252 if (use_lwx_insns()) {
1253 even = ptr;
1254 odd = tmp;
1255 UASM_i_LWX(p, even, scratch, tmp);
1256 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1257 UASM_i_LWX(p, odd, scratch, tmp);
1258 } else {
1259 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1260 even = tmp;
1261 odd = ptr;
1262 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1263 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1264 }
1265 if (cpu_has_rixi) {
1266 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1267 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1268 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1269 } else {
1270 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1271 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1272 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1273 }
1274 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1275
1276 if (c0_scratch_reg >= 0) {
1277 uasm_i_ehb(p);
1278 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1279 build_tlb_write_entry(p, l, r, tlb_random);
1280 uasm_l_leave(l, *p);
1281 rv.restore_scratch = 1;
1282 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1283 build_tlb_write_entry(p, l, r, tlb_random);
1284 uasm_l_leave(l, *p);
1285 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1286 } else {
1287 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1288 build_tlb_write_entry(p, l, r, tlb_random);
1289 uasm_l_leave(l, *p);
1290 rv.restore_scratch = 1;
1291 }
1292
1293 uasm_i_eret(p); /* return from trap */
1294
1295 return rv;
1296}
1297
1298/*
1299 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1300 * because EXL == 0. If we wrap, we can also use the 32 instruction
1301 * slots before the XTLB refill exception handler which belong to the
1302 * unused TLB refill exception.
1303 */
1304#define MIPS64_REFILL_INSNS 32
1305
1306static void build_r4000_tlb_refill_handler(void)
1307{
1308 u32 *p = tlb_handler;
1309 struct uasm_label *l = labels;
1310 struct uasm_reloc *r = relocs;
1311 u32 *f;
1312 unsigned int final_len;
1313 struct mips_huge_tlb_info htlb_info __maybe_unused;
1314 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1315
1316 memset(tlb_handler, 0, sizeof(tlb_handler));
1317 memset(labels, 0, sizeof(labels));
1318 memset(relocs, 0, sizeof(relocs));
1319 memset(final_handler, 0, sizeof(final_handler));
1320
1321 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1322 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1323 scratch_reg);
1324 vmalloc_mode = refill_scratch;
1325 } else {
1326 htlb_info.huge_pte = K0;
1327 htlb_info.restore_scratch = 0;
1328 htlb_info.need_reload_pte = true;
1329 vmalloc_mode = refill_noscratch;
1330 /*
1331 * create the plain linear handler
1332 */
1333 if (bcm1250_m3_war()) {
1334 unsigned int segbits = 44;
1335
1336 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1337 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1338 uasm_i_xor(&p, K0, K0, K1);
1339 uasm_i_dsrl_safe(&p, K1, K0, 62);
1340 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1341 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1342 uasm_i_or(&p, K0, K0, K1);
1343 uasm_il_bnez(&p, &r, K0, label_leave);
1344 /* No need for uasm_i_nop */
1345 }
1346
1347#ifdef CONFIG_64BIT
1348 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1349#else
1350 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1351#endif
1352
1353#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1354 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1355#endif
1356
1357 build_get_ptep(&p, K0, K1);
1358 build_update_entries(&p, K0, K1);
1359 build_tlb_write_entry(&p, &l, &r, tlb_random);
1360 uasm_l_leave(&l, p);
1361 uasm_i_eret(&p); /* return from trap */
1362 }
1363#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1364 uasm_l_tlb_huge_update(&l, p);
1365 if (htlb_info.need_reload_pte)
1366 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1367 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1368 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1369 htlb_info.restore_scratch);
1370#endif
1371
1372#ifdef CONFIG_64BIT
1373 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1374#endif
1375
1376 /*
1377 * Overflow check: For the 64bit handler, we need at least one
1378 * free instruction slot for the wrap-around branch. In worst
1379 * case, if the intended insertion point is a delay slot, we
1380 * need three, with the second nop'ed and the third being
1381 * unused.
1382 */
1383 switch (boot_cpu_type()) {
1384 default:
1385 if (sizeof(long) == 4) {
1386 fallthrough;
1387 case CPU_LOONGSON2EF:
1388 /* Loongson2 ebase is different than r4k, we have more space */
1389 if ((p - tlb_handler) > 64)
1390 panic("TLB refill handler space exceeded");
1391 /*
1392 * Now fold the handler in the TLB refill handler space.
1393 */
1394 f = final_handler;
1395 /* Simplest case, just copy the handler. */
1396 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1397 final_len = p - tlb_handler;
1398 break;
1399 } else {
1400 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1401 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1402 && uasm_insn_has_bdelay(relocs,
1403 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1404 panic("TLB refill handler space exceeded");
1405 /*
1406 * Now fold the handler in the TLB refill handler space.
1407 */
1408 f = final_handler + MIPS64_REFILL_INSNS;
1409 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1410 /* Just copy the handler. */
1411 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1412 final_len = p - tlb_handler;
1413 } else {
1414#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1415 const enum label_id ls = label_tlb_huge_update;
1416#else
1417 const enum label_id ls = label_vmalloc;
1418#endif
1419 u32 *split;
1420 int ov = 0;
1421 int i;
1422
1423 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1424 ;
1425 BUG_ON(i == ARRAY_SIZE(labels));
1426 split = labels[i].addr;
1427
1428 /*
1429 * See if we have overflown one way or the other.
1430 */
1431 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1432 split < p - MIPS64_REFILL_INSNS)
1433 ov = 1;
1434
1435 if (ov) {
1436 /*
1437 * Split two instructions before the end. One
1438 * for the branch and one for the instruction
1439 * in the delay slot.
1440 */
1441 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1442
1443 /*
1444 * If the branch would fall in a delay slot,
1445 * we must back up an additional instruction
1446 * so that it is no longer in a delay slot.
1447 */
1448 if (uasm_insn_has_bdelay(relocs, split - 1))
1449 split--;
1450 }
1451 /* Copy first part of the handler. */
1452 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1453 f += split - tlb_handler;
1454
1455 if (ov) {
1456 /* Insert branch. */
1457 uasm_l_split(&l, final_handler);
1458 uasm_il_b(&f, &r, label_split);
1459 if (uasm_insn_has_bdelay(relocs, split))
1460 uasm_i_nop(&f);
1461 else {
1462 uasm_copy_handler(relocs, labels,
1463 split, split + 1, f);
1464 uasm_move_labels(labels, f, f + 1, -1);
1465 f++;
1466 split++;
1467 }
1468 }
1469
1470 /* Copy the rest of the handler. */
1471 uasm_copy_handler(relocs, labels, split, p, final_handler);
1472 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1473 (p - split);
1474 }
1475 }
1476 break;
1477 }
1478
1479 uasm_resolve_relocs(relocs, labels);
1480 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1481 final_len);
1482
1483 memcpy((void *)ebase, final_handler, 0x100);
1484 local_flush_icache_range(ebase, ebase + 0x100);
1485 dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100));
1486}
1487
1488static void setup_pw(void)
1489{
1490 unsigned int pwctl;
1491 unsigned long pgd_i, pgd_w;
1492#ifndef __PAGETABLE_PMD_FOLDED
1493 unsigned long pmd_i, pmd_w;
1494#endif
1495 unsigned long pt_i, pt_w;
1496 unsigned long pte_i, pte_w;
1497#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1498 unsigned long psn;
1499
1500 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */
1501#endif
1502 pgd_i = PGDIR_SHIFT; /* 1st level PGD */
1503#ifndef __PAGETABLE_PMD_FOLDED
1504 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
1505
1506 pmd_i = PMD_SHIFT; /* 2nd level PMD */
1507 pmd_w = PMD_SHIFT - PAGE_SHIFT;
1508#else
1509 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
1510#endif
1511
1512 pt_i = PAGE_SHIFT; /* 3rd level PTE */
1513 pt_w = PAGE_SHIFT - 3;
1514
1515 pte_i = ilog2(_PAGE_GLOBAL);
1516 pte_w = 0;
1517 pwctl = 1 << 30; /* Set PWDirExt */
1518
1519#ifndef __PAGETABLE_PMD_FOLDED
1520 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
1521 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
1522#else
1523 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
1524 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
1525#endif
1526
1527#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1528 pwctl |= (1 << 6 | psn);
1529#endif
1530 write_c0_pwctl(pwctl);
1531 write_c0_kpgd((long)swapper_pg_dir);
1532 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
1533}
1534
1535static void build_loongson3_tlb_refill_handler(void)
1536{
1537 u32 *p = tlb_handler;
1538 struct uasm_label *l = labels;
1539 struct uasm_reloc *r = relocs;
1540
1541 memset(labels, 0, sizeof(labels));
1542 memset(relocs, 0, sizeof(relocs));
1543 memset(tlb_handler, 0, sizeof(tlb_handler));
1544
1545 if (check_for_high_segbits) {
1546 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1547 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1548 uasm_il_beqz(&p, &r, K1, label_vmalloc);
1549 uasm_i_nop(&p);
1550
1551 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
1552 uasm_i_nop(&p);
1553 uasm_l_vmalloc(&l, p);
1554 }
1555
1556 uasm_i_dmfc0(&p, K1, C0_PGD);
1557
1558 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
1559#ifndef __PAGETABLE_PMD_FOLDED
1560 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
1561#endif
1562 uasm_i_ldpte(&p, K1, 0); /* even */
1563 uasm_i_ldpte(&p, K1, 1); /* odd */
1564 uasm_i_tlbwr(&p);
1565
1566 /* restore page mask */
1567 if (PM_DEFAULT_MASK >> 16) {
1568 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
1569 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
1570 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1571 } else if (PM_DEFAULT_MASK) {
1572 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
1573 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1574 } else {
1575 uasm_i_mtc0(&p, 0, C0_PAGEMASK);
1576 }
1577
1578 uasm_i_eret(&p);
1579
1580 if (check_for_high_segbits) {
1581 uasm_l_large_segbits_fault(&l, p);
1582 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
1583 uasm_i_jr(&p, K1);
1584 uasm_i_nop(&p);
1585 }
1586
1587 uasm_resolve_relocs(relocs, labels);
1588 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
1589 local_flush_icache_range(ebase + 0x80, ebase + 0x100);
1590 dump_handler("loongson3_tlb_refill",
1591 (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100));
1592}
1593
1594static void build_setup_pgd(void)
1595{
1596 const int a0 = 4;
1597 const int __maybe_unused a1 = 5;
1598 const int __maybe_unused a2 = 6;
1599 u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd);
1600#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1601 long pgdc = (long)pgd_current;
1602#endif
1603
1604 memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p);
1605 memset(labels, 0, sizeof(labels));
1606 memset(relocs, 0, sizeof(relocs));
1607 pgd_reg = allocate_kscratch();
1608#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1609 if (pgd_reg == -1) {
1610 struct uasm_label *l = labels;
1611 struct uasm_reloc *r = relocs;
1612
1613 /* PGD << 11 in c0_Context */
1614 /*
1615 * If it is a ckseg0 address, convert to a physical
1616 * address. Shifting right by 29 and adding 4 will
1617 * result in zero for these addresses.
1618 *
1619 */
1620 UASM_i_SRA(&p, a1, a0, 29);
1621 UASM_i_ADDIU(&p, a1, a1, 4);
1622 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1623 uasm_i_nop(&p);
1624 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1625 uasm_l_tlbl_goaround1(&l, p);
1626 UASM_i_SLL(&p, a0, a0, 11);
1627 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1628 uasm_i_jr(&p, 31);
1629 uasm_i_ehb(&p);
1630 } else {
1631 /* PGD in c0_KScratch */
1632 if (cpu_has_ldpte)
1633 UASM_i_MTC0(&p, a0, C0_PWBASE);
1634 else
1635 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1636 uasm_i_jr(&p, 31);
1637 uasm_i_ehb(&p);
1638 }
1639#else
1640#ifdef CONFIG_SMP
1641 /* Save PGD to pgd_current[smp_processor_id()] */
1642 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1643 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1644 UASM_i_LA_mostly(&p, a2, pgdc);
1645 UASM_i_ADDU(&p, a2, a2, a1);
1646 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1647#else
1648 UASM_i_LA_mostly(&p, a2, pgdc);
1649 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1650#endif /* SMP */
1651
1652 /* if pgd_reg is allocated, save PGD also to scratch register */
1653 if (pgd_reg != -1) {
1654 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1655 uasm_i_jr(&p, 31);
1656 uasm_i_ehb(&p);
1657 } else {
1658 uasm_i_jr(&p, 31);
1659 uasm_i_nop(&p);
1660 }
1661#endif
1662 if (p >= (u32 *)tlbmiss_handler_setup_pgd_end)
1663 panic("tlbmiss_handler_setup_pgd space exceeded");
1664
1665 uasm_resolve_relocs(relocs, labels);
1666 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1667 (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd));
1668
1669 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1670 tlbmiss_handler_setup_pgd_end);
1671}
1672
1673static void
1674iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1675{
1676#ifdef CONFIG_SMP
1677 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
1678 uasm_i_sync(p, 0);
1679# ifdef CONFIG_PHYS_ADDR_T_64BIT
1680 if (cpu_has_64bits)
1681 uasm_i_lld(p, pte, 0, ptr);
1682 else
1683# endif
1684 UASM_i_LL(p, pte, 0, ptr);
1685#else
1686# ifdef CONFIG_PHYS_ADDR_T_64BIT
1687 if (cpu_has_64bits)
1688 uasm_i_ld(p, pte, 0, ptr);
1689 else
1690# endif
1691 UASM_i_LW(p, pte, 0, ptr);
1692#endif
1693}
1694
1695static void
1696iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1697 unsigned int mode, unsigned int scratch)
1698{
1699 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1700 unsigned int swmode = mode & ~hwmode;
1701
1702 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
1703 uasm_i_lui(p, scratch, swmode >> 16);
1704 uasm_i_or(p, pte, pte, scratch);
1705 BUG_ON(swmode & 0xffff);
1706 } else {
1707 uasm_i_ori(p, pte, pte, mode);
1708 }
1709
1710#ifdef CONFIG_SMP
1711# ifdef CONFIG_PHYS_ADDR_T_64BIT
1712 if (cpu_has_64bits)
1713 uasm_i_scd(p, pte, 0, ptr);
1714 else
1715# endif
1716 UASM_i_SC(p, pte, 0, ptr);
1717
1718 if (r10000_llsc_war())
1719 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1720 else
1721 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1722
1723# ifdef CONFIG_PHYS_ADDR_T_64BIT
1724 if (!cpu_has_64bits) {
1725 /* no uasm_i_nop needed */
1726 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1727 uasm_i_ori(p, pte, pte, hwmode);
1728 BUG_ON(hwmode & ~0xffff);
1729 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1730 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1731 /* no uasm_i_nop needed */
1732 uasm_i_lw(p, pte, 0, ptr);
1733 } else
1734 uasm_i_nop(p);
1735# else
1736 uasm_i_nop(p);
1737# endif
1738#else
1739# ifdef CONFIG_PHYS_ADDR_T_64BIT
1740 if (cpu_has_64bits)
1741 uasm_i_sd(p, pte, 0, ptr);
1742 else
1743# endif
1744 UASM_i_SW(p, pte, 0, ptr);
1745
1746# ifdef CONFIG_PHYS_ADDR_T_64BIT
1747 if (!cpu_has_64bits) {
1748 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1749 uasm_i_ori(p, pte, pte, hwmode);
1750 BUG_ON(hwmode & ~0xffff);
1751 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1752 uasm_i_lw(p, pte, 0, ptr);
1753 }
1754# endif
1755#endif
1756}
1757
1758/*
1759 * Check if PTE is present, if not then jump to LABEL. PTR points to
1760 * the page table where this PTE is located, PTE will be re-loaded
1761 * with it's original value.
1762 */
1763static void
1764build_pte_present(u32 **p, struct uasm_reloc **r,
1765 int pte, int ptr, int scratch, enum label_id lid)
1766{
1767 int t = scratch >= 0 ? scratch : pte;
1768 int cur = pte;
1769
1770 if (cpu_has_rixi) {
1771 if (use_bbit_insns()) {
1772 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1773 uasm_i_nop(p);
1774 } else {
1775 if (_PAGE_PRESENT_SHIFT) {
1776 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1777 cur = t;
1778 }
1779 uasm_i_andi(p, t, cur, 1);
1780 uasm_il_beqz(p, r, t, lid);
1781 if (pte == t)
1782 /* You lose the SMP race :-(*/
1783 iPTE_LW(p, pte, ptr);
1784 }
1785 } else {
1786 if (_PAGE_PRESENT_SHIFT) {
1787 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1788 cur = t;
1789 }
1790 uasm_i_andi(p, t, cur,
1791 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
1792 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
1793 uasm_il_bnez(p, r, t, lid);
1794 if (pte == t)
1795 /* You lose the SMP race :-(*/
1796 iPTE_LW(p, pte, ptr);
1797 }
1798}
1799
1800/* Make PTE valid, store result in PTR. */
1801static void
1802build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1803 unsigned int ptr, unsigned int scratch)
1804{
1805 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1806
1807 iPTE_SW(p, r, pte, ptr, mode, scratch);
1808}
1809
1810/*
1811 * Check if PTE can be written to, if not branch to LABEL. Regardless
1812 * restore PTE with value from PTR when done.
1813 */
1814static void
1815build_pte_writable(u32 **p, struct uasm_reloc **r,
1816 unsigned int pte, unsigned int ptr, int scratch,
1817 enum label_id lid)
1818{
1819 int t = scratch >= 0 ? scratch : pte;
1820 int cur = pte;
1821
1822 if (_PAGE_PRESENT_SHIFT) {
1823 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1824 cur = t;
1825 }
1826 uasm_i_andi(p, t, cur,
1827 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1828 uasm_i_xori(p, t, t,
1829 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1830 uasm_il_bnez(p, r, t, lid);
1831 if (pte == t)
1832 /* You lose the SMP race :-(*/
1833 iPTE_LW(p, pte, ptr);
1834 else
1835 uasm_i_nop(p);
1836}
1837
1838/* Make PTE writable, update software status bits as well, then store
1839 * at PTR.
1840 */
1841static void
1842build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1843 unsigned int ptr, unsigned int scratch)
1844{
1845 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1846 | _PAGE_DIRTY);
1847
1848 iPTE_SW(p, r, pte, ptr, mode, scratch);
1849}
1850
1851/*
1852 * Check if PTE can be modified, if not branch to LABEL. Regardless
1853 * restore PTE with value from PTR when done.
1854 */
1855static void
1856build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1857 unsigned int pte, unsigned int ptr, int scratch,
1858 enum label_id lid)
1859{
1860 if (use_bbit_insns()) {
1861 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1862 uasm_i_nop(p);
1863 } else {
1864 int t = scratch >= 0 ? scratch : pte;
1865 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1866 uasm_i_andi(p, t, t, 1);
1867 uasm_il_beqz(p, r, t, lid);
1868 if (pte == t)
1869 /* You lose the SMP race :-(*/
1870 iPTE_LW(p, pte, ptr);
1871 }
1872}
1873
1874#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1875
1876
1877/*
1878 * R3000 style TLB load/store/modify handlers.
1879 */
1880
1881/*
1882 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1883 * Then it returns.
1884 */
1885static void
1886build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1887{
1888 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1889 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1890 uasm_i_tlbwi(p);
1891 uasm_i_jr(p, tmp);
1892 uasm_i_rfe(p); /* branch delay */
1893}
1894
1895/*
1896 * This places the pte into ENTRYLO0 and writes it with tlbwi
1897 * or tlbwr as appropriate. This is because the index register
1898 * may have the probe fail bit set as a result of a trap on a
1899 * kseg2 access, i.e. without refill. Then it returns.
1900 */
1901static void
1902build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1903 struct uasm_reloc **r, unsigned int pte,
1904 unsigned int tmp)
1905{
1906 uasm_i_mfc0(p, tmp, C0_INDEX);
1907 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1908 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1909 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1910 uasm_i_tlbwi(p); /* cp0 delay */
1911 uasm_i_jr(p, tmp);
1912 uasm_i_rfe(p); /* branch delay */
1913 uasm_l_r3000_write_probe_fail(l, *p);
1914 uasm_i_tlbwr(p); /* cp0 delay */
1915 uasm_i_jr(p, tmp);
1916 uasm_i_rfe(p); /* branch delay */
1917}
1918
1919static void
1920build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1921 unsigned int ptr)
1922{
1923 long pgdc = (long)pgd_current;
1924
1925 uasm_i_mfc0(p, pte, C0_BADVADDR);
1926 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1927 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1928 uasm_i_srl(p, pte, pte, 22); /* load delay */
1929 uasm_i_sll(p, pte, pte, 2);
1930 uasm_i_addu(p, ptr, ptr, pte);
1931 uasm_i_mfc0(p, pte, C0_CONTEXT);
1932 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1933 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1934 uasm_i_addu(p, ptr, ptr, pte);
1935 uasm_i_lw(p, pte, 0, ptr);
1936 uasm_i_tlbp(p); /* load delay */
1937}
1938
1939static void build_r3000_tlb_load_handler(void)
1940{
1941 u32 *p = (u32 *)handle_tlbl;
1942 struct uasm_label *l = labels;
1943 struct uasm_reloc *r = relocs;
1944
1945 memset(p, 0, handle_tlbl_end - (char *)p);
1946 memset(labels, 0, sizeof(labels));
1947 memset(relocs, 0, sizeof(relocs));
1948
1949 build_r3000_tlbchange_handler_head(&p, K0, K1);
1950 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1951 uasm_i_nop(&p); /* load delay */
1952 build_make_valid(&p, &r, K0, K1, -1);
1953 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1954
1955 uasm_l_nopage_tlbl(&l, p);
1956 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1957 uasm_i_nop(&p);
1958
1959 if (p >= (u32 *)handle_tlbl_end)
1960 panic("TLB load handler fastpath space exceeded");
1961
1962 uasm_resolve_relocs(relocs, labels);
1963 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1964 (unsigned int)(p - (u32 *)handle_tlbl));
1965
1966 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end);
1967}
1968
1969static void build_r3000_tlb_store_handler(void)
1970{
1971 u32 *p = (u32 *)handle_tlbs;
1972 struct uasm_label *l = labels;
1973 struct uasm_reloc *r = relocs;
1974
1975 memset(p, 0, handle_tlbs_end - (char *)p);
1976 memset(labels, 0, sizeof(labels));
1977 memset(relocs, 0, sizeof(relocs));
1978
1979 build_r3000_tlbchange_handler_head(&p, K0, K1);
1980 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1981 uasm_i_nop(&p); /* load delay */
1982 build_make_write(&p, &r, K0, K1, -1);
1983 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1984
1985 uasm_l_nopage_tlbs(&l, p);
1986 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1987 uasm_i_nop(&p);
1988
1989 if (p >= (u32 *)handle_tlbs_end)
1990 panic("TLB store handler fastpath space exceeded");
1991
1992 uasm_resolve_relocs(relocs, labels);
1993 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1994 (unsigned int)(p - (u32 *)handle_tlbs));
1995
1996 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end);
1997}
1998
1999static void build_r3000_tlb_modify_handler(void)
2000{
2001 u32 *p = (u32 *)handle_tlbm;
2002 struct uasm_label *l = labels;
2003 struct uasm_reloc *r = relocs;
2004
2005 memset(p, 0, handle_tlbm_end - (char *)p);
2006 memset(labels, 0, sizeof(labels));
2007 memset(relocs, 0, sizeof(relocs));
2008
2009 build_r3000_tlbchange_handler_head(&p, K0, K1);
2010 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
2011 uasm_i_nop(&p); /* load delay */
2012 build_make_write(&p, &r, K0, K1, -1);
2013 build_r3000_pte_reload_tlbwi(&p, K0, K1);
2014
2015 uasm_l_nopage_tlbm(&l, p);
2016 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2017 uasm_i_nop(&p);
2018
2019 if (p >= (u32 *)handle_tlbm_end)
2020 panic("TLB modify handler fastpath space exceeded");
2021
2022 uasm_resolve_relocs(relocs, labels);
2023 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2024 (unsigned int)(p - (u32 *)handle_tlbm));
2025
2026 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end);
2027}
2028#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
2029
2030static bool cpu_has_tlbex_tlbp_race(void)
2031{
2032 /*
2033 * When a Hardware Table Walker is running it can replace TLB entries
2034 * at any time, leading to a race between it & the CPU.
2035 */
2036 if (cpu_has_htw)
2037 return true;
2038
2039 /*
2040 * If the CPU shares FTLB RAM with its siblings then our entry may be
2041 * replaced at any time by a sibling performing a write to the FTLB.
2042 */
2043 if (cpu_has_shared_ftlb_ram)
2044 return true;
2045
2046 /* In all other cases there ought to be no race condition to handle */
2047 return false;
2048}
2049
2050/*
2051 * R4000 style TLB load/store/modify handlers.
2052 */
2053static struct work_registers
2054build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
2055 struct uasm_reloc **r)
2056{
2057 struct work_registers wr = build_get_work_registers(p);
2058
2059#ifdef CONFIG_64BIT
2060 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
2061#else
2062 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
2063#endif
2064
2065#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2066 /*
2067 * For huge tlb entries, pmd doesn't contain an address but
2068 * instead contains the tlb pte. Check the PAGE_HUGE bit and
2069 * see if we need to jump to huge tlb processing.
2070 */
2071 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
2072#endif
2073
2074 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
2075 UASM_i_LW(p, wr.r2, 0, wr.r2);
2076 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
2077 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
2078 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
2079
2080#ifdef CONFIG_SMP
2081 uasm_l_smp_pgtable_change(l, *p);
2082#endif
2083 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
2084 if (!m4kc_tlbp_war()) {
2085 build_tlb_probe_entry(p);
2086 if (cpu_has_tlbex_tlbp_race()) {
2087 /* race condition happens, leaving */
2088 uasm_i_ehb(p);
2089 uasm_i_mfc0(p, wr.r3, C0_INDEX);
2090 uasm_il_bltz(p, r, wr.r3, label_leave);
2091 uasm_i_nop(p);
2092 }
2093 }
2094 return wr;
2095}
2096
2097static void
2098build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
2099 struct uasm_reloc **r, unsigned int tmp,
2100 unsigned int ptr)
2101{
2102 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
2103 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
2104 build_update_entries(p, tmp, ptr);
2105 build_tlb_write_entry(p, l, r, tlb_indexed);
2106 uasm_l_leave(l, *p);
2107 build_restore_work_registers(p);
2108 uasm_i_eret(p); /* return from trap */
2109
2110#ifdef CONFIG_64BIT
2111 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
2112#endif
2113}
2114
2115static void build_r4000_tlb_load_handler(void)
2116{
2117 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl);
2118 struct uasm_label *l = labels;
2119 struct uasm_reloc *r = relocs;
2120 struct work_registers wr;
2121
2122 memset(p, 0, handle_tlbl_end - (char *)p);
2123 memset(labels, 0, sizeof(labels));
2124 memset(relocs, 0, sizeof(relocs));
2125
2126 if (bcm1250_m3_war()) {
2127 unsigned int segbits = 44;
2128
2129 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
2130 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
2131 uasm_i_xor(&p, K0, K0, K1);
2132 uasm_i_dsrl_safe(&p, K1, K0, 62);
2133 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
2134 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
2135 uasm_i_or(&p, K0, K0, K1);
2136 uasm_il_bnez(&p, &r, K0, label_leave);
2137 /* No need for uasm_i_nop */
2138 }
2139
2140 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2141 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2142 if (m4kc_tlbp_war())
2143 build_tlb_probe_entry(&p);
2144
2145 if (cpu_has_rixi && !cpu_has_rixiex) {
2146 /*
2147 * If the page is not _PAGE_VALID, RI or XI could not
2148 * have triggered it. Skip the expensive test..
2149 */
2150 if (use_bbit_insns()) {
2151 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2152 label_tlbl_goaround1);
2153 } else {
2154 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2155 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
2156 }
2157 uasm_i_nop(&p);
2158
2159 /*
2160 * Warn if something may race with us & replace the TLB entry
2161 * before we read it here. Everything with such races should
2162 * also have dedicated RiXi exception handlers, so this
2163 * shouldn't be hit.
2164 */
2165 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2166
2167 uasm_i_tlbr(&p);
2168
2169 switch (current_cpu_type()) {
2170 default:
2171 if (cpu_has_mips_r2_exec_hazard) {
2172 uasm_i_ehb(&p);
2173 fallthrough;
2174
2175 case CPU_CAVIUM_OCTEON:
2176 case CPU_CAVIUM_OCTEON_PLUS:
2177 case CPU_CAVIUM_OCTEON2:
2178 break;
2179 }
2180 }
2181
2182 /* Examine entrylo 0 or 1 based on ptr. */
2183 if (use_bbit_insns()) {
2184 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2185 } else {
2186 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2187 uasm_i_beqz(&p, wr.r3, 8);
2188 }
2189 /* load it in the delay slot*/
2190 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2191 /* load it if ptr is odd */
2192 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2193 /*
2194 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2195 * XI must have triggered it.
2196 */
2197 if (use_bbit_insns()) {
2198 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2199 uasm_i_nop(&p);
2200 uasm_l_tlbl_goaround1(&l, p);
2201 } else {
2202 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2203 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2204 uasm_i_nop(&p);
2205 }
2206 uasm_l_tlbl_goaround1(&l, p);
2207 }
2208 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
2209 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2210
2211#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2212 /*
2213 * This is the entry point when build_r4000_tlbchange_handler_head
2214 * spots a huge page.
2215 */
2216 uasm_l_tlb_huge_update(&l, p);
2217 iPTE_LW(&p, wr.r1, wr.r2);
2218 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2219 build_tlb_probe_entry(&p);
2220
2221 if (cpu_has_rixi && !cpu_has_rixiex) {
2222 /*
2223 * If the page is not _PAGE_VALID, RI or XI could not
2224 * have triggered it. Skip the expensive test..
2225 */
2226 if (use_bbit_insns()) {
2227 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2228 label_tlbl_goaround2);
2229 } else {
2230 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2231 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2232 }
2233 uasm_i_nop(&p);
2234
2235 /*
2236 * Warn if something may race with us & replace the TLB entry
2237 * before we read it here. Everything with such races should
2238 * also have dedicated RiXi exception handlers, so this
2239 * shouldn't be hit.
2240 */
2241 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2242
2243 uasm_i_tlbr(&p);
2244
2245 switch (current_cpu_type()) {
2246 default:
2247 if (cpu_has_mips_r2_exec_hazard) {
2248 uasm_i_ehb(&p);
2249
2250 case CPU_CAVIUM_OCTEON:
2251 case CPU_CAVIUM_OCTEON_PLUS:
2252 case CPU_CAVIUM_OCTEON2:
2253 break;
2254 }
2255 }
2256
2257 /* Examine entrylo 0 or 1 based on ptr. */
2258 if (use_bbit_insns()) {
2259 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2260 } else {
2261 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2262 uasm_i_beqz(&p, wr.r3, 8);
2263 }
2264 /* load it in the delay slot*/
2265 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2266 /* load it if ptr is odd */
2267 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2268 /*
2269 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2270 * XI must have triggered it.
2271 */
2272 if (use_bbit_insns()) {
2273 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2274 } else {
2275 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2276 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2277 }
2278 if (PM_DEFAULT_MASK == 0)
2279 uasm_i_nop(&p);
2280 /*
2281 * We clobbered C0_PAGEMASK, restore it. On the other branch
2282 * it is restored in build_huge_tlb_write_entry.
2283 */
2284 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2285
2286 uasm_l_tlbl_goaround2(&l, p);
2287 }
2288 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2289 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2290#endif
2291
2292 uasm_l_nopage_tlbl(&l, p);
2293 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2294 uasm_i_sync(&p, 0);
2295 build_restore_work_registers(&p);
2296#ifdef CONFIG_CPU_MICROMIPS
2297 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2298 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2299 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2300 uasm_i_jr(&p, K0);
2301 } else
2302#endif
2303 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2304 uasm_i_nop(&p);
2305
2306 if (p >= (u32 *)handle_tlbl_end)
2307 panic("TLB load handler fastpath space exceeded");
2308
2309 uasm_resolve_relocs(relocs, labels);
2310 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2311 (unsigned int)(p - (u32 *)handle_tlbl));
2312
2313 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end);
2314}
2315
2316static void build_r4000_tlb_store_handler(void)
2317{
2318 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs);
2319 struct uasm_label *l = labels;
2320 struct uasm_reloc *r = relocs;
2321 struct work_registers wr;
2322
2323 memset(p, 0, handle_tlbs_end - (char *)p);
2324 memset(labels, 0, sizeof(labels));
2325 memset(relocs, 0, sizeof(relocs));
2326
2327 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2328 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2329 if (m4kc_tlbp_war())
2330 build_tlb_probe_entry(&p);
2331 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2332 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2333
2334#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2335 /*
2336 * This is the entry point when
2337 * build_r4000_tlbchange_handler_head spots a huge page.
2338 */
2339 uasm_l_tlb_huge_update(&l, p);
2340 iPTE_LW(&p, wr.r1, wr.r2);
2341 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2342 build_tlb_probe_entry(&p);
2343 uasm_i_ori(&p, wr.r1, wr.r1,
2344 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2345 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2346#endif
2347
2348 uasm_l_nopage_tlbs(&l, p);
2349 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2350 uasm_i_sync(&p, 0);
2351 build_restore_work_registers(&p);
2352#ifdef CONFIG_CPU_MICROMIPS
2353 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2354 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2355 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2356 uasm_i_jr(&p, K0);
2357 } else
2358#endif
2359 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2360 uasm_i_nop(&p);
2361
2362 if (p >= (u32 *)handle_tlbs_end)
2363 panic("TLB store handler fastpath space exceeded");
2364
2365 uasm_resolve_relocs(relocs, labels);
2366 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2367 (unsigned int)(p - (u32 *)handle_tlbs));
2368
2369 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end);
2370}
2371
2372static void build_r4000_tlb_modify_handler(void)
2373{
2374 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm);
2375 struct uasm_label *l = labels;
2376 struct uasm_reloc *r = relocs;
2377 struct work_registers wr;
2378
2379 memset(p, 0, handle_tlbm_end - (char *)p);
2380 memset(labels, 0, sizeof(labels));
2381 memset(relocs, 0, sizeof(relocs));
2382
2383 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2384 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2385 if (m4kc_tlbp_war())
2386 build_tlb_probe_entry(&p);
2387 /* Present and writable bits set, set accessed and dirty bits. */
2388 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2389 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2390
2391#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2392 /*
2393 * This is the entry point when
2394 * build_r4000_tlbchange_handler_head spots a huge page.
2395 */
2396 uasm_l_tlb_huge_update(&l, p);
2397 iPTE_LW(&p, wr.r1, wr.r2);
2398 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2399 build_tlb_probe_entry(&p);
2400 uasm_i_ori(&p, wr.r1, wr.r1,
2401 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2402 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
2403#endif
2404
2405 uasm_l_nopage_tlbm(&l, p);
2406 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2407 uasm_i_sync(&p, 0);
2408 build_restore_work_registers(&p);
2409#ifdef CONFIG_CPU_MICROMIPS
2410 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2411 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2412 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2413 uasm_i_jr(&p, K0);
2414 } else
2415#endif
2416 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2417 uasm_i_nop(&p);
2418
2419 if (p >= (u32 *)handle_tlbm_end)
2420 panic("TLB modify handler fastpath space exceeded");
2421
2422 uasm_resolve_relocs(relocs, labels);
2423 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2424 (unsigned int)(p - (u32 *)handle_tlbm));
2425
2426 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end);
2427}
2428
2429static void flush_tlb_handlers(void)
2430{
2431 local_flush_icache_range((unsigned long)handle_tlbl,
2432 (unsigned long)handle_tlbl_end);
2433 local_flush_icache_range((unsigned long)handle_tlbs,
2434 (unsigned long)handle_tlbs_end);
2435 local_flush_icache_range((unsigned long)handle_tlbm,
2436 (unsigned long)handle_tlbm_end);
2437 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2438 (unsigned long)tlbmiss_handler_setup_pgd_end);
2439}
2440
2441static void print_htw_config(void)
2442{
2443 unsigned long config;
2444 unsigned int pwctl;
2445 const int field = 2 * sizeof(unsigned long);
2446
2447 config = read_c0_pwfield();
2448 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2449 field, config,
2450 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2451 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2452 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2453 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2454 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2455
2456 config = read_c0_pwsize();
2457 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2458 field, config,
2459 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
2460 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2461 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2462 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2463 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2464 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2465
2466 pwctl = read_c0_pwctl();
2467 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2468 pwctl,
2469 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2470 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
2471 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
2472 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
2473 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2474 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2475 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2476}
2477
2478static void config_htw_params(void)
2479{
2480 unsigned long pwfield, pwsize, ptei;
2481 unsigned int config;
2482
2483 /*
2484 * We are using 2-level page tables, so we only need to
2485 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2486 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2487 * write values less than 0xc in these fields because the entire
2488 * write will be dropped. As a result of which, we must preserve
2489 * the original reset values and overwrite only what we really want.
2490 */
2491
2492 pwfield = read_c0_pwfield();
2493 /* re-initialize the GDI field */
2494 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2495 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2496 /* re-initialize the PTI field including the even/odd bit */
2497 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2498 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2499 if (CONFIG_PGTABLE_LEVELS >= 3) {
2500 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2501 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2502 }
2503 /* Set the PTEI right shift */
2504 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2505 pwfield |= ptei;
2506 write_c0_pwfield(pwfield);
2507 /* Check whether the PTEI value is supported */
2508 back_to_back_c0_hazard();
2509 pwfield = read_c0_pwfield();
2510 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2511 != ptei) {
2512 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2513 ptei);
2514 /*
2515 * Drop option to avoid HTW being enabled via another path
2516 * (eg htw_reset())
2517 */
2518 current_cpu_data.options &= ~MIPS_CPU_HTW;
2519 return;
2520 }
2521
2522 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2523 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2524 if (CONFIG_PGTABLE_LEVELS >= 3)
2525 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2526
2527 /* Set pointer size to size of directory pointers */
2528 if (IS_ENABLED(CONFIG_64BIT))
2529 pwsize |= MIPS_PWSIZE_PS_MASK;
2530 /* PTEs may be multiple pointers long (e.g. with XPA) */
2531 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
2532 & MIPS_PWSIZE_PTEW_MASK;
2533
2534 write_c0_pwsize(pwsize);
2535
2536 /* Make sure everything is set before we enable the HTW */
2537 back_to_back_c0_hazard();
2538
2539 /*
2540 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2541 * the pwctl fields.
2542 */
2543 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2544 if (IS_ENABLED(CONFIG_64BIT))
2545 config |= MIPS_PWCTL_XU_MASK;
2546 write_c0_pwctl(config);
2547 pr_info("Hardware Page Table Walker enabled\n");
2548
2549 print_htw_config();
2550}
2551
2552static void config_xpa_params(void)
2553{
2554#ifdef CONFIG_XPA
2555 unsigned int pagegrain;
2556
2557 if (mips_xpa_disabled) {
2558 pr_info("Extended Physical Addressing (XPA) disabled\n");
2559 return;
2560 }
2561
2562 pagegrain = read_c0_pagegrain();
2563 write_c0_pagegrain(pagegrain | PG_ELPA);
2564 back_to_back_c0_hazard();
2565 pagegrain = read_c0_pagegrain();
2566
2567 if (pagegrain & PG_ELPA)
2568 pr_info("Extended Physical Addressing (XPA) enabled\n");
2569 else
2570 panic("Extended Physical Addressing (XPA) disabled");
2571#endif
2572}
2573
2574static void check_pabits(void)
2575{
2576 unsigned long entry;
2577 unsigned pabits, fillbits;
2578
2579 if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2580 /*
2581 * We'll only be making use of the fact that we can rotate bits
2582 * into the fill if the CPU supports RIXI, so don't bother
2583 * probing this for CPUs which don't.
2584 */
2585 return;
2586 }
2587
2588 write_c0_entrylo0(~0ul);
2589 back_to_back_c0_hazard();
2590 entry = read_c0_entrylo0();
2591
2592 /* clear all non-PFN bits */
2593 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
2594 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
2595
2596 /* find a lower bound on PABITS, and upper bound on fill bits */
2597 pabits = fls_long(entry) + 6;
2598 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
2599
2600 /* minus the RI & XI bits */
2601 fillbits -= min_t(unsigned, fillbits, 2);
2602
2603 if (fillbits >= ilog2(_PAGE_NO_EXEC))
2604 fill_includes_sw_bits = true;
2605
2606 pr_debug("Entry* registers contain %u fill bits\n", fillbits);
2607}
2608
2609void build_tlb_refill_handler(void)
2610{
2611 /*
2612 * The refill handler is generated per-CPU, multi-node systems
2613 * may have local storage for it. The other handlers are only
2614 * needed once.
2615 */
2616 static int run_once = 0;
2617
2618 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
2619 panic("Kernels supporting XPA currently require CPUs with RIXI");
2620
2621 output_pgtable_bits_defines();
2622 check_pabits();
2623
2624#ifdef CONFIG_64BIT
2625 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2626#endif
2627
2628 if (cpu_has_3kex) {
2629#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2630 if (!run_once) {
2631 build_setup_pgd();
2632 build_r3000_tlb_refill_handler();
2633 build_r3000_tlb_load_handler();
2634 build_r3000_tlb_store_handler();
2635 build_r3000_tlb_modify_handler();
2636 flush_tlb_handlers();
2637 run_once++;
2638 }
2639#else
2640 panic("No R3000 TLB refill handler");
2641#endif
2642 return;
2643 }
2644
2645 if (cpu_has_ldpte)
2646 setup_pw();
2647
2648 if (!run_once) {
2649 scratch_reg = allocate_kscratch();
2650 build_setup_pgd();
2651 build_r4000_tlb_load_handler();
2652 build_r4000_tlb_store_handler();
2653 build_r4000_tlb_modify_handler();
2654 if (cpu_has_ldpte)
2655 build_loongson3_tlb_refill_handler();
2656 else
2657 build_r4000_tlb_refill_handler();
2658 flush_tlb_handlers();
2659 run_once++;
2660 }
2661 if (cpu_has_xpa)
2662 config_xpa_params();
2663 if (cpu_has_htw)
2664 config_htw_params();
2665}
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
13 *
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
16 *
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
20 *
21 * (Condolences to Napoleon XIV)
22 */
23
24#include <linux/bug.h>
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/smp.h>
28#include <linux/string.h>
29#include <linux/init.h>
30#include <linux/cache.h>
31
32#include <asm/cacheflush.h>
33#include <asm/pgtable.h>
34#include <asm/war.h>
35#include <asm/uasm.h>
36#include <asm/setup.h>
37
38/*
39 * TLB load/store/modify handlers.
40 *
41 * Only the fastpath gets synthesized at runtime, the slowpath for
42 * do_page_fault remains normal asm.
43 */
44extern void tlb_do_page_fault_0(void);
45extern void tlb_do_page_fault_1(void);
46
47struct work_registers {
48 int r1;
49 int r2;
50 int r3;
51};
52
53struct tlb_reg_save {
54 unsigned long a;
55 unsigned long b;
56} ____cacheline_aligned_in_smp;
57
58static struct tlb_reg_save handler_reg_save[NR_CPUS];
59
60static inline int r45k_bvahwbug(void)
61{
62 /* XXX: We should probe for the presence of this bug, but we don't. */
63 return 0;
64}
65
66static inline int r4k_250MHZhwbug(void)
67{
68 /* XXX: We should probe for the presence of this bug, but we don't. */
69 return 0;
70}
71
72static inline int __maybe_unused bcm1250_m3_war(void)
73{
74 return BCM1250_M3_WAR;
75}
76
77static inline int __maybe_unused r10000_llsc_war(void)
78{
79 return R10000_LLSC_WAR;
80}
81
82static int use_bbit_insns(void)
83{
84 switch (current_cpu_type()) {
85 case CPU_CAVIUM_OCTEON:
86 case CPU_CAVIUM_OCTEON_PLUS:
87 case CPU_CAVIUM_OCTEON2:
88 return 1;
89 default:
90 return 0;
91 }
92}
93
94static int use_lwx_insns(void)
95{
96 switch (current_cpu_type()) {
97 case CPU_CAVIUM_OCTEON2:
98 return 1;
99 default:
100 return 0;
101 }
102}
103#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
104 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
105static bool scratchpad_available(void)
106{
107 return true;
108}
109static int scratchpad_offset(int i)
110{
111 /*
112 * CVMSEG starts at address -32768 and extends for
113 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
114 */
115 i += 1; /* Kernel use starts at the top and works down. */
116 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
117}
118#else
119static bool scratchpad_available(void)
120{
121 return false;
122}
123static int scratchpad_offset(int i)
124{
125 BUG();
126 /* Really unreachable, but evidently some GCC want this. */
127 return 0;
128}
129#endif
130/*
131 * Found by experiment: At least some revisions of the 4kc throw under
132 * some circumstances a machine check exception, triggered by invalid
133 * values in the index register. Delaying the tlbp instruction until
134 * after the next branch, plus adding an additional nop in front of
135 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
136 * why; it's not an issue caused by the core RTL.
137 *
138 */
139static int __cpuinit m4kc_tlbp_war(void)
140{
141 return (current_cpu_data.processor_id & 0xffff00) ==
142 (PRID_COMP_MIPS | PRID_IMP_4KC);
143}
144
145/* Handle labels (which must be positive integers). */
146enum label_id {
147 label_second_part = 1,
148 label_leave,
149 label_vmalloc,
150 label_vmalloc_done,
151 label_tlbw_hazard,
152 label_split,
153 label_tlbl_goaround1,
154 label_tlbl_goaround2,
155 label_nopage_tlbl,
156 label_nopage_tlbs,
157 label_nopage_tlbm,
158 label_smp_pgtable_change,
159 label_r3000_write_probe_fail,
160 label_large_segbits_fault,
161#ifdef CONFIG_HUGETLB_PAGE
162 label_tlb_huge_update,
163#endif
164};
165
166UASM_L_LA(_second_part)
167UASM_L_LA(_leave)
168UASM_L_LA(_vmalloc)
169UASM_L_LA(_vmalloc_done)
170UASM_L_LA(_tlbw_hazard)
171UASM_L_LA(_split)
172UASM_L_LA(_tlbl_goaround1)
173UASM_L_LA(_tlbl_goaround2)
174UASM_L_LA(_nopage_tlbl)
175UASM_L_LA(_nopage_tlbs)
176UASM_L_LA(_nopage_tlbm)
177UASM_L_LA(_smp_pgtable_change)
178UASM_L_LA(_r3000_write_probe_fail)
179UASM_L_LA(_large_segbits_fault)
180#ifdef CONFIG_HUGETLB_PAGE
181UASM_L_LA(_tlb_huge_update)
182#endif
183
184/*
185 * For debug purposes.
186 */
187static inline void dump_handler(const u32 *handler, int count)
188{
189 int i;
190
191 pr_debug("\t.set push\n");
192 pr_debug("\t.set noreorder\n");
193
194 for (i = 0; i < count; i++)
195 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
196
197 pr_debug("\t.set pop\n");
198}
199
200/* The only general purpose registers allowed in TLB handlers. */
201#define K0 26
202#define K1 27
203
204/* Some CP0 registers */
205#define C0_INDEX 0, 0
206#define C0_ENTRYLO0 2, 0
207#define C0_TCBIND 2, 2
208#define C0_ENTRYLO1 3, 0
209#define C0_CONTEXT 4, 0
210#define C0_PAGEMASK 5, 0
211#define C0_BADVADDR 8, 0
212#define C0_ENTRYHI 10, 0
213#define C0_EPC 14, 0
214#define C0_XCONTEXT 20, 0
215
216#ifdef CONFIG_64BIT
217# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
218#else
219# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
220#endif
221
222/* The worst case length of the handler is around 18 instructions for
223 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
224 * Maximum space available is 32 instructions for R3000 and 64
225 * instructions for R4000.
226 *
227 * We deliberately chose a buffer size of 128, so we won't scribble
228 * over anything important on overflow before we panic.
229 */
230static u32 tlb_handler[128] __cpuinitdata;
231
232/* simply assume worst case size for labels and relocs */
233static struct uasm_label labels[128] __cpuinitdata;
234static struct uasm_reloc relocs[128] __cpuinitdata;
235
236#ifdef CONFIG_64BIT
237static int check_for_high_segbits __cpuinitdata;
238#endif
239
240static int check_for_high_segbits __cpuinitdata;
241
242static unsigned int kscratch_used_mask __cpuinitdata;
243
244static int __cpuinit allocate_kscratch(void)
245{
246 int r;
247 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
248
249 r = ffs(a);
250
251 if (r == 0)
252 return -1;
253
254 r--; /* make it zero based */
255
256 kscratch_used_mask |= (1 << r);
257
258 return r;
259}
260
261static int scratch_reg __cpuinitdata;
262static int pgd_reg __cpuinitdata;
263enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
264
265static struct work_registers __cpuinit build_get_work_registers(u32 **p)
266{
267 struct work_registers r;
268
269 int smp_processor_id_reg;
270 int smp_processor_id_sel;
271 int smp_processor_id_shift;
272
273 if (scratch_reg > 0) {
274 /* Save in CPU local C0_KScratch? */
275 UASM_i_MTC0(p, 1, 31, scratch_reg);
276 r.r1 = K0;
277 r.r2 = K1;
278 r.r3 = 1;
279 return r;
280 }
281
282 if (num_possible_cpus() > 1) {
283#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
284 smp_processor_id_shift = 51;
285 smp_processor_id_reg = 20; /* XContext */
286 smp_processor_id_sel = 0;
287#else
288# ifdef CONFIG_32BIT
289 smp_processor_id_shift = 25;
290 smp_processor_id_reg = 4; /* Context */
291 smp_processor_id_sel = 0;
292# endif
293# ifdef CONFIG_64BIT
294 smp_processor_id_shift = 26;
295 smp_processor_id_reg = 4; /* Context */
296 smp_processor_id_sel = 0;
297# endif
298#endif
299 /* Get smp_processor_id */
300 UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel);
301 UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift);
302
303 /* handler_reg_save index in K0 */
304 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
305
306 UASM_i_LA(p, K1, (long)&handler_reg_save);
307 UASM_i_ADDU(p, K0, K0, K1);
308 } else {
309 UASM_i_LA(p, K0, (long)&handler_reg_save);
310 }
311 /* K0 now points to save area, save $1 and $2 */
312 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
313 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
314
315 r.r1 = K1;
316 r.r2 = 1;
317 r.r3 = 2;
318 return r;
319}
320
321static void __cpuinit build_restore_work_registers(u32 **p)
322{
323 if (scratch_reg > 0) {
324 UASM_i_MFC0(p, 1, 31, scratch_reg);
325 return;
326 }
327 /* K0 already points to save area, restore $1 and $2 */
328 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
329 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
330}
331
332#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
333
334/*
335 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
336 * we cannot do r3000 under these circumstances.
337 *
338 * Declare pgd_current here instead of including mmu_context.h to avoid type
339 * conflicts for tlbmiss_handler_setup_pgd
340 */
341extern unsigned long pgd_current[];
342
343/*
344 * The R3000 TLB handler is simple.
345 */
346static void __cpuinit build_r3000_tlb_refill_handler(void)
347{
348 long pgdc = (long)pgd_current;
349 u32 *p;
350
351 memset(tlb_handler, 0, sizeof(tlb_handler));
352 p = tlb_handler;
353
354 uasm_i_mfc0(&p, K0, C0_BADVADDR);
355 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
356 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
357 uasm_i_srl(&p, K0, K0, 22); /* load delay */
358 uasm_i_sll(&p, K0, K0, 2);
359 uasm_i_addu(&p, K1, K1, K0);
360 uasm_i_mfc0(&p, K0, C0_CONTEXT);
361 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
362 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
363 uasm_i_addu(&p, K1, K1, K0);
364 uasm_i_lw(&p, K0, 0, K1);
365 uasm_i_nop(&p); /* load delay */
366 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
367 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
368 uasm_i_tlbwr(&p); /* cp0 delay */
369 uasm_i_jr(&p, K1);
370 uasm_i_rfe(&p); /* branch delay */
371
372 if (p > tlb_handler + 32)
373 panic("TLB refill handler space exceeded");
374
375 pr_debug("Wrote TLB refill handler (%u instructions).\n",
376 (unsigned int)(p - tlb_handler));
377
378 memcpy((void *)ebase, tlb_handler, 0x80);
379
380 dump_handler((u32 *)ebase, 32);
381}
382#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
383
384/*
385 * The R4000 TLB handler is much more complicated. We have two
386 * consecutive handler areas with 32 instructions space each.
387 * Since they aren't used at the same time, we can overflow in the
388 * other one.To keep things simple, we first assume linear space,
389 * then we relocate it to the final handler layout as needed.
390 */
391static u32 final_handler[64] __cpuinitdata;
392
393/*
394 * Hazards
395 *
396 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
397 * 2. A timing hazard exists for the TLBP instruction.
398 *
399 * stalling_instruction
400 * TLBP
401 *
402 * The JTLB is being read for the TLBP throughout the stall generated by the
403 * previous instruction. This is not really correct as the stalling instruction
404 * can modify the address used to access the JTLB. The failure symptom is that
405 * the TLBP instruction will use an address created for the stalling instruction
406 * and not the address held in C0_ENHI and thus report the wrong results.
407 *
408 * The software work-around is to not allow the instruction preceding the TLBP
409 * to stall - make it an NOP or some other instruction guaranteed not to stall.
410 *
411 * Errata 2 will not be fixed. This errata is also on the R5000.
412 *
413 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
414 */
415static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
416{
417 switch (current_cpu_type()) {
418 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
419 case CPU_R4600:
420 case CPU_R4700:
421 case CPU_R5000:
422 case CPU_R5000A:
423 case CPU_NEVADA:
424 uasm_i_nop(p);
425 uasm_i_tlbp(p);
426 break;
427
428 default:
429 uasm_i_tlbp(p);
430 break;
431 }
432}
433
434/*
435 * Write random or indexed TLB entry, and care about the hazards from
436 * the preceding mtc0 and for the following eret.
437 */
438enum tlb_write_entry { tlb_random, tlb_indexed };
439
440static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
441 struct uasm_reloc **r,
442 enum tlb_write_entry wmode)
443{
444 void(*tlbw)(u32 **) = NULL;
445
446 switch (wmode) {
447 case tlb_random: tlbw = uasm_i_tlbwr; break;
448 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
449 }
450
451 if (cpu_has_mips_r2) {
452 if (cpu_has_mips_r2_exec_hazard)
453 uasm_i_ehb(p);
454 tlbw(p);
455 return;
456 }
457
458 switch (current_cpu_type()) {
459 case CPU_R4000PC:
460 case CPU_R4000SC:
461 case CPU_R4000MC:
462 case CPU_R4400PC:
463 case CPU_R4400SC:
464 case CPU_R4400MC:
465 /*
466 * This branch uses up a mtc0 hazard nop slot and saves
467 * two nops after the tlbw instruction.
468 */
469 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
470 tlbw(p);
471 uasm_l_tlbw_hazard(l, *p);
472 uasm_i_nop(p);
473 break;
474
475 case CPU_R4600:
476 case CPU_R4700:
477 case CPU_R5000:
478 case CPU_R5000A:
479 uasm_i_nop(p);
480 tlbw(p);
481 uasm_i_nop(p);
482 break;
483
484 case CPU_R4300:
485 case CPU_5KC:
486 case CPU_TX49XX:
487 case CPU_PR4450:
488 case CPU_XLR:
489 uasm_i_nop(p);
490 tlbw(p);
491 break;
492
493 case CPU_R10000:
494 case CPU_R12000:
495 case CPU_R14000:
496 case CPU_4KC:
497 case CPU_4KEC:
498 case CPU_M14KC:
499 case CPU_SB1:
500 case CPU_SB1A:
501 case CPU_4KSC:
502 case CPU_20KC:
503 case CPU_25KF:
504 case CPU_BMIPS32:
505 case CPU_BMIPS3300:
506 case CPU_BMIPS4350:
507 case CPU_BMIPS4380:
508 case CPU_BMIPS5000:
509 case CPU_LOONGSON2:
510 case CPU_R5500:
511 if (m4kc_tlbp_war())
512 uasm_i_nop(p);
513 case CPU_ALCHEMY:
514 tlbw(p);
515 break;
516
517 case CPU_NEVADA:
518 uasm_i_nop(p); /* QED specifies 2 nops hazard */
519 /*
520 * This branch uses up a mtc0 hazard nop slot and saves
521 * a nop after the tlbw instruction.
522 */
523 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
524 tlbw(p);
525 uasm_l_tlbw_hazard(l, *p);
526 break;
527
528 case CPU_RM7000:
529 uasm_i_nop(p);
530 uasm_i_nop(p);
531 uasm_i_nop(p);
532 uasm_i_nop(p);
533 tlbw(p);
534 break;
535
536 case CPU_RM9000:
537 /*
538 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
539 * use of the JTLB for instructions should not occur for 4
540 * cpu cycles and use for data translations should not occur
541 * for 3 cpu cycles.
542 */
543 uasm_i_ssnop(p);
544 uasm_i_ssnop(p);
545 uasm_i_ssnop(p);
546 uasm_i_ssnop(p);
547 tlbw(p);
548 uasm_i_ssnop(p);
549 uasm_i_ssnop(p);
550 uasm_i_ssnop(p);
551 uasm_i_ssnop(p);
552 break;
553
554 case CPU_VR4111:
555 case CPU_VR4121:
556 case CPU_VR4122:
557 case CPU_VR4181:
558 case CPU_VR4181A:
559 uasm_i_nop(p);
560 uasm_i_nop(p);
561 tlbw(p);
562 uasm_i_nop(p);
563 uasm_i_nop(p);
564 break;
565
566 case CPU_VR4131:
567 case CPU_VR4133:
568 case CPU_R5432:
569 uasm_i_nop(p);
570 uasm_i_nop(p);
571 tlbw(p);
572 break;
573
574 case CPU_JZRISC:
575 tlbw(p);
576 uasm_i_nop(p);
577 break;
578
579 default:
580 panic("No TLB refill handler yet (CPU type: %d)",
581 current_cpu_data.cputype);
582 break;
583 }
584}
585
586static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
587 unsigned int reg)
588{
589 if (kernel_uses_smartmips_rixi) {
590 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
591 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
592 } else {
593#ifdef CONFIG_64BIT_PHYS_ADDR
594 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
595#else
596 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
597#endif
598 }
599}
600
601#ifdef CONFIG_HUGETLB_PAGE
602
603static __cpuinit void build_restore_pagemask(u32 **p,
604 struct uasm_reloc **r,
605 unsigned int tmp,
606 enum label_id lid,
607 int restore_scratch)
608{
609 if (restore_scratch) {
610 /* Reset default page size */
611 if (PM_DEFAULT_MASK >> 16) {
612 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
613 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
614 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
615 uasm_il_b(p, r, lid);
616 } else if (PM_DEFAULT_MASK) {
617 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
618 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
619 uasm_il_b(p, r, lid);
620 } else {
621 uasm_i_mtc0(p, 0, C0_PAGEMASK);
622 uasm_il_b(p, r, lid);
623 }
624 if (scratch_reg > 0)
625 UASM_i_MFC0(p, 1, 31, scratch_reg);
626 else
627 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
628 } else {
629 /* Reset default page size */
630 if (PM_DEFAULT_MASK >> 16) {
631 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
632 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
633 uasm_il_b(p, r, lid);
634 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
635 } else if (PM_DEFAULT_MASK) {
636 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
637 uasm_il_b(p, r, lid);
638 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
639 } else {
640 uasm_il_b(p, r, lid);
641 uasm_i_mtc0(p, 0, C0_PAGEMASK);
642 }
643 }
644}
645
646static __cpuinit void build_huge_tlb_write_entry(u32 **p,
647 struct uasm_label **l,
648 struct uasm_reloc **r,
649 unsigned int tmp,
650 enum tlb_write_entry wmode,
651 int restore_scratch)
652{
653 /* Set huge page tlb entry size */
654 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
655 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
656 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
657
658 build_tlb_write_entry(p, l, r, wmode);
659
660 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
661}
662
663/*
664 * Check if Huge PTE is present, if so then jump to LABEL.
665 */
666static void __cpuinit
667build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
668 unsigned int pmd, int lid)
669{
670 UASM_i_LW(p, tmp, 0, pmd);
671 if (use_bbit_insns()) {
672 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
673 } else {
674 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
675 uasm_il_bnez(p, r, tmp, lid);
676 }
677}
678
679static __cpuinit void build_huge_update_entries(u32 **p,
680 unsigned int pte,
681 unsigned int tmp)
682{
683 int small_sequence;
684
685 /*
686 * A huge PTE describes an area the size of the
687 * configured huge page size. This is twice the
688 * of the large TLB entry size we intend to use.
689 * A TLB entry half the size of the configured
690 * huge page size is configured into entrylo0
691 * and entrylo1 to cover the contiguous huge PTE
692 * address space.
693 */
694 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
695
696 /* We can clobber tmp. It isn't used after this.*/
697 if (!small_sequence)
698 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
699
700 build_convert_pte_to_entrylo(p, pte);
701 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
702 /* convert to entrylo1 */
703 if (small_sequence)
704 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
705 else
706 UASM_i_ADDU(p, pte, pte, tmp);
707
708 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
709}
710
711static __cpuinit void build_huge_handler_tail(u32 **p,
712 struct uasm_reloc **r,
713 struct uasm_label **l,
714 unsigned int pte,
715 unsigned int ptr)
716{
717#ifdef CONFIG_SMP
718 UASM_i_SC(p, pte, 0, ptr);
719 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
720 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
721#else
722 UASM_i_SW(p, pte, 0, ptr);
723#endif
724 build_huge_update_entries(p, pte, ptr);
725 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
726}
727#endif /* CONFIG_HUGETLB_PAGE */
728
729#ifdef CONFIG_64BIT
730/*
731 * TMP and PTR are scratch.
732 * TMP will be clobbered, PTR will hold the pmd entry.
733 */
734static void __cpuinit
735build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
736 unsigned int tmp, unsigned int ptr)
737{
738#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
739 long pgdc = (long)pgd_current;
740#endif
741 /*
742 * The vmalloc handling is not in the hotpath.
743 */
744 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
745
746 if (check_for_high_segbits) {
747 /*
748 * The kernel currently implicitely assumes that the
749 * MIPS SEGBITS parameter for the processor is
750 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
751 * allocate virtual addresses outside the maximum
752 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
753 * that doesn't prevent user code from accessing the
754 * higher xuseg addresses. Here, we make sure that
755 * everything but the lower xuseg addresses goes down
756 * the module_alloc/vmalloc path.
757 */
758 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
759 uasm_il_bnez(p, r, ptr, label_vmalloc);
760 } else {
761 uasm_il_bltz(p, r, tmp, label_vmalloc);
762 }
763 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
764
765#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
766 if (pgd_reg != -1) {
767 /* pgd is in pgd_reg */
768 UASM_i_MFC0(p, ptr, 31, pgd_reg);
769 } else {
770 /*
771 * &pgd << 11 stored in CONTEXT [23..63].
772 */
773 UASM_i_MFC0(p, ptr, C0_CONTEXT);
774
775 /* Clear lower 23 bits of context. */
776 uasm_i_dins(p, ptr, 0, 0, 23);
777
778 /* 1 0 1 0 1 << 6 xkphys cached */
779 uasm_i_ori(p, ptr, ptr, 0x540);
780 uasm_i_drotr(p, ptr, ptr, 11);
781 }
782#elif defined(CONFIG_SMP)
783# ifdef CONFIG_MIPS_MT_SMTC
784 /*
785 * SMTC uses TCBind value as "CPU" index
786 */
787 uasm_i_mfc0(p, ptr, C0_TCBIND);
788 uasm_i_dsrl_safe(p, ptr, ptr, 19);
789# else
790 /*
791 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
792 * stored in CONTEXT.
793 */
794 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
795 uasm_i_dsrl_safe(p, ptr, ptr, 23);
796# endif
797 UASM_i_LA_mostly(p, tmp, pgdc);
798 uasm_i_daddu(p, ptr, ptr, tmp);
799 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
800 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
801#else
802 UASM_i_LA_mostly(p, ptr, pgdc);
803 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
804#endif
805
806 uasm_l_vmalloc_done(l, *p);
807
808 /* get pgd offset in bytes */
809 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
810
811 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
812 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
813#ifndef __PAGETABLE_PMD_FOLDED
814 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
815 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
816 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
817 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
818 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
819#endif
820}
821
822/*
823 * BVADDR is the faulting address, PTR is scratch.
824 * PTR will hold the pgd for vmalloc.
825 */
826static void __cpuinit
827build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
828 unsigned int bvaddr, unsigned int ptr,
829 enum vmalloc64_mode mode)
830{
831 long swpd = (long)swapper_pg_dir;
832 int single_insn_swpd;
833 int did_vmalloc_branch = 0;
834
835 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
836
837 uasm_l_vmalloc(l, *p);
838
839 if (mode != not_refill && check_for_high_segbits) {
840 if (single_insn_swpd) {
841 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
842 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
843 did_vmalloc_branch = 1;
844 /* fall through */
845 } else {
846 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
847 }
848 }
849 if (!did_vmalloc_branch) {
850 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
851 uasm_il_b(p, r, label_vmalloc_done);
852 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
853 } else {
854 UASM_i_LA_mostly(p, ptr, swpd);
855 uasm_il_b(p, r, label_vmalloc_done);
856 if (uasm_in_compat_space_p(swpd))
857 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
858 else
859 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
860 }
861 }
862 if (mode != not_refill && check_for_high_segbits) {
863 uasm_l_large_segbits_fault(l, *p);
864 /*
865 * We get here if we are an xsseg address, or if we are
866 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
867 *
868 * Ignoring xsseg (assume disabled so would generate
869 * (address errors?), the only remaining possibility
870 * is the upper xuseg addresses. On processors with
871 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
872 * addresses would have taken an address error. We try
873 * to mimic that here by taking a load/istream page
874 * fault.
875 */
876 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
877 uasm_i_jr(p, ptr);
878
879 if (mode == refill_scratch) {
880 if (scratch_reg > 0)
881 UASM_i_MFC0(p, 1, 31, scratch_reg);
882 else
883 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
884 } else {
885 uasm_i_nop(p);
886 }
887 }
888}
889
890#else /* !CONFIG_64BIT */
891
892/*
893 * TMP and PTR are scratch.
894 * TMP will be clobbered, PTR will hold the pgd entry.
895 */
896static void __cpuinit __maybe_unused
897build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
898{
899 long pgdc = (long)pgd_current;
900
901 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
902#ifdef CONFIG_SMP
903#ifdef CONFIG_MIPS_MT_SMTC
904 /*
905 * SMTC uses TCBind value as "CPU" index
906 */
907 uasm_i_mfc0(p, ptr, C0_TCBIND);
908 UASM_i_LA_mostly(p, tmp, pgdc);
909 uasm_i_srl(p, ptr, ptr, 19);
910#else
911 /*
912 * smp_processor_id() << 3 is stored in CONTEXT.
913 */
914 uasm_i_mfc0(p, ptr, C0_CONTEXT);
915 UASM_i_LA_mostly(p, tmp, pgdc);
916 uasm_i_srl(p, ptr, ptr, 23);
917#endif
918 uasm_i_addu(p, ptr, tmp, ptr);
919#else
920 UASM_i_LA_mostly(p, ptr, pgdc);
921#endif
922 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
923 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
924 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
925 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
926 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
927}
928
929#endif /* !CONFIG_64BIT */
930
931static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
932{
933 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
934 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
935
936 switch (current_cpu_type()) {
937 case CPU_VR41XX:
938 case CPU_VR4111:
939 case CPU_VR4121:
940 case CPU_VR4122:
941 case CPU_VR4131:
942 case CPU_VR4181:
943 case CPU_VR4181A:
944 case CPU_VR4133:
945 shift += 2;
946 break;
947
948 default:
949 break;
950 }
951
952 if (shift)
953 UASM_i_SRL(p, ctx, ctx, shift);
954 uasm_i_andi(p, ctx, ctx, mask);
955}
956
957static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
958{
959 /*
960 * Bug workaround for the Nevada. It seems as if under certain
961 * circumstances the move from cp0_context might produce a
962 * bogus result when the mfc0 instruction and its consumer are
963 * in a different cacheline or a load instruction, probably any
964 * memory reference, is between them.
965 */
966 switch (current_cpu_type()) {
967 case CPU_NEVADA:
968 UASM_i_LW(p, ptr, 0, ptr);
969 GET_CONTEXT(p, tmp); /* get context reg */
970 break;
971
972 default:
973 GET_CONTEXT(p, tmp); /* get context reg */
974 UASM_i_LW(p, ptr, 0, ptr);
975 break;
976 }
977
978 build_adjust_context(p, tmp);
979 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
980}
981
982static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
983 unsigned int ptep)
984{
985 /*
986 * 64bit address support (36bit on a 32bit CPU) in a 32bit
987 * Kernel is a special case. Only a few CPUs use it.
988 */
989#ifdef CONFIG_64BIT_PHYS_ADDR
990 if (cpu_has_64bits) {
991 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
992 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
993 if (kernel_uses_smartmips_rixi) {
994 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
995 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
996 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
997 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
998 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
999 } else {
1000 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1001 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1002 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1003 }
1004 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1005 } else {
1006 int pte_off_even = sizeof(pte_t) / 2;
1007 int pte_off_odd = pte_off_even + sizeof(pte_t);
1008
1009 /* The pte entries are pre-shifted */
1010 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1011 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1012 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1013 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1014 }
1015#else
1016 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
1017 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1018 if (r45k_bvahwbug())
1019 build_tlb_probe_entry(p);
1020 if (kernel_uses_smartmips_rixi) {
1021 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
1022 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
1023 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1024 if (r4k_250MHZhwbug())
1025 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1026 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1027 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1028 } else {
1029 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1030 if (r4k_250MHZhwbug())
1031 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1032 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1033 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1034 if (r45k_bvahwbug())
1035 uasm_i_mfc0(p, tmp, C0_INDEX);
1036 }
1037 if (r4k_250MHZhwbug())
1038 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1039 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1040#endif
1041}
1042
1043struct mips_huge_tlb_info {
1044 int huge_pte;
1045 int restore_scratch;
1046};
1047
1048static struct mips_huge_tlb_info __cpuinit
1049build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1050 struct uasm_reloc **r, unsigned int tmp,
1051 unsigned int ptr, int c0_scratch)
1052{
1053 struct mips_huge_tlb_info rv;
1054 unsigned int even, odd;
1055 int vmalloc_branch_delay_filled = 0;
1056 const int scratch = 1; /* Our extra working register */
1057
1058 rv.huge_pte = scratch;
1059 rv.restore_scratch = 0;
1060
1061 if (check_for_high_segbits) {
1062 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1063
1064 if (pgd_reg != -1)
1065 UASM_i_MFC0(p, ptr, 31, pgd_reg);
1066 else
1067 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1068
1069 if (c0_scratch >= 0)
1070 UASM_i_MTC0(p, scratch, 31, c0_scratch);
1071 else
1072 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1073
1074 uasm_i_dsrl_safe(p, scratch, tmp,
1075 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1076 uasm_il_bnez(p, r, scratch, label_vmalloc);
1077
1078 if (pgd_reg == -1) {
1079 vmalloc_branch_delay_filled = 1;
1080 /* Clear lower 23 bits of context. */
1081 uasm_i_dins(p, ptr, 0, 0, 23);
1082 }
1083 } else {
1084 if (pgd_reg != -1)
1085 UASM_i_MFC0(p, ptr, 31, pgd_reg);
1086 else
1087 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1088
1089 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1090
1091 if (c0_scratch >= 0)
1092 UASM_i_MTC0(p, scratch, 31, c0_scratch);
1093 else
1094 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1095
1096 if (pgd_reg == -1)
1097 /* Clear lower 23 bits of context. */
1098 uasm_i_dins(p, ptr, 0, 0, 23);
1099
1100 uasm_il_bltz(p, r, tmp, label_vmalloc);
1101 }
1102
1103 if (pgd_reg == -1) {
1104 vmalloc_branch_delay_filled = 1;
1105 /* 1 0 1 0 1 << 6 xkphys cached */
1106 uasm_i_ori(p, ptr, ptr, 0x540);
1107 uasm_i_drotr(p, ptr, ptr, 11);
1108 }
1109
1110#ifdef __PAGETABLE_PMD_FOLDED
1111#define LOC_PTEP scratch
1112#else
1113#define LOC_PTEP ptr
1114#endif
1115
1116 if (!vmalloc_branch_delay_filled)
1117 /* get pgd offset in bytes */
1118 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1119
1120 uasm_l_vmalloc_done(l, *p);
1121
1122 /*
1123 * tmp ptr
1124 * fall-through case = badvaddr *pgd_current
1125 * vmalloc case = badvaddr swapper_pg_dir
1126 */
1127
1128 if (vmalloc_branch_delay_filled)
1129 /* get pgd offset in bytes */
1130 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1131
1132#ifdef __PAGETABLE_PMD_FOLDED
1133 GET_CONTEXT(p, tmp); /* get context reg */
1134#endif
1135 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1136
1137 if (use_lwx_insns()) {
1138 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1139 } else {
1140 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1141 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1142 }
1143
1144#ifndef __PAGETABLE_PMD_FOLDED
1145 /* get pmd offset in bytes */
1146 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1147 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1148 GET_CONTEXT(p, tmp); /* get context reg */
1149
1150 if (use_lwx_insns()) {
1151 UASM_i_LWX(p, scratch, scratch, ptr);
1152 } else {
1153 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1154 UASM_i_LW(p, scratch, 0, ptr);
1155 }
1156#endif
1157 /* Adjust the context during the load latency. */
1158 build_adjust_context(p, tmp);
1159
1160#ifdef CONFIG_HUGETLB_PAGE
1161 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1162 /*
1163 * The in the LWX case we don't want to do the load in the
1164 * delay slot. It cannot issue in the same cycle and may be
1165 * speculative and unneeded.
1166 */
1167 if (use_lwx_insns())
1168 uasm_i_nop(p);
1169#endif /* CONFIG_HUGETLB_PAGE */
1170
1171
1172 /* build_update_entries */
1173 if (use_lwx_insns()) {
1174 even = ptr;
1175 odd = tmp;
1176 UASM_i_LWX(p, even, scratch, tmp);
1177 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1178 UASM_i_LWX(p, odd, scratch, tmp);
1179 } else {
1180 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1181 even = tmp;
1182 odd = ptr;
1183 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1184 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1185 }
1186 if (kernel_uses_smartmips_rixi) {
1187 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC));
1188 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC));
1189 uasm_i_drotr(p, even, even,
1190 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1191 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1192 uasm_i_drotr(p, odd, odd,
1193 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1194 } else {
1195 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1196 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1197 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1198 }
1199 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1200
1201 if (c0_scratch >= 0) {
1202 UASM_i_MFC0(p, scratch, 31, c0_scratch);
1203 build_tlb_write_entry(p, l, r, tlb_random);
1204 uasm_l_leave(l, *p);
1205 rv.restore_scratch = 1;
1206 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1207 build_tlb_write_entry(p, l, r, tlb_random);
1208 uasm_l_leave(l, *p);
1209 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1210 } else {
1211 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1212 build_tlb_write_entry(p, l, r, tlb_random);
1213 uasm_l_leave(l, *p);
1214 rv.restore_scratch = 1;
1215 }
1216
1217 uasm_i_eret(p); /* return from trap */
1218
1219 return rv;
1220}
1221
1222/*
1223 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1224 * because EXL == 0. If we wrap, we can also use the 32 instruction
1225 * slots before the XTLB refill exception handler which belong to the
1226 * unused TLB refill exception.
1227 */
1228#define MIPS64_REFILL_INSNS 32
1229
1230static void __cpuinit build_r4000_tlb_refill_handler(void)
1231{
1232 u32 *p = tlb_handler;
1233 struct uasm_label *l = labels;
1234 struct uasm_reloc *r = relocs;
1235 u32 *f;
1236 unsigned int final_len;
1237 struct mips_huge_tlb_info htlb_info __maybe_unused;
1238 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1239
1240 memset(tlb_handler, 0, sizeof(tlb_handler));
1241 memset(labels, 0, sizeof(labels));
1242 memset(relocs, 0, sizeof(relocs));
1243 memset(final_handler, 0, sizeof(final_handler));
1244
1245 if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) {
1246 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1247 scratch_reg);
1248 vmalloc_mode = refill_scratch;
1249 } else {
1250 htlb_info.huge_pte = K0;
1251 htlb_info.restore_scratch = 0;
1252 vmalloc_mode = refill_noscratch;
1253 /*
1254 * create the plain linear handler
1255 */
1256 if (bcm1250_m3_war()) {
1257 unsigned int segbits = 44;
1258
1259 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1260 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1261 uasm_i_xor(&p, K0, K0, K1);
1262 uasm_i_dsrl_safe(&p, K1, K0, 62);
1263 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1264 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1265 uasm_i_or(&p, K0, K0, K1);
1266 uasm_il_bnez(&p, &r, K0, label_leave);
1267 /* No need for uasm_i_nop */
1268 }
1269
1270#ifdef CONFIG_64BIT
1271 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1272#else
1273 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1274#endif
1275
1276#ifdef CONFIG_HUGETLB_PAGE
1277 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1278#endif
1279
1280 build_get_ptep(&p, K0, K1);
1281 build_update_entries(&p, K0, K1);
1282 build_tlb_write_entry(&p, &l, &r, tlb_random);
1283 uasm_l_leave(&l, p);
1284 uasm_i_eret(&p); /* return from trap */
1285 }
1286#ifdef CONFIG_HUGETLB_PAGE
1287 uasm_l_tlb_huge_update(&l, p);
1288 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1289 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1290 htlb_info.restore_scratch);
1291#endif
1292
1293#ifdef CONFIG_64BIT
1294 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1295#endif
1296
1297 /*
1298 * Overflow check: For the 64bit handler, we need at least one
1299 * free instruction slot for the wrap-around branch. In worst
1300 * case, if the intended insertion point is a delay slot, we
1301 * need three, with the second nop'ed and the third being
1302 * unused.
1303 */
1304 /* Loongson2 ebase is different than r4k, we have more space */
1305#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1306 if ((p - tlb_handler) > 64)
1307 panic("TLB refill handler space exceeded");
1308#else
1309 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1310 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1311 && uasm_insn_has_bdelay(relocs,
1312 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1313 panic("TLB refill handler space exceeded");
1314#endif
1315
1316 /*
1317 * Now fold the handler in the TLB refill handler space.
1318 */
1319#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1320 f = final_handler;
1321 /* Simplest case, just copy the handler. */
1322 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1323 final_len = p - tlb_handler;
1324#else /* CONFIG_64BIT */
1325 f = final_handler + MIPS64_REFILL_INSNS;
1326 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1327 /* Just copy the handler. */
1328 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1329 final_len = p - tlb_handler;
1330 } else {
1331#if defined(CONFIG_HUGETLB_PAGE)
1332 const enum label_id ls = label_tlb_huge_update;
1333#else
1334 const enum label_id ls = label_vmalloc;
1335#endif
1336 u32 *split;
1337 int ov = 0;
1338 int i;
1339
1340 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1341 ;
1342 BUG_ON(i == ARRAY_SIZE(labels));
1343 split = labels[i].addr;
1344
1345 /*
1346 * See if we have overflown one way or the other.
1347 */
1348 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1349 split < p - MIPS64_REFILL_INSNS)
1350 ov = 1;
1351
1352 if (ov) {
1353 /*
1354 * Split two instructions before the end. One
1355 * for the branch and one for the instruction
1356 * in the delay slot.
1357 */
1358 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1359
1360 /*
1361 * If the branch would fall in a delay slot,
1362 * we must back up an additional instruction
1363 * so that it is no longer in a delay slot.
1364 */
1365 if (uasm_insn_has_bdelay(relocs, split - 1))
1366 split--;
1367 }
1368 /* Copy first part of the handler. */
1369 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1370 f += split - tlb_handler;
1371
1372 if (ov) {
1373 /* Insert branch. */
1374 uasm_l_split(&l, final_handler);
1375 uasm_il_b(&f, &r, label_split);
1376 if (uasm_insn_has_bdelay(relocs, split))
1377 uasm_i_nop(&f);
1378 else {
1379 uasm_copy_handler(relocs, labels,
1380 split, split + 1, f);
1381 uasm_move_labels(labels, f, f + 1, -1);
1382 f++;
1383 split++;
1384 }
1385 }
1386
1387 /* Copy the rest of the handler. */
1388 uasm_copy_handler(relocs, labels, split, p, final_handler);
1389 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1390 (p - split);
1391 }
1392#endif /* CONFIG_64BIT */
1393
1394 uasm_resolve_relocs(relocs, labels);
1395 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1396 final_len);
1397
1398 memcpy((void *)ebase, final_handler, 0x100);
1399
1400 dump_handler((u32 *)ebase, 64);
1401}
1402
1403/*
1404 * 128 instructions for the fastpath handler is generous and should
1405 * never be exceeded.
1406 */
1407#define FASTPATH_SIZE 128
1408
1409u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
1410u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
1411u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
1412#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1413u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned;
1414
1415static void __cpuinit build_r4000_setup_pgd(void)
1416{
1417 const int a0 = 4;
1418 const int a1 = 5;
1419 u32 *p = tlbmiss_handler_setup_pgd;
1420 struct uasm_label *l = labels;
1421 struct uasm_reloc *r = relocs;
1422
1423 memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd));
1424 memset(labels, 0, sizeof(labels));
1425 memset(relocs, 0, sizeof(relocs));
1426
1427 pgd_reg = allocate_kscratch();
1428
1429 if (pgd_reg == -1) {
1430 /* PGD << 11 in c0_Context */
1431 /*
1432 * If it is a ckseg0 address, convert to a physical
1433 * address. Shifting right by 29 and adding 4 will
1434 * result in zero for these addresses.
1435 *
1436 */
1437 UASM_i_SRA(&p, a1, a0, 29);
1438 UASM_i_ADDIU(&p, a1, a1, 4);
1439 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1440 uasm_i_nop(&p);
1441 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1442 uasm_l_tlbl_goaround1(&l, p);
1443 UASM_i_SLL(&p, a0, a0, 11);
1444 uasm_i_jr(&p, 31);
1445 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1446 } else {
1447 /* PGD in c0_KScratch */
1448 uasm_i_jr(&p, 31);
1449 UASM_i_MTC0(&p, a0, 31, pgd_reg);
1450 }
1451 if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd))
1452 panic("tlbmiss_handler_setup_pgd space exceeded");
1453 uasm_resolve_relocs(relocs, labels);
1454 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1455 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1456
1457 dump_handler(tlbmiss_handler_setup_pgd,
1458 ARRAY_SIZE(tlbmiss_handler_setup_pgd));
1459}
1460#endif
1461
1462static void __cpuinit
1463iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1464{
1465#ifdef CONFIG_SMP
1466# ifdef CONFIG_64BIT_PHYS_ADDR
1467 if (cpu_has_64bits)
1468 uasm_i_lld(p, pte, 0, ptr);
1469 else
1470# endif
1471 UASM_i_LL(p, pte, 0, ptr);
1472#else
1473# ifdef CONFIG_64BIT_PHYS_ADDR
1474 if (cpu_has_64bits)
1475 uasm_i_ld(p, pte, 0, ptr);
1476 else
1477# endif
1478 UASM_i_LW(p, pte, 0, ptr);
1479#endif
1480}
1481
1482static void __cpuinit
1483iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1484 unsigned int mode)
1485{
1486#ifdef CONFIG_64BIT_PHYS_ADDR
1487 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1488#endif
1489
1490 uasm_i_ori(p, pte, pte, mode);
1491#ifdef CONFIG_SMP
1492# ifdef CONFIG_64BIT_PHYS_ADDR
1493 if (cpu_has_64bits)
1494 uasm_i_scd(p, pte, 0, ptr);
1495 else
1496# endif
1497 UASM_i_SC(p, pte, 0, ptr);
1498
1499 if (r10000_llsc_war())
1500 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1501 else
1502 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1503
1504# ifdef CONFIG_64BIT_PHYS_ADDR
1505 if (!cpu_has_64bits) {
1506 /* no uasm_i_nop needed */
1507 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1508 uasm_i_ori(p, pte, pte, hwmode);
1509 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1510 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1511 /* no uasm_i_nop needed */
1512 uasm_i_lw(p, pte, 0, ptr);
1513 } else
1514 uasm_i_nop(p);
1515# else
1516 uasm_i_nop(p);
1517# endif
1518#else
1519# ifdef CONFIG_64BIT_PHYS_ADDR
1520 if (cpu_has_64bits)
1521 uasm_i_sd(p, pte, 0, ptr);
1522 else
1523# endif
1524 UASM_i_SW(p, pte, 0, ptr);
1525
1526# ifdef CONFIG_64BIT_PHYS_ADDR
1527 if (!cpu_has_64bits) {
1528 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1529 uasm_i_ori(p, pte, pte, hwmode);
1530 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1531 uasm_i_lw(p, pte, 0, ptr);
1532 }
1533# endif
1534#endif
1535}
1536
1537/*
1538 * Check if PTE is present, if not then jump to LABEL. PTR points to
1539 * the page table where this PTE is located, PTE will be re-loaded
1540 * with it's original value.
1541 */
1542static void __cpuinit
1543build_pte_present(u32 **p, struct uasm_reloc **r,
1544 int pte, int ptr, int scratch, enum label_id lid)
1545{
1546 int t = scratch >= 0 ? scratch : pte;
1547
1548 if (kernel_uses_smartmips_rixi) {
1549 if (use_bbit_insns()) {
1550 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1551 uasm_i_nop(p);
1552 } else {
1553 uasm_i_andi(p, t, pte, _PAGE_PRESENT);
1554 uasm_il_beqz(p, r, t, lid);
1555 if (pte == t)
1556 /* You lose the SMP race :-(*/
1557 iPTE_LW(p, pte, ptr);
1558 }
1559 } else {
1560 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ);
1561 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ);
1562 uasm_il_bnez(p, r, t, lid);
1563 if (pte == t)
1564 /* You lose the SMP race :-(*/
1565 iPTE_LW(p, pte, ptr);
1566 }
1567}
1568
1569/* Make PTE valid, store result in PTR. */
1570static void __cpuinit
1571build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1572 unsigned int ptr)
1573{
1574 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1575
1576 iPTE_SW(p, r, pte, ptr, mode);
1577}
1578
1579/*
1580 * Check if PTE can be written to, if not branch to LABEL. Regardless
1581 * restore PTE with value from PTR when done.
1582 */
1583static void __cpuinit
1584build_pte_writable(u32 **p, struct uasm_reloc **r,
1585 unsigned int pte, unsigned int ptr, int scratch,
1586 enum label_id lid)
1587{
1588 int t = scratch >= 0 ? scratch : pte;
1589
1590 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE);
1591 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE);
1592 uasm_il_bnez(p, r, t, lid);
1593 if (pte == t)
1594 /* You lose the SMP race :-(*/
1595 iPTE_LW(p, pte, ptr);
1596 else
1597 uasm_i_nop(p);
1598}
1599
1600/* Make PTE writable, update software status bits as well, then store
1601 * at PTR.
1602 */
1603static void __cpuinit
1604build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1605 unsigned int ptr)
1606{
1607 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1608 | _PAGE_DIRTY);
1609
1610 iPTE_SW(p, r, pte, ptr, mode);
1611}
1612
1613/*
1614 * Check if PTE can be modified, if not branch to LABEL. Regardless
1615 * restore PTE with value from PTR when done.
1616 */
1617static void __cpuinit
1618build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1619 unsigned int pte, unsigned int ptr, int scratch,
1620 enum label_id lid)
1621{
1622 if (use_bbit_insns()) {
1623 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1624 uasm_i_nop(p);
1625 } else {
1626 int t = scratch >= 0 ? scratch : pte;
1627 uasm_i_andi(p, t, pte, _PAGE_WRITE);
1628 uasm_il_beqz(p, r, t, lid);
1629 if (pte == t)
1630 /* You lose the SMP race :-(*/
1631 iPTE_LW(p, pte, ptr);
1632 }
1633}
1634
1635#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1636
1637
1638/*
1639 * R3000 style TLB load/store/modify handlers.
1640 */
1641
1642/*
1643 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1644 * Then it returns.
1645 */
1646static void __cpuinit
1647build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1648{
1649 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1650 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1651 uasm_i_tlbwi(p);
1652 uasm_i_jr(p, tmp);
1653 uasm_i_rfe(p); /* branch delay */
1654}
1655
1656/*
1657 * This places the pte into ENTRYLO0 and writes it with tlbwi
1658 * or tlbwr as appropriate. This is because the index register
1659 * may have the probe fail bit set as a result of a trap on a
1660 * kseg2 access, i.e. without refill. Then it returns.
1661 */
1662static void __cpuinit
1663build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1664 struct uasm_reloc **r, unsigned int pte,
1665 unsigned int tmp)
1666{
1667 uasm_i_mfc0(p, tmp, C0_INDEX);
1668 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1669 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1670 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1671 uasm_i_tlbwi(p); /* cp0 delay */
1672 uasm_i_jr(p, tmp);
1673 uasm_i_rfe(p); /* branch delay */
1674 uasm_l_r3000_write_probe_fail(l, *p);
1675 uasm_i_tlbwr(p); /* cp0 delay */
1676 uasm_i_jr(p, tmp);
1677 uasm_i_rfe(p); /* branch delay */
1678}
1679
1680static void __cpuinit
1681build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1682 unsigned int ptr)
1683{
1684 long pgdc = (long)pgd_current;
1685
1686 uasm_i_mfc0(p, pte, C0_BADVADDR);
1687 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1688 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1689 uasm_i_srl(p, pte, pte, 22); /* load delay */
1690 uasm_i_sll(p, pte, pte, 2);
1691 uasm_i_addu(p, ptr, ptr, pte);
1692 uasm_i_mfc0(p, pte, C0_CONTEXT);
1693 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1694 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1695 uasm_i_addu(p, ptr, ptr, pte);
1696 uasm_i_lw(p, pte, 0, ptr);
1697 uasm_i_tlbp(p); /* load delay */
1698}
1699
1700static void __cpuinit build_r3000_tlb_load_handler(void)
1701{
1702 u32 *p = handle_tlbl;
1703 struct uasm_label *l = labels;
1704 struct uasm_reloc *r = relocs;
1705
1706 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1707 memset(labels, 0, sizeof(labels));
1708 memset(relocs, 0, sizeof(relocs));
1709
1710 build_r3000_tlbchange_handler_head(&p, K0, K1);
1711 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1712 uasm_i_nop(&p); /* load delay */
1713 build_make_valid(&p, &r, K0, K1);
1714 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1715
1716 uasm_l_nopage_tlbl(&l, p);
1717 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1718 uasm_i_nop(&p);
1719
1720 if ((p - handle_tlbl) > FASTPATH_SIZE)
1721 panic("TLB load handler fastpath space exceeded");
1722
1723 uasm_resolve_relocs(relocs, labels);
1724 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1725 (unsigned int)(p - handle_tlbl));
1726
1727 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1728}
1729
1730static void __cpuinit build_r3000_tlb_store_handler(void)
1731{
1732 u32 *p = handle_tlbs;
1733 struct uasm_label *l = labels;
1734 struct uasm_reloc *r = relocs;
1735
1736 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1737 memset(labels, 0, sizeof(labels));
1738 memset(relocs, 0, sizeof(relocs));
1739
1740 build_r3000_tlbchange_handler_head(&p, K0, K1);
1741 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1742 uasm_i_nop(&p); /* load delay */
1743 build_make_write(&p, &r, K0, K1);
1744 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1745
1746 uasm_l_nopage_tlbs(&l, p);
1747 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1748 uasm_i_nop(&p);
1749
1750 if ((p - handle_tlbs) > FASTPATH_SIZE)
1751 panic("TLB store handler fastpath space exceeded");
1752
1753 uasm_resolve_relocs(relocs, labels);
1754 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1755 (unsigned int)(p - handle_tlbs));
1756
1757 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1758}
1759
1760static void __cpuinit build_r3000_tlb_modify_handler(void)
1761{
1762 u32 *p = handle_tlbm;
1763 struct uasm_label *l = labels;
1764 struct uasm_reloc *r = relocs;
1765
1766 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1767 memset(labels, 0, sizeof(labels));
1768 memset(relocs, 0, sizeof(relocs));
1769
1770 build_r3000_tlbchange_handler_head(&p, K0, K1);
1771 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1772 uasm_i_nop(&p); /* load delay */
1773 build_make_write(&p, &r, K0, K1);
1774 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1775
1776 uasm_l_nopage_tlbm(&l, p);
1777 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1778 uasm_i_nop(&p);
1779
1780 if ((p - handle_tlbm) > FASTPATH_SIZE)
1781 panic("TLB modify handler fastpath space exceeded");
1782
1783 uasm_resolve_relocs(relocs, labels);
1784 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1785 (unsigned int)(p - handle_tlbm));
1786
1787 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1788}
1789#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1790
1791/*
1792 * R4000 style TLB load/store/modify handlers.
1793 */
1794static struct work_registers __cpuinit
1795build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1796 struct uasm_reloc **r)
1797{
1798 struct work_registers wr = build_get_work_registers(p);
1799
1800#ifdef CONFIG_64BIT
1801 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1802#else
1803 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1804#endif
1805
1806#ifdef CONFIG_HUGETLB_PAGE
1807 /*
1808 * For huge tlb entries, pmd doesn't contain an address but
1809 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1810 * see if we need to jump to huge tlb processing.
1811 */
1812 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1813#endif
1814
1815 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
1816 UASM_i_LW(p, wr.r2, 0, wr.r2);
1817 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1818 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1819 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1820
1821#ifdef CONFIG_SMP
1822 uasm_l_smp_pgtable_change(l, *p);
1823#endif
1824 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
1825 if (!m4kc_tlbp_war())
1826 build_tlb_probe_entry(p);
1827 return wr;
1828}
1829
1830static void __cpuinit
1831build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1832 struct uasm_reloc **r, unsigned int tmp,
1833 unsigned int ptr)
1834{
1835 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1836 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1837 build_update_entries(p, tmp, ptr);
1838 build_tlb_write_entry(p, l, r, tlb_indexed);
1839 uasm_l_leave(l, *p);
1840 build_restore_work_registers(p);
1841 uasm_i_eret(p); /* return from trap */
1842
1843#ifdef CONFIG_64BIT
1844 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1845#endif
1846}
1847
1848static void __cpuinit build_r4000_tlb_load_handler(void)
1849{
1850 u32 *p = handle_tlbl;
1851 struct uasm_label *l = labels;
1852 struct uasm_reloc *r = relocs;
1853 struct work_registers wr;
1854
1855 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1856 memset(labels, 0, sizeof(labels));
1857 memset(relocs, 0, sizeof(relocs));
1858
1859 if (bcm1250_m3_war()) {
1860 unsigned int segbits = 44;
1861
1862 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1863 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1864 uasm_i_xor(&p, K0, K0, K1);
1865 uasm_i_dsrl_safe(&p, K1, K0, 62);
1866 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1867 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1868 uasm_i_or(&p, K0, K0, K1);
1869 uasm_il_bnez(&p, &r, K0, label_leave);
1870 /* No need for uasm_i_nop */
1871 }
1872
1873 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
1874 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1875 if (m4kc_tlbp_war())
1876 build_tlb_probe_entry(&p);
1877
1878 if (kernel_uses_smartmips_rixi) {
1879 /*
1880 * If the page is not _PAGE_VALID, RI or XI could not
1881 * have triggered it. Skip the expensive test..
1882 */
1883 if (use_bbit_insns()) {
1884 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1885 label_tlbl_goaround1);
1886 } else {
1887 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1888 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
1889 }
1890 uasm_i_nop(&p);
1891
1892 uasm_i_tlbr(&p);
1893 /* Examine entrylo 0 or 1 based on ptr. */
1894 if (use_bbit_insns()) {
1895 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
1896 } else {
1897 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
1898 uasm_i_beqz(&p, wr.r3, 8);
1899 }
1900 /* load it in the delay slot*/
1901 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
1902 /* load it if ptr is odd */
1903 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
1904 /*
1905 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1906 * XI must have triggered it.
1907 */
1908 if (use_bbit_insns()) {
1909 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
1910 uasm_i_nop(&p);
1911 uasm_l_tlbl_goaround1(&l, p);
1912 } else {
1913 uasm_i_andi(&p, wr.r3, wr.r3, 2);
1914 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
1915 uasm_i_nop(&p);
1916 }
1917 uasm_l_tlbl_goaround1(&l, p);
1918 }
1919 build_make_valid(&p, &r, wr.r1, wr.r2);
1920 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1921
1922#ifdef CONFIG_HUGETLB_PAGE
1923 /*
1924 * This is the entry point when build_r4000_tlbchange_handler_head
1925 * spots a huge page.
1926 */
1927 uasm_l_tlb_huge_update(&l, p);
1928 iPTE_LW(&p, wr.r1, wr.r2);
1929 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1930 build_tlb_probe_entry(&p);
1931
1932 if (kernel_uses_smartmips_rixi) {
1933 /*
1934 * If the page is not _PAGE_VALID, RI or XI could not
1935 * have triggered it. Skip the expensive test..
1936 */
1937 if (use_bbit_insns()) {
1938 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1939 label_tlbl_goaround2);
1940 } else {
1941 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1942 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
1943 }
1944 uasm_i_nop(&p);
1945
1946 uasm_i_tlbr(&p);
1947 /* Examine entrylo 0 or 1 based on ptr. */
1948 if (use_bbit_insns()) {
1949 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
1950 } else {
1951 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
1952 uasm_i_beqz(&p, wr.r3, 8);
1953 }
1954 /* load it in the delay slot*/
1955 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
1956 /* load it if ptr is odd */
1957 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
1958 /*
1959 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1960 * XI must have triggered it.
1961 */
1962 if (use_bbit_insns()) {
1963 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
1964 } else {
1965 uasm_i_andi(&p, wr.r3, wr.r3, 2);
1966 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
1967 }
1968 if (PM_DEFAULT_MASK == 0)
1969 uasm_i_nop(&p);
1970 /*
1971 * We clobbered C0_PAGEMASK, restore it. On the other branch
1972 * it is restored in build_huge_tlb_write_entry.
1973 */
1974 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
1975
1976 uasm_l_tlbl_goaround2(&l, p);
1977 }
1978 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
1979 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
1980#endif
1981
1982 uasm_l_nopage_tlbl(&l, p);
1983 build_restore_work_registers(&p);
1984 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1985 uasm_i_nop(&p);
1986
1987 if ((p - handle_tlbl) > FASTPATH_SIZE)
1988 panic("TLB load handler fastpath space exceeded");
1989
1990 uasm_resolve_relocs(relocs, labels);
1991 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1992 (unsigned int)(p - handle_tlbl));
1993
1994 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1995}
1996
1997static void __cpuinit build_r4000_tlb_store_handler(void)
1998{
1999 u32 *p = handle_tlbs;
2000 struct uasm_label *l = labels;
2001 struct uasm_reloc *r = relocs;
2002 struct work_registers wr;
2003
2004 memset(handle_tlbs, 0, sizeof(handle_tlbs));
2005 memset(labels, 0, sizeof(labels));
2006 memset(relocs, 0, sizeof(relocs));
2007
2008 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2009 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2010 if (m4kc_tlbp_war())
2011 build_tlb_probe_entry(&p);
2012 build_make_write(&p, &r, wr.r1, wr.r2);
2013 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2014
2015#ifdef CONFIG_HUGETLB_PAGE
2016 /*
2017 * This is the entry point when
2018 * build_r4000_tlbchange_handler_head spots a huge page.
2019 */
2020 uasm_l_tlb_huge_update(&l, p);
2021 iPTE_LW(&p, wr.r1, wr.r2);
2022 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2023 build_tlb_probe_entry(&p);
2024 uasm_i_ori(&p, wr.r1, wr.r1,
2025 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2026 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2027#endif
2028
2029 uasm_l_nopage_tlbs(&l, p);
2030 build_restore_work_registers(&p);
2031 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2032 uasm_i_nop(&p);
2033
2034 if ((p - handle_tlbs) > FASTPATH_SIZE)
2035 panic("TLB store handler fastpath space exceeded");
2036
2037 uasm_resolve_relocs(relocs, labels);
2038 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2039 (unsigned int)(p - handle_tlbs));
2040
2041 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
2042}
2043
2044static void __cpuinit build_r4000_tlb_modify_handler(void)
2045{
2046 u32 *p = handle_tlbm;
2047 struct uasm_label *l = labels;
2048 struct uasm_reloc *r = relocs;
2049 struct work_registers wr;
2050
2051 memset(handle_tlbm, 0, sizeof(handle_tlbm));
2052 memset(labels, 0, sizeof(labels));
2053 memset(relocs, 0, sizeof(relocs));
2054
2055 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2056 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2057 if (m4kc_tlbp_war())
2058 build_tlb_probe_entry(&p);
2059 /* Present and writable bits set, set accessed and dirty bits. */
2060 build_make_write(&p, &r, wr.r1, wr.r2);
2061 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2062
2063#ifdef CONFIG_HUGETLB_PAGE
2064 /*
2065 * This is the entry point when
2066 * build_r4000_tlbchange_handler_head spots a huge page.
2067 */
2068 uasm_l_tlb_huge_update(&l, p);
2069 iPTE_LW(&p, wr.r1, wr.r2);
2070 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2071 build_tlb_probe_entry(&p);
2072 uasm_i_ori(&p, wr.r1, wr.r1,
2073 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2074 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2075#endif
2076
2077 uasm_l_nopage_tlbm(&l, p);
2078 build_restore_work_registers(&p);
2079 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2080 uasm_i_nop(&p);
2081
2082 if ((p - handle_tlbm) > FASTPATH_SIZE)
2083 panic("TLB modify handler fastpath space exceeded");
2084
2085 uasm_resolve_relocs(relocs, labels);
2086 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2087 (unsigned int)(p - handle_tlbm));
2088
2089 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
2090}
2091
2092void __cpuinit build_tlb_refill_handler(void)
2093{
2094 /*
2095 * The refill handler is generated per-CPU, multi-node systems
2096 * may have local storage for it. The other handlers are only
2097 * needed once.
2098 */
2099 static int run_once = 0;
2100
2101#ifdef CONFIG_64BIT
2102 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2103#endif
2104
2105 switch (current_cpu_type()) {
2106 case CPU_R2000:
2107 case CPU_R3000:
2108 case CPU_R3000A:
2109 case CPU_R3081E:
2110 case CPU_TX3912:
2111 case CPU_TX3922:
2112 case CPU_TX3927:
2113#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2114 build_r3000_tlb_refill_handler();
2115 if (!run_once) {
2116 build_r3000_tlb_load_handler();
2117 build_r3000_tlb_store_handler();
2118 build_r3000_tlb_modify_handler();
2119 run_once++;
2120 }
2121#else
2122 panic("No R3000 TLB refill handler");
2123#endif
2124 break;
2125
2126 case CPU_R6000:
2127 case CPU_R6000A:
2128 panic("No R6000 TLB refill handler yet");
2129 break;
2130
2131 case CPU_R8000:
2132 panic("No R8000 TLB refill handler yet");
2133 break;
2134
2135 default:
2136 if (!run_once) {
2137 scratch_reg = allocate_kscratch();
2138#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2139 build_r4000_setup_pgd();
2140#endif
2141 build_r4000_tlb_load_handler();
2142 build_r4000_tlb_store_handler();
2143 build_r4000_tlb_modify_handler();
2144 run_once++;
2145 }
2146 build_r4000_tlb_refill_handler();
2147 }
2148}
2149
2150void __cpuinit flush_tlb_handlers(void)
2151{
2152 local_flush_icache_range((unsigned long)handle_tlbl,
2153 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
2154 local_flush_icache_range((unsigned long)handle_tlbs,
2155 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
2156 local_flush_icache_range((unsigned long)handle_tlbm,
2157 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
2158#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2159 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2160 (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm));
2161#endif
2162}