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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
4 *
5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2007 Secret Lab Technologies Ltd.
7 */
8
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/console.h>
12#include <linux/serial.h>
13#include <linux/serial_core.h>
14#include <linux/tty.h>
15#include <linux/tty_flip.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_device.h>
23#include <linux/of_platform.h>
24#include <linux/clk.h>
25
26#define ULITE_NAME "ttyUL"
27#define ULITE_MAJOR 204
28#define ULITE_MINOR 187
29#define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS
30
31/* ---------------------------------------------------------------------
32 * Register definitions
33 *
34 * For register details see datasheet:
35 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
36 */
37
38#define ULITE_RX 0x00
39#define ULITE_TX 0x04
40#define ULITE_STATUS 0x08
41#define ULITE_CONTROL 0x0c
42
43#define ULITE_REGION 16
44
45#define ULITE_STATUS_RXVALID 0x01
46#define ULITE_STATUS_RXFULL 0x02
47#define ULITE_STATUS_TXEMPTY 0x04
48#define ULITE_STATUS_TXFULL 0x08
49#define ULITE_STATUS_IE 0x10
50#define ULITE_STATUS_OVERRUN 0x20
51#define ULITE_STATUS_FRAME 0x40
52#define ULITE_STATUS_PARITY 0x80
53
54#define ULITE_CONTROL_RST_TX 0x01
55#define ULITE_CONTROL_RST_RX 0x02
56#define ULITE_CONTROL_IE 0x10
57
58/* Static pointer to console port */
59#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
60static struct uart_port *console_port;
61#endif
62
63struct uartlite_data {
64 const struct uartlite_reg_ops *reg_ops;
65 struct clk *clk;
66};
67
68struct uartlite_reg_ops {
69 u32 (*in)(void __iomem *addr);
70 void (*out)(u32 val, void __iomem *addr);
71};
72
73static u32 uartlite_inbe32(void __iomem *addr)
74{
75 return ioread32be(addr);
76}
77
78static void uartlite_outbe32(u32 val, void __iomem *addr)
79{
80 iowrite32be(val, addr);
81}
82
83static const struct uartlite_reg_ops uartlite_be = {
84 .in = uartlite_inbe32,
85 .out = uartlite_outbe32,
86};
87
88static u32 uartlite_inle32(void __iomem *addr)
89{
90 return ioread32(addr);
91}
92
93static void uartlite_outle32(u32 val, void __iomem *addr)
94{
95 iowrite32(val, addr);
96}
97
98static const struct uartlite_reg_ops uartlite_le = {
99 .in = uartlite_inle32,
100 .out = uartlite_outle32,
101};
102
103static inline u32 uart_in32(u32 offset, struct uart_port *port)
104{
105 struct uartlite_data *pdata = port->private_data;
106
107 return pdata->reg_ops->in(port->membase + offset);
108}
109
110static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
111{
112 struct uartlite_data *pdata = port->private_data;
113
114 pdata->reg_ops->out(val, port->membase + offset);
115}
116
117static struct uart_port ulite_ports[ULITE_NR_UARTS];
118
119/* ---------------------------------------------------------------------
120 * Core UART driver operations
121 */
122
123static int ulite_receive(struct uart_port *port, int stat)
124{
125 struct tty_port *tport = &port->state->port;
126 unsigned char ch = 0;
127 char flag = TTY_NORMAL;
128
129 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
130 | ULITE_STATUS_FRAME)) == 0)
131 return 0;
132
133 /* stats */
134 if (stat & ULITE_STATUS_RXVALID) {
135 port->icount.rx++;
136 ch = uart_in32(ULITE_RX, port);
137
138 if (stat & ULITE_STATUS_PARITY)
139 port->icount.parity++;
140 }
141
142 if (stat & ULITE_STATUS_OVERRUN)
143 port->icount.overrun++;
144
145 if (stat & ULITE_STATUS_FRAME)
146 port->icount.frame++;
147
148
149 /* drop byte with parity error if IGNPAR specificed */
150 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
151 stat &= ~ULITE_STATUS_RXVALID;
152
153 stat &= port->read_status_mask;
154
155 if (stat & ULITE_STATUS_PARITY)
156 flag = TTY_PARITY;
157
158
159 stat &= ~port->ignore_status_mask;
160
161 if (stat & ULITE_STATUS_RXVALID)
162 tty_insert_flip_char(tport, ch, flag);
163
164 if (stat & ULITE_STATUS_FRAME)
165 tty_insert_flip_char(tport, 0, TTY_FRAME);
166
167 if (stat & ULITE_STATUS_OVERRUN)
168 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
169
170 return 1;
171}
172
173static int ulite_transmit(struct uart_port *port, int stat)
174{
175 struct circ_buf *xmit = &port->state->xmit;
176
177 if (stat & ULITE_STATUS_TXFULL)
178 return 0;
179
180 if (port->x_char) {
181 uart_out32(port->x_char, ULITE_TX, port);
182 port->x_char = 0;
183 port->icount.tx++;
184 return 1;
185 }
186
187 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
188 return 0;
189
190 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
192 port->icount.tx++;
193
194 /* wake up */
195 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
196 uart_write_wakeup(port);
197
198 return 1;
199}
200
201static irqreturn_t ulite_isr(int irq, void *dev_id)
202{
203 struct uart_port *port = dev_id;
204 int stat, busy, n = 0;
205 unsigned long flags;
206
207 do {
208 spin_lock_irqsave(&port->lock, flags);
209 stat = uart_in32(ULITE_STATUS, port);
210 busy = ulite_receive(port, stat);
211 busy |= ulite_transmit(port, stat);
212 spin_unlock_irqrestore(&port->lock, flags);
213 n++;
214 } while (busy);
215
216 /* work done? */
217 if (n > 1) {
218 tty_flip_buffer_push(&port->state->port);
219 return IRQ_HANDLED;
220 } else {
221 return IRQ_NONE;
222 }
223}
224
225static unsigned int ulite_tx_empty(struct uart_port *port)
226{
227 unsigned long flags;
228 unsigned int ret;
229
230 spin_lock_irqsave(&port->lock, flags);
231 ret = uart_in32(ULITE_STATUS, port);
232 spin_unlock_irqrestore(&port->lock, flags);
233
234 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
235}
236
237static unsigned int ulite_get_mctrl(struct uart_port *port)
238{
239 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
240}
241
242static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
243{
244 /* N/A */
245}
246
247static void ulite_stop_tx(struct uart_port *port)
248{
249 /* N/A */
250}
251
252static void ulite_start_tx(struct uart_port *port)
253{
254 ulite_transmit(port, uart_in32(ULITE_STATUS, port));
255}
256
257static void ulite_stop_rx(struct uart_port *port)
258{
259 /* don't forward any more data (like !CREAD) */
260 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
261 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
262}
263
264static void ulite_break_ctl(struct uart_port *port, int ctl)
265{
266 /* N/A */
267}
268
269static int ulite_startup(struct uart_port *port)
270{
271 struct uartlite_data *pdata = port->private_data;
272 int ret;
273
274 ret = clk_enable(pdata->clk);
275 if (ret) {
276 dev_err(port->dev, "Failed to enable clock\n");
277 return ret;
278 }
279
280 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
281 "uartlite", port);
282 if (ret)
283 return ret;
284
285 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
286 ULITE_CONTROL, port);
287 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
288
289 return 0;
290}
291
292static void ulite_shutdown(struct uart_port *port)
293{
294 struct uartlite_data *pdata = port->private_data;
295
296 uart_out32(0, ULITE_CONTROL, port);
297 uart_in32(ULITE_CONTROL, port); /* dummy */
298 free_irq(port->irq, port);
299 clk_disable(pdata->clk);
300}
301
302static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
303 struct ktermios *old)
304{
305 unsigned long flags;
306 unsigned int baud;
307
308 spin_lock_irqsave(&port->lock, flags);
309
310 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
311 | ULITE_STATUS_TXFULL;
312
313 if (termios->c_iflag & INPCK)
314 port->read_status_mask |=
315 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
316
317 port->ignore_status_mask = 0;
318 if (termios->c_iflag & IGNPAR)
319 port->ignore_status_mask |= ULITE_STATUS_PARITY
320 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
321
322 /* ignore all characters if CREAD is not set */
323 if ((termios->c_cflag & CREAD) == 0)
324 port->ignore_status_mask |=
325 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
326 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
327
328 /* update timeout */
329 baud = uart_get_baud_rate(port, termios, old, 0, 460800);
330 uart_update_timeout(port, termios->c_cflag, baud);
331
332 spin_unlock_irqrestore(&port->lock, flags);
333}
334
335static const char *ulite_type(struct uart_port *port)
336{
337 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
338}
339
340static void ulite_release_port(struct uart_port *port)
341{
342 release_mem_region(port->mapbase, ULITE_REGION);
343 iounmap(port->membase);
344 port->membase = NULL;
345}
346
347static int ulite_request_port(struct uart_port *port)
348{
349 struct uartlite_data *pdata = port->private_data;
350 int ret;
351
352 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
353 port, (unsigned long long) port->mapbase);
354
355 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
356 dev_err(port->dev, "Memory region busy\n");
357 return -EBUSY;
358 }
359
360 port->membase = ioremap(port->mapbase, ULITE_REGION);
361 if (!port->membase) {
362 dev_err(port->dev, "Unable to map registers\n");
363 release_mem_region(port->mapbase, ULITE_REGION);
364 return -EBUSY;
365 }
366
367 pdata->reg_ops = &uartlite_be;
368 ret = uart_in32(ULITE_CONTROL, port);
369 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
370 ret = uart_in32(ULITE_STATUS, port);
371 /* Endianess detection */
372 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
373 pdata->reg_ops = &uartlite_le;
374
375 return 0;
376}
377
378static void ulite_config_port(struct uart_port *port, int flags)
379{
380 if (!ulite_request_port(port))
381 port->type = PORT_UARTLITE;
382}
383
384static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
385{
386 /* we don't want the core code to modify any port params */
387 return -EINVAL;
388}
389
390static void ulite_pm(struct uart_port *port, unsigned int state,
391 unsigned int oldstate)
392{
393 struct uartlite_data *pdata = port->private_data;
394
395 if (!state)
396 clk_enable(pdata->clk);
397 else
398 clk_disable(pdata->clk);
399}
400
401#ifdef CONFIG_CONSOLE_POLL
402static int ulite_get_poll_char(struct uart_port *port)
403{
404 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
405 return NO_POLL_CHAR;
406
407 return uart_in32(ULITE_RX, port);
408}
409
410static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
411{
412 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
413 cpu_relax();
414
415 /* write char to device */
416 uart_out32(ch, ULITE_TX, port);
417}
418#endif
419
420static const struct uart_ops ulite_ops = {
421 .tx_empty = ulite_tx_empty,
422 .set_mctrl = ulite_set_mctrl,
423 .get_mctrl = ulite_get_mctrl,
424 .stop_tx = ulite_stop_tx,
425 .start_tx = ulite_start_tx,
426 .stop_rx = ulite_stop_rx,
427 .break_ctl = ulite_break_ctl,
428 .startup = ulite_startup,
429 .shutdown = ulite_shutdown,
430 .set_termios = ulite_set_termios,
431 .type = ulite_type,
432 .release_port = ulite_release_port,
433 .request_port = ulite_request_port,
434 .config_port = ulite_config_port,
435 .verify_port = ulite_verify_port,
436 .pm = ulite_pm,
437#ifdef CONFIG_CONSOLE_POLL
438 .poll_get_char = ulite_get_poll_char,
439 .poll_put_char = ulite_put_poll_char,
440#endif
441};
442
443/* ---------------------------------------------------------------------
444 * Console driver operations
445 */
446
447#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
448static void ulite_console_wait_tx(struct uart_port *port)
449{
450 u8 val;
451 unsigned long timeout;
452
453 /*
454 * Spin waiting for TX fifo to have space available.
455 * When using the Microblaze Debug Module this can take up to 1s
456 */
457 timeout = jiffies + msecs_to_jiffies(1000);
458 while (1) {
459 val = uart_in32(ULITE_STATUS, port);
460 if ((val & ULITE_STATUS_TXFULL) == 0)
461 break;
462 if (time_after(jiffies, timeout)) {
463 dev_warn(port->dev,
464 "timeout waiting for TX buffer empty\n");
465 break;
466 }
467 cpu_relax();
468 }
469}
470
471static void ulite_console_putchar(struct uart_port *port, int ch)
472{
473 ulite_console_wait_tx(port);
474 uart_out32(ch, ULITE_TX, port);
475}
476
477static void ulite_console_write(struct console *co, const char *s,
478 unsigned int count)
479{
480 struct uart_port *port = console_port;
481 unsigned long flags;
482 unsigned int ier;
483 int locked = 1;
484
485 if (oops_in_progress) {
486 locked = spin_trylock_irqsave(&port->lock, flags);
487 } else
488 spin_lock_irqsave(&port->lock, flags);
489
490 /* save and disable interrupt */
491 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
492 uart_out32(0, ULITE_CONTROL, port);
493
494 uart_console_write(port, s, count, ulite_console_putchar);
495
496 ulite_console_wait_tx(port);
497
498 /* restore interrupt state */
499 if (ier)
500 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
501
502 if (locked)
503 spin_unlock_irqrestore(&port->lock, flags);
504}
505
506static int ulite_console_setup(struct console *co, char *options)
507{
508 struct uart_port *port = NULL;
509 int baud = 9600;
510 int bits = 8;
511 int parity = 'n';
512 int flow = 'n';
513
514 if (co->index >= 0 && co->index < ULITE_NR_UARTS)
515 port = ulite_ports + co->index;
516
517 /* Has the device been initialized yet? */
518 if (!port || !port->mapbase) {
519 pr_debug("console on ttyUL%i not present\n", co->index);
520 return -ENODEV;
521 }
522
523 console_port = port;
524
525 /* not initialized yet? */
526 if (!port->membase) {
527 if (ulite_request_port(port))
528 return -ENODEV;
529 }
530
531 if (options)
532 uart_parse_options(options, &baud, &parity, &bits, &flow);
533
534 return uart_set_options(port, co, baud, parity, bits, flow);
535}
536
537static struct uart_driver ulite_uart_driver;
538
539static struct console ulite_console = {
540 .name = ULITE_NAME,
541 .write = ulite_console_write,
542 .device = uart_console_device,
543 .setup = ulite_console_setup,
544 .flags = CON_PRINTBUFFER,
545 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
546 .data = &ulite_uart_driver,
547};
548
549static void early_uartlite_putc(struct uart_port *port, int c)
550{
551 /*
552 * Limit how many times we'll spin waiting for TX FIFO status.
553 * This will prevent lockups if the base address is incorrectly
554 * set, or any other issue on the UARTLITE.
555 * This limit is pretty arbitrary, unless we are at about 10 baud
556 * we'll never timeout on a working UART.
557 */
558
559 unsigned retries = 1000000;
560 /* read status bit - 0x8 offset */
561 while (--retries && (readl(port->membase + 8) & (1 << 3)))
562 ;
563
564 /* Only attempt the iowrite if we didn't timeout */
565 /* write to TX_FIFO - 0x4 offset */
566 if (retries)
567 writel(c & 0xff, port->membase + 4);
568}
569
570static void early_uartlite_write(struct console *console,
571 const char *s, unsigned n)
572{
573 struct earlycon_device *device = console->data;
574 uart_console_write(&device->port, s, n, early_uartlite_putc);
575}
576
577static int __init early_uartlite_setup(struct earlycon_device *device,
578 const char *options)
579{
580 if (!device->port.membase)
581 return -ENODEV;
582
583 device->con->write = early_uartlite_write;
584 return 0;
585}
586EARLYCON_DECLARE(uartlite, early_uartlite_setup);
587OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
588OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
589
590#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
591
592static struct uart_driver ulite_uart_driver = {
593 .owner = THIS_MODULE,
594 .driver_name = "uartlite",
595 .dev_name = ULITE_NAME,
596 .major = ULITE_MAJOR,
597 .minor = ULITE_MINOR,
598 .nr = ULITE_NR_UARTS,
599#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
600 .cons = &ulite_console,
601#endif
602};
603
604/* ---------------------------------------------------------------------
605 * Port assignment functions (mapping devices to uart_port structures)
606 */
607
608/** ulite_assign: register a uartlite device with the driver
609 *
610 * @dev: pointer to device structure
611 * @id: requested id number. Pass -1 for automatic port assignment
612 * @base: base address of uartlite registers
613 * @irq: irq number for uartlite
614 * @pdata: private data for uartlite
615 *
616 * Returns: 0 on success, <0 otherwise
617 */
618static int ulite_assign(struct device *dev, int id, u32 base, int irq,
619 struct uartlite_data *pdata)
620{
621 struct uart_port *port;
622 int rc;
623
624 /* if id = -1; then scan for a free id and use that */
625 if (id < 0) {
626 for (id = 0; id < ULITE_NR_UARTS; id++)
627 if (ulite_ports[id].mapbase == 0)
628 break;
629 }
630 if (id < 0 || id >= ULITE_NR_UARTS) {
631 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
632 return -EINVAL;
633 }
634
635 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
636 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
637 ULITE_NAME, id);
638 return -EBUSY;
639 }
640
641 port = &ulite_ports[id];
642
643 spin_lock_init(&port->lock);
644 port->fifosize = 16;
645 port->regshift = 2;
646 port->iotype = UPIO_MEM;
647 port->iobase = 1; /* mark port in use */
648 port->mapbase = base;
649 port->membase = NULL;
650 port->ops = &ulite_ops;
651 port->irq = irq;
652 port->flags = UPF_BOOT_AUTOCONF;
653 port->dev = dev;
654 port->type = PORT_UNKNOWN;
655 port->line = id;
656 port->private_data = pdata;
657
658 dev_set_drvdata(dev, port);
659
660 /* Register the port */
661 rc = uart_add_one_port(&ulite_uart_driver, port);
662 if (rc) {
663 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
664 port->mapbase = 0;
665 dev_set_drvdata(dev, NULL);
666 return rc;
667 }
668
669 return 0;
670}
671
672/** ulite_release: register a uartlite device with the driver
673 *
674 * @dev: pointer to device structure
675 */
676static int ulite_release(struct device *dev)
677{
678 struct uart_port *port = dev_get_drvdata(dev);
679 int rc = 0;
680
681 if (port) {
682 rc = uart_remove_one_port(&ulite_uart_driver, port);
683 dev_set_drvdata(dev, NULL);
684 port->mapbase = 0;
685 }
686
687 return rc;
688}
689
690/**
691 * ulite_suspend - Stop the device.
692 *
693 * @dev: handle to the device structure.
694 * Return: 0 always.
695 */
696static int __maybe_unused ulite_suspend(struct device *dev)
697{
698 struct uart_port *port = dev_get_drvdata(dev);
699
700 if (port)
701 uart_suspend_port(&ulite_uart_driver, port);
702
703 return 0;
704}
705
706/**
707 * ulite_resume - Resume the device.
708 *
709 * @dev: handle to the device structure.
710 * Return: 0 on success, errno otherwise.
711 */
712static int __maybe_unused ulite_resume(struct device *dev)
713{
714 struct uart_port *port = dev_get_drvdata(dev);
715
716 if (port)
717 uart_resume_port(&ulite_uart_driver, port);
718
719 return 0;
720}
721
722/* ---------------------------------------------------------------------
723 * Platform bus binding
724 */
725
726static SIMPLE_DEV_PM_OPS(ulite_pm_ops, ulite_suspend, ulite_resume);
727
728#if defined(CONFIG_OF)
729/* Match table for of_platform binding */
730static const struct of_device_id ulite_of_match[] = {
731 { .compatible = "xlnx,opb-uartlite-1.00.b", },
732 { .compatible = "xlnx,xps-uartlite-1.00.a", },
733 {}
734};
735MODULE_DEVICE_TABLE(of, ulite_of_match);
736#endif /* CONFIG_OF */
737
738static int ulite_probe(struct platform_device *pdev)
739{
740 struct resource *res;
741 struct uartlite_data *pdata;
742 int irq, ret;
743 int id = pdev->id;
744#ifdef CONFIG_OF
745 const __be32 *prop;
746
747 prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
748 if (prop)
749 id = be32_to_cpup(prop);
750#endif
751 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
752 GFP_KERNEL);
753 if (!pdata)
754 return -ENOMEM;
755
756 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
757 if (!res)
758 return -ENODEV;
759
760 irq = platform_get_irq(pdev, 0);
761 if (irq < 0)
762 return irq;
763
764 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
765 if (IS_ERR(pdata->clk)) {
766 if (PTR_ERR(pdata->clk) != -ENOENT)
767 return PTR_ERR(pdata->clk);
768
769 /*
770 * Clock framework support is optional, continue on
771 * anyways if we don't find a matching clock.
772 */
773 pdata->clk = NULL;
774 }
775
776 ret = clk_prepare_enable(pdata->clk);
777 if (ret) {
778 dev_err(&pdev->dev, "Failed to prepare clock\n");
779 return ret;
780 }
781
782 if (!ulite_uart_driver.state) {
783 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n");
784 ret = uart_register_driver(&ulite_uart_driver);
785 if (ret < 0) {
786 dev_err(&pdev->dev, "Failed to register driver\n");
787 return ret;
788 }
789 }
790
791 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
792
793 clk_disable(pdata->clk);
794
795 return ret;
796}
797
798static int ulite_remove(struct platform_device *pdev)
799{
800 struct uart_port *port = dev_get_drvdata(&pdev->dev);
801 struct uartlite_data *pdata = port->private_data;
802
803 clk_disable_unprepare(pdata->clk);
804 return ulite_release(&pdev->dev);
805}
806
807/* work with hotplug and coldplug */
808MODULE_ALIAS("platform:uartlite");
809
810static struct platform_driver ulite_platform_driver = {
811 .probe = ulite_probe,
812 .remove = ulite_remove,
813 .driver = {
814 .name = "uartlite",
815 .of_match_table = of_match_ptr(ulite_of_match),
816 .pm = &ulite_pm_ops,
817 },
818};
819
820/* ---------------------------------------------------------------------
821 * Module setup/teardown
822 */
823
824static int __init ulite_init(void)
825{
826
827 pr_debug("uartlite: calling platform_driver_register()\n");
828 return platform_driver_register(&ulite_platform_driver);
829}
830
831static void __exit ulite_exit(void)
832{
833 platform_driver_unregister(&ulite_platform_driver);
834 if (ulite_uart_driver.state)
835 uart_unregister_driver(&ulite_uart_driver);
836}
837
838module_init(ulite_init);
839module_exit(ulite_exit);
840
841MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
842MODULE_DESCRIPTION("Xilinx uartlite serial driver");
843MODULE_LICENSE("GPL");
1/*
2 * uartlite.c: Serial driver for Xilinx uartlite serial controller
3 *
4 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2007 Secret Lab Technologies Ltd.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/platform_device.h>
13#include <linux/module.h>
14#include <linux/console.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/delay.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22#include <asm/io.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_device.h>
26#include <linux/of_platform.h>
27
28#define ULITE_NAME "ttyUL"
29#define ULITE_MAJOR 204
30#define ULITE_MINOR 187
31#define ULITE_NR_UARTS 4
32
33/* ---------------------------------------------------------------------
34 * Register definitions
35 *
36 * For register details see datasheet:
37 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
38 */
39
40#define ULITE_RX 0x00
41#define ULITE_TX 0x04
42#define ULITE_STATUS 0x08
43#define ULITE_CONTROL 0x0c
44
45#define ULITE_REGION 16
46
47#define ULITE_STATUS_RXVALID 0x01
48#define ULITE_STATUS_RXFULL 0x02
49#define ULITE_STATUS_TXEMPTY 0x04
50#define ULITE_STATUS_TXFULL 0x08
51#define ULITE_STATUS_IE 0x10
52#define ULITE_STATUS_OVERRUN 0x20
53#define ULITE_STATUS_FRAME 0x40
54#define ULITE_STATUS_PARITY 0x80
55
56#define ULITE_CONTROL_RST_TX 0x01
57#define ULITE_CONTROL_RST_RX 0x02
58#define ULITE_CONTROL_IE 0x10
59
60
61static struct uart_port ulite_ports[ULITE_NR_UARTS];
62
63/* ---------------------------------------------------------------------
64 * Core UART driver operations
65 */
66
67static int ulite_receive(struct uart_port *port, int stat)
68{
69 struct tty_struct *tty = port->state->port.tty;
70 unsigned char ch = 0;
71 char flag = TTY_NORMAL;
72
73 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
74 | ULITE_STATUS_FRAME)) == 0)
75 return 0;
76
77 /* stats */
78 if (stat & ULITE_STATUS_RXVALID) {
79 port->icount.rx++;
80 ch = ioread32be(port->membase + ULITE_RX);
81
82 if (stat & ULITE_STATUS_PARITY)
83 port->icount.parity++;
84 }
85
86 if (stat & ULITE_STATUS_OVERRUN)
87 port->icount.overrun++;
88
89 if (stat & ULITE_STATUS_FRAME)
90 port->icount.frame++;
91
92
93 /* drop byte with parity error if IGNPAR specificed */
94 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
95 stat &= ~ULITE_STATUS_RXVALID;
96
97 stat &= port->read_status_mask;
98
99 if (stat & ULITE_STATUS_PARITY)
100 flag = TTY_PARITY;
101
102
103 stat &= ~port->ignore_status_mask;
104
105 if (stat & ULITE_STATUS_RXVALID)
106 tty_insert_flip_char(tty, ch, flag);
107
108 if (stat & ULITE_STATUS_FRAME)
109 tty_insert_flip_char(tty, 0, TTY_FRAME);
110
111 if (stat & ULITE_STATUS_OVERRUN)
112 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
113
114 return 1;
115}
116
117static int ulite_transmit(struct uart_port *port, int stat)
118{
119 struct circ_buf *xmit = &port->state->xmit;
120
121 if (stat & ULITE_STATUS_TXFULL)
122 return 0;
123
124 if (port->x_char) {
125 iowrite32be(port->x_char, port->membase + ULITE_TX);
126 port->x_char = 0;
127 port->icount.tx++;
128 return 1;
129 }
130
131 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
132 return 0;
133
134 iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
135 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
136 port->icount.tx++;
137
138 /* wake up */
139 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
140 uart_write_wakeup(port);
141
142 return 1;
143}
144
145static irqreturn_t ulite_isr(int irq, void *dev_id)
146{
147 struct uart_port *port = dev_id;
148 int busy, n = 0;
149
150 do {
151 int stat = ioread32be(port->membase + ULITE_STATUS);
152 busy = ulite_receive(port, stat);
153 busy |= ulite_transmit(port, stat);
154 n++;
155 } while (busy);
156
157 /* work done? */
158 if (n > 1) {
159 tty_flip_buffer_push(port->state->port.tty);
160 return IRQ_HANDLED;
161 } else {
162 return IRQ_NONE;
163 }
164}
165
166static unsigned int ulite_tx_empty(struct uart_port *port)
167{
168 unsigned long flags;
169 unsigned int ret;
170
171 spin_lock_irqsave(&port->lock, flags);
172 ret = ioread32be(port->membase + ULITE_STATUS);
173 spin_unlock_irqrestore(&port->lock, flags);
174
175 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
176}
177
178static unsigned int ulite_get_mctrl(struct uart_port *port)
179{
180 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
181}
182
183static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
184{
185 /* N/A */
186}
187
188static void ulite_stop_tx(struct uart_port *port)
189{
190 /* N/A */
191}
192
193static void ulite_start_tx(struct uart_port *port)
194{
195 ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
196}
197
198static void ulite_stop_rx(struct uart_port *port)
199{
200 /* don't forward any more data (like !CREAD) */
201 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
202 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
203}
204
205static void ulite_enable_ms(struct uart_port *port)
206{
207 /* N/A */
208}
209
210static void ulite_break_ctl(struct uart_port *port, int ctl)
211{
212 /* N/A */
213}
214
215static int ulite_startup(struct uart_port *port)
216{
217 int ret;
218
219 ret = request_irq(port->irq, ulite_isr,
220 IRQF_SHARED | IRQF_SAMPLE_RANDOM, "uartlite", port);
221 if (ret)
222 return ret;
223
224 iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
225 port->membase + ULITE_CONTROL);
226 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
227
228 return 0;
229}
230
231static void ulite_shutdown(struct uart_port *port)
232{
233 iowrite32be(0, port->membase + ULITE_CONTROL);
234 ioread32be(port->membase + ULITE_CONTROL); /* dummy */
235 free_irq(port->irq, port);
236}
237
238static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
239 struct ktermios *old)
240{
241 unsigned long flags;
242 unsigned int baud;
243
244 spin_lock_irqsave(&port->lock, flags);
245
246 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
247 | ULITE_STATUS_TXFULL;
248
249 if (termios->c_iflag & INPCK)
250 port->read_status_mask |=
251 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
252
253 port->ignore_status_mask = 0;
254 if (termios->c_iflag & IGNPAR)
255 port->ignore_status_mask |= ULITE_STATUS_PARITY
256 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
257
258 /* ignore all characters if CREAD is not set */
259 if ((termios->c_cflag & CREAD) == 0)
260 port->ignore_status_mask |=
261 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
262 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
263
264 /* update timeout */
265 baud = uart_get_baud_rate(port, termios, old, 0, 460800);
266 uart_update_timeout(port, termios->c_cflag, baud);
267
268 spin_unlock_irqrestore(&port->lock, flags);
269}
270
271static const char *ulite_type(struct uart_port *port)
272{
273 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
274}
275
276static void ulite_release_port(struct uart_port *port)
277{
278 release_mem_region(port->mapbase, ULITE_REGION);
279 iounmap(port->membase);
280 port->membase = NULL;
281}
282
283static int ulite_request_port(struct uart_port *port)
284{
285 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
286 port, (unsigned long long) port->mapbase);
287
288 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
289 dev_err(port->dev, "Memory region busy\n");
290 return -EBUSY;
291 }
292
293 port->membase = ioremap(port->mapbase, ULITE_REGION);
294 if (!port->membase) {
295 dev_err(port->dev, "Unable to map registers\n");
296 release_mem_region(port->mapbase, ULITE_REGION);
297 return -EBUSY;
298 }
299
300 return 0;
301}
302
303static void ulite_config_port(struct uart_port *port, int flags)
304{
305 if (!ulite_request_port(port))
306 port->type = PORT_UARTLITE;
307}
308
309static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
310{
311 /* we don't want the core code to modify any port params */
312 return -EINVAL;
313}
314
315#ifdef CONFIG_CONSOLE_POLL
316static int ulite_get_poll_char(struct uart_port *port)
317{
318 if (!(ioread32be(port->membase + ULITE_STATUS)
319 & ULITE_STATUS_RXVALID))
320 return NO_POLL_CHAR;
321
322 return ioread32be(port->membase + ULITE_RX);
323}
324
325static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
326{
327 while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)
328 cpu_relax();
329
330 /* write char to device */
331 iowrite32be(ch, port->membase + ULITE_TX);
332}
333#endif
334
335static struct uart_ops ulite_ops = {
336 .tx_empty = ulite_tx_empty,
337 .set_mctrl = ulite_set_mctrl,
338 .get_mctrl = ulite_get_mctrl,
339 .stop_tx = ulite_stop_tx,
340 .start_tx = ulite_start_tx,
341 .stop_rx = ulite_stop_rx,
342 .enable_ms = ulite_enable_ms,
343 .break_ctl = ulite_break_ctl,
344 .startup = ulite_startup,
345 .shutdown = ulite_shutdown,
346 .set_termios = ulite_set_termios,
347 .type = ulite_type,
348 .release_port = ulite_release_port,
349 .request_port = ulite_request_port,
350 .config_port = ulite_config_port,
351 .verify_port = ulite_verify_port,
352#ifdef CONFIG_CONSOLE_POLL
353 .poll_get_char = ulite_get_poll_char,
354 .poll_put_char = ulite_put_poll_char,
355#endif
356};
357
358/* ---------------------------------------------------------------------
359 * Console driver operations
360 */
361
362#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
363static void ulite_console_wait_tx(struct uart_port *port)
364{
365 int i;
366 u8 val;
367
368 /* Spin waiting for TX fifo to have space available */
369 for (i = 0; i < 100000; i++) {
370 val = ioread32be(port->membase + ULITE_STATUS);
371 if ((val & ULITE_STATUS_TXFULL) == 0)
372 break;
373 cpu_relax();
374 }
375}
376
377static void ulite_console_putchar(struct uart_port *port, int ch)
378{
379 ulite_console_wait_tx(port);
380 iowrite32be(ch, port->membase + ULITE_TX);
381}
382
383static void ulite_console_write(struct console *co, const char *s,
384 unsigned int count)
385{
386 struct uart_port *port = &ulite_ports[co->index];
387 unsigned long flags;
388 unsigned int ier;
389 int locked = 1;
390
391 if (oops_in_progress) {
392 locked = spin_trylock_irqsave(&port->lock, flags);
393 } else
394 spin_lock_irqsave(&port->lock, flags);
395
396 /* save and disable interrupt */
397 ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
398 iowrite32be(0, port->membase + ULITE_CONTROL);
399
400 uart_console_write(port, s, count, ulite_console_putchar);
401
402 ulite_console_wait_tx(port);
403
404 /* restore interrupt state */
405 if (ier)
406 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
407
408 if (locked)
409 spin_unlock_irqrestore(&port->lock, flags);
410}
411
412static int __devinit ulite_console_setup(struct console *co, char *options)
413{
414 struct uart_port *port;
415 int baud = 9600;
416 int bits = 8;
417 int parity = 'n';
418 int flow = 'n';
419
420 if (co->index < 0 || co->index >= ULITE_NR_UARTS)
421 return -EINVAL;
422
423 port = &ulite_ports[co->index];
424
425 /* Has the device been initialized yet? */
426 if (!port->mapbase) {
427 pr_debug("console on ttyUL%i not present\n", co->index);
428 return -ENODEV;
429 }
430
431 /* not initialized yet? */
432 if (!port->membase) {
433 if (ulite_request_port(port))
434 return -ENODEV;
435 }
436
437 if (options)
438 uart_parse_options(options, &baud, &parity, &bits, &flow);
439
440 return uart_set_options(port, co, baud, parity, bits, flow);
441}
442
443static struct uart_driver ulite_uart_driver;
444
445static struct console ulite_console = {
446 .name = ULITE_NAME,
447 .write = ulite_console_write,
448 .device = uart_console_device,
449 .setup = ulite_console_setup,
450 .flags = CON_PRINTBUFFER,
451 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
452 .data = &ulite_uart_driver,
453};
454
455static int __init ulite_console_init(void)
456{
457 register_console(&ulite_console);
458 return 0;
459}
460
461console_initcall(ulite_console_init);
462
463#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
464
465static struct uart_driver ulite_uart_driver = {
466 .owner = THIS_MODULE,
467 .driver_name = "uartlite",
468 .dev_name = ULITE_NAME,
469 .major = ULITE_MAJOR,
470 .minor = ULITE_MINOR,
471 .nr = ULITE_NR_UARTS,
472#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
473 .cons = &ulite_console,
474#endif
475};
476
477/* ---------------------------------------------------------------------
478 * Port assignment functions (mapping devices to uart_port structures)
479 */
480
481/** ulite_assign: register a uartlite device with the driver
482 *
483 * @dev: pointer to device structure
484 * @id: requested id number. Pass -1 for automatic port assignment
485 * @base: base address of uartlite registers
486 * @irq: irq number for uartlite
487 *
488 * Returns: 0 on success, <0 otherwise
489 */
490static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
491{
492 struct uart_port *port;
493 int rc;
494
495 /* if id = -1; then scan for a free id and use that */
496 if (id < 0) {
497 for (id = 0; id < ULITE_NR_UARTS; id++)
498 if (ulite_ports[id].mapbase == 0)
499 break;
500 }
501 if (id < 0 || id >= ULITE_NR_UARTS) {
502 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
503 return -EINVAL;
504 }
505
506 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
507 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
508 ULITE_NAME, id);
509 return -EBUSY;
510 }
511
512 port = &ulite_ports[id];
513
514 spin_lock_init(&port->lock);
515 port->fifosize = 16;
516 port->regshift = 2;
517 port->iotype = UPIO_MEM;
518 port->iobase = 1; /* mark port in use */
519 port->mapbase = base;
520 port->membase = NULL;
521 port->ops = &ulite_ops;
522 port->irq = irq;
523 port->flags = UPF_BOOT_AUTOCONF;
524 port->dev = dev;
525 port->type = PORT_UNKNOWN;
526 port->line = id;
527
528 dev_set_drvdata(dev, port);
529
530 /* Register the port */
531 rc = uart_add_one_port(&ulite_uart_driver, port);
532 if (rc) {
533 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
534 port->mapbase = 0;
535 dev_set_drvdata(dev, NULL);
536 return rc;
537 }
538
539 return 0;
540}
541
542/** ulite_release: register a uartlite device with the driver
543 *
544 * @dev: pointer to device structure
545 */
546static int __devexit ulite_release(struct device *dev)
547{
548 struct uart_port *port = dev_get_drvdata(dev);
549 int rc = 0;
550
551 if (port) {
552 rc = uart_remove_one_port(&ulite_uart_driver, port);
553 dev_set_drvdata(dev, NULL);
554 port->mapbase = 0;
555 }
556
557 return rc;
558}
559
560/* ---------------------------------------------------------------------
561 * Platform bus binding
562 */
563
564#if defined(CONFIG_OF)
565/* Match table for of_platform binding */
566static struct of_device_id ulite_of_match[] __devinitdata = {
567 { .compatible = "xlnx,opb-uartlite-1.00.b", },
568 { .compatible = "xlnx,xps-uartlite-1.00.a", },
569 {}
570};
571MODULE_DEVICE_TABLE(of, ulite_of_match);
572#endif /* CONFIG_OF */
573
574static int __devinit ulite_probe(struct platform_device *pdev)
575{
576 struct resource *res, *res2;
577 int id = pdev->id;
578#ifdef CONFIG_OF
579 const __be32 *prop;
580
581 prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
582 if (prop)
583 id = be32_to_cpup(prop);
584#endif
585
586 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
587 if (!res)
588 return -ENODEV;
589
590 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
591 if (!res2)
592 return -ENODEV;
593
594 return ulite_assign(&pdev->dev, id, res->start, res2->start);
595}
596
597static int __devexit ulite_remove(struct platform_device *pdev)
598{
599 return ulite_release(&pdev->dev);
600}
601
602/* work with hotplug and coldplug */
603MODULE_ALIAS("platform:uartlite");
604
605static struct platform_driver ulite_platform_driver = {
606 .probe = ulite_probe,
607 .remove = __devexit_p(ulite_remove),
608 .driver = {
609 .owner = THIS_MODULE,
610 .name = "uartlite",
611 .of_match_table = of_match_ptr(ulite_of_match),
612 },
613};
614
615/* ---------------------------------------------------------------------
616 * Module setup/teardown
617 */
618
619int __init ulite_init(void)
620{
621 int ret;
622
623 pr_debug("uartlite: calling uart_register_driver()\n");
624 ret = uart_register_driver(&ulite_uart_driver);
625 if (ret)
626 goto err_uart;
627
628 pr_debug("uartlite: calling platform_driver_register()\n");
629 ret = platform_driver_register(&ulite_platform_driver);
630 if (ret)
631 goto err_plat;
632
633 return 0;
634
635err_plat:
636 uart_unregister_driver(&ulite_uart_driver);
637err_uart:
638 printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
639 return ret;
640}
641
642void __exit ulite_exit(void)
643{
644 platform_driver_unregister(&ulite_platform_driver);
645 uart_unregister_driver(&ulite_uart_driver);
646}
647
648module_init(ulite_init);
649module_exit(ulite_exit);
650
651MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
652MODULE_DESCRIPTION("Xilinx uartlite serial driver");
653MODULE_LICENSE("GPL");