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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 Stefan Roese <sr@denx.de>
4 */
5
6/ {
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "st,spear600";
10
11 cpus {
12 #address-cells = <0>;
13 #size-cells = <0>;
14
15 cpu {
16 compatible = "arm,arm926ej-s";
17 device_type = "cpu";
18 };
19 };
20
21 memory {
22 device_type = "memory";
23 reg = <0 0x40000000>;
24 };
25
26 ahb {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
30 ranges = <0xd0000000 0xd0000000 0x30000000>;
31
32 vic0: interrupt-controller@f1100000 {
33 compatible = "arm,pl190-vic";
34 interrupt-controller;
35 reg = <0xf1100000 0x1000>;
36 #interrupt-cells = <1>;
37 };
38
39 vic1: interrupt-controller@f1000000 {
40 compatible = "arm,pl190-vic";
41 interrupt-controller;
42 reg = <0xf1000000 0x1000>;
43 #interrupt-cells = <1>;
44 };
45
46 clcd: clcd@fc200000 {
47 compatible = "arm,pl110", "arm,primecell";
48 reg = <0xfc200000 0x1000>;
49 interrupt-parent = <&vic1>;
50 interrupts = <12>;
51 status = "disabled";
52 };
53
54 dmac: dma@fc400000 {
55 compatible = "arm,pl080", "arm,primecell";
56 reg = <0xfc400000 0x1000>;
57 interrupt-parent = <&vic1>;
58 interrupts = <10>;
59 status = "disabled";
60 };
61
62 gmac: ethernet@e0800000 {
63 compatible = "st,spear600-gmac";
64 reg = <0xe0800000 0x8000>;
65 interrupt-parent = <&vic1>;
66 interrupts = <24 23>;
67 interrupt-names = "macirq", "eth_wake_irq";
68 phy-mode = "gmii";
69 status = "disabled";
70 };
71
72 fsmc: flash@d1800000 {
73 compatible = "st,spear600-fsmc-nand";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0xd1800000 0x1000 /* FSMC Register */
77 0xd2000000 0x0010 /* NAND Base DATA */
78 0xd2020000 0x0010 /* NAND Base ADDR */
79 0xd2010000 0x0010>; /* NAND Base CMD */
80 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
81 status = "disabled";
82 };
83
84 smi: flash@fc000000 {
85 compatible = "st,spear600-smi";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 reg = <0xfc000000 0x1000>;
89 interrupt-parent = <&vic1>;
90 interrupts = <12>;
91 status = "disabled";
92 };
93
94 ehci_usb0: ehci@e1800000 {
95 compatible = "st,spear600-ehci", "usb-ehci";
96 reg = <0xe1800000 0x1000>;
97 interrupt-parent = <&vic1>;
98 interrupts = <27>;
99 status = "disabled";
100 };
101
102 ehci_usb1: ehci@e2000000 {
103 compatible = "st,spear600-ehci", "usb-ehci";
104 reg = <0xe2000000 0x1000>;
105 interrupt-parent = <&vic1>;
106 interrupts = <29>;
107 status = "disabled";
108 };
109
110 ohci_usb0: ohci@e1900000 {
111 compatible = "st,spear600-ohci", "usb-ohci";
112 reg = <0xe1900000 0x1000>;
113 interrupt-parent = <&vic1>;
114 interrupts = <26>;
115 status = "disabled";
116 };
117
118 ohci_usb1: ohci@e2100000 {
119 compatible = "st,spear600-ohci", "usb-ohci";
120 reg = <0xe2100000 0x1000>;
121 interrupt-parent = <&vic1>;
122 interrupts = <28>;
123 status = "disabled";
124 };
125
126 apb {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "simple-bus";
130 ranges = <0xd0000000 0xd0000000 0x30000000>;
131
132 uart0: serial@d0000000 {
133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0xd0000000 0x1000>;
135 interrupt-parent = <&vic0>;
136 interrupts = <24>;
137 status = "disabled";
138 };
139
140 uart1: serial@d0080000 {
141 compatible = "arm,pl011", "arm,primecell";
142 reg = <0xd0080000 0x1000>;
143 interrupt-parent = <&vic0>;
144 interrupts = <25>;
145 status = "disabled";
146 };
147
148 /* local/cpu GPIO */
149 gpio0: gpio@f0100000 {
150 #gpio-cells = <2>;
151 compatible = "arm,pl061", "arm,primecell";
152 gpio-controller;
153 reg = <0xf0100000 0x1000>;
154 interrupt-parent = <&vic0>;
155 interrupts = <18>;
156 };
157
158 /* basic GPIO */
159 gpio1: gpio@fc980000 {
160 #gpio-cells = <2>;
161 compatible = "arm,pl061", "arm,primecell";
162 gpio-controller;
163 reg = <0xfc980000 0x1000>;
164 interrupt-parent = <&vic1>;
165 interrupts = <19>;
166 };
167
168 /* appl GPIO */
169 gpio2: gpio@d8100000 {
170 #gpio-cells = <2>;
171 compatible = "arm,pl061", "arm,primecell";
172 gpio-controller;
173 reg = <0xd8100000 0x1000>;
174 interrupt-parent = <&vic1>;
175 interrupts = <4>;
176 };
177
178 i2c: i2c@d0200000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "snps,designware-i2c";
182 reg = <0xd0200000 0x1000>;
183 interrupt-parent = <&vic0>;
184 interrupts = <28>;
185 status = "disabled";
186 };
187
188 rtc: rtc@fc900000 {
189 compatible = "st,spear600-rtc";
190 reg = <0xfc900000 0x1000>;
191 interrupt-parent = <&vic0>;
192 interrupts = <10>;
193 status = "disabled";
194 };
195
196 timer@f0000000 {
197 compatible = "st,spear-timer";
198 reg = <0xf0000000 0x400>;
199 interrupt-parent = <&vic0>;
200 interrupts = <16>;
201 };
202
203 adc: adc@d820b000 {
204 compatible = "st,spear600-adc";
205 reg = <0xd820b000 0x1000>;
206 interrupt-parent = <&vic1>;
207 interrupts = <6>;
208 status = "disabled";
209 };
210 };
211 };
212};
1/*
2 * Copyright 2012 Stefan Roese <sr@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "st,spear600";
16
17 cpus {
18 cpu@0 {
19 compatible = "arm,arm926ejs";
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x40000000>;
26 };
27
28 ahb {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "simple-bus";
32 ranges = <0xd0000000 0xd0000000 0x30000000>;
33
34 vic0: interrupt-controller@f1100000 {
35 compatible = "arm,pl190-vic";
36 interrupt-controller;
37 reg = <0xf1100000 0x1000>;
38 #interrupt-cells = <1>;
39 };
40
41 vic1: interrupt-controller@f1000000 {
42 compatible = "arm,pl190-vic";
43 interrupt-controller;
44 reg = <0xf1000000 0x1000>;
45 #interrupt-cells = <1>;
46 };
47
48 dma@fc400000 {
49 compatible = "arm,pl080", "arm,primecell";
50 reg = <0xfc400000 0x1000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <10>;
53 status = "disabled";
54 };
55
56 gmac: ethernet@e0800000 {
57 compatible = "st,spear600-gmac";
58 reg = <0xe0800000 0x8000>;
59 interrupt-parent = <&vic1>;
60 interrupts = <24 23>;
61 interrupt-names = "macirq", "eth_wake_irq";
62 status = "disabled";
63 };
64
65 fsmc: flash@d1800000 {
66 compatible = "st,spear600-fsmc-nand";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 reg = <0xd1800000 0x1000 /* FSMC Register */
70 0xd2000000 0x4000>; /* NAND Base */
71 reg-names = "fsmc_regs", "nand_data";
72 st,ale-off = <0x20000>;
73 st,cle-off = <0x10000>;
74 status = "disabled";
75 };
76
77 smi: flash@fc000000 {
78 compatible = "st,spear600-smi";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 reg = <0xfc000000 0x1000>;
82 interrupt-parent = <&vic1>;
83 interrupts = <12>;
84 status = "disabled";
85 };
86
87 ehci@e1800000 {
88 compatible = "st,spear600-ehci", "usb-ehci";
89 reg = <0xe1800000 0x1000>;
90 interrupt-parent = <&vic1>;
91 interrupts = <27>;
92 status = "disabled";
93 };
94
95 ehci@e2000000 {
96 compatible = "st,spear600-ehci", "usb-ehci";
97 reg = <0xe2000000 0x1000>;
98 interrupt-parent = <&vic1>;
99 interrupts = <29>;
100 status = "disabled";
101 };
102
103 ohci@e1900000 {
104 compatible = "st,spear600-ohci", "usb-ohci";
105 reg = <0xe1900000 0x1000>;
106 interrupt-parent = <&vic1>;
107 interrupts = <26>;
108 status = "disabled";
109 };
110
111 ohci@e2100000 {
112 compatible = "st,spear600-ohci", "usb-ohci";
113 reg = <0xe2100000 0x1000>;
114 interrupt-parent = <&vic1>;
115 interrupts = <28>;
116 status = "disabled";
117 };
118
119 apb {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "simple-bus";
123 ranges = <0xd0000000 0xd0000000 0x30000000>;
124
125 serial@d0000000 {
126 compatible = "arm,pl011", "arm,primecell";
127 reg = <0xd0000000 0x1000>;
128 interrupt-parent = <&vic0>;
129 interrupts = <24>;
130 status = "disabled";
131 };
132
133 serial@d0080000 {
134 compatible = "arm,pl011", "arm,primecell";
135 reg = <0xd0080000 0x1000>;
136 interrupt-parent = <&vic0>;
137 interrupts = <25>;
138 status = "disabled";
139 };
140
141 /* local/cpu GPIO */
142 gpio0: gpio@f0100000 {
143 #gpio-cells = <2>;
144 compatible = "arm,pl061", "arm,primecell";
145 gpio-controller;
146 reg = <0xf0100000 0x1000>;
147 interrupt-parent = <&vic0>;
148 interrupts = <18>;
149 };
150
151 /* basic GPIO */
152 gpio1: gpio@fc980000 {
153 #gpio-cells = <2>;
154 compatible = "arm,pl061", "arm,primecell";
155 gpio-controller;
156 reg = <0xfc980000 0x1000>;
157 interrupt-parent = <&vic1>;
158 interrupts = <19>;
159 };
160
161 /* appl GPIO */
162 gpio2: gpio@d8100000 {
163 #gpio-cells = <2>;
164 compatible = "arm,pl061", "arm,primecell";
165 gpio-controller;
166 reg = <0xd8100000 0x1000>;
167 interrupt-parent = <&vic1>;
168 interrupts = <4>;
169 };
170
171 i2c@d0200000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "snps,designware-i2c";
175 reg = <0xd0200000 0x1000>;
176 interrupt-parent = <&vic0>;
177 interrupts = <28>;
178 status = "disabled";
179 };
180
181 timer@f0000000 {
182 compatible = "st,spear-timer";
183 reg = <0xf0000000 0x400>;
184 interrupt-parent = <&vic0>;
185 interrupts = <16>;
186 };
187 };
188 };
189};