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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * STX GP3 - 8560 ADS Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 */
7
8/dts-v1/;
9
10/ {
11 model = "stx,gp3";
12 compatible = "stx,gp3-8560", "stx,gp3";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 pci0 = &pci0;
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,8560@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
33 i-cache-size = <32768>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
37 next-level-cache = <&L2>;
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x10000000>;
44 };
45
46 soc@fdf00000 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 device_type = "soc";
50 ranges = <0 0xfdf00000 0x100000>;
51 bus-frequency = <0>;
52 compatible = "fsl,mpc8560-immr", "simple-bus";
53
54 ecm-law@0 {
55 compatible = "fsl,ecm-law";
56 reg = <0x0 0x1000>;
57 fsl,num-laws = <8>;
58 };
59
60 ecm@1000 {
61 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
62 reg = <0x1000 0x1000>;
63 interrupts = <17 2>;
64 interrupt-parent = <&mpic>;
65 };
66
67 memory-controller@2000 {
68 compatible = "fsl,mpc8540-memory-controller";
69 reg = <0x2000 0x1000>;
70 interrupt-parent = <&mpic>;
71 interrupts = <18 2>;
72 };
73
74 L2: l2-cache-controller@20000 {
75 compatible = "fsl,mpc8540-l2-cache-controller";
76 reg = <0x20000 0x1000>;
77 cache-line-size = <32>;
78 cache-size = <0x40000>; // L2, 256K
79 interrupt-parent = <&mpic>;
80 interrupts = <16 2>;
81 };
82
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 dma@21300 {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
98 reg = <0x21300 0x4>;
99 ranges = <0x0 0x21100 0x200>;
100 cell-index = <0>;
101 dma-channel@0 {
102 compatible = "fsl,mpc8560-dma-channel",
103 "fsl,eloplus-dma-channel";
104 reg = <0x0 0x80>;
105 cell-index = <0>;
106 interrupt-parent = <&mpic>;
107 interrupts = <20 2>;
108 };
109 dma-channel@80 {
110 compatible = "fsl,mpc8560-dma-channel",
111 "fsl,eloplus-dma-channel";
112 reg = <0x80 0x80>;
113 cell-index = <1>;
114 interrupt-parent = <&mpic>;
115 interrupts = <21 2>;
116 };
117 dma-channel@100 {
118 compatible = "fsl,mpc8560-dma-channel",
119 "fsl,eloplus-dma-channel";
120 reg = <0x100 0x80>;
121 cell-index = <2>;
122 interrupt-parent = <&mpic>;
123 interrupts = <22 2>;
124 };
125 dma-channel@180 {
126 compatible = "fsl,mpc8560-dma-channel",
127 "fsl,eloplus-dma-channel";
128 reg = <0x180 0x80>;
129 cell-index = <3>;
130 interrupt-parent = <&mpic>;
131 interrupts = <23 2>;
132 };
133 };
134
135 enet0: ethernet@24000 {
136 #address-cells = <1>;
137 #size-cells = <1>;
138 cell-index = <0>;
139 device_type = "network";
140 model = "TSEC";
141 compatible = "gianfar";
142 reg = <0x24000 0x1000>;
143 ranges = <0x0 0x24000 0x1000>;
144 local-mac-address = [ 00 00 00 00 00 00 ];
145 interrupts = <29 2 30 2 34 2>;
146 interrupt-parent = <&mpic>;
147 tbi-handle = <&tbi0>;
148 phy-handle = <&phy2>;
149
150 mdio@520 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "fsl,gianfar-mdio";
154 reg = <0x520 0x20>;
155
156 phy2: ethernet-phy@2 {
157 interrupt-parent = <&mpic>;
158 interrupts = <5 4>;
159 reg = <2>;
160 };
161 phy4: ethernet-phy@4 {
162 interrupt-parent = <&mpic>;
163 interrupts = <5 4>;
164 reg = <4>;
165 };
166 tbi0: tbi-phy@11 {
167 reg = <0x11>;
168 device_type = "tbi-phy";
169 };
170 };
171 };
172
173 enet1: ethernet@25000 {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 cell-index = <1>;
177 device_type = "network";
178 model = "TSEC";
179 compatible = "gianfar";
180 reg = <0x25000 0x1000>;
181 ranges = <0x0 0x25000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <35 2 36 2 40 2>;
184 interrupt-parent = <&mpic>;
185 tbi-handle = <&tbi1>;
186 phy-handle = <&phy4>;
187
188 mdio@520 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,gianfar-tbi";
192 reg = <0x520 0x20>;
193
194 tbi1: tbi-phy@11 {
195 reg = <0x11>;
196 device_type = "tbi-phy";
197 };
198 };
199 };
200
201 mpic: pic@40000 {
202 interrupt-controller;
203 #address-cells = <0>;
204 #interrupt-cells = <2>;
205 reg = <0x40000 0x40000>;
206 compatible = "chrp,open-pic";
207 device_type = "open-pic";
208 };
209
210 cpm@919c0 {
211 #address-cells = <1>;
212 #size-cells = <1>;
213 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
214 reg = <0x919c0 0x30>;
215 ranges;
216
217 muram@80000 {
218 #address-cells = <1>;
219 #size-cells = <1>;
220 ranges = <0 0x80000 0x10000>;
221
222 data@0 {
223 compatible = "fsl,cpm-muram-data";
224 reg = <0 0x4000 0x9000 0x2000>;
225 };
226 };
227
228 brg@919f0 {
229 compatible = "fsl,mpc8560-brg",
230 "fsl,cpm2-brg",
231 "fsl,cpm-brg";
232 reg = <0x919f0 0x10 0x915f0 0x10>;
233 clock-frequency = <0>;
234 };
235
236 cpmpic: pic@90c00 {
237 interrupt-controller;
238 #address-cells = <0>;
239 #interrupt-cells = <2>;
240 interrupts = <46 2>;
241 interrupt-parent = <&mpic>;
242 reg = <0x90c00 0x80>;
243 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
244 };
245
246 serial0: serial@91a20 {
247 device_type = "serial";
248 compatible = "fsl,mpc8560-scc-uart",
249 "fsl,cpm2-scc-uart";
250 reg = <0x91a20 0x20 0x88100 0x100>;
251 fsl,cpm-brg = <2>;
252 fsl,cpm-command = <0x4a00000>;
253 interrupts = <41 8>;
254 interrupt-parent = <&cpmpic>;
255 };
256 };
257 };
258
259 pci0: pci@fdf08000 {
260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
261 interrupt-map = <
262
263 /* IDSEL 0x0c */
264 0x6000 0 0 1 &mpic 1 1
265 0x6000 0 0 2 &mpic 2 1
266 0x6000 0 0 3 &mpic 3 1
267 0x6000 0 0 4 &mpic 4 1
268
269 /* IDSEL 0x0d */
270 0x6800 0 0 1 &mpic 4 1
271 0x6800 0 0 2 &mpic 1 1
272 0x6800 0 0 3 &mpic 2 1
273 0x6800 0 0 4 &mpic 3 1
274
275 /* IDSEL 0x0e */
276 0x7000 0 0 1 &mpic 3 1
277 0x7000 0 0 2 &mpic 4 1
278 0x7000 0 0 3 &mpic 1 1
279 0x7000 0 0 4 &mpic 2 1
280
281 /* IDSEL 0x0f */
282 0x7800 0 0 1 &mpic 2 1
283 0x7800 0 0 2 &mpic 3 1
284 0x7800 0 0 3 &mpic 4 1
285 0x7800 0 0 4 &mpic 1 1>;
286
287 interrupt-parent = <&mpic>;
288 interrupts = <24 2>;
289 bus-range = <0 0>;
290 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
291 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
292 clock-frequency = <66666666>;
293 #interrupt-cells = <1>;
294 #size-cells = <2>;
295 #address-cells = <3>;
296 reg = <0xfdf08000 0x1000>;
297 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
298 device_type = "pci";
299 };
300};
1/*
2 * STX GP3 - 8560 ADS Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "stx,gp3";
16 compatible = "stx,gp3-8560", "stx,gp3";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 pci0 = &pci0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8560@0 {
32 device_type = "cpu";
33 reg = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
41 next-level-cache = <&L2>;
42 };
43 };
44
45 memory {
46 device_type = "memory";
47 reg = <0x00000000 0x10000000>;
48 };
49
50 soc@fdf00000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 device_type = "soc";
54 ranges = <0 0xfdf00000 0x100000>;
55 bus-frequency = <0>;
56 compatible = "fsl,mpc8560-immr", "simple-bus";
57
58 ecm-law@0 {
59 compatible = "fsl,ecm-law";
60 reg = <0x0 0x1000>;
61 fsl,num-laws = <8>;
62 };
63
64 ecm@1000 {
65 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
66 reg = <0x1000 0x1000>;
67 interrupts = <17 2>;
68 interrupt-parent = <&mpic>;
69 };
70
71 memory-controller@2000 {
72 compatible = "fsl,mpc8540-memory-controller";
73 reg = <0x2000 0x1000>;
74 interrupt-parent = <&mpic>;
75 interrupts = <18 2>;
76 };
77
78 L2: l2-cache-controller@20000 {
79 compatible = "fsl,mpc8540-l2-cache-controller";
80 reg = <0x20000 0x1000>;
81 cache-line-size = <32>;
82 cache-size = <0x40000>; // L2, 256K
83 interrupt-parent = <&mpic>;
84 interrupts = <16 2>;
85 };
86
87 i2c@3000 {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 cell-index = <0>;
91 compatible = "fsl-i2c";
92 reg = <0x3000 0x100>;
93 interrupts = <43 2>;
94 interrupt-parent = <&mpic>;
95 dfsrr;
96 };
97
98 dma@21300 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
102 reg = <0x21300 0x4>;
103 ranges = <0x0 0x21100 0x200>;
104 cell-index = <0>;
105 dma-channel@0 {
106 compatible = "fsl,mpc8560-dma-channel",
107 "fsl,eloplus-dma-channel";
108 reg = <0x0 0x80>;
109 cell-index = <0>;
110 interrupt-parent = <&mpic>;
111 interrupts = <20 2>;
112 };
113 dma-channel@80 {
114 compatible = "fsl,mpc8560-dma-channel",
115 "fsl,eloplus-dma-channel";
116 reg = <0x80 0x80>;
117 cell-index = <1>;
118 interrupt-parent = <&mpic>;
119 interrupts = <21 2>;
120 };
121 dma-channel@100 {
122 compatible = "fsl,mpc8560-dma-channel",
123 "fsl,eloplus-dma-channel";
124 reg = <0x100 0x80>;
125 cell-index = <2>;
126 interrupt-parent = <&mpic>;
127 interrupts = <22 2>;
128 };
129 dma-channel@180 {
130 compatible = "fsl,mpc8560-dma-channel",
131 "fsl,eloplus-dma-channel";
132 reg = <0x180 0x80>;
133 cell-index = <3>;
134 interrupt-parent = <&mpic>;
135 interrupts = <23 2>;
136 };
137 };
138
139 enet0: ethernet@24000 {
140 #address-cells = <1>;
141 #size-cells = <1>;
142 cell-index = <0>;
143 device_type = "network";
144 model = "TSEC";
145 compatible = "gianfar";
146 reg = <0x24000 0x1000>;
147 ranges = <0x0 0x24000 0x1000>;
148 local-mac-address = [ 00 00 00 00 00 00 ];
149 interrupts = <29 2 30 2 34 2>;
150 interrupt-parent = <&mpic>;
151 tbi-handle = <&tbi0>;
152 phy-handle = <&phy2>;
153
154 mdio@520 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "fsl,gianfar-mdio";
158 reg = <0x520 0x20>;
159
160 phy2: ethernet-phy@2 {
161 interrupt-parent = <&mpic>;
162 interrupts = <5 4>;
163 reg = <2>;
164 };
165 phy4: ethernet-phy@4 {
166 interrupt-parent = <&mpic>;
167 interrupts = <5 4>;
168 reg = <4>;
169 };
170 tbi0: tbi-phy@11 {
171 reg = <0x11>;
172 device_type = "tbi-phy";
173 };
174 };
175 };
176
177 enet1: ethernet@25000 {
178 #address-cells = <1>;
179 #size-cells = <1>;
180 cell-index = <1>;
181 device_type = "network";
182 model = "TSEC";
183 compatible = "gianfar";
184 reg = <0x25000 0x1000>;
185 ranges = <0x0 0x25000 0x1000>;
186 local-mac-address = [ 00 00 00 00 00 00 ];
187 interrupts = <35 2 36 2 40 2>;
188 interrupt-parent = <&mpic>;
189 tbi-handle = <&tbi1>;
190 phy-handle = <&phy4>;
191
192 mdio@520 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "fsl,gianfar-tbi";
196 reg = <0x520 0x20>;
197
198 tbi1: tbi-phy@11 {
199 reg = <0x11>;
200 device_type = "tbi-phy";
201 };
202 };
203 };
204
205 mpic: pic@40000 {
206 interrupt-controller;
207 #address-cells = <0>;
208 #interrupt-cells = <2>;
209 reg = <0x40000 0x40000>;
210 compatible = "chrp,open-pic";
211 device_type = "open-pic";
212 };
213
214 cpm@919c0 {
215 #address-cells = <1>;
216 #size-cells = <1>;
217 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
218 reg = <0x919c0 0x30>;
219 ranges;
220
221 muram@80000 {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0 0x80000 0x10000>;
225
226 data@0 {
227 compatible = "fsl,cpm-muram-data";
228 reg = <0 0x4000 0x9000 0x2000>;
229 };
230 };
231
232 brg@919f0 {
233 compatible = "fsl,mpc8560-brg",
234 "fsl,cpm2-brg",
235 "fsl,cpm-brg";
236 reg = <0x919f0 0x10 0x915f0 0x10>;
237 clock-frequency = <0>;
238 };
239
240 cpmpic: pic@90c00 {
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <2>;
244 interrupts = <46 2>;
245 interrupt-parent = <&mpic>;
246 reg = <0x90c00 0x80>;
247 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
248 };
249
250 serial0: serial@91a20 {
251 device_type = "serial";
252 compatible = "fsl,mpc8560-scc-uart",
253 "fsl,cpm2-scc-uart";
254 reg = <0x91a20 0x20 0x88100 0x100>;
255 fsl,cpm-brg = <2>;
256 fsl,cpm-command = <0x4a00000>;
257 interrupts = <41 8>;
258 interrupt-parent = <&cpmpic>;
259 };
260 };
261 };
262
263 pci0: pci@fdf08000 {
264 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
265 interrupt-map = <
266
267 /* IDSEL 0x0c */
268 0x6000 0 0 1 &mpic 1 1
269 0x6000 0 0 2 &mpic 2 1
270 0x6000 0 0 3 &mpic 3 1
271 0x6000 0 0 4 &mpic 4 1
272
273 /* IDSEL 0x0d */
274 0x6800 0 0 1 &mpic 4 1
275 0x6800 0 0 2 &mpic 1 1
276 0x6800 0 0 3 &mpic 2 1
277 0x6800 0 0 4 &mpic 3 1
278
279 /* IDSEL 0x0e */
280 0x7000 0 0 1 &mpic 3 1
281 0x7000 0 0 2 &mpic 4 1
282 0x7000 0 0 3 &mpic 1 1
283 0x7000 0 0 4 &mpic 2 1
284
285 /* IDSEL 0x0f */
286 0x7800 0 0 1 &mpic 2 1
287 0x7800 0 0 2 &mpic 3 1
288 0x7800 0 0 3 &mpic 4 1
289 0x7800 0 0 4 &mpic 1 1>;
290
291 interrupt-parent = <&mpic>;
292 interrupts = <24 2>;
293 bus-range = <0 0>;
294 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
295 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
296 clock-frequency = <66666666>;
297 #interrupt-cells = <1>;
298 #size-cells = <2>;
299 #address-cells = <3>;
300 reg = <0xfdf08000 0x1000>;
301 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
302 device_type = "pci";
303 };
304};