1// SPDX-License-Identifier: GPL-2.0-or-later
 2/*
 3 * SBC8548 Device Tree Source
 4 *
 5 * Copyright 2007 Wind River Systems Inc.
 6 *
 7 * Paul Gortmaker (see MAINTAINERS for contact information)
 
 
 
 
 
 8 */
 9
10/{
11	model = "SBC8548";
12	compatible = "SBC8548";
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	aliases {
17		ethernet0 = &enet0;
18		ethernet1 = &enet1;
19		serial0 = &serial0;
20		serial1 = &serial1;
21		pci0 = &pci0;
22		pci1 = &pci1;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		PowerPC,8548@0 {
30			device_type = "cpu";
31			reg = <0>;
32			d-cache-line-size = <0x20>;	// 32 bytes
33			i-cache-line-size = <0x20>;	// 32 bytes
34			d-cache-size = <0x8000>;	// L1, 32K
35			i-cache-size = <0x8000>;	// L1, 32K
36			timebase-frequency = <0>;	// From uboot
37			bus-frequency = <0>;
38			clock-frequency = <0>;
39			next-level-cache = <&L2>;
40		};
41	};
42
43	memory {
44		device_type = "memory";
45		reg = <0x00000000 0x10000000>;
46	};
47
48};

 
 1/*
 2 * SBC8548 Device Tree Source
 3 *
 4 * Copyright 2007 Wind River Systems Inc.
 5 *
 6 * Paul Gortmaker (see MAINTAINERS for contact information)
 7 *
 8 * This program is free software; you can redistribute  it and/or modify it
 9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13
14/{
15	model = "SBC8548";
16	compatible = "SBC8548";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26		pci1 = &pci1;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		PowerPC,8548@0 {
34			device_type = "cpu";
35			reg = <0>;
36			d-cache-line-size = <0x20>;	// 32 bytes
37			i-cache-line-size = <0x20>;	// 32 bytes
38			d-cache-size = <0x8000>;	// L1, 32K
39			i-cache-size = <0x8000>;	// L1, 32K
40			timebase-frequency = <0>;	// From uboot
41			bus-frequency = <0>;
42			clock-frequency = <0>;
43			next-level-cache = <&L2>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x00000000 0x10000000>;
50	};
51
52};