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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * AT91 Power Management
4 *
5 * Copyright (C) 2005 David Brownell
6 */
7#ifndef __ARCH_ARM_MACH_AT91_PM
8#define __ARCH_ARM_MACH_AT91_PM
9
10#include <asm/proc-fns.h>
11
12#include <linux/mfd/syscon/atmel-mc.h>
13#include <soc/at91/at91sam9_ddrsdr.h>
14#include <soc/at91/at91sam9_sdramc.h>
15
16#define AT91_MEMCTRL_MC 0
17#define AT91_MEMCTRL_SDRAMC 1
18#define AT91_MEMCTRL_DDRSDR 2
19
20#define AT91_PM_STANDBY 0x00
21#define AT91_PM_ULP0 0x01
22#define AT91_PM_ULP0_FAST 0x02
23#define AT91_PM_ULP1 0x03
24#define AT91_PM_BACKUP 0x04
25
26#ifndef __ASSEMBLY__
27struct at91_pm_data {
28 void __iomem *pmc;
29 void __iomem *ramc[2];
30 unsigned long uhp_udp_mask;
31 unsigned int memctrl;
32 unsigned int mode;
33 void __iomem *shdwc;
34 void __iomem *sfrbu;
35 unsigned int standby_mode;
36 unsigned int suspend_mode;
37 unsigned int pmc_mckr_offset;
38 unsigned int pmc_version;
39};
40#endif
41
42#endif
1/*
2 * AT91 Power Management
3 *
4 * Copyright (C) 2005 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef __ARCH_ARM_MACH_AT91_PM
12#define __ARCH_ARM_MACH_AT91_PM
13
14#include <asm/proc-fns.h>
15
16#include <mach/at91_ramc.h>
17#include <mach/at91rm9200_sdramc.h>
18
19#ifdef CONFIG_PM
20extern void at91_pm_set_standby(void (*at91_standby)(void));
21#else
22static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
23#endif
24
25/*
26 * The AT91RM9200 goes into self-refresh mode with this command, and will
27 * terminate self-refresh automatically on the next SDRAM access.
28 *
29 * Self-refresh mode is exited as soon as a memory access is made, but we don't
30 * know for sure when that happens. However, we need to restore the low-power
31 * mode if it was enabled before going idle. Restoring low-power mode while
32 * still in self-refresh is "not recommended", but seems to work.
33 */
34
35static inline void at91rm9200_standby(void)
36{
37 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
38
39 asm volatile(
40 "b 1f\n\t"
41 ".align 5\n\t"
42 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
43 " str %0, [%1, %2]\n\t"
44 " str %3, [%1, %4]\n\t"
45 " mcr p15, 0, %0, c7, c0, 4\n\t"
46 " str %5, [%1, %2]"
47 :
48 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
49 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
50 "r" (lpr));
51}
52
53/* We manage both DDRAM/SDRAM controllers, we need more than one value to
54 * remember.
55 */
56static inline void at91_ddr_standby(void)
57{
58 /* Those two values allow us to delay self-refresh activation
59 * to the maximum. */
60 u32 lpr0, lpr1 = 0;
61 u32 saved_lpr0, saved_lpr1 = 0;
62
63 if (at91_ramc_base[1]) {
64 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
65 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
66 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
67 }
68
69 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
70 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
71 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
72
73 /* self-refresh mode now */
74 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
75 if (at91_ramc_base[1])
76 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
77
78 cpu_do_idle();
79
80 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
81 if (at91_ramc_base[1])
82 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
83}
84
85/* We manage both DDRAM/SDRAM controllers, we need more than one value to
86 * remember.
87 */
88static inline void at91sam9_sdram_standby(void)
89{
90 u32 lpr0, lpr1 = 0;
91 u32 saved_lpr0, saved_lpr1 = 0;
92
93 if (at91_ramc_base[1]) {
94 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
95 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
96 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
97 }
98
99 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
100 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
101 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
102
103 /* self-refresh mode now */
104 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
105 if (at91_ramc_base[1])
106 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
107
108 cpu_do_idle();
109
110 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
111 if (at91_ramc_base[1])
112 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
113}
114
115#endif