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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
5 *
6 * Copyright (C) 2005 David Brownell
7 */
8
9#include <linux/genalloc.h>
10#include <linux/io.h>
11#include <linux/of_address.h>
12#include <linux/of.h>
13#include <linux/of_platform.h>
14#include <linux/parser.h>
15#include <linux/suspend.h>
16
17#include <linux/clk/at91_pmc.h>
18#include <linux/platform_data/atmel.h>
19
20#include <soc/at91/pm.h>
21
22#include <asm/cacheflush.h>
23#include <asm/fncpy.h>
24#include <asm/system_misc.h>
25#include <asm/suspend.h>
26
27#include "generic.h"
28#include "pm.h"
29
30struct at91_soc_pm {
31 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
32 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
33 const struct of_device_id *ws_ids;
34 struct at91_pm_data data;
35};
36
37static struct at91_soc_pm soc_pm = {
38 .data = {
39 .standby_mode = AT91_PM_STANDBY,
40 .suspend_mode = AT91_PM_ULP0,
41 },
42};
43
44static const match_table_t pm_modes __initconst = {
45 { AT91_PM_STANDBY, "standby" },
46 { AT91_PM_ULP0, "ulp0" },
47 { AT91_PM_ULP0_FAST, "ulp0-fast" },
48 { AT91_PM_ULP1, "ulp1" },
49 { AT91_PM_BACKUP, "backup" },
50 { -1, NULL },
51};
52
53#define at91_ramc_read(id, field) \
54 __raw_readl(soc_pm.data.ramc[id] + field)
55
56#define at91_ramc_write(id, field, value) \
57 __raw_writel(value, soc_pm.data.ramc[id] + field)
58
59static int at91_pm_valid_state(suspend_state_t state)
60{
61 switch (state) {
62 case PM_SUSPEND_ON:
63 case PM_SUSPEND_STANDBY:
64 case PM_SUSPEND_MEM:
65 return 1;
66
67 default:
68 return 0;
69 }
70}
71
72static int canary = 0xA5A5A5A5;
73
74static struct at91_pm_bu {
75 int suspended;
76 unsigned long reserved;
77 phys_addr_t canary;
78 phys_addr_t resume;
79} *pm_bu;
80
81struct wakeup_source_info {
82 unsigned int pmc_fsmr_bit;
83 unsigned int shdwc_mr_bit;
84 bool set_polarity;
85};
86
87static const struct wakeup_source_info ws_info[] = {
88 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
89 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
90 { .pmc_fsmr_bit = AT91_PMC_USBAL },
91 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
92 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
93 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
94};
95
96static const struct of_device_id sama5d2_ws_ids[] = {
97 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
98 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
99 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
100 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
101 { .compatible = "usb-ohci", .data = &ws_info[2] },
102 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
103 { .compatible = "usb-ehci", .data = &ws_info[2] },
104 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
105 { /* sentinel */ }
106};
107
108static const struct of_device_id sam9x60_ws_ids[] = {
109 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
110 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
111 { .compatible = "usb-ohci", .data = &ws_info[2] },
112 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
113 { .compatible = "usb-ehci", .data = &ws_info[2] },
114 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
115 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
116 { /* sentinel */ }
117};
118
119static int at91_pm_config_ws(unsigned int pm_mode, bool set)
120{
121 const struct wakeup_source_info *wsi;
122 const struct of_device_id *match;
123 struct platform_device *pdev;
124 struct device_node *np;
125 unsigned int mode = 0, polarity = 0, val = 0;
126
127 if (pm_mode != AT91_PM_ULP1)
128 return 0;
129
130 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
131 return -EPERM;
132
133 if (!set) {
134 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
135 return 0;
136 }
137
138 if (soc_pm.config_shdwc_ws)
139 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
140
141 /* SHDWC.MR */
142 val = readl(soc_pm.data.shdwc + 0x04);
143
144 /* Loop through defined wakeup sources. */
145 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
146 pdev = of_find_device_by_node(np);
147 if (!pdev)
148 continue;
149
150 if (device_may_wakeup(&pdev->dev)) {
151 wsi = match->data;
152
153 /* Check if enabled on SHDWC. */
154 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
155 goto put_device;
156
157 mode |= wsi->pmc_fsmr_bit;
158 if (wsi->set_polarity)
159 polarity |= wsi->pmc_fsmr_bit;
160 }
161
162put_device:
163 put_device(&pdev->dev);
164 }
165
166 if (mode) {
167 if (soc_pm.config_pmc_ws)
168 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
169 } else {
170 pr_err("AT91: PM: no ULP1 wakeup sources found!");
171 }
172
173 return mode ? 0 : -EPERM;
174}
175
176static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
177 u32 *polarity)
178{
179 u32 val;
180
181 /* SHDWC.WUIR */
182 val = readl(shdwc + 0x0c);
183 *mode |= (val & 0x3ff);
184 *polarity |= ((val >> 16) & 0x3ff);
185
186 return 0;
187}
188
189static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
190{
191 writel(mode, pmc + AT91_PMC_FSMR);
192 writel(polarity, pmc + AT91_PMC_FSPR);
193
194 return 0;
195}
196
197static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
198{
199 writel(mode, pmc + AT91_PMC_FSMR);
200
201 return 0;
202}
203
204/*
205 * Called after processes are frozen, but before we shutdown devices.
206 */
207static int at91_pm_begin(suspend_state_t state)
208{
209 switch (state) {
210 case PM_SUSPEND_MEM:
211 soc_pm.data.mode = soc_pm.data.suspend_mode;
212 break;
213
214 case PM_SUSPEND_STANDBY:
215 soc_pm.data.mode = soc_pm.data.standby_mode;
216 break;
217
218 default:
219 soc_pm.data.mode = -1;
220 }
221
222 return at91_pm_config_ws(soc_pm.data.mode, true);
223}
224
225/*
226 * Verify that all the clocks are correct before entering
227 * slow-clock mode.
228 */
229static int at91_pm_verify_clocks(void)
230{
231 unsigned long scsr;
232 int i;
233
234 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
235
236 /* USB must not be using PLLB */
237 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
238 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
239 return 0;
240 }
241
242 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
243 for (i = 0; i < 4; i++) {
244 u32 css;
245
246 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
247 continue;
248 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
249 if (css != AT91_PMC_CSS_SLOW) {
250 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
251 return 0;
252 }
253 }
254
255 return 1;
256}
257
258/*
259 * Call this from platform driver suspend() to see how deeply to suspend.
260 * For example, some controllers (like OHCI) need one of the PLL clocks
261 * in order to act as a wakeup source, and those are not available when
262 * going into slow clock mode.
263 *
264 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
265 * the very same problem (but not using at91 main_clk), and it'd be better
266 * to add one generic API rather than lots of platform-specific ones.
267 */
268int at91_suspend_entering_slow_clock(void)
269{
270 return (soc_pm.data.mode >= AT91_PM_ULP0);
271}
272EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
273
274static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
275extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
276extern u32 at91_pm_suspend_in_sram_sz;
277
278static int at91_suspend_finish(unsigned long val)
279{
280 flush_cache_all();
281 outer_disable();
282
283 at91_suspend_sram_fn(&soc_pm.data);
284
285 return 0;
286}
287
288static void at91_pm_suspend(suspend_state_t state)
289{
290 if (soc_pm.data.mode == AT91_PM_BACKUP) {
291 pm_bu->suspended = 1;
292
293 cpu_suspend(0, at91_suspend_finish);
294
295 /* The SRAM is lost between suspend cycles */
296 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
297 &at91_pm_suspend_in_sram,
298 at91_pm_suspend_in_sram_sz);
299 } else {
300 at91_suspend_finish(0);
301 }
302
303 outer_resume();
304}
305
306/*
307 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
308 * event sources; and reduces DRAM power. But otherwise it's identical to
309 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
310 *
311 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
312 * suspend more deeply, the master clock switches to the clk32k and turns off
313 * the main oscillator
314 *
315 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
316 */
317static int at91_pm_enter(suspend_state_t state)
318{
319#ifdef CONFIG_PINCTRL_AT91
320 /*
321 * FIXME: this is needed to communicate between the pinctrl driver and
322 * the PM implementation in the machine. Possibly part of the PM
323 * implementation should be moved down into the pinctrl driver and get
324 * called as part of the generic suspend/resume path.
325 */
326 at91_pinctrl_gpio_suspend();
327#endif
328
329 switch (state) {
330 case PM_SUSPEND_MEM:
331 case PM_SUSPEND_STANDBY:
332 /*
333 * Ensure that clocks are in a valid state.
334 */
335 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
336 !at91_pm_verify_clocks())
337 goto error;
338
339 at91_pm_suspend(state);
340
341 break;
342
343 case PM_SUSPEND_ON:
344 cpu_do_idle();
345 break;
346
347 default:
348 pr_debug("AT91: PM - bogus suspend state %d\n", state);
349 goto error;
350 }
351
352error:
353#ifdef CONFIG_PINCTRL_AT91
354 at91_pinctrl_gpio_resume();
355#endif
356 return 0;
357}
358
359/*
360 * Called right prior to thawing processes.
361 */
362static void at91_pm_end(void)
363{
364 at91_pm_config_ws(soc_pm.data.mode, false);
365}
366
367
368static const struct platform_suspend_ops at91_pm_ops = {
369 .valid = at91_pm_valid_state,
370 .begin = at91_pm_begin,
371 .enter = at91_pm_enter,
372 .end = at91_pm_end,
373};
374
375static struct platform_device at91_cpuidle_device = {
376 .name = "cpuidle-at91",
377};
378
379/*
380 * The AT91RM9200 goes into self-refresh mode with this command, and will
381 * terminate self-refresh automatically on the next SDRAM access.
382 *
383 * Self-refresh mode is exited as soon as a memory access is made, but we don't
384 * know for sure when that happens. However, we need to restore the low-power
385 * mode if it was enabled before going idle. Restoring low-power mode while
386 * still in self-refresh is "not recommended", but seems to work.
387 */
388static void at91rm9200_standby(void)
389{
390 asm volatile(
391 "b 1f\n\t"
392 ".align 5\n\t"
393 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
394 " str %2, [%1, %3]\n\t"
395 " mcr p15, 0, %0, c7, c0, 4\n\t"
396 :
397 : "r" (0), "r" (soc_pm.data.ramc[0]),
398 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
399}
400
401/* We manage both DDRAM/SDRAM controllers, we need more than one value to
402 * remember.
403 */
404static void at91_ddr_standby(void)
405{
406 /* Those two values allow us to delay self-refresh activation
407 * to the maximum. */
408 u32 lpr0, lpr1 = 0;
409 u32 mdr, saved_mdr0, saved_mdr1 = 0;
410 u32 saved_lpr0, saved_lpr1 = 0;
411
412 /* LPDDR1 --> force DDR2 mode during self-refresh */
413 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
414 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
415 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
416 mdr |= AT91_DDRSDRC_MD_DDR2;
417 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
418 }
419
420 if (soc_pm.data.ramc[1]) {
421 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
422 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
423 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
424 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
425 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
426 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
427 mdr |= AT91_DDRSDRC_MD_DDR2;
428 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
429 }
430 }
431
432 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
433 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
434 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
435
436 /* self-refresh mode now */
437 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
438 if (soc_pm.data.ramc[1])
439 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
440
441 cpu_do_idle();
442
443 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
444 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
445 if (soc_pm.data.ramc[1]) {
446 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
447 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
448 }
449}
450
451static void sama5d3_ddr_standby(void)
452{
453 u32 lpr0;
454 u32 saved_lpr0;
455
456 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
457 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
458 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
459
460 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
461
462 cpu_do_idle();
463
464 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
465}
466
467/* We manage both DDRAM/SDRAM controllers, we need more than one value to
468 * remember.
469 */
470static void at91sam9_sdram_standby(void)
471{
472 u32 lpr0, lpr1 = 0;
473 u32 saved_lpr0, saved_lpr1 = 0;
474
475 if (soc_pm.data.ramc[1]) {
476 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
477 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
478 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
479 }
480
481 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
482 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
483 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
484
485 /* self-refresh mode now */
486 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
487 if (soc_pm.data.ramc[1])
488 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
489
490 cpu_do_idle();
491
492 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
493 if (soc_pm.data.ramc[1])
494 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
495}
496
497struct ramc_info {
498 void (*idle)(void);
499 unsigned int memctrl;
500};
501
502static const struct ramc_info ramc_infos[] __initconst = {
503 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
504 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
505 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
506 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
507};
508
509static const struct of_device_id ramc_ids[] __initconst = {
510 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
511 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
512 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
513 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
514 { /*sentinel*/ }
515};
516
517static __init int at91_dt_ramc(void)
518{
519 struct device_node *np;
520 const struct of_device_id *of_id;
521 int idx = 0;
522 void *standby = NULL;
523 const struct ramc_info *ramc;
524 int ret;
525
526 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
527 soc_pm.data.ramc[idx] = of_iomap(np, 0);
528 if (!soc_pm.data.ramc[idx]) {
529 pr_err("unable to map ramc[%d] cpu registers\n", idx);
530 ret = -ENOMEM;
531 goto unmap_ramc;
532 }
533
534 ramc = of_id->data;
535 if (!standby)
536 standby = ramc->idle;
537 soc_pm.data.memctrl = ramc->memctrl;
538
539 idx++;
540 }
541
542 if (!idx) {
543 pr_err("unable to find compatible ram controller node in dtb\n");
544 ret = -ENODEV;
545 goto unmap_ramc;
546 }
547
548 if (!standby) {
549 pr_warn("ramc no standby function available\n");
550 return 0;
551 }
552
553 at91_cpuidle_device.dev.platform_data = standby;
554
555 return 0;
556
557unmap_ramc:
558 while (idx)
559 iounmap(soc_pm.data.ramc[--idx]);
560
561 return ret;
562}
563
564static void at91rm9200_idle(void)
565{
566 /*
567 * Disable the processor clock. The processor will be automatically
568 * re-enabled by an interrupt or by a reset.
569 */
570 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
571}
572
573static void at91sam9_idle(void)
574{
575 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
576 cpu_do_idle();
577}
578
579static void __init at91_pm_sram_init(void)
580{
581 struct gen_pool *sram_pool;
582 phys_addr_t sram_pbase;
583 unsigned long sram_base;
584 struct device_node *node;
585 struct platform_device *pdev = NULL;
586
587 for_each_compatible_node(node, NULL, "mmio-sram") {
588 pdev = of_find_device_by_node(node);
589 if (pdev) {
590 of_node_put(node);
591 break;
592 }
593 }
594
595 if (!pdev) {
596 pr_warn("%s: failed to find sram device!\n", __func__);
597 return;
598 }
599
600 sram_pool = gen_pool_get(&pdev->dev, NULL);
601 if (!sram_pool) {
602 pr_warn("%s: sram pool unavailable!\n", __func__);
603 goto out_put_device;
604 }
605
606 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
607 if (!sram_base) {
608 pr_warn("%s: unable to alloc sram!\n", __func__);
609 goto out_put_device;
610 }
611
612 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
613 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
614 at91_pm_suspend_in_sram_sz, false);
615 if (!at91_suspend_sram_fn) {
616 pr_warn("SRAM: Could not map\n");
617 goto out_put_device;
618 }
619
620 /* Copy the pm suspend handler to SRAM */
621 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
622 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
623 return;
624
625out_put_device:
626 put_device(&pdev->dev);
627 return;
628}
629
630static bool __init at91_is_pm_mode_active(int pm_mode)
631{
632 return (soc_pm.data.standby_mode == pm_mode ||
633 soc_pm.data.suspend_mode == pm_mode);
634}
635
636static int __init at91_pm_backup_init(void)
637{
638 struct gen_pool *sram_pool;
639 struct device_node *np;
640 struct platform_device *pdev = NULL;
641 int ret = -ENODEV;
642
643 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
644 return -EPERM;
645
646 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
647 return 0;
648
649 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
650 if (!np) {
651 pr_warn("%s: failed to find sfrbu!\n", __func__);
652 return ret;
653 }
654
655 soc_pm.data.sfrbu = of_iomap(np, 0);
656 of_node_put(np);
657
658 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
659 if (!np)
660 goto securam_fail_no_ref_dev;
661
662 pdev = of_find_device_by_node(np);
663 of_node_put(np);
664 if (!pdev) {
665 pr_warn("%s: failed to find securam device!\n", __func__);
666 goto securam_fail_no_ref_dev;
667 }
668
669 sram_pool = gen_pool_get(&pdev->dev, NULL);
670 if (!sram_pool) {
671 pr_warn("%s: securam pool unavailable!\n", __func__);
672 goto securam_fail;
673 }
674
675 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
676 if (!pm_bu) {
677 pr_warn("%s: unable to alloc securam!\n", __func__);
678 ret = -ENOMEM;
679 goto securam_fail;
680 }
681
682 pm_bu->suspended = 0;
683 pm_bu->canary = __pa_symbol(&canary);
684 pm_bu->resume = __pa_symbol(cpu_resume);
685
686 return 0;
687
688securam_fail:
689 put_device(&pdev->dev);
690securam_fail_no_ref_dev:
691 iounmap(soc_pm.data.sfrbu);
692 soc_pm.data.sfrbu = NULL;
693 return ret;
694}
695
696static void __init at91_pm_use_default_mode(int pm_mode)
697{
698 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
699 return;
700
701 if (soc_pm.data.standby_mode == pm_mode)
702 soc_pm.data.standby_mode = AT91_PM_ULP0;
703 if (soc_pm.data.suspend_mode == pm_mode)
704 soc_pm.data.suspend_mode = AT91_PM_ULP0;
705}
706
707static const struct of_device_id atmel_shdwc_ids[] = {
708 { .compatible = "atmel,sama5d2-shdwc" },
709 { .compatible = "microchip,sam9x60-shdwc" },
710 { /* sentinel. */ }
711};
712
713static void __init at91_pm_modes_init(void)
714{
715 struct device_node *np;
716 int ret;
717
718 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
719 !at91_is_pm_mode_active(AT91_PM_ULP1))
720 return;
721
722 np = of_find_matching_node(NULL, atmel_shdwc_ids);
723 if (!np) {
724 pr_warn("%s: failed to find shdwc!\n", __func__);
725 goto ulp1_default;
726 }
727
728 soc_pm.data.shdwc = of_iomap(np, 0);
729 of_node_put(np);
730
731 ret = at91_pm_backup_init();
732 if (ret) {
733 if (!at91_is_pm_mode_active(AT91_PM_ULP1))
734 goto unmap;
735 else
736 goto backup_default;
737 }
738
739 return;
740
741unmap:
742 iounmap(soc_pm.data.shdwc);
743 soc_pm.data.shdwc = NULL;
744ulp1_default:
745 at91_pm_use_default_mode(AT91_PM_ULP1);
746backup_default:
747 at91_pm_use_default_mode(AT91_PM_BACKUP);
748}
749
750struct pmc_info {
751 unsigned long uhp_udp_mask;
752 unsigned long mckr;
753 unsigned long version;
754};
755
756static const struct pmc_info pmc_infos[] __initconst = {
757 {
758 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
759 .mckr = 0x30,
760 .version = AT91_PMC_V1,
761 },
762
763 {
764 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
765 .mckr = 0x30,
766 .version = AT91_PMC_V1,
767 },
768 {
769 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
770 .mckr = 0x30,
771 .version = AT91_PMC_V1,
772 },
773 { .uhp_udp_mask = 0,
774 .mckr = 0x30,
775 .version = AT91_PMC_V1,
776 },
777 {
778 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
779 .mckr = 0x28,
780 .version = AT91_PMC_V2,
781 },
782};
783
784static const struct of_device_id atmel_pmc_ids[] __initconst = {
785 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
786 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
787 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
788 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
789 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
790 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
791 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
792 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
793 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
794 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
795 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
796 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
797 { /* sentinel */ },
798};
799
800static void __init at91_pm_modes_validate(const int *modes, int len)
801{
802 u8 i, standby = 0, suspend = 0;
803 int mode;
804
805 for (i = 0; i < len; i++) {
806 if (standby && suspend)
807 break;
808
809 if (modes[i] == soc_pm.data.standby_mode && !standby) {
810 standby = 1;
811 continue;
812 }
813
814 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
815 suspend = 1;
816 continue;
817 }
818 }
819
820 if (!standby) {
821 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
822 mode = AT91_PM_ULP0;
823 else
824 mode = AT91_PM_STANDBY;
825
826 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
827 pm_modes[soc_pm.data.standby_mode].pattern,
828 pm_modes[mode].pattern);
829 soc_pm.data.standby_mode = mode;
830 }
831
832 if (!suspend) {
833 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
834 mode = AT91_PM_STANDBY;
835 else
836 mode = AT91_PM_ULP0;
837
838 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
839 pm_modes[soc_pm.data.suspend_mode].pattern,
840 pm_modes[mode].pattern);
841 soc_pm.data.suspend_mode = mode;
842 }
843}
844
845static void __init at91_pm_init(void (*pm_idle)(void))
846{
847 struct device_node *pmc_np;
848 const struct of_device_id *of_id;
849 const struct pmc_info *pmc;
850
851 if (at91_cpuidle_device.dev.platform_data)
852 platform_device_register(&at91_cpuidle_device);
853
854 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
855 soc_pm.data.pmc = of_iomap(pmc_np, 0);
856 of_node_put(pmc_np);
857 if (!soc_pm.data.pmc) {
858 pr_err("AT91: PM not supported, PMC not found\n");
859 return;
860 }
861
862 pmc = of_id->data;
863 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
864 soc_pm.data.pmc_mckr_offset = pmc->mckr;
865 soc_pm.data.pmc_version = pmc->version;
866
867 if (pm_idle)
868 arm_pm_idle = pm_idle;
869
870 at91_pm_sram_init();
871
872 if (at91_suspend_sram_fn) {
873 suspend_set_ops(&at91_pm_ops);
874 pr_info("AT91: PM: standby: %s, suspend: %s\n",
875 pm_modes[soc_pm.data.standby_mode].pattern,
876 pm_modes[soc_pm.data.suspend_mode].pattern);
877 } else {
878 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
879 }
880}
881
882void __init at91rm9200_pm_init(void)
883{
884 int ret;
885
886 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
887 return;
888
889 /*
890 * Force STANDBY and ULP0 mode to avoid calling
891 * at91_pm_modes_validate() which may increase booting time.
892 * Platform supports anyway only STANDBY and ULP0 modes.
893 */
894 soc_pm.data.standby_mode = AT91_PM_STANDBY;
895 soc_pm.data.suspend_mode = AT91_PM_ULP0;
896
897 ret = at91_dt_ramc();
898 if (ret)
899 return;
900
901 /*
902 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
903 */
904 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
905
906 at91_pm_init(at91rm9200_idle);
907}
908
909void __init sam9x60_pm_init(void)
910{
911 static const int modes[] __initconst = {
912 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
913 };
914 int ret;
915
916 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
917 return;
918
919 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
920 at91_pm_modes_init();
921 ret = at91_dt_ramc();
922 if (ret)
923 return;
924
925 at91_pm_init(NULL);
926
927 soc_pm.ws_ids = sam9x60_ws_ids;
928 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
929}
930
931void __init at91sam9_pm_init(void)
932{
933 int ret;
934
935 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
936 return;
937
938 /*
939 * Force STANDBY and ULP0 mode to avoid calling
940 * at91_pm_modes_validate() which may increase booting time.
941 * Platform supports anyway only STANDBY and ULP0 modes.
942 */
943 soc_pm.data.standby_mode = AT91_PM_STANDBY;
944 soc_pm.data.suspend_mode = AT91_PM_ULP0;
945
946 ret = at91_dt_ramc();
947 if (ret)
948 return;
949
950 at91_pm_init(at91sam9_idle);
951}
952
953void __init sama5_pm_init(void)
954{
955 static const int modes[] __initconst = {
956 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
957 };
958 int ret;
959
960 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
961 return;
962
963 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
964 ret = at91_dt_ramc();
965 if (ret)
966 return;
967
968 at91_pm_init(NULL);
969}
970
971void __init sama5d2_pm_init(void)
972{
973 static const int modes[] __initconst = {
974 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
975 AT91_PM_BACKUP,
976 };
977 int ret;
978
979 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
980 return;
981
982 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
983 at91_pm_modes_init();
984 ret = at91_dt_ramc();
985 if (ret)
986 return;
987
988 at91_pm_init(NULL);
989
990 soc_pm.ws_ids = sama5d2_ws_ids;
991 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
992 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
993}
994
995static int __init at91_pm_modes_select(char *str)
996{
997 char *s;
998 substring_t args[MAX_OPT_ARGS];
999 int standby, suspend;
1000
1001 if (!str)
1002 return 0;
1003
1004 s = strsep(&str, ",");
1005 standby = match_token(s, pm_modes, args);
1006 if (standby < 0)
1007 return 0;
1008
1009 suspend = match_token(str, pm_modes, args);
1010 if (suspend < 0)
1011 return 0;
1012
1013 soc_pm.data.standby_mode = standby;
1014 soc_pm.data.suspend_mode = suspend;
1015
1016 return 0;
1017}
1018early_param("atmel.pm_modes", at91_pm_modes_select);
1/*
2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
4 *
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/gpio.h>
14#include <linux/suspend.h>
15#include <linux/sched.h>
16#include <linux/proc_fs.h>
17#include <linux/interrupt.h>
18#include <linux/sysfs.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/clk/at91_pmc.h>
23
24#include <asm/irq.h>
25#include <linux/atomic.h>
26#include <asm/mach/time.h>
27#include <asm/mach/irq.h>
28
29#include <mach/cpu.h>
30#include <mach/hardware.h>
31
32#include "at91_aic.h"
33#include "generic.h"
34#include "pm.h"
35
36/*
37 * Show the reason for the previous system reset.
38 */
39
40#include "at91_rstc.h"
41#include "at91_shdwc.h"
42
43static void (*at91_pm_standby)(void);
44
45static void __init show_reset_status(void)
46{
47 static char reset[] __initdata = "reset";
48
49 static char general[] __initdata = "general";
50 static char wakeup[] __initdata = "wakeup";
51 static char watchdog[] __initdata = "watchdog";
52 static char software[] __initdata = "software";
53 static char user[] __initdata = "user";
54 static char unknown[] __initdata = "unknown";
55
56 static char signal[] __initdata = "signal";
57 static char rtc[] __initdata = "rtc";
58 static char rtt[] __initdata = "rtt";
59 static char restore[] __initdata = "power-restored";
60
61 char *reason, *r2 = reset;
62 u32 reset_type, wake_type;
63
64 if (!at91_shdwc_base || !at91_rstc_base)
65 return;
66
67 reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
68 wake_type = at91_shdwc_read(AT91_SHDW_SR);
69
70 switch (reset_type) {
71 case AT91_RSTC_RSTTYP_GENERAL:
72 reason = general;
73 break;
74 case AT91_RSTC_RSTTYP_WAKEUP:
75 /* board-specific code enabled the wakeup sources */
76 reason = wakeup;
77
78 /* "wakeup signal" */
79 if (wake_type & AT91_SHDW_WAKEUP0)
80 r2 = signal;
81 else {
82 r2 = reason;
83 if (wake_type & AT91_SHDW_RTTWK) /* rtt wakeup */
84 reason = rtt;
85 else if (wake_type & AT91_SHDW_RTCWK) /* rtc wakeup */
86 reason = rtc;
87 else if (wake_type == 0) /* power-restored wakeup */
88 reason = restore;
89 else /* unknown wakeup */
90 reason = unknown;
91 }
92 break;
93 case AT91_RSTC_RSTTYP_WATCHDOG:
94 reason = watchdog;
95 break;
96 case AT91_RSTC_RSTTYP_SOFTWARE:
97 reason = software;
98 break;
99 case AT91_RSTC_RSTTYP_USER:
100 reason = user;
101 break;
102 default:
103 reason = unknown;
104 break;
105 }
106 pr_info("AT91: Starting after %s %s\n", reason, r2);
107}
108
109static int at91_pm_valid_state(suspend_state_t state)
110{
111 switch (state) {
112 case PM_SUSPEND_ON:
113 case PM_SUSPEND_STANDBY:
114 case PM_SUSPEND_MEM:
115 return 1;
116
117 default:
118 return 0;
119 }
120}
121
122
123static suspend_state_t target_state;
124
125/*
126 * Called after processes are frozen, but before we shutdown devices.
127 */
128static int at91_pm_begin(suspend_state_t state)
129{
130 target_state = state;
131 return 0;
132}
133
134/*
135 * Verify that all the clocks are correct before entering
136 * slow-clock mode.
137 */
138static int at91_pm_verify_clocks(void)
139{
140 unsigned long scsr;
141 int i;
142
143 scsr = at91_pmc_read(AT91_PMC_SCSR);
144
145 /* USB must not be using PLLB */
146 if (cpu_is_at91rm9200()) {
147 if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
148 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
149 return 0;
150 }
151 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()
152 || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) {
153 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
154 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
155 return 0;
156 }
157 }
158
159 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
160 for (i = 0; i < 4; i++) {
161 u32 css;
162
163 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
164 continue;
165
166 css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
167 if (css != AT91_PMC_CSS_SLOW) {
168 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
169 return 0;
170 }
171 }
172
173 return 1;
174}
175
176/*
177 * Call this from platform driver suspend() to see how deeply to suspend.
178 * For example, some controllers (like OHCI) need one of the PLL clocks
179 * in order to act as a wakeup source, and those are not available when
180 * going into slow clock mode.
181 *
182 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
183 * the very same problem (but not using at91 main_clk), and it'd be better
184 * to add one generic API rather than lots of platform-specific ones.
185 */
186int at91_suspend_entering_slow_clock(void)
187{
188 return (target_state == PM_SUSPEND_MEM);
189}
190EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
191
192
193static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
194 void __iomem *ramc1, int memctrl);
195
196#ifdef CONFIG_AT91_SLOW_CLOCK
197extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
198 void __iomem *ramc1, int memctrl);
199extern u32 at91_slow_clock_sz;
200#endif
201
202static int at91_pm_enter(suspend_state_t state)
203{
204 if (of_have_populated_dt())
205 at91_pinctrl_gpio_suspend();
206 else
207 at91_gpio_suspend();
208 at91_irq_suspend();
209
210 pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
211 /* remember all the always-wake irqs */
212 (at91_pmc_read(AT91_PMC_PCSR)
213 | (1 << AT91_ID_FIQ)
214 | (1 << AT91_ID_SYS)
215 | (at91_get_extern_irq()))
216 & at91_aic_read(AT91_AIC_IMR),
217 state);
218
219 switch (state) {
220 /*
221 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
222 * drivers must suspend more deeply: only the master clock
223 * controller may be using the main oscillator.
224 */
225 case PM_SUSPEND_MEM:
226 /*
227 * Ensure that clocks are in a valid state.
228 */
229 if (!at91_pm_verify_clocks())
230 goto error;
231
232 /*
233 * Enter slow clock mode by switching over to clk32k and
234 * turning off the main oscillator; reverse on wakeup.
235 */
236 if (slow_clock) {
237 int memctrl = AT91_MEMCTRL_SDRAMC;
238
239 if (cpu_is_at91rm9200())
240 memctrl = AT91_MEMCTRL_MC;
241 else if (cpu_is_at91sam9g45())
242 memctrl = AT91_MEMCTRL_DDRSDR;
243#ifdef CONFIG_AT91_SLOW_CLOCK
244 /* copy slow_clock handler to SRAM, and call it */
245 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
246#endif
247 slow_clock(at91_pmc_base, at91_ramc_base[0],
248 at91_ramc_base[1], memctrl);
249 break;
250 } else {
251 pr_info("AT91: PM - no slow clock mode enabled ...\n");
252 /* FALLTHROUGH leaving master clock alone */
253 }
254
255 /*
256 * STANDBY mode has *all* drivers suspended; ignores irqs not
257 * marked as 'wakeup' event sources; and reduces DRAM power.
258 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
259 * nothing fancy done with main or cpu clocks.
260 */
261 case PM_SUSPEND_STANDBY:
262 /*
263 * NOTE: the Wait-for-Interrupt instruction needs to be
264 * in icache so no SDRAM accesses are needed until the
265 * wakeup IRQ occurs and self-refresh is terminated.
266 * For ARM 926 based chips, this requirement is weaker
267 * as at91sam9 can access a RAM in self-refresh mode.
268 */
269 if (at91_pm_standby)
270 at91_pm_standby();
271 break;
272
273 case PM_SUSPEND_ON:
274 cpu_do_idle();
275 break;
276
277 default:
278 pr_debug("AT91: PM - bogus suspend state %d\n", state);
279 goto error;
280 }
281
282 pr_debug("AT91: PM - wakeup %08x\n",
283 at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR));
284
285error:
286 target_state = PM_SUSPEND_ON;
287 at91_irq_resume();
288 if (of_have_populated_dt())
289 at91_pinctrl_gpio_resume();
290 else
291 at91_gpio_resume();
292 return 0;
293}
294
295/*
296 * Called right prior to thawing processes.
297 */
298static void at91_pm_end(void)
299{
300 target_state = PM_SUSPEND_ON;
301}
302
303
304static const struct platform_suspend_ops at91_pm_ops = {
305 .valid = at91_pm_valid_state,
306 .begin = at91_pm_begin,
307 .enter = at91_pm_enter,
308 .end = at91_pm_end,
309};
310
311static struct platform_device at91_cpuidle_device = {
312 .name = "cpuidle-at91",
313};
314
315void at91_pm_set_standby(void (*at91_standby)(void))
316{
317 if (at91_standby) {
318 at91_cpuidle_device.dev.platform_data = at91_standby;
319 at91_pm_standby = at91_standby;
320 }
321}
322
323static int __init at91_pm_init(void)
324{
325#ifdef CONFIG_AT91_SLOW_CLOCK
326 slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
327#endif
328
329 pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
330
331 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
332 if (cpu_is_at91rm9200())
333 at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
334
335 if (at91_cpuidle_device.dev.platform_data)
336 platform_device_register(&at91_cpuidle_device);
337
338 suspend_set_ops(&at91_pm_ops);
339
340 show_reset_status();
341 return 0;
342}
343arch_initcall(at91_pm_init);