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1/*
2 * Generic EDAC defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12#ifndef _LINUX_EDAC_H_
13#define _LINUX_EDAC_H_
14
15#include <linux/atomic.h>
16#include <linux/device.h>
17#include <linux/completion.h>
18#include <linux/workqueue.h>
19#include <linux/debugfs.h>
20#include <linux/numa.h>
21
22#define EDAC_DEVICE_NAME_LEN 31
23
24struct device;
25
26#define EDAC_OPSTATE_INVAL -1
27#define EDAC_OPSTATE_POLL 0
28#define EDAC_OPSTATE_NMI 1
29#define EDAC_OPSTATE_INT 2
30
31extern int edac_op_state;
32
33struct bus_type *edac_get_sysfs_subsys(void);
34
35static inline void opstate_init(void)
36{
37 switch (edac_op_state) {
38 case EDAC_OPSTATE_POLL:
39 case EDAC_OPSTATE_NMI:
40 break;
41 default:
42 edac_op_state = EDAC_OPSTATE_POLL;
43 }
44 return;
45}
46
47/* Max length of a DIMM label*/
48#define EDAC_MC_LABEL_LEN 31
49
50/* Maximum size of the location string */
51#define LOCATION_SIZE 256
52
53/* Defines the maximum number of labels that can be reported */
54#define EDAC_MAX_LABELS 8
55
56/* String used to join two or more labels */
57#define OTHER_LABEL " or "
58
59/**
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
61 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
62 * @DEV_X1: 1 bit for data
63 * @DEV_X2: 2 bits for data
64 * @DEV_X4: 4 bits for data
65 * @DEV_X8: 8 bits for data
66 * @DEV_X16: 16 bits for data
67 * @DEV_X32: 32 bits for data
68 * @DEV_X64: 64 bits for data
69 *
70 * Typical values are x4 and x8.
71 */
72enum dev_type {
73 DEV_UNKNOWN = 0,
74 DEV_X1,
75 DEV_X2,
76 DEV_X4,
77 DEV_X8,
78 DEV_X16,
79 DEV_X32, /* Do these parts exist? */
80 DEV_X64 /* Do these parts exist? */
81};
82
83#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
84#define DEV_FLAG_X1 BIT(DEV_X1)
85#define DEV_FLAG_X2 BIT(DEV_X2)
86#define DEV_FLAG_X4 BIT(DEV_X4)
87#define DEV_FLAG_X8 BIT(DEV_X8)
88#define DEV_FLAG_X16 BIT(DEV_X16)
89#define DEV_FLAG_X32 BIT(DEV_X32)
90#define DEV_FLAG_X64 BIT(DEV_X64)
91
92/**
93 * enum hw_event_mc_err_type - type of the detected error
94 *
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
96 * corrected error was detected
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
98 * can't be corrected by ECC, but it is not
99 * fatal (maybe it is on an unused memory area,
100 * or the memory controller could recover from
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
103 * error whose handling is not urgent. This could
104 * be due to hardware data poisoning where the
105 * system can continue operation until the poisoned
106 * data is consumed. Preemptive measures may also
107 * be taken, e.g. offlining pages, etc.
108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
109 * be recovered.
110 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
111 * type of error: informational logs.
112 */
113enum hw_event_mc_err_type {
114 HW_EVENT_ERR_CORRECTED,
115 HW_EVENT_ERR_UNCORRECTED,
116 HW_EVENT_ERR_DEFERRED,
117 HW_EVENT_ERR_FATAL,
118 HW_EVENT_ERR_INFO,
119};
120
121static inline char *mc_event_error_type(const unsigned int err_type)
122{
123 switch (err_type) {
124 case HW_EVENT_ERR_CORRECTED:
125 return "Corrected";
126 case HW_EVENT_ERR_UNCORRECTED:
127 return "Uncorrected";
128 case HW_EVENT_ERR_DEFERRED:
129 return "Deferred";
130 case HW_EVENT_ERR_FATAL:
131 return "Fatal";
132 default:
133 case HW_EVENT_ERR_INFO:
134 return "Info";
135 }
136}
137
138/**
139 * enum mem_type - memory types. For a more detailed reference, please see
140 * http://en.wikipedia.org/wiki/DRAM
141 *
142 * @MEM_EMPTY: Empty csrow
143 * @MEM_RESERVED: Reserved csrow type
144 * @MEM_UNKNOWN: Unknown csrow type
145 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
146 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
147 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
148 * @MEM_SDR: SDR - Single data rate SDRAM
149 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
150 * They use 3 pins for chip select: Pins 0 and 2 are
151 * for rank 0; pins 1 and 3 are for rank 1, if the memory
152 * is dual-rank.
153 * @MEM_RDR: Registered SDR SDRAM
154 * @MEM_DDR: Double data rate SDRAM
155 * http://en.wikipedia.org/wiki/DDR_SDRAM
156 * @MEM_RDDR: Registered Double data rate SDRAM
157 * This is a variant of the DDR memories.
158 * A registered memory has a buffer inside it, hiding
159 * part of the memory details to the memory controller.
160 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
161 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
162 * Those memories are labeled as "PC2-" instead of "PC" to
163 * differentiate from DDR.
164 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
165 * and JESD206.
166 * Those memories are accessed per DIMM slot, and not by
167 * a chip select signal.
168 * @MEM_RDDR2: Registered DDR2 RAM
169 * This is a variant of the DDR2 memories.
170 * @MEM_XDR: Rambus XDR
171 * It is an evolution of the original RAMBUS memories,
172 * created to compete with DDR2. Weren't used on any
173 * x86 arch, but cell_edac PPC memory controller uses it.
174 * @MEM_DDR3: DDR3 RAM
175 * @MEM_RDDR3: Registered DDR3 RAM
176 * This is a variant of the DDR3 memories.
177 * @MEM_LRDDR3: Load-Reduced DDR3 memory.
178 * @MEM_LPDDR3: Low-Power DDR3 memory.
179 * @MEM_DDR4: Unbuffered DDR4 RAM
180 * @MEM_RDDR4: Registered DDR4 RAM
181 * This is a variant of the DDR4 memories.
182 * @MEM_LRDDR4: Load-Reduced DDR4 memory.
183 * @MEM_LPDDR4: Low-Power DDR4 memory.
184 * @MEM_DDR5: Unbuffered DDR5 RAM
185 * @MEM_NVDIMM: Non-volatile RAM
186 * @MEM_WIO2: Wide I/O 2.
187 */
188enum mem_type {
189 MEM_EMPTY = 0,
190 MEM_RESERVED,
191 MEM_UNKNOWN,
192 MEM_FPM,
193 MEM_EDO,
194 MEM_BEDO,
195 MEM_SDR,
196 MEM_RDR,
197 MEM_DDR,
198 MEM_RDDR,
199 MEM_RMBS,
200 MEM_DDR2,
201 MEM_FB_DDR2,
202 MEM_RDDR2,
203 MEM_XDR,
204 MEM_DDR3,
205 MEM_RDDR3,
206 MEM_LRDDR3,
207 MEM_LPDDR3,
208 MEM_DDR4,
209 MEM_RDDR4,
210 MEM_LRDDR4,
211 MEM_LPDDR4,
212 MEM_DDR5,
213 MEM_NVDIMM,
214 MEM_WIO2,
215};
216
217#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
218#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
219#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
220#define MEM_FLAG_FPM BIT(MEM_FPM)
221#define MEM_FLAG_EDO BIT(MEM_EDO)
222#define MEM_FLAG_BEDO BIT(MEM_BEDO)
223#define MEM_FLAG_SDR BIT(MEM_SDR)
224#define MEM_FLAG_RDR BIT(MEM_RDR)
225#define MEM_FLAG_DDR BIT(MEM_DDR)
226#define MEM_FLAG_RDDR BIT(MEM_RDDR)
227#define MEM_FLAG_RMBS BIT(MEM_RMBS)
228#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
229#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
230#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
231#define MEM_FLAG_XDR BIT(MEM_XDR)
232#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
233#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
234#define MEM_FLAG_LPDDR3 BIT(MEM_LPDDR3)
235#define MEM_FLAG_DDR4 BIT(MEM_DDR4)
236#define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
237#define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
238#define MEM_FLAG_LPDDR4 BIT(MEM_LPDDR4)
239#define MEM_FLAG_DDR5 BIT(MEM_DDR5)
240#define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM)
241#define MEM_FLAG_WIO2 BIT(MEM_WIO2)
242
243/**
244 * enum edac_type - Error Detection and Correction capabilities and mode
245 * @EDAC_UNKNOWN: Unknown if ECC is available
246 * @EDAC_NONE: Doesn't support ECC
247 * @EDAC_RESERVED: Reserved ECC type
248 * @EDAC_PARITY: Detects parity errors
249 * @EDAC_EC: Error Checking - no correction
250 * @EDAC_SECDED: Single bit error correction, Double detection
251 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
252 * @EDAC_S4ECD4ED: Chipkill x4 devices
253 * @EDAC_S8ECD8ED: Chipkill x8 devices
254 * @EDAC_S16ECD16ED: Chipkill x16 devices
255 */
256enum edac_type {
257 EDAC_UNKNOWN = 0,
258 EDAC_NONE,
259 EDAC_RESERVED,
260 EDAC_PARITY,
261 EDAC_EC,
262 EDAC_SECDED,
263 EDAC_S2ECD2ED,
264 EDAC_S4ECD4ED,
265 EDAC_S8ECD8ED,
266 EDAC_S16ECD16ED,
267};
268
269#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
270#define EDAC_FLAG_NONE BIT(EDAC_NONE)
271#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
272#define EDAC_FLAG_EC BIT(EDAC_EC)
273#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
274#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
275#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
276#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
277#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
278
279/**
280 * enum scrub_type - scrubbing capabilities
281 * @SCRUB_UNKNOWN: Unknown if scrubber is available
282 * @SCRUB_NONE: No scrubber
283 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
284 * @SCRUB_SW_SRC: Software scrub only errors
285 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
286 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
287 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
288 * @SCRUB_HW_SRC: Hardware scrub only errors
289 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
290 * @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
291 */
292enum scrub_type {
293 SCRUB_UNKNOWN = 0,
294 SCRUB_NONE,
295 SCRUB_SW_PROG,
296 SCRUB_SW_SRC,
297 SCRUB_SW_PROG_SRC,
298 SCRUB_SW_TUNABLE,
299 SCRUB_HW_PROG,
300 SCRUB_HW_SRC,
301 SCRUB_HW_PROG_SRC,
302 SCRUB_HW_TUNABLE
303};
304
305#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
306#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
307#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
308#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
309#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
310#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
311#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
312#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
313
314/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
315
316/* EDAC internal operation states */
317#define OP_ALLOC 0x100
318#define OP_RUNNING_POLL 0x201
319#define OP_RUNNING_INTERRUPT 0x202
320#define OP_RUNNING_POLL_INTR 0x203
321#define OP_OFFLINE 0x300
322
323/**
324 * enum edac_mc_layer_type - memory controller hierarchy layer
325 *
326 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
327 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
328 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
329 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
330 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
331 * as a single memory area. This is used when
332 * retrieving errors from a firmware driven driver.
333 *
334 * This enum is used by the drivers to tell edac_mc_sysfs what name should
335 * be used when describing a memory stick location.
336 */
337enum edac_mc_layer_type {
338 EDAC_MC_LAYER_BRANCH,
339 EDAC_MC_LAYER_CHANNEL,
340 EDAC_MC_LAYER_SLOT,
341 EDAC_MC_LAYER_CHIP_SELECT,
342 EDAC_MC_LAYER_ALL_MEM,
343};
344
345/**
346 * struct edac_mc_layer - describes the memory controller hierarchy
347 * @type: layer type
348 * @size: number of components per layer. For example,
349 * if the channel layer has two channels, size = 2
350 * @is_virt_csrow: This layer is part of the "csrow" when old API
351 * compatibility mode is enabled. Otherwise, it is
352 * a channel
353 */
354struct edac_mc_layer {
355 enum edac_mc_layer_type type;
356 unsigned size;
357 bool is_virt_csrow;
358};
359
360/*
361 * Maximum number of layers used by the memory controller to uniquely
362 * identify a single memory stick.
363 * NOTE: Changing this constant requires not only to change the constant
364 * below, but also to change the existing code at the core, as there are
365 * some code there that are optimized for 3 layers.
366 */
367#define EDAC_MAX_LAYERS 3
368
369struct dimm_info {
370 struct device dev;
371
372 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
373
374 /* Memory location data */
375 unsigned int location[EDAC_MAX_LAYERS];
376
377 struct mem_ctl_info *mci; /* the parent */
378 unsigned int idx; /* index within the parent dimm array */
379
380 u32 grain; /* granularity of reported error in bytes */
381 enum dev_type dtype; /* memory device type */
382 enum mem_type mtype; /* memory dimm type */
383 enum edac_type edac_mode; /* EDAC mode for this dimm */
384
385 u32 nr_pages; /* number of pages on this dimm */
386
387 unsigned int csrow, cschannel; /* Points to the old API data */
388
389 u16 smbios_handle; /* Handle for SMBIOS type 17 */
390
391 u32 ce_count;
392 u32 ue_count;
393};
394
395/**
396 * struct rank_info - contains the information for one DIMM rank
397 *
398 * @chan_idx: channel number where the rank is (typically, 0 or 1)
399 * @ce_count: number of correctable errors for this rank
400 * @csrow: A pointer to the chip select row structure (the parent
401 * structure). The location of the rank is given by
402 * the (csrow->csrow_idx, chan_idx) vector.
403 * @dimm: A pointer to the DIMM structure, where the DIMM label
404 * information is stored.
405 *
406 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
407 * This is a bad assumption, but it makes this patch easier. Later
408 * patches in this series will fix this issue.
409 */
410struct rank_info {
411 int chan_idx;
412 struct csrow_info *csrow;
413 struct dimm_info *dimm;
414
415 u32 ce_count; /* Correctable Errors for this csrow */
416};
417
418struct csrow_info {
419 struct device dev;
420
421 /* Used only by edac_mc_find_csrow_by_page() */
422 unsigned long first_page; /* first page number in csrow */
423 unsigned long last_page; /* last page number in csrow */
424 unsigned long page_mask; /* used for interleaving -
425 * 0UL for non intlv */
426
427 int csrow_idx; /* the chip-select row */
428
429 u32 ue_count; /* Uncorrectable Errors for this csrow */
430 u32 ce_count; /* Correctable Errors for this csrow */
431
432 struct mem_ctl_info *mci; /* the parent */
433
434 /* channel information for this csrow */
435 u32 nr_channels;
436 struct rank_info **channels;
437};
438
439/*
440 * struct errcount_attribute - used to store the several error counts
441 */
442struct errcount_attribute_data {
443 int n_layers;
444 int pos[EDAC_MAX_LAYERS];
445 int layer0, layer1, layer2;
446};
447
448/**
449 * struct edac_raw_error_desc - Raw error report structure
450 * @grain: minimum granularity for an error report, in bytes
451 * @error_count: number of errors of the same type
452 * @type: severity of the error (CE/UE/Fatal)
453 * @top_layer: top layer of the error (layer[0])
454 * @mid_layer: middle layer of the error (layer[1])
455 * @low_layer: low layer of the error (layer[2])
456 * @page_frame_number: page where the error happened
457 * @offset_in_page: page offset
458 * @syndrome: syndrome of the error (or 0 if unknown or if
459 * the syndrome is not applicable)
460 * @msg: error message
461 * @location: location of the error
462 * @label: label of the affected DIMM(s)
463 * @other_detail: other driver-specific detail about the error
464 */
465struct edac_raw_error_desc {
466 char location[LOCATION_SIZE];
467 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
468 long grain;
469
470 u16 error_count;
471 enum hw_event_mc_err_type type;
472 int top_layer;
473 int mid_layer;
474 int low_layer;
475 unsigned long page_frame_number;
476 unsigned long offset_in_page;
477 unsigned long syndrome;
478 const char *msg;
479 const char *other_detail;
480};
481
482/* MEMORY controller information structure
483 */
484struct mem_ctl_info {
485 struct device dev;
486 struct bus_type *bus;
487
488 struct list_head link; /* for global list of mem_ctl_info structs */
489
490 struct module *owner; /* Module owner of this control struct */
491
492 unsigned long mtype_cap; /* memory types supported by mc */
493 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
494 unsigned long edac_cap; /* configuration capabilities - this is
495 * closely related to edac_ctl_cap. The
496 * difference is that the controller may be
497 * capable of s4ecd4ed which would be listed
498 * in edac_ctl_cap, but if channels aren't
499 * capable of s4ecd4ed then the edac_cap would
500 * not have that capability.
501 */
502 unsigned long scrub_cap; /* chipset scrub capabilities */
503 enum scrub_type scrub_mode; /* current scrub mode */
504
505 /* Translates sdram memory scrub rate given in bytes/sec to the
506 internal representation and configures whatever else needs
507 to be configured.
508 */
509 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
510
511 /* Get the current sdram memory scrub rate from the internal
512 representation and converts it to the closest matching
513 bandwidth in bytes/sec.
514 */
515 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
516
517
518 /* pointer to edac checking routine */
519 void (*edac_check) (struct mem_ctl_info * mci);
520
521 /*
522 * Remaps memory pages: controller pages to physical pages.
523 * For most MC's, this will be NULL.
524 */
525 /* FIXME - why not send the phys page to begin with? */
526 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
527 unsigned long page);
528 int mc_idx;
529 struct csrow_info **csrows;
530 unsigned int nr_csrows, num_cschannel;
531
532 /*
533 * Memory Controller hierarchy
534 *
535 * There are basically two types of memory controller: the ones that
536 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
537 * All old memory controllers enumerate memories per rank, but most
538 * of the recent drivers enumerate memories per DIMM, instead.
539 * When the memory controller is per rank, csbased is true.
540 */
541 unsigned int n_layers;
542 struct edac_mc_layer *layers;
543 bool csbased;
544
545 /*
546 * DIMM info. Will eventually remove the entire csrows_info some day
547 */
548 unsigned int tot_dimms;
549 struct dimm_info **dimms;
550
551 /*
552 * FIXME - what about controllers on other busses? - IDs must be
553 * unique. dev pointer should be sufficiently unique, but
554 * BUS:SLOT.FUNC numbers may not be unique.
555 */
556 struct device *pdev;
557 const char *mod_name;
558 const char *ctl_name;
559 const char *dev_name;
560 void *pvt_info;
561 unsigned long start_time; /* mci load start time (in jiffies) */
562
563 /*
564 * drivers shouldn't access those fields directly, as the core
565 * already handles that.
566 */
567 u32 ce_noinfo_count, ue_noinfo_count;
568 u32 ue_mc, ce_mc;
569
570 struct completion complete;
571
572 /* Additional top controller level attributes, but specified
573 * by the low level driver.
574 *
575 * Set by the low level driver to provide attributes at the
576 * controller level.
577 * An array of structures, NULL terminated
578 *
579 * If attributes are desired, then set to array of attributes
580 * If no attributes are desired, leave NULL
581 */
582 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
583
584 /* work struct for this MC */
585 struct delayed_work work;
586
587 /*
588 * Used to report an error - by being at the global struct
589 * makes the memory allocated by the EDAC core
590 */
591 struct edac_raw_error_desc error_desc;
592
593 /* the internal state of this controller instance */
594 int op_state;
595
596 struct dentry *debugfs;
597 u8 fake_inject_layer[EDAC_MAX_LAYERS];
598 bool fake_inject_ue;
599 u16 fake_inject_count;
600};
601
602#define mci_for_each_dimm(mci, dimm) \
603 for ((dimm) = (mci)->dimms[0]; \
604 (dimm); \
605 (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \
606 ? (mci)->dimms[(dimm)->idx + 1] \
607 : NULL)
608
609/**
610 * edac_get_dimm - Get DIMM info from a memory controller given by
611 * [layer0,layer1,layer2] position
612 *
613 * @mci: MC descriptor struct mem_ctl_info
614 * @layer0: layer0 position
615 * @layer1: layer1 position. Unused if n_layers < 2
616 * @layer2: layer2 position. Unused if n_layers < 3
617 *
618 * For 1 layer, this function returns "dimms[layer0]";
619 *
620 * For 2 layers, this function is similar to allocating a two-dimensional
621 * array and returning "dimms[layer0][layer1]";
622 *
623 * For 3 layers, this function is similar to allocating a tri-dimensional
624 * array and returning "dimms[layer0][layer1][layer2]";
625 */
626static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci,
627 int layer0, int layer1, int layer2)
628{
629 int index;
630
631 if (layer0 < 0
632 || (mci->n_layers > 1 && layer1 < 0)
633 || (mci->n_layers > 2 && layer2 < 0))
634 return NULL;
635
636 index = layer0;
637
638 if (mci->n_layers > 1)
639 index = index * mci->layers[1].size + layer1;
640
641 if (mci->n_layers > 2)
642 index = index * mci->layers[2].size + layer2;
643
644 if (index < 0 || index >= mci->tot_dimms)
645 return NULL;
646
647 if (WARN_ON_ONCE(mci->dimms[index]->idx != index))
648 return NULL;
649
650 return mci->dimms[index];
651}
652#endif /* _LINUX_EDAC_H_ */
1/*
2 * Generic EDAC defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12#ifndef _LINUX_EDAC_H_
13#define _LINUX_EDAC_H_
14
15#include <linux/atomic.h>
16#include <linux/device.h>
17#include <linux/completion.h>
18#include <linux/workqueue.h>
19#include <linux/debugfs.h>
20
21struct device;
22
23#define EDAC_OPSTATE_INVAL -1
24#define EDAC_OPSTATE_POLL 0
25#define EDAC_OPSTATE_NMI 1
26#define EDAC_OPSTATE_INT 2
27
28extern int edac_op_state;
29extern int edac_err_assert;
30extern atomic_t edac_handlers;
31extern struct bus_type edac_subsys;
32
33extern int edac_handler_set(void);
34extern void edac_atomic_assert_error(void);
35extern struct bus_type *edac_get_sysfs_subsys(void);
36extern void edac_put_sysfs_subsys(void);
37
38enum {
39 EDAC_REPORTING_ENABLED,
40 EDAC_REPORTING_DISABLED,
41 EDAC_REPORTING_FORCE
42};
43
44extern int edac_report_status;
45#ifdef CONFIG_EDAC
46static inline int get_edac_report_status(void)
47{
48 return edac_report_status;
49}
50
51static inline void set_edac_report_status(int new)
52{
53 edac_report_status = new;
54}
55#else
56static inline int get_edac_report_status(void)
57{
58 return EDAC_REPORTING_DISABLED;
59}
60
61static inline void set_edac_report_status(int new)
62{
63}
64#endif
65
66static inline void opstate_init(void)
67{
68 switch (edac_op_state) {
69 case EDAC_OPSTATE_POLL:
70 case EDAC_OPSTATE_NMI:
71 break;
72 default:
73 edac_op_state = EDAC_OPSTATE_POLL;
74 }
75 return;
76}
77
78/* Max length of a DIMM label*/
79#define EDAC_MC_LABEL_LEN 31
80
81/* Maximum size of the location string */
82#define LOCATION_SIZE 256
83
84/* Defines the maximum number of labels that can be reported */
85#define EDAC_MAX_LABELS 8
86
87/* String used to join two or more labels */
88#define OTHER_LABEL " or "
89
90/**
91 * enum dev_type - describe the type of memory DRAM chips used at the stick
92 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
93 * @DEV_X1: 1 bit for data
94 * @DEV_X2: 2 bits for data
95 * @DEV_X4: 4 bits for data
96 * @DEV_X8: 8 bits for data
97 * @DEV_X16: 16 bits for data
98 * @DEV_X32: 32 bits for data
99 * @DEV_X64: 64 bits for data
100 *
101 * Typical values are x4 and x8.
102 */
103enum dev_type {
104 DEV_UNKNOWN = 0,
105 DEV_X1,
106 DEV_X2,
107 DEV_X4,
108 DEV_X8,
109 DEV_X16,
110 DEV_X32, /* Do these parts exist? */
111 DEV_X64 /* Do these parts exist? */
112};
113
114#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
115#define DEV_FLAG_X1 BIT(DEV_X1)
116#define DEV_FLAG_X2 BIT(DEV_X2)
117#define DEV_FLAG_X4 BIT(DEV_X4)
118#define DEV_FLAG_X8 BIT(DEV_X8)
119#define DEV_FLAG_X16 BIT(DEV_X16)
120#define DEV_FLAG_X32 BIT(DEV_X32)
121#define DEV_FLAG_X64 BIT(DEV_X64)
122
123/**
124 * enum hw_event_mc_err_type - type of the detected error
125 *
126 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
127 * corrected error was detected
128 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
129 * can't be corrected by ECC, but it is not
130 * fatal (maybe it is on an unused memory area,
131 * or the memory controller could recover from
132 * it for example, by re-trying the operation).
133 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
134 * be recovered.
135 */
136enum hw_event_mc_err_type {
137 HW_EVENT_ERR_CORRECTED,
138 HW_EVENT_ERR_UNCORRECTED,
139 HW_EVENT_ERR_FATAL,
140 HW_EVENT_ERR_INFO,
141};
142
143static inline char *mc_event_error_type(const unsigned int err_type)
144{
145 switch (err_type) {
146 case HW_EVENT_ERR_CORRECTED:
147 return "Corrected";
148 case HW_EVENT_ERR_UNCORRECTED:
149 return "Uncorrected";
150 case HW_EVENT_ERR_FATAL:
151 return "Fatal";
152 default:
153 case HW_EVENT_ERR_INFO:
154 return "Info";
155 }
156}
157
158/**
159 * enum mem_type - memory types. For a more detailed reference, please see
160 * http://en.wikipedia.org/wiki/DRAM
161 *
162 * @MEM_EMPTY Empty csrow
163 * @MEM_RESERVED: Reserved csrow type
164 * @MEM_UNKNOWN: Unknown csrow type
165 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
166 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
167 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
168 * @MEM_SDR: SDR - Single data rate SDRAM
169 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
170 * They use 3 pins for chip select: Pins 0 and 2 are
171 * for rank 0; pins 1 and 3 are for rank 1, if the memory
172 * is dual-rank.
173 * @MEM_RDR: Registered SDR SDRAM
174 * @MEM_DDR: Double data rate SDRAM
175 * http://en.wikipedia.org/wiki/DDR_SDRAM
176 * @MEM_RDDR: Registered Double data rate SDRAM
177 * This is a variant of the DDR memories.
178 * A registered memory has a buffer inside it, hiding
179 * part of the memory details to the memory controller.
180 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
181 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
182 * Those memories are labed as "PC2-" instead of "PC" to
183 * differenciate from DDR.
184 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
185 * and JESD206.
186 * Those memories are accessed per DIMM slot, and not by
187 * a chip select signal.
188 * @MEM_RDDR2: Registered DDR2 RAM
189 * This is a variant of the DDR2 memories.
190 * @MEM_XDR: Rambus XDR
191 * It is an evolution of the original RAMBUS memories,
192 * created to compete with DDR2. Weren't used on any
193 * x86 arch, but cell_edac PPC memory controller uses it.
194 * @MEM_DDR3: DDR3 RAM
195 * @MEM_RDDR3: Registered DDR3 RAM
196 * This is a variant of the DDR3 memories.
197 */
198enum mem_type {
199 MEM_EMPTY = 0,
200 MEM_RESERVED,
201 MEM_UNKNOWN,
202 MEM_FPM,
203 MEM_EDO,
204 MEM_BEDO,
205 MEM_SDR,
206 MEM_RDR,
207 MEM_DDR,
208 MEM_RDDR,
209 MEM_RMBS,
210 MEM_DDR2,
211 MEM_FB_DDR2,
212 MEM_RDDR2,
213 MEM_XDR,
214 MEM_DDR3,
215 MEM_RDDR3,
216};
217
218#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
219#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
220#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
221#define MEM_FLAG_FPM BIT(MEM_FPM)
222#define MEM_FLAG_EDO BIT(MEM_EDO)
223#define MEM_FLAG_BEDO BIT(MEM_BEDO)
224#define MEM_FLAG_SDR BIT(MEM_SDR)
225#define MEM_FLAG_RDR BIT(MEM_RDR)
226#define MEM_FLAG_DDR BIT(MEM_DDR)
227#define MEM_FLAG_RDDR BIT(MEM_RDDR)
228#define MEM_FLAG_RMBS BIT(MEM_RMBS)
229#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
230#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
231#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
232#define MEM_FLAG_XDR BIT(MEM_XDR)
233#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
234#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
235
236/**
237 * enum edac-type - Error Detection and Correction capabilities and mode
238 * @EDAC_UNKNOWN: Unknown if ECC is available
239 * @EDAC_NONE: Doesn't support ECC
240 * @EDAC_RESERVED: Reserved ECC type
241 * @EDAC_PARITY: Detects parity errors
242 * @EDAC_EC: Error Checking - no correction
243 * @EDAC_SECDED: Single bit error correction, Double detection
244 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
245 * @EDAC_S4ECD4ED: Chipkill x4 devices
246 * @EDAC_S8ECD8ED: Chipkill x8 devices
247 * @EDAC_S16ECD16ED: Chipkill x16 devices
248 */
249enum edac_type {
250 EDAC_UNKNOWN = 0,
251 EDAC_NONE,
252 EDAC_RESERVED,
253 EDAC_PARITY,
254 EDAC_EC,
255 EDAC_SECDED,
256 EDAC_S2ECD2ED,
257 EDAC_S4ECD4ED,
258 EDAC_S8ECD8ED,
259 EDAC_S16ECD16ED,
260};
261
262#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
263#define EDAC_FLAG_NONE BIT(EDAC_NONE)
264#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
265#define EDAC_FLAG_EC BIT(EDAC_EC)
266#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
267#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
268#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
269#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
270#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
271
272/**
273 * enum scrub_type - scrubbing capabilities
274 * @SCRUB_UNKNOWN Unknown if scrubber is available
275 * @SCRUB_NONE: No scrubber
276 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
277 * @SCRUB_SW_SRC: Software scrub only errors
278 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
279 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
280 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
281 * @SCRUB_HW_SRC: Hardware scrub only errors
282 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
283 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
284 */
285enum scrub_type {
286 SCRUB_UNKNOWN = 0,
287 SCRUB_NONE,
288 SCRUB_SW_PROG,
289 SCRUB_SW_SRC,
290 SCRUB_SW_PROG_SRC,
291 SCRUB_SW_TUNABLE,
292 SCRUB_HW_PROG,
293 SCRUB_HW_SRC,
294 SCRUB_HW_PROG_SRC,
295 SCRUB_HW_TUNABLE
296};
297
298#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
299#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
300#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
301#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
302#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
303#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
304#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
305#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
306
307/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
308
309/* EDAC internal operation states */
310#define OP_ALLOC 0x100
311#define OP_RUNNING_POLL 0x201
312#define OP_RUNNING_INTERRUPT 0x202
313#define OP_RUNNING_POLL_INTR 0x203
314#define OP_OFFLINE 0x300
315
316/*
317 * Concepts used at the EDAC subsystem
318 *
319 * There are several things to be aware of that aren't at all obvious:
320 *
321 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
322 *
323 * These are some of the many terms that are thrown about that don't always
324 * mean what people think they mean (Inconceivable!). In the interest of
325 * creating a common ground for discussion, terms and their definitions
326 * will be established.
327 *
328 * Memory devices: The individual DRAM chips on a memory stick. These
329 * devices commonly output 4 and 8 bits each (x4, x8).
330 * Grouping several of these in parallel provides the
331 * number of bits that the memory controller expects:
332 * typically 72 bits, in order to provide 64 bits +
333 * 8 bits of ECC data.
334 *
335 * Memory Stick: A printed circuit board that aggregates multiple
336 * memory devices in parallel. In general, this is the
337 * Field Replaceable Unit (FRU) which gets replaced, in
338 * the case of excessive errors. Most often it is also
339 * called DIMM (Dual Inline Memory Module).
340 *
341 * Memory Socket: A physical connector on the motherboard that accepts
342 * a single memory stick. Also called as "slot" on several
343 * datasheets.
344 *
345 * Channel: A memory controller channel, responsible to communicate
346 * with a group of DIMMs. Each channel has its own
347 * independent control (command) and data bus, and can
348 * be used independently or grouped with other channels.
349 *
350 * Branch: It is typically the highest hierarchy on a
351 * Fully-Buffered DIMM memory controller.
352 * Typically, it contains two channels.
353 * Two channels at the same branch can be used in single
354 * mode or in lockstep mode.
355 * When lockstep is enabled, the cacheline is doubled,
356 * but it generally brings some performance penalty.
357 * Also, it is generally not possible to point to just one
358 * memory stick when an error occurs, as the error
359 * correction code is calculated using two DIMMs instead
360 * of one. Due to that, it is capable of correcting more
361 * errors than on single mode.
362 *
363 * Single-channel: The data accessed by the memory controller is contained
364 * into one dimm only. E. g. if the data is 64 bits-wide,
365 * the data flows to the CPU using one 64 bits parallel
366 * access.
367 * Typically used with SDR, DDR, DDR2 and DDR3 memories.
368 * FB-DIMM and RAMBUS use a different concept for channel,
369 * so this concept doesn't apply there.
370 *
371 * Double-channel: The data size accessed by the memory controller is
372 * interlaced into two dimms, accessed at the same time.
373 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
374 * the data flows to the CPU using a 128 bits parallel
375 * access.
376 *
377 * Chip-select row: This is the name of the DRAM signal used to select the
378 * DRAM ranks to be accessed. Common chip-select rows for
379 * single channel are 64 bits, for dual channel 128 bits.
380 * It may not be visible by the memory controller, as some
381 * DIMM types have a memory buffer that can hide direct
382 * access to it from the Memory Controller.
383 *
384 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
385 * Motherboards commonly drive two chip-select pins to
386 * a memory stick. A single-ranked stick, will occupy
387 * only one of those rows. The other will be unused.
388 *
389 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
390 * access different sets of memory devices. The two
391 * rows cannot be accessed concurrently.
392 *
393 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
394 * A double-sided stick has two chip-select rows which
395 * access different sets of memory devices. The two
396 * rows cannot be accessed concurrently. "Double-sided"
397 * is irrespective of the memory devices being mounted
398 * on both sides of the memory stick.
399 *
400 * Socket set: All of the memory sticks that are required for
401 * a single memory access or all of the memory sticks
402 * spanned by a chip-select row. A single socket set
403 * has two chip-select rows and if double-sided sticks
404 * are used these will occupy those chip-select rows.
405 *
406 * Bank: This term is avoided because it is unclear when
407 * needing to distinguish between chip-select rows and
408 * socket sets.
409 *
410 * Controller pages:
411 *
412 * Physical pages:
413 *
414 * Virtual pages:
415 *
416 *
417 * STRUCTURE ORGANIZATION AND CHOICES
418 *
419 *
420 *
421 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
422 */
423
424/**
425 * enum edac_mc_layer - memory controller hierarchy layer
426 *
427 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
428 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
429 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
430 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
431 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
432 * as a single memory area. This is used when
433 * retrieving errors from a firmware driven driver.
434 *
435 * This enum is used by the drivers to tell edac_mc_sysfs what name should
436 * be used when describing a memory stick location.
437 */
438enum edac_mc_layer_type {
439 EDAC_MC_LAYER_BRANCH,
440 EDAC_MC_LAYER_CHANNEL,
441 EDAC_MC_LAYER_SLOT,
442 EDAC_MC_LAYER_CHIP_SELECT,
443 EDAC_MC_LAYER_ALL_MEM,
444};
445
446/**
447 * struct edac_mc_layer - describes the memory controller hierarchy
448 * @layer: layer type
449 * @size: number of components per layer. For example,
450 * if the channel layer has two channels, size = 2
451 * @is_virt_csrow: This layer is part of the "csrow" when old API
452 * compatibility mode is enabled. Otherwise, it is
453 * a channel
454 */
455struct edac_mc_layer {
456 enum edac_mc_layer_type type;
457 unsigned size;
458 bool is_virt_csrow;
459};
460
461/*
462 * Maximum number of layers used by the memory controller to uniquely
463 * identify a single memory stick.
464 * NOTE: Changing this constant requires not only to change the constant
465 * below, but also to change the existing code at the core, as there are
466 * some code there that are optimized for 3 layers.
467 */
468#define EDAC_MAX_LAYERS 3
469
470/**
471 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array
472 * for the element given by [layer0,layer1,layer2] position
473 *
474 * @layers: a struct edac_mc_layer array, describing how many elements
475 * were allocated for each layer
476 * @n_layers: Number of layers at the @layers array
477 * @layer0: layer0 position
478 * @layer1: layer1 position. Unused if n_layers < 2
479 * @layer2: layer2 position. Unused if n_layers < 3
480 *
481 * For 1 layer, this macro returns &var[layer0] - &var
482 * For 2 layers, this macro is similar to allocate a bi-dimensional array
483 * and to return "&var[layer0][layer1] - &var"
484 * For 3 layers, this macro is similar to allocate a tri-dimensional array
485 * and to return "&var[layer0][layer1][layer2] - &var"
486 *
487 * A loop could be used here to make it more generic, but, as we only have
488 * 3 layers, this is a little faster.
489 * By design, layers can never be 0 or more than 3. If that ever happens,
490 * a NULL is returned, causing an OOPS during the memory allocation routine,
491 * with would point to the developer that he's doing something wrong.
492 */
493#define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
494 int __i; \
495 if ((nlayers) == 1) \
496 __i = layer0; \
497 else if ((nlayers) == 2) \
498 __i = (layer1) + ((layers[1]).size * (layer0)); \
499 else if ((nlayers) == 3) \
500 __i = (layer2) + ((layers[2]).size * ((layer1) + \
501 ((layers[1]).size * (layer0)))); \
502 else \
503 __i = -EINVAL; \
504 __i; \
505})
506
507/**
508 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
509 * for the element given by [layer0,layer1,layer2] position
510 *
511 * @layers: a struct edac_mc_layer array, describing how many elements
512 * were allocated for each layer
513 * @var: name of the var where we want to get the pointer
514 * (like mci->dimms)
515 * @n_layers: Number of layers at the @layers array
516 * @layer0: layer0 position
517 * @layer1: layer1 position. Unused if n_layers < 2
518 * @layer2: layer2 position. Unused if n_layers < 3
519 *
520 * For 1 layer, this macro returns &var[layer0]
521 * For 2 layers, this macro is similar to allocate a bi-dimensional array
522 * and to return "&var[layer0][layer1]"
523 * For 3 layers, this macro is similar to allocate a tri-dimensional array
524 * and to return "&var[layer0][layer1][layer2]"
525 */
526#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
527 typeof(*var) __p; \
528 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
529 if (___i < 0) \
530 __p = NULL; \
531 else \
532 __p = (var)[___i]; \
533 __p; \
534})
535
536struct dimm_info {
537 struct device dev;
538
539 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
540
541 /* Memory location data */
542 unsigned location[EDAC_MAX_LAYERS];
543
544 struct mem_ctl_info *mci; /* the parent */
545
546 u32 grain; /* granularity of reported error in bytes */
547 enum dev_type dtype; /* memory device type */
548 enum mem_type mtype; /* memory dimm type */
549 enum edac_type edac_mode; /* EDAC mode for this dimm */
550
551 u32 nr_pages; /* number of pages on this dimm */
552
553 unsigned csrow, cschannel; /* Points to the old API data */
554};
555
556/**
557 * struct rank_info - contains the information for one DIMM rank
558 *
559 * @chan_idx: channel number where the rank is (typically, 0 or 1)
560 * @ce_count: number of correctable errors for this rank
561 * @csrow: A pointer to the chip select row structure (the parent
562 * structure). The location of the rank is given by
563 * the (csrow->csrow_idx, chan_idx) vector.
564 * @dimm: A pointer to the DIMM structure, where the DIMM label
565 * information is stored.
566 *
567 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
568 * This is a bad assumption, but it makes this patch easier. Later
569 * patches in this series will fix this issue.
570 */
571struct rank_info {
572 int chan_idx;
573 struct csrow_info *csrow;
574 struct dimm_info *dimm;
575
576 u32 ce_count; /* Correctable Errors for this csrow */
577};
578
579struct csrow_info {
580 struct device dev;
581
582 /* Used only by edac_mc_find_csrow_by_page() */
583 unsigned long first_page; /* first page number in csrow */
584 unsigned long last_page; /* last page number in csrow */
585 unsigned long page_mask; /* used for interleaving -
586 * 0UL for non intlv */
587
588 int csrow_idx; /* the chip-select row */
589
590 u32 ue_count; /* Uncorrectable Errors for this csrow */
591 u32 ce_count; /* Correctable Errors for this csrow */
592
593 struct mem_ctl_info *mci; /* the parent */
594
595 /* channel information for this csrow */
596 u32 nr_channels;
597 struct rank_info **channels;
598};
599
600/*
601 * struct errcount_attribute - used to store the several error counts
602 */
603struct errcount_attribute_data {
604 int n_layers;
605 int pos[EDAC_MAX_LAYERS];
606 int layer0, layer1, layer2;
607};
608
609/**
610 * edac_raw_error_desc - Raw error report structure
611 * @grain: minimum granularity for an error report, in bytes
612 * @error_count: number of errors of the same type
613 * @top_layer: top layer of the error (layer[0])
614 * @mid_layer: middle layer of the error (layer[1])
615 * @low_layer: low layer of the error (layer[2])
616 * @page_frame_number: page where the error happened
617 * @offset_in_page: page offset
618 * @syndrome: syndrome of the error (or 0 if unknown or if
619 * the syndrome is not applicable)
620 * @msg: error message
621 * @location: location of the error
622 * @label: label of the affected DIMM(s)
623 * @other_detail: other driver-specific detail about the error
624 * @enable_per_layer_report: if false, the error affects all layers
625 * (typically, a memory controller error)
626 */
627struct edac_raw_error_desc {
628 /*
629 * NOTE: everything before grain won't be cleaned by
630 * edac_raw_error_desc_clean()
631 */
632 char location[LOCATION_SIZE];
633 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
634 long grain;
635
636 /* the vars below and grain will be cleaned on every new error report */
637 u16 error_count;
638 int top_layer;
639 int mid_layer;
640 int low_layer;
641 unsigned long page_frame_number;
642 unsigned long offset_in_page;
643 unsigned long syndrome;
644 const char *msg;
645 const char *other_detail;
646 bool enable_per_layer_report;
647};
648
649/* MEMORY controller information structure
650 */
651struct mem_ctl_info {
652 struct device dev;
653 struct bus_type *bus;
654
655 struct list_head link; /* for global list of mem_ctl_info structs */
656
657 struct module *owner; /* Module owner of this control struct */
658
659 unsigned long mtype_cap; /* memory types supported by mc */
660 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
661 unsigned long edac_cap; /* configuration capabilities - this is
662 * closely related to edac_ctl_cap. The
663 * difference is that the controller may be
664 * capable of s4ecd4ed which would be listed
665 * in edac_ctl_cap, but if channels aren't
666 * capable of s4ecd4ed then the edac_cap would
667 * not have that capability.
668 */
669 unsigned long scrub_cap; /* chipset scrub capabilities */
670 enum scrub_type scrub_mode; /* current scrub mode */
671
672 /* Translates sdram memory scrub rate given in bytes/sec to the
673 internal representation and configures whatever else needs
674 to be configured.
675 */
676 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
677
678 /* Get the current sdram memory scrub rate from the internal
679 representation and converts it to the closest matching
680 bandwidth in bytes/sec.
681 */
682 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
683
684
685 /* pointer to edac checking routine */
686 void (*edac_check) (struct mem_ctl_info * mci);
687
688 /*
689 * Remaps memory pages: controller pages to physical pages.
690 * For most MC's, this will be NULL.
691 */
692 /* FIXME - why not send the phys page to begin with? */
693 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
694 unsigned long page);
695 int mc_idx;
696 struct csrow_info **csrows;
697 unsigned nr_csrows, num_cschannel;
698
699 /*
700 * Memory Controller hierarchy
701 *
702 * There are basically two types of memory controller: the ones that
703 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
704 * All old memory controllers enumerate memories per rank, but most
705 * of the recent drivers enumerate memories per DIMM, instead.
706 * When the memory controller is per rank, csbased is true.
707 */
708 unsigned n_layers;
709 struct edac_mc_layer *layers;
710 bool csbased;
711
712 /*
713 * DIMM info. Will eventually remove the entire csrows_info some day
714 */
715 unsigned tot_dimms;
716 struct dimm_info **dimms;
717
718 /*
719 * FIXME - what about controllers on other busses? - IDs must be
720 * unique. dev pointer should be sufficiently unique, but
721 * BUS:SLOT.FUNC numbers may not be unique.
722 */
723 struct device *pdev;
724 const char *mod_name;
725 const char *mod_ver;
726 const char *ctl_name;
727 const char *dev_name;
728 void *pvt_info;
729 unsigned long start_time; /* mci load start time (in jiffies) */
730
731 /*
732 * drivers shouldn't access those fields directly, as the core
733 * already handles that.
734 */
735 u32 ce_noinfo_count, ue_noinfo_count;
736 u32 ue_mc, ce_mc;
737 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
738
739 struct completion complete;
740
741 /* Additional top controller level attributes, but specified
742 * by the low level driver.
743 *
744 * Set by the low level driver to provide attributes at the
745 * controller level.
746 * An array of structures, NULL terminated
747 *
748 * If attributes are desired, then set to array of attributes
749 * If no attributes are desired, leave NULL
750 */
751 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
752
753 /* work struct for this MC */
754 struct delayed_work work;
755
756 /*
757 * Used to report an error - by being at the global struct
758 * makes the memory allocated by the EDAC core
759 */
760 struct edac_raw_error_desc error_desc;
761
762 /* the internal state of this controller instance */
763 int op_state;
764
765#ifdef CONFIG_EDAC_DEBUG
766 struct dentry *debugfs;
767 u8 fake_inject_layer[EDAC_MAX_LAYERS];
768 u32 fake_inject_ue;
769 u16 fake_inject_count;
770#endif
771};
772
773/*
774 * Maximum number of memory controllers in the coherent fabric.
775 */
776#define EDAC_MAX_MCS 16
777
778#endif