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1/*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef __CSIO_HW_CHIP_H__
35#define __CSIO_HW_CHIP_H__
36
37#include "csio_defs.h"
38
39/* Define MACRO values */
40#define CSIO_HW_T5 0x5000
41#define CSIO_T5_FCOE_ASIC 0x5600
42#define CSIO_HW_T6 0x6000
43#define CSIO_T6_FCOE_ASIC 0x6600
44#define CSIO_HW_CHIP_MASK 0xF000
45
46#define T5_REGMAP_SIZE (332 * 1024)
47#define FW_FNAME_T5 "cxgb4/t5fw.bin"
48#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
49#define FW_FNAME_T6 "cxgb4/t6fw.bin"
50#define FW_CFG_NAME_T6 "cxgb4/t6-config.txt"
51
52#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
53#define CHELSIO_CHIP_FPGA 0x100
54#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
55#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
56
57#define CHELSIO_T5 0x5
58#define CHELSIO_T6 0x6
59
60enum chip_type {
61 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
62 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
63 T5_FIRST_REV = T5_A0,
64 T5_LAST_REV = T5_A1,
65
66 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
67 T6_FIRST_REV = T6_A0,
68 T6_LAST_REV = T6_A0,
69};
70
71static inline int csio_is_t5(uint16_t chip)
72{
73 return (chip == CSIO_HW_T5);
74}
75
76static inline int csio_is_t6(uint16_t chip)
77{
78 return (chip == CSIO_HW_T6);
79}
80
81/* Define MACRO DEFINITIONS */
82#define CSIO_DEVICE(devid, idx) \
83 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
84
85#include "t4fw_api.h"
86#include "t4fw_version.h"
87
88#define FW_VERSION(chip) ( \
89 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
90 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
91 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
92 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
93#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
94
95struct fw_info {
96 u8 chip;
97 char *fs_name;
98 char *fw_mod_name;
99 struct fw_hdr fw_hdr;
100};
101
102/* Declare ENUMS */
103enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
104
105enum {
106 MEMWIN_APERTURE = 2048,
107 MEMWIN_BASE = 0x1b800,
108};
109
110/* Slow path handlers */
111struct intr_info {
112 unsigned int mask; /* bits to check in interrupt status */
113 const char *msg; /* message to print or NULL */
114 short stat_idx; /* stat counter to increment or -1 */
115 unsigned short fatal; /* whether the condition reported is fatal */
116};
117
118/* T4/T5 Chip specific ops */
119struct csio_hw;
120struct csio_hw_chip_ops {
121 int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
122 void (*chip_pcie_intr_handler)(struct csio_hw *);
123 uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
124 int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
125 __be32 *, uint64_t *);
126 int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
127 __be32 *, uint64_t *);
128 int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
129 u32, uint32_t *, int);
130 void (*chip_dfs_create_ext_mem)(struct csio_hw *);
131};
132
133extern struct csio_hw_chip_ops t5_ops;
134
135#endif /* #ifndef __CSIO_HW_CHIP_H__ */
1/*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef __CSIO_HW_CHIP_H__
35#define __CSIO_HW_CHIP_H__
36
37#include "csio_defs.h"
38
39/* FCoE device IDs for T4 */
40#define CSIO_DEVID_T440DBG_FCOE 0x4600
41#define CSIO_DEVID_T420CR_FCOE 0x4601
42#define CSIO_DEVID_T422CR_FCOE 0x4602
43#define CSIO_DEVID_T440CR_FCOE 0x4603
44#define CSIO_DEVID_T420BCH_FCOE 0x4604
45#define CSIO_DEVID_T440BCH_FCOE 0x4605
46#define CSIO_DEVID_T440CH_FCOE 0x4606
47#define CSIO_DEVID_T420SO_FCOE 0x4607
48#define CSIO_DEVID_T420CX_FCOE 0x4608
49#define CSIO_DEVID_T420BT_FCOE 0x4609
50#define CSIO_DEVID_T404BT_FCOE 0x460A
51#define CSIO_DEVID_B420_FCOE 0x460B
52#define CSIO_DEVID_B404_FCOE 0x460C
53#define CSIO_DEVID_T480CR_FCOE 0x460D
54#define CSIO_DEVID_T440LPCR_FCOE 0x460E
55#define CSIO_DEVID_AMSTERDAM_T4_FCOE 0x460F
56#define CSIO_DEVID_HUAWEI_T480_FCOE 0x4680
57#define CSIO_DEVID_HUAWEI_T440_FCOE 0x4681
58#define CSIO_DEVID_HUAWEI_STG310_FCOE 0x4682
59#define CSIO_DEVID_ACROMAG_XMC_XAUI 0x4683
60#define CSIO_DEVID_ACROMAG_XMC_SFP_FCOE 0x4684
61#define CSIO_DEVID_QUANTA_MEZZ_SFP_FCOE 0x4685
62#define CSIO_DEVID_HUAWEI_10GT_FCOE 0x4686
63#define CSIO_DEVID_HUAWEI_T440_TOE_FCOE 0x4687
64
65/* FCoE device IDs for T5 */
66#define CSIO_DEVID_T580DBG_FCOE 0x5600
67#define CSIO_DEVID_T520CR_FCOE 0x5601
68#define CSIO_DEVID_T522CR_FCOE 0x5602
69#define CSIO_DEVID_T540CR_FCOE 0x5603
70#define CSIO_DEVID_T520BCH_FCOE 0x5604
71#define CSIO_DEVID_T540BCH_FCOE 0x5605
72#define CSIO_DEVID_T540CH_FCOE 0x5606
73#define CSIO_DEVID_T520SO_FCOE 0x5607
74#define CSIO_DEVID_T520CX_FCOE 0x5608
75#define CSIO_DEVID_T520BT_FCOE 0x5609
76#define CSIO_DEVID_T504BT_FCOE 0x560A
77#define CSIO_DEVID_B520_FCOE 0x560B
78#define CSIO_DEVID_B504_FCOE 0x560C
79#define CSIO_DEVID_T580CR2_FCOE 0x560D
80#define CSIO_DEVID_T540LPCR_FCOE 0x560E
81#define CSIO_DEVID_AMSTERDAM_T5_FCOE 0x560F
82#define CSIO_DEVID_T580LPCR_FCOE 0x5610
83#define CSIO_DEVID_T520LLCR_FCOE 0x5611
84#define CSIO_DEVID_T560CR_FCOE 0x5612
85#define CSIO_DEVID_T580CR_FCOE 0x5613
86
87/* Define MACRO values */
88#define CSIO_HW_T4 0x4000
89#define CSIO_T4_FCOE_ASIC 0x4600
90#define CSIO_HW_T5 0x5000
91#define CSIO_T5_FCOE_ASIC 0x5600
92#define CSIO_HW_CHIP_MASK 0xF000
93#define T4_REGMAP_SIZE (160 * 1024)
94#define T5_REGMAP_SIZE (332 * 1024)
95#define FW_FNAME_T4 "cxgb4/t4fw.bin"
96#define FW_FNAME_T5 "cxgb4/t5fw.bin"
97#define FW_CFG_NAME_T4 "cxgb4/t4-config.txt"
98#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
99
100/* Define static functions */
101static inline int csio_is_t4(uint16_t chip)
102{
103 return (chip == CSIO_HW_T4);
104}
105
106static inline int csio_is_t5(uint16_t chip)
107{
108 return (chip == CSIO_HW_T5);
109}
110
111/* Define MACRO DEFINITIONS */
112#define CSIO_DEVICE(devid, idx) \
113 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
114
115#define CSIO_HW_PIDX(hw, index) \
116 (csio_is_t4(hw->chip_id) ? (PIDX(index)) : \
117 (PIDX_T5(index) | DBTYPE(1U)))
118
119#define CSIO_HW_LP_INT_THRESH(hw, val) \
120 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH(val)) : \
121 (V_LP_INT_THRESH_T5(val)))
122
123#define CSIO_HW_M_LP_INT_THRESH(hw) \
124 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_MASK) : (M_LP_INT_THRESH_T5))
125
126#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
127 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
128 (T5_PORT_REG(port, MAC_PORT_INT_CAUSE)))
129
130#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0)
131#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
132#define FW_VERSION_MICRO(hw) (csio_is_t4(hw->chip_id) ? 8 : 0)
133
134#define CSIO_FW_FNAME(hw) \
135 (csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
136
137#define CSIO_CF_FNAME(hw) \
138 (csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
139
140/* Declare ENUMS */
141enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
142
143enum {
144 MEMWIN_APERTURE = 2048,
145 MEMWIN_BASE = 0x1b800,
146 MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */
147};
148
149/* Slow path handlers */
150struct intr_info {
151 unsigned int mask; /* bits to check in interrupt status */
152 const char *msg; /* message to print or NULL */
153 short stat_idx; /* stat counter to increment or -1 */
154 unsigned short fatal; /* whether the condition reported is fatal */
155};
156
157/* T4/T5 Chip specific ops */
158struct csio_hw;
159struct csio_hw_chip_ops {
160 int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
161 void (*chip_pcie_intr_handler)(struct csio_hw *);
162 uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
163 int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
164 __be32 *, uint64_t *);
165 int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
166 __be32 *, uint64_t *);
167 int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
168 u32, uint32_t *, int);
169 void (*chip_dfs_create_ext_mem)(struct csio_hw *);
170};
171
172extern struct csio_hw_chip_ops t4_ops;
173extern struct csio_hw_chip_ops t5_ops;
174
175#endif /* #ifndef __CSIO_HW_CHIP_H__ */