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1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
30#include <linux/slab.h>
31#include <linux/delay.h>
32#include <linux/hdmi.h>
33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39
40static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
41{
42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
43}
44
45static void
46assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
47{
48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 uint32_t enabled_bits;
51
52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
53
54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
55 "HDMI port enabled, expecting disabled\n");
56}
57
58struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
59{
60 struct intel_digital_port *intel_dig_port =
61 container_of(encoder, struct intel_digital_port, base.base);
62 return &intel_dig_port->hdmi;
63}
64
65static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
66{
67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
68}
69
70static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
71{
72 switch (type) {
73 case HDMI_INFOFRAME_TYPE_AVI:
74 return VIDEO_DIP_SELECT_AVI;
75 case HDMI_INFOFRAME_TYPE_SPD:
76 return VIDEO_DIP_SELECT_SPD;
77 case HDMI_INFOFRAME_TYPE_VENDOR:
78 return VIDEO_DIP_SELECT_VENDOR;
79 default:
80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
81 return 0;
82 }
83}
84
85static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
86{
87 switch (type) {
88 case HDMI_INFOFRAME_TYPE_AVI:
89 return VIDEO_DIP_ENABLE_AVI;
90 case HDMI_INFOFRAME_TYPE_SPD:
91 return VIDEO_DIP_ENABLE_SPD;
92 case HDMI_INFOFRAME_TYPE_VENDOR:
93 return VIDEO_DIP_ENABLE_VENDOR;
94 default:
95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
96 return 0;
97 }
98}
99
100static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
101{
102 switch (type) {
103 case HDMI_INFOFRAME_TYPE_AVI:
104 return VIDEO_DIP_ENABLE_AVI_HSW;
105 case HDMI_INFOFRAME_TYPE_SPD:
106 return VIDEO_DIP_ENABLE_SPD_HSW;
107 case HDMI_INFOFRAME_TYPE_VENDOR:
108 return VIDEO_DIP_ENABLE_VS_HSW;
109 default:
110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
111 return 0;
112 }
113}
114
115static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
116 enum transcoder cpu_transcoder,
117 struct drm_i915_private *dev_priv)
118{
119 switch (type) {
120 case HDMI_INFOFRAME_TYPE_AVI:
121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
122 case HDMI_INFOFRAME_TYPE_SPD:
123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
124 case HDMI_INFOFRAME_TYPE_VENDOR:
125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
126 default:
127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
128 return 0;
129 }
130}
131
132static void g4x_write_infoframe(struct drm_encoder *encoder,
133 enum hdmi_infoframe_type type,
134 const void *frame, ssize_t len)
135{
136 const uint32_t *data = frame;
137 struct drm_device *dev = encoder->dev;
138 struct drm_i915_private *dev_priv = dev->dev_private;
139 u32 val = I915_READ(VIDEO_DIP_CTL);
140 int i;
141
142 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
143
144 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
145 val |= g4x_infoframe_index(type);
146
147 val &= ~g4x_infoframe_enable(type);
148
149 I915_WRITE(VIDEO_DIP_CTL, val);
150
151 mmiowb();
152 for (i = 0; i < len; i += 4) {
153 I915_WRITE(VIDEO_DIP_DATA, *data);
154 data++;
155 }
156 /* Write every possible data byte to force correct ECC calculation. */
157 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
158 I915_WRITE(VIDEO_DIP_DATA, 0);
159 mmiowb();
160
161 val |= g4x_infoframe_enable(type);
162 val &= ~VIDEO_DIP_FREQ_MASK;
163 val |= VIDEO_DIP_FREQ_VSYNC;
164
165 I915_WRITE(VIDEO_DIP_CTL, val);
166 POSTING_READ(VIDEO_DIP_CTL);
167}
168
169static void ibx_write_infoframe(struct drm_encoder *encoder,
170 enum hdmi_infoframe_type type,
171 const void *frame, ssize_t len)
172{
173 const uint32_t *data = frame;
174 struct drm_device *dev = encoder->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
177 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
178 u32 val = I915_READ(reg);
179
180 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
181
182 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
183 val |= g4x_infoframe_index(type);
184
185 val &= ~g4x_infoframe_enable(type);
186
187 I915_WRITE(reg, val);
188
189 mmiowb();
190 for (i = 0; i < len; i += 4) {
191 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
192 data++;
193 }
194 /* Write every possible data byte to force correct ECC calculation. */
195 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
197 mmiowb();
198
199 val |= g4x_infoframe_enable(type);
200 val &= ~VIDEO_DIP_FREQ_MASK;
201 val |= VIDEO_DIP_FREQ_VSYNC;
202
203 I915_WRITE(reg, val);
204 POSTING_READ(reg);
205}
206
207static void cpt_write_infoframe(struct drm_encoder *encoder,
208 enum hdmi_infoframe_type type,
209 const void *frame, ssize_t len)
210{
211 const uint32_t *data = frame;
212 struct drm_device *dev = encoder->dev;
213 struct drm_i915_private *dev_priv = dev->dev_private;
214 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
215 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
216 u32 val = I915_READ(reg);
217
218 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
219
220 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
221 val |= g4x_infoframe_index(type);
222
223 /* The DIP control register spec says that we need to update the AVI
224 * infoframe without clearing its enable bit */
225 if (type != HDMI_INFOFRAME_TYPE_AVI)
226 val &= ~g4x_infoframe_enable(type);
227
228 I915_WRITE(reg, val);
229
230 mmiowb();
231 for (i = 0; i < len; i += 4) {
232 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
233 data++;
234 }
235 /* Write every possible data byte to force correct ECC calculation. */
236 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
238 mmiowb();
239
240 val |= g4x_infoframe_enable(type);
241 val &= ~VIDEO_DIP_FREQ_MASK;
242 val |= VIDEO_DIP_FREQ_VSYNC;
243
244 I915_WRITE(reg, val);
245 POSTING_READ(reg);
246}
247
248static void vlv_write_infoframe(struct drm_encoder *encoder,
249 enum hdmi_infoframe_type type,
250 const void *frame, ssize_t len)
251{
252 const uint32_t *data = frame;
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
256 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
257 u32 val = I915_READ(reg);
258
259 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
260
261 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
262 val |= g4x_infoframe_index(type);
263
264 val &= ~g4x_infoframe_enable(type);
265
266 I915_WRITE(reg, val);
267
268 mmiowb();
269 for (i = 0; i < len; i += 4) {
270 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
271 data++;
272 }
273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
275 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
276 mmiowb();
277
278 val |= g4x_infoframe_enable(type);
279 val &= ~VIDEO_DIP_FREQ_MASK;
280 val |= VIDEO_DIP_FREQ_VSYNC;
281
282 I915_WRITE(reg, val);
283 POSTING_READ(reg);
284}
285
286static void hsw_write_infoframe(struct drm_encoder *encoder,
287 enum hdmi_infoframe_type type,
288 const void *frame, ssize_t len)
289{
290 const uint32_t *data = frame;
291 struct drm_device *dev = encoder->dev;
292 struct drm_i915_private *dev_priv = dev->dev_private;
293 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
294 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
295 u32 data_reg;
296 int i;
297 u32 val = I915_READ(ctl_reg);
298
299 data_reg = hsw_infoframe_data_reg(type,
300 intel_crtc->config.cpu_transcoder,
301 dev_priv);
302 if (data_reg == 0)
303 return;
304
305 val &= ~hsw_infoframe_enable(type);
306 I915_WRITE(ctl_reg, val);
307
308 mmiowb();
309 for (i = 0; i < len; i += 4) {
310 I915_WRITE(data_reg + i, *data);
311 data++;
312 }
313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
315 I915_WRITE(data_reg + i, 0);
316 mmiowb();
317
318 val |= hsw_infoframe_enable(type);
319 I915_WRITE(ctl_reg, val);
320 POSTING_READ(ctl_reg);
321}
322
323/*
324 * The data we write to the DIP data buffer registers is 1 byte bigger than the
325 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
326 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
327 * used for both technologies.
328 *
329 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
330 * DW1: DB3 | DB2 | DB1 | DB0
331 * DW2: DB7 | DB6 | DB5 | DB4
332 * DW3: ...
333 *
334 * (HB is Header Byte, DB is Data Byte)
335 *
336 * The hdmi pack() functions don't know about that hardware specific hole so we
337 * trick them by giving an offset into the buffer and moving back the header
338 * bytes by one.
339 */
340static void intel_write_infoframe(struct drm_encoder *encoder,
341 union hdmi_infoframe *frame)
342{
343 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
344 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
345 ssize_t len;
346
347 /* see comment above for the reason for this offset */
348 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
349 if (len < 0)
350 return;
351
352 /* Insert the 'hole' (see big comment above) at position 3 */
353 buffer[0] = buffer[1];
354 buffer[1] = buffer[2];
355 buffer[2] = buffer[3];
356 buffer[3] = 0;
357 len++;
358
359 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
360}
361
362static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
363 struct drm_display_mode *adjusted_mode)
364{
365 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
366 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
367 union hdmi_infoframe frame;
368 int ret;
369
370 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
371 adjusted_mode);
372 if (ret < 0) {
373 DRM_ERROR("couldn't fill AVI infoframe\n");
374 return;
375 }
376
377 if (intel_hdmi->rgb_quant_range_selectable) {
378 if (intel_crtc->config.limited_color_range)
379 frame.avi.quantization_range =
380 HDMI_QUANTIZATION_RANGE_LIMITED;
381 else
382 frame.avi.quantization_range =
383 HDMI_QUANTIZATION_RANGE_FULL;
384 }
385
386 intel_write_infoframe(encoder, &frame);
387}
388
389static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
390{
391 union hdmi_infoframe frame;
392 int ret;
393
394 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
395 if (ret < 0) {
396 DRM_ERROR("couldn't fill SPD infoframe\n");
397 return;
398 }
399
400 frame.spd.sdi = HDMI_SPD_SDI_PC;
401
402 intel_write_infoframe(encoder, &frame);
403}
404
405static void
406intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
407 struct drm_display_mode *adjusted_mode)
408{
409 union hdmi_infoframe frame;
410 int ret;
411
412 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
413 adjusted_mode);
414 if (ret < 0)
415 return;
416
417 intel_write_infoframe(encoder, &frame);
418}
419
420static void g4x_set_infoframes(struct drm_encoder *encoder,
421 struct drm_display_mode *adjusted_mode)
422{
423 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
424 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
425 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
426 u32 reg = VIDEO_DIP_CTL;
427 u32 val = I915_READ(reg);
428 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
429
430 assert_hdmi_port_disabled(intel_hdmi);
431
432 /* If the registers were not initialized yet, they might be zeroes,
433 * which means we're selecting the AVI DIP and we're setting its
434 * frequency to once. This seems to really confuse the HW and make
435 * things stop working (the register spec says the AVI always needs to
436 * be sent every VSync). So here we avoid writing to the register more
437 * than we need and also explicitly select the AVI DIP and explicitly
438 * set its frequency to every VSync. Avoiding to write it twice seems to
439 * be enough to solve the problem, but being defensive shouldn't hurt us
440 * either. */
441 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
442
443 if (!intel_hdmi->has_hdmi_sink) {
444 if (!(val & VIDEO_DIP_ENABLE))
445 return;
446 val &= ~VIDEO_DIP_ENABLE;
447 I915_WRITE(reg, val);
448 POSTING_READ(reg);
449 return;
450 }
451
452 if (port != (val & VIDEO_DIP_PORT_MASK)) {
453 if (val & VIDEO_DIP_ENABLE) {
454 val &= ~VIDEO_DIP_ENABLE;
455 I915_WRITE(reg, val);
456 POSTING_READ(reg);
457 }
458 val &= ~VIDEO_DIP_PORT_MASK;
459 val |= port;
460 }
461
462 val |= VIDEO_DIP_ENABLE;
463 val &= ~VIDEO_DIP_ENABLE_VENDOR;
464
465 I915_WRITE(reg, val);
466 POSTING_READ(reg);
467
468 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
469 intel_hdmi_set_spd_infoframe(encoder);
470 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
471}
472
473static void ibx_set_infoframes(struct drm_encoder *encoder,
474 struct drm_display_mode *adjusted_mode)
475{
476 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
477 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
478 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
479 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
480 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
481 u32 val = I915_READ(reg);
482 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
483
484 assert_hdmi_port_disabled(intel_hdmi);
485
486 /* See the big comment in g4x_set_infoframes() */
487 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
488
489 if (!intel_hdmi->has_hdmi_sink) {
490 if (!(val & VIDEO_DIP_ENABLE))
491 return;
492 val &= ~VIDEO_DIP_ENABLE;
493 I915_WRITE(reg, val);
494 POSTING_READ(reg);
495 return;
496 }
497
498 if (port != (val & VIDEO_DIP_PORT_MASK)) {
499 if (val & VIDEO_DIP_ENABLE) {
500 val &= ~VIDEO_DIP_ENABLE;
501 I915_WRITE(reg, val);
502 POSTING_READ(reg);
503 }
504 val &= ~VIDEO_DIP_PORT_MASK;
505 val |= port;
506 }
507
508 val |= VIDEO_DIP_ENABLE;
509 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
510 VIDEO_DIP_ENABLE_GCP);
511
512 I915_WRITE(reg, val);
513 POSTING_READ(reg);
514
515 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
516 intel_hdmi_set_spd_infoframe(encoder);
517 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
518}
519
520static void cpt_set_infoframes(struct drm_encoder *encoder,
521 struct drm_display_mode *adjusted_mode)
522{
523 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
524 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
525 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
526 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
527 u32 val = I915_READ(reg);
528
529 assert_hdmi_port_disabled(intel_hdmi);
530
531 /* See the big comment in g4x_set_infoframes() */
532 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
533
534 if (!intel_hdmi->has_hdmi_sink) {
535 if (!(val & VIDEO_DIP_ENABLE))
536 return;
537 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
538 I915_WRITE(reg, val);
539 POSTING_READ(reg);
540 return;
541 }
542
543 /* Set both together, unset both together: see the spec. */
544 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
545 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
546 VIDEO_DIP_ENABLE_GCP);
547
548 I915_WRITE(reg, val);
549 POSTING_READ(reg);
550
551 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
552 intel_hdmi_set_spd_infoframe(encoder);
553 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
554}
555
556static void vlv_set_infoframes(struct drm_encoder *encoder,
557 struct drm_display_mode *adjusted_mode)
558{
559 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
560 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
561 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
562 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
563 u32 val = I915_READ(reg);
564
565 assert_hdmi_port_disabled(intel_hdmi);
566
567 /* See the big comment in g4x_set_infoframes() */
568 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
569
570 if (!intel_hdmi->has_hdmi_sink) {
571 if (!(val & VIDEO_DIP_ENABLE))
572 return;
573 val &= ~VIDEO_DIP_ENABLE;
574 I915_WRITE(reg, val);
575 POSTING_READ(reg);
576 return;
577 }
578
579 val |= VIDEO_DIP_ENABLE;
580 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
581 VIDEO_DIP_ENABLE_GCP);
582
583 I915_WRITE(reg, val);
584 POSTING_READ(reg);
585
586 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
587 intel_hdmi_set_spd_infoframe(encoder);
588 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
589}
590
591static void hsw_set_infoframes(struct drm_encoder *encoder,
592 struct drm_display_mode *adjusted_mode)
593{
594 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
595 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
596 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
597 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
598 u32 val = I915_READ(reg);
599
600 assert_hdmi_port_disabled(intel_hdmi);
601
602 if (!intel_hdmi->has_hdmi_sink) {
603 I915_WRITE(reg, 0);
604 POSTING_READ(reg);
605 return;
606 }
607
608 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
609 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
610
611 I915_WRITE(reg, val);
612 POSTING_READ(reg);
613
614 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
615 intel_hdmi_set_spd_infoframe(encoder);
616 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
617}
618
619static void intel_hdmi_mode_set(struct intel_encoder *encoder)
620{
621 struct drm_device *dev = encoder->base.dev;
622 struct drm_i915_private *dev_priv = dev->dev_private;
623 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
624 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
625 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
626 u32 hdmi_val;
627
628 hdmi_val = SDVO_ENCODING_HDMI;
629 if (!HAS_PCH_SPLIT(dev))
630 hdmi_val |= intel_hdmi->color_range;
631 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
632 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
633 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
634 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
635
636 if (crtc->config.pipe_bpp > 24)
637 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
638 else
639 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
640
641 /* Required on CPT */
642 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
643 hdmi_val |= HDMI_MODE_SELECT_HDMI;
644
645 if (intel_hdmi->has_audio) {
646 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
647 pipe_name(crtc->pipe));
648 hdmi_val |= SDVO_AUDIO_ENABLE;
649 hdmi_val |= HDMI_MODE_SELECT_HDMI;
650 intel_write_eld(&encoder->base, adjusted_mode);
651 }
652
653 if (HAS_PCH_CPT(dev))
654 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
655 else
656 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
657
658 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
659 POSTING_READ(intel_hdmi->hdmi_reg);
660
661 intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
662}
663
664static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
665 enum pipe *pipe)
666{
667 struct drm_device *dev = encoder->base.dev;
668 struct drm_i915_private *dev_priv = dev->dev_private;
669 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
670 enum intel_display_power_domain power_domain;
671 u32 tmp;
672
673 power_domain = intel_display_port_power_domain(encoder);
674 if (!intel_display_power_enabled(dev_priv, power_domain))
675 return false;
676
677 tmp = I915_READ(intel_hdmi->hdmi_reg);
678
679 if (!(tmp & SDVO_ENABLE))
680 return false;
681
682 if (HAS_PCH_CPT(dev))
683 *pipe = PORT_TO_PIPE_CPT(tmp);
684 else
685 *pipe = PORT_TO_PIPE(tmp);
686
687 return true;
688}
689
690static void intel_hdmi_get_config(struct intel_encoder *encoder,
691 struct intel_crtc_config *pipe_config)
692{
693 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
694 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
695 u32 tmp, flags = 0;
696 int dotclock;
697
698 tmp = I915_READ(intel_hdmi->hdmi_reg);
699
700 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
701 flags |= DRM_MODE_FLAG_PHSYNC;
702 else
703 flags |= DRM_MODE_FLAG_NHSYNC;
704
705 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
706 flags |= DRM_MODE_FLAG_PVSYNC;
707 else
708 flags |= DRM_MODE_FLAG_NVSYNC;
709
710 pipe_config->adjusted_mode.flags |= flags;
711
712 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
713 dotclock = pipe_config->port_clock * 2 / 3;
714 else
715 dotclock = pipe_config->port_clock;
716
717 if (HAS_PCH_SPLIT(dev_priv->dev))
718 ironlake_check_encoder_dotclock(pipe_config, dotclock);
719
720 pipe_config->adjusted_mode.crtc_clock = dotclock;
721}
722
723static void intel_enable_hdmi(struct intel_encoder *encoder)
724{
725 struct drm_device *dev = encoder->base.dev;
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
728 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
729 u32 temp;
730 u32 enable_bits = SDVO_ENABLE;
731
732 if (intel_hdmi->has_audio)
733 enable_bits |= SDVO_AUDIO_ENABLE;
734
735 temp = I915_READ(intel_hdmi->hdmi_reg);
736
737 /* HW workaround for IBX, we need to move the port to transcoder A
738 * before disabling it, so restore the transcoder select bit here. */
739 if (HAS_PCH_IBX(dev))
740 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
741
742 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
743 * we do this anyway which shows more stable in testing.
744 */
745 if (HAS_PCH_SPLIT(dev)) {
746 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
747 POSTING_READ(intel_hdmi->hdmi_reg);
748 }
749
750 temp |= enable_bits;
751
752 I915_WRITE(intel_hdmi->hdmi_reg, temp);
753 POSTING_READ(intel_hdmi->hdmi_reg);
754
755 /* HW workaround, need to write this twice for issue that may result
756 * in first write getting masked.
757 */
758 if (HAS_PCH_SPLIT(dev)) {
759 I915_WRITE(intel_hdmi->hdmi_reg, temp);
760 POSTING_READ(intel_hdmi->hdmi_reg);
761 }
762}
763
764static void vlv_enable_hdmi(struct intel_encoder *encoder)
765{
766}
767
768static void intel_disable_hdmi(struct intel_encoder *encoder)
769{
770 struct drm_device *dev = encoder->base.dev;
771 struct drm_i915_private *dev_priv = dev->dev_private;
772 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
773 u32 temp;
774 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
775
776 temp = I915_READ(intel_hdmi->hdmi_reg);
777
778 /* HW workaround for IBX, we need to move the port to transcoder A
779 * before disabling it. */
780 if (HAS_PCH_IBX(dev)) {
781 struct drm_crtc *crtc = encoder->base.crtc;
782 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
783
784 if (temp & SDVO_PIPE_B_SELECT) {
785 temp &= ~SDVO_PIPE_B_SELECT;
786 I915_WRITE(intel_hdmi->hdmi_reg, temp);
787 POSTING_READ(intel_hdmi->hdmi_reg);
788
789 /* Again we need to write this twice. */
790 I915_WRITE(intel_hdmi->hdmi_reg, temp);
791 POSTING_READ(intel_hdmi->hdmi_reg);
792
793 /* Transcoder selection bits only update
794 * effectively on vblank. */
795 if (crtc)
796 intel_wait_for_vblank(dev, pipe);
797 else
798 msleep(50);
799 }
800 }
801
802 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
803 * we do this anyway which shows more stable in testing.
804 */
805 if (HAS_PCH_SPLIT(dev)) {
806 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
807 POSTING_READ(intel_hdmi->hdmi_reg);
808 }
809
810 temp &= ~enable_bits;
811
812 I915_WRITE(intel_hdmi->hdmi_reg, temp);
813 POSTING_READ(intel_hdmi->hdmi_reg);
814
815 /* HW workaround, need to write this twice for issue that may result
816 * in first write getting masked.
817 */
818 if (HAS_PCH_SPLIT(dev)) {
819 I915_WRITE(intel_hdmi->hdmi_reg, temp);
820 POSTING_READ(intel_hdmi->hdmi_reg);
821 }
822}
823
824static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
825{
826 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
827
828 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
829 return 165000;
830 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
831 return 300000;
832 else
833 return 225000;
834}
835
836static enum drm_mode_status
837intel_hdmi_mode_valid(struct drm_connector *connector,
838 struct drm_display_mode *mode)
839{
840 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
841 true))
842 return MODE_CLOCK_HIGH;
843 if (mode->clock < 20000)
844 return MODE_CLOCK_LOW;
845
846 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
847 return MODE_NO_DBLESCAN;
848
849 return MODE_OK;
850}
851
852static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
853{
854 struct drm_device *dev = crtc->base.dev;
855 struct intel_encoder *encoder;
856 int count = 0, count_hdmi = 0;
857
858 if (!HAS_PCH_SPLIT(dev))
859 return false;
860
861 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
862 if (encoder->new_crtc != crtc)
863 continue;
864
865 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
866 count++;
867 }
868
869 /*
870 * HDMI 12bpc affects the clocks, so it's only possible
871 * when not cloning with other encoder types.
872 */
873 return count_hdmi > 0 && count_hdmi == count;
874}
875
876bool intel_hdmi_compute_config(struct intel_encoder *encoder,
877 struct intel_crtc_config *pipe_config)
878{
879 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
880 struct drm_device *dev = encoder->base.dev;
881 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
882 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
883 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
884 int desired_bpp;
885
886 if (intel_hdmi->color_range_auto) {
887 /* See CEA-861-E - 5.1 Default Encoding Parameters */
888 if (intel_hdmi->has_hdmi_sink &&
889 drm_match_cea_mode(adjusted_mode) > 1)
890 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
891 else
892 intel_hdmi->color_range = 0;
893 }
894
895 if (intel_hdmi->color_range)
896 pipe_config->limited_color_range = true;
897
898 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
899 pipe_config->has_pch_encoder = true;
900
901 /*
902 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
903 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
904 * outputs. We also need to check that the higher clock still fits
905 * within limits.
906 */
907 if (pipe_config->pipe_bpp > 8*3 && intel_hdmi->has_hdmi_sink &&
908 clock_12bpc <= portclock_limit &&
909 hdmi_12bpc_possible(encoder->new_crtc)) {
910 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
911 desired_bpp = 12*3;
912
913 /* Need to adjust the port link by 1.5x for 12bpc. */
914 pipe_config->port_clock = clock_12bpc;
915 } else {
916 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
917 desired_bpp = 8*3;
918 }
919
920 if (!pipe_config->bw_constrained) {
921 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
922 pipe_config->pipe_bpp = desired_bpp;
923 }
924
925 if (adjusted_mode->crtc_clock > portclock_limit) {
926 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
927 return false;
928 }
929
930 return true;
931}
932
933static enum drm_connector_status
934intel_hdmi_detect(struct drm_connector *connector, bool force)
935{
936 struct drm_device *dev = connector->dev;
937 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
938 struct intel_digital_port *intel_dig_port =
939 hdmi_to_dig_port(intel_hdmi);
940 struct intel_encoder *intel_encoder = &intel_dig_port->base;
941 struct drm_i915_private *dev_priv = dev->dev_private;
942 struct edid *edid;
943 enum intel_display_power_domain power_domain;
944 enum drm_connector_status status = connector_status_disconnected;
945
946 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
947 connector->base.id, drm_get_connector_name(connector));
948
949 power_domain = intel_display_port_power_domain(intel_encoder);
950 intel_display_power_get(dev_priv, power_domain);
951
952 intel_hdmi->has_hdmi_sink = false;
953 intel_hdmi->has_audio = false;
954 intel_hdmi->rgb_quant_range_selectable = false;
955 edid = drm_get_edid(connector,
956 intel_gmbus_get_adapter(dev_priv,
957 intel_hdmi->ddc_bus));
958
959 if (edid) {
960 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
961 status = connector_status_connected;
962 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
963 intel_hdmi->has_hdmi_sink =
964 drm_detect_hdmi_monitor(edid);
965 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
966 intel_hdmi->rgb_quant_range_selectable =
967 drm_rgb_quant_range_selectable(edid);
968 }
969 kfree(edid);
970 }
971
972 if (status == connector_status_connected) {
973 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
974 intel_hdmi->has_audio =
975 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
976 intel_encoder->type = INTEL_OUTPUT_HDMI;
977 }
978
979 intel_display_power_put(dev_priv, power_domain);
980
981 return status;
982}
983
984static int intel_hdmi_get_modes(struct drm_connector *connector)
985{
986 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
987 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
988 struct drm_i915_private *dev_priv = connector->dev->dev_private;
989 enum intel_display_power_domain power_domain;
990 int ret;
991
992 /* We should parse the EDID data and find out if it's an HDMI sink so
993 * we can send audio to it.
994 */
995
996 power_domain = intel_display_port_power_domain(intel_encoder);
997 intel_display_power_get(dev_priv, power_domain);
998
999 ret = intel_ddc_get_modes(connector,
1000 intel_gmbus_get_adapter(dev_priv,
1001 intel_hdmi->ddc_bus));
1002
1003 intel_display_power_put(dev_priv, power_domain);
1004
1005 return ret;
1006}
1007
1008static bool
1009intel_hdmi_detect_audio(struct drm_connector *connector)
1010{
1011 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1012 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1013 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1014 enum intel_display_power_domain power_domain;
1015 struct edid *edid;
1016 bool has_audio = false;
1017
1018 power_domain = intel_display_port_power_domain(intel_encoder);
1019 intel_display_power_get(dev_priv, power_domain);
1020
1021 edid = drm_get_edid(connector,
1022 intel_gmbus_get_adapter(dev_priv,
1023 intel_hdmi->ddc_bus));
1024 if (edid) {
1025 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1026 has_audio = drm_detect_monitor_audio(edid);
1027 kfree(edid);
1028 }
1029
1030 intel_display_power_put(dev_priv, power_domain);
1031
1032 return has_audio;
1033}
1034
1035static int
1036intel_hdmi_set_property(struct drm_connector *connector,
1037 struct drm_property *property,
1038 uint64_t val)
1039{
1040 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1041 struct intel_digital_port *intel_dig_port =
1042 hdmi_to_dig_port(intel_hdmi);
1043 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1044 int ret;
1045
1046 ret = drm_object_property_set_value(&connector->base, property, val);
1047 if (ret)
1048 return ret;
1049
1050 if (property == dev_priv->force_audio_property) {
1051 enum hdmi_force_audio i = val;
1052 bool has_audio;
1053
1054 if (i == intel_hdmi->force_audio)
1055 return 0;
1056
1057 intel_hdmi->force_audio = i;
1058
1059 if (i == HDMI_AUDIO_AUTO)
1060 has_audio = intel_hdmi_detect_audio(connector);
1061 else
1062 has_audio = (i == HDMI_AUDIO_ON);
1063
1064 if (i == HDMI_AUDIO_OFF_DVI)
1065 intel_hdmi->has_hdmi_sink = 0;
1066
1067 intel_hdmi->has_audio = has_audio;
1068 goto done;
1069 }
1070
1071 if (property == dev_priv->broadcast_rgb_property) {
1072 bool old_auto = intel_hdmi->color_range_auto;
1073 uint32_t old_range = intel_hdmi->color_range;
1074
1075 switch (val) {
1076 case INTEL_BROADCAST_RGB_AUTO:
1077 intel_hdmi->color_range_auto = true;
1078 break;
1079 case INTEL_BROADCAST_RGB_FULL:
1080 intel_hdmi->color_range_auto = false;
1081 intel_hdmi->color_range = 0;
1082 break;
1083 case INTEL_BROADCAST_RGB_LIMITED:
1084 intel_hdmi->color_range_auto = false;
1085 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1086 break;
1087 default:
1088 return -EINVAL;
1089 }
1090
1091 if (old_auto == intel_hdmi->color_range_auto &&
1092 old_range == intel_hdmi->color_range)
1093 return 0;
1094
1095 goto done;
1096 }
1097
1098 return -EINVAL;
1099
1100done:
1101 if (intel_dig_port->base.base.crtc)
1102 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1103
1104 return 0;
1105}
1106
1107static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1108{
1109 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1110 struct drm_device *dev = encoder->base.dev;
1111 struct drm_i915_private *dev_priv = dev->dev_private;
1112 struct intel_crtc *intel_crtc =
1113 to_intel_crtc(encoder->base.crtc);
1114 enum dpio_channel port = vlv_dport_to_channel(dport);
1115 int pipe = intel_crtc->pipe;
1116 u32 val;
1117
1118 if (!IS_VALLEYVIEW(dev))
1119 return;
1120
1121 /* Enable clock channels for this port */
1122 mutex_lock(&dev_priv->dpio_lock);
1123 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1124 val = 0;
1125 if (pipe)
1126 val |= (1<<21);
1127 else
1128 val &= ~(1<<21);
1129 val |= 0x001000c4;
1130 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1131
1132 /* HDMI 1.0V-2dB */
1133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1136 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1137 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1138 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1139 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1140 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1141
1142 /* Program lane clock */
1143 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1144 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1145 mutex_unlock(&dev_priv->dpio_lock);
1146
1147 intel_enable_hdmi(encoder);
1148
1149 vlv_wait_port_ready(dev_priv, dport);
1150}
1151
1152static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1153{
1154 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1155 struct drm_device *dev = encoder->base.dev;
1156 struct drm_i915_private *dev_priv = dev->dev_private;
1157 struct intel_crtc *intel_crtc =
1158 to_intel_crtc(encoder->base.crtc);
1159 enum dpio_channel port = vlv_dport_to_channel(dport);
1160 int pipe = intel_crtc->pipe;
1161
1162 if (!IS_VALLEYVIEW(dev))
1163 return;
1164
1165 /* Program Tx lane resets to default */
1166 mutex_lock(&dev_priv->dpio_lock);
1167 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1168 DPIO_PCS_TX_LANE2_RESET |
1169 DPIO_PCS_TX_LANE1_RESET);
1170 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1171 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1172 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1173 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1174 DPIO_PCS_CLK_SOFT_RESET);
1175
1176 /* Fix up inter-pair skew failure */
1177 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1178 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1179 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1180
1181 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1182 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1183 mutex_unlock(&dev_priv->dpio_lock);
1184}
1185
1186static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1187{
1188 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1189 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1190 struct intel_crtc *intel_crtc =
1191 to_intel_crtc(encoder->base.crtc);
1192 enum dpio_channel port = vlv_dport_to_channel(dport);
1193 int pipe = intel_crtc->pipe;
1194
1195 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1196 mutex_lock(&dev_priv->dpio_lock);
1197 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1198 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1199 mutex_unlock(&dev_priv->dpio_lock);
1200}
1201
1202static void intel_hdmi_destroy(struct drm_connector *connector)
1203{
1204 drm_connector_cleanup(connector);
1205 kfree(connector);
1206}
1207
1208static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1209 .dpms = intel_connector_dpms,
1210 .detect = intel_hdmi_detect,
1211 .fill_modes = drm_helper_probe_single_connector_modes,
1212 .set_property = intel_hdmi_set_property,
1213 .destroy = intel_hdmi_destroy,
1214};
1215
1216static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1217 .get_modes = intel_hdmi_get_modes,
1218 .mode_valid = intel_hdmi_mode_valid,
1219 .best_encoder = intel_best_encoder,
1220};
1221
1222static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1223 .destroy = intel_encoder_destroy,
1224};
1225
1226static void
1227intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1228{
1229 intel_attach_force_audio_property(connector);
1230 intel_attach_broadcast_rgb_property(connector);
1231 intel_hdmi->color_range_auto = true;
1232}
1233
1234void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1235 struct intel_connector *intel_connector)
1236{
1237 struct drm_connector *connector = &intel_connector->base;
1238 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1240 struct drm_device *dev = intel_encoder->base.dev;
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 enum port port = intel_dig_port->port;
1243
1244 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1245 DRM_MODE_CONNECTOR_HDMIA);
1246 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1247
1248 connector->interlace_allowed = 1;
1249 connector->doublescan_allowed = 0;
1250 connector->stereo_allowed = 1;
1251
1252 switch (port) {
1253 case PORT_B:
1254 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1255 intel_encoder->hpd_pin = HPD_PORT_B;
1256 break;
1257 case PORT_C:
1258 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1259 intel_encoder->hpd_pin = HPD_PORT_C;
1260 break;
1261 case PORT_D:
1262 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1263 intel_encoder->hpd_pin = HPD_PORT_D;
1264 break;
1265 case PORT_A:
1266 intel_encoder->hpd_pin = HPD_PORT_A;
1267 /* Internal port only for eDP. */
1268 default:
1269 BUG();
1270 }
1271
1272 if (IS_VALLEYVIEW(dev)) {
1273 intel_hdmi->write_infoframe = vlv_write_infoframe;
1274 intel_hdmi->set_infoframes = vlv_set_infoframes;
1275 } else if (!HAS_PCH_SPLIT(dev)) {
1276 intel_hdmi->write_infoframe = g4x_write_infoframe;
1277 intel_hdmi->set_infoframes = g4x_set_infoframes;
1278 } else if (HAS_DDI(dev)) {
1279 intel_hdmi->write_infoframe = hsw_write_infoframe;
1280 intel_hdmi->set_infoframes = hsw_set_infoframes;
1281 } else if (HAS_PCH_IBX(dev)) {
1282 intel_hdmi->write_infoframe = ibx_write_infoframe;
1283 intel_hdmi->set_infoframes = ibx_set_infoframes;
1284 } else {
1285 intel_hdmi->write_infoframe = cpt_write_infoframe;
1286 intel_hdmi->set_infoframes = cpt_set_infoframes;
1287 }
1288
1289 if (HAS_DDI(dev))
1290 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1291 else
1292 intel_connector->get_hw_state = intel_connector_get_hw_state;
1293 intel_connector->unregister = intel_connector_unregister;
1294
1295 intel_hdmi_add_properties(intel_hdmi, connector);
1296
1297 intel_connector_attach_encoder(intel_connector, intel_encoder);
1298 drm_sysfs_connector_add(connector);
1299
1300 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1301 * 0xd. Failure to do so will result in spurious interrupts being
1302 * generated on the port when a cable is not attached.
1303 */
1304 if (IS_G4X(dev) && !IS_GM45(dev)) {
1305 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1306 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1307 }
1308}
1309
1310void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1311{
1312 struct intel_digital_port *intel_dig_port;
1313 struct intel_encoder *intel_encoder;
1314 struct intel_connector *intel_connector;
1315
1316 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1317 if (!intel_dig_port)
1318 return;
1319
1320 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1321 if (!intel_connector) {
1322 kfree(intel_dig_port);
1323 return;
1324 }
1325
1326 intel_encoder = &intel_dig_port->base;
1327
1328 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1329 DRM_MODE_ENCODER_TMDS);
1330
1331 intel_encoder->compute_config = intel_hdmi_compute_config;
1332 intel_encoder->mode_set = intel_hdmi_mode_set;
1333 intel_encoder->disable = intel_disable_hdmi;
1334 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1335 intel_encoder->get_config = intel_hdmi_get_config;
1336 if (IS_VALLEYVIEW(dev)) {
1337 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1338 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1339 intel_encoder->enable = vlv_enable_hdmi;
1340 intel_encoder->post_disable = vlv_hdmi_post_disable;
1341 } else {
1342 intel_encoder->enable = intel_enable_hdmi;
1343 }
1344
1345 intel_encoder->type = INTEL_OUTPUT_HDMI;
1346 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1347 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1348 /*
1349 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1350 * to work on real hardware. And since g4x can send infoframes to
1351 * only one port anyway, nothing is lost by allowing it.
1352 */
1353 if (IS_G4X(dev))
1354 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1355
1356 intel_dig_port->port = port;
1357 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1358 intel_dig_port->dp.output_reg = 0;
1359
1360 intel_hdmi_init_connector(intel_dig_port, intel_connector);
1361}