1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
  4 *
  5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
  7 */
  8
  9#include <linux/bitfield.h>
 10#include <linux/clk.h>
 11#include <linux/delay.h>
 12#include <linux/module.h>
 13#include <linux/of_platform.h>
 14#include <linux/pinctrl/consumer.h>
 15#include <linux/reset.h>
 16
 17#include <sound/dmaengine_pcm.h>
 18#include <sound/core.h>
 19
 20#include "stm32_sai.h"
 21
 22static const struct stm32_sai_conf stm32_sai_conf_f4 = {
 23	.version = STM_SAI_STM32F4,
 24	.fifo_size = 8,
 25	.has_spdif_pdm = false,
 26};
 27
 28/*
 29 * Default settings for stm32 H7 socs and next.
 30 * These default settings will be overridden if the soc provides
 31 * support of hardware configuration registers.
 32 */
 33static const struct stm32_sai_conf stm32_sai_conf_h7 = {
 34	.version = STM_SAI_STM32H7,
 35	.fifo_size = 8,
 36	.has_spdif_pdm = true,
 37};
 38
 39static const struct of_device_id stm32_sai_ids[] = {
 40	{ .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
 41	{ .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
 42	{}
 43};
 44
 45static int stm32_sai_pclk_disable(struct device *dev)
 46{
 47	struct stm32_sai_data *sai = dev_get_drvdata(dev);
 48
 49	clk_disable_unprepare(sai->pclk);
 50
 51	return 0;
 52}
 53
 54static int stm32_sai_pclk_enable(struct device *dev)
 55{
 56	struct stm32_sai_data *sai = dev_get_drvdata(dev);
 57	int ret;
 58
 59	ret = clk_prepare_enable(sai->pclk);
 60	if (ret) {
 61		dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
 62		return ret;
 63	}
 64
 65	return 0;
 66}
 67
 68static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
 69{
 70	int ret;
 71
 72	/* Enable peripheral clock to allow GCR register access */
 73	ret = stm32_sai_pclk_enable(&sai->pdev->dev);
 74	if (ret)
 75		return ret;
 76
 77	writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
 78
 79	stm32_sai_pclk_disable(&sai->pdev->dev);
 80
 81	return 0;
 82}
 83
 84static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
 85{
 86	u32 prev_synco;
 87	int ret;
 88
 89	/* Enable peripheral clock to allow GCR register access */
 90	ret = stm32_sai_pclk_enable(&sai->pdev->dev);
 91	if (ret)
 92		return ret;
 93
 94	dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
 95		sai->pdev->dev.of_node,
 96		synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
 97
 98	prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
 99	if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
100		dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
101			sai->pdev->dev.of_node,
102			prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
103		stm32_sai_pclk_disable(&sai->pdev->dev);
104		return -EINVAL;
105	}
106
107	writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
108
109	stm32_sai_pclk_disable(&sai->pdev->dev);
110
111	return 0;
112}
113
114static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
115			      struct device_node *np_provider,
116			      int synco, int synci)
117{
118	struct platform_device *pdev = of_find_device_by_node(np_provider);
119	struct stm32_sai_data *sai_provider;
120	int ret;
121
122	if (!pdev) {
123		dev_err(&sai_client->pdev->dev,
124			"Device not found for node %pOFn\n", np_provider);
125		of_node_put(np_provider);
126		return -ENODEV;
127	}
128
129	sai_provider = platform_get_drvdata(pdev);
130	if (!sai_provider) {
131		dev_err(&sai_client->pdev->dev,
132			"SAI sync provider data not found\n");
133		ret = -EINVAL;
134		goto error;
135	}
136
137	/* Configure sync client */
138	ret = stm32_sai_sync_conf_client(sai_client, synci);
139	if (ret < 0)
140		goto error;
141
142	/* Configure sync provider */
143	ret = stm32_sai_sync_conf_provider(sai_provider, synco);
144
145error:
146	put_device(&pdev->dev);
147	of_node_put(np_provider);
148	return ret;
149}
150
151static int stm32_sai_probe(struct platform_device *pdev)
152{
153	struct stm32_sai_data *sai;
154	struct reset_control *rst;
155	const struct of_device_id *of_id;
156	u32 val;
157	int ret;
158
159	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
160	if (!sai)
161		return -ENOMEM;
162
163	sai->base = devm_platform_ioremap_resource(pdev, 0);
164	if (IS_ERR(sai->base))
165		return PTR_ERR(sai->base);
166
167	of_id = of_match_device(stm32_sai_ids, &pdev->dev);
168	if (of_id)
169		memcpy(&sai->conf, (const struct stm32_sai_conf *)of_id->data,
170		       sizeof(struct stm32_sai_conf));
171	else
172		return -EINVAL;
173
174	if (!STM_SAI_IS_F4(sai)) {
175		sai->pclk = devm_clk_get(&pdev->dev, "pclk");
176		if (IS_ERR(sai->pclk)) {
177			if (PTR_ERR(sai->pclk) != -EPROBE_DEFER)
178				dev_err(&pdev->dev, "missing bus clock pclk: %ld\n",
179					PTR_ERR(sai->pclk));
180			return PTR_ERR(sai->pclk);
181		}
182	}
183
184	sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
185	if (IS_ERR(sai->clk_x8k)) {
186		if (PTR_ERR(sai->clk_x8k) != -EPROBE_DEFER)
187			dev_err(&pdev->dev, "missing x8k parent clock: %ld\n",
188				PTR_ERR(sai->clk_x8k));
189		return PTR_ERR(sai->clk_x8k);
190	}
191
192	sai->clk_x11k = devm_clk_get(&pdev->dev, "x11k");
193	if (IS_ERR(sai->clk_x11k)) {
194		if (PTR_ERR(sai->clk_x11k) != -EPROBE_DEFER)
195			dev_err(&pdev->dev, "missing x11k parent clock: %ld\n",
196				PTR_ERR(sai->clk_x11k));
197		return PTR_ERR(sai->clk_x11k);
198	}
199
200	/* init irqs */
201	sai->irq = platform_get_irq(pdev, 0);
202	if (sai->irq < 0)
203		return sai->irq;
204
205	/* reset */
206	rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
207	if (IS_ERR(rst)) {
208		if (PTR_ERR(rst) != -EPROBE_DEFER)
209			dev_err(&pdev->dev, "Reset controller error %ld\n",
210				PTR_ERR(rst));
211		return PTR_ERR(rst);
212	}
213	reset_control_assert(rst);
214	udelay(2);
215	reset_control_deassert(rst);
216
217	/* Enable peripheral clock to allow register access */
218	ret = clk_prepare_enable(sai->pclk);
219	if (ret) {
220		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
221		return ret;
222	}
223
224	val = FIELD_GET(SAI_IDR_ID_MASK,
225			readl_relaxed(sai->base + STM_SAI_IDR));
226	if (val == SAI_IPIDR_NUMBER) {
227		val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
228		sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
229		sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
230						      val);
231
232		val = readl_relaxed(sai->base + STM_SAI_VERR);
233		sai->conf.version = val;
234
235		dev_dbg(&pdev->dev, "SAI version: %lu.%lu registered\n",
236			FIELD_GET(SAI_VERR_MAJ_MASK, val),
237			FIELD_GET(SAI_VERR_MIN_MASK, val));
238	}
239	clk_disable_unprepare(sai->pclk);
240
241	sai->pdev = pdev;
242	sai->set_sync = &stm32_sai_set_sync;
243	platform_set_drvdata(pdev, sai);
244
245	return devm_of_platform_populate(&pdev->dev);
246}
247
248#ifdef CONFIG_PM_SLEEP
249/*
250 * When pins are shared by two sai sub instances, pins have to be defined
251 * in sai parent node. In this case, pins state is not managed by alsa fw.
252 * These pins are managed in suspend/resume callbacks.
253 */
254static int stm32_sai_suspend(struct device *dev)
255{
256	struct stm32_sai_data *sai = dev_get_drvdata(dev);
257	int ret;
258
259	ret = stm32_sai_pclk_enable(dev);
260	if (ret)
261		return ret;
262
263	sai->gcr = readl_relaxed(sai->base);
264	stm32_sai_pclk_disable(dev);
265
266	return pinctrl_pm_select_sleep_state(dev);
267}
268
269static int stm32_sai_resume(struct device *dev)
270{
271	struct stm32_sai_data *sai = dev_get_drvdata(dev);
272	int ret;
273
274	ret = stm32_sai_pclk_enable(dev);
275	if (ret)
276		return ret;
277
278	writel_relaxed(sai->gcr, sai->base);
279	stm32_sai_pclk_disable(dev);
280
281	return pinctrl_pm_select_default_state(dev);
282}
283#endif /* CONFIG_PM_SLEEP */
284
285static const struct dev_pm_ops stm32_sai_pm_ops = {
286	SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_suspend, stm32_sai_resume)
287};
288
289MODULE_DEVICE_TABLE(of, stm32_sai_ids);
290
291static struct platform_driver stm32_sai_driver = {
292	.driver = {
293		.name = "st,stm32-sai",
294		.of_match_table = stm32_sai_ids,
295		.pm = &stm32_sai_pm_ops,
296	},
297	.probe = stm32_sai_probe,
298};
299
300module_platform_driver(stm32_sai_driver);
301
302MODULE_DESCRIPTION("STM32 Soc SAI Interface");
303MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
304MODULE_ALIAS("platform:st,stm32-sai");
305MODULE_LICENSE("GPL v2");