1/*
   2 * Copyright © 2008 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 * Authors:
  24 *    Keith Packard <keithp@keithp.com>
  25 *
  26 */
  27
  28#include <linux/export.h>
  29#include <linux/i2c.h>
  30#include <linux/notifier.h>
  31#include <linux/slab.h>
  32#include <linux/types.h>
  33
  34#include <asm/byteorder.h>
  35
  36#include <drm/drm_atomic_helper.h>
  37#include <drm/drm_crtc.h>
  38#include <drm/drm_dp_helper.h>
  39#include <drm/drm_edid.h>
  40#include <drm/drm_probe_helper.h>
  41
  42#include "g4x_dp.h"
  43#include "i915_debugfs.h"
  44#include "i915_drv.h"
  45#include "intel_atomic.h"
  46#include "intel_audio.h"
  47#include "intel_connector.h"
  48#include "intel_ddi.h"
  49#include "intel_de.h"
  50#include "intel_display_types.h"
  51#include "intel_dp.h"
  52#include "intel_dp_aux.h"
  53#include "intel_dp_hdcp.h"
  54#include "intel_dp_link_training.h"
  55#include "intel_dp_mst.h"
  56#include "intel_dpio_phy.h"
  57#include "intel_dpll.h"
  58#include "intel_fifo_underrun.h"
  59#include "intel_hdcp.h"
  60#include "intel_hdmi.h"
  61#include "intel_hotplug.h"
  62#include "intel_lspcon.h"
  63#include "intel_lvds.h"
  64#include "intel_panel.h"
  65#include "intel_pps.h"
  66#include "intel_psr.h"
  67#include "intel_sideband.h"
  68#include "intel_tc.h"
  69#include "intel_vdsc.h"
  70#include "intel_vrr.h"
  71
  72#define DP_DPRX_ESI_LEN 14
  73
  74/* DP DSC throughput values used for slice count calculations KPixels/s */
  75#define DP_DSC_PEAK_PIXEL_RATE			2720000
  76#define DP_DSC_MAX_ENC_THROUGHPUT_0		340000
  77#define DP_DSC_MAX_ENC_THROUGHPUT_1		400000
  78
  79/* DP DSC FEC Overhead factor = 1/(0.972261) */
  80#define DP_DSC_FEC_OVERHEAD_FACTOR		972261
  81
  82/* Compliance test status bits  */
  83#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
  84#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  85#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  86#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  87
  88
  89/* Constants for DP DSC configurations */
  90static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  91
  92/* With Single pipe configuration, HW is capable of supporting maximum
  93 * of 4 slices per line.
  94 */
  95static const u8 valid_dsc_slicecount[] = {1, 2, 4};
  96
  97/**
  98 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  99 * @intel_dp: DP struct
 100 *
 101 * If a CPU or PCH DP output is attached to an eDP panel, this function
 102 * will return true, and false otherwise.
 103 */
 104bool intel_dp_is_edp(struct intel_dp *intel_dp)
 105{
 106	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 107
 108	return dig_port->base.type == INTEL_OUTPUT_EDP;
 109}
 110
 111static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 112static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 113
 114/* update sink rates from dpcd */
 115static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 116{
 117	static const int dp_rates[] = {
 118		162000, 270000, 540000, 810000
 119	};
 120	int i, max_rate;
 121	int max_lttpr_rate;
 122
 123	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 124		/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 125		static const int quirk_rates[] = { 162000, 270000, 324000 };
 126
 127		memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 128		intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 129
 130		return;
 131	}
 132
 133	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 134	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 135	if (max_lttpr_rate)
 136		max_rate = min(max_rate, max_lttpr_rate);
 137
 138	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 139		if (dp_rates[i] > max_rate)
 140			break;
 141		intel_dp->sink_rates[i] = dp_rates[i];
 142	}
 143
 144	intel_dp->num_sink_rates = i;
 145}
 146
 147/* Get length of rates array potentially limited by max_rate. */
 148static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 149{
 150	int i;
 151
 152	/* Limit results by potentially reduced max rate */
 153	for (i = 0; i < len; i++) {
 154		if (rates[len - i - 1] <= max_rate)
 155			return len - i;
 156	}
 157
 158	return 0;
 159}
 160
 161/* Get length of common rates array potentially limited by max_rate. */
 162static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 163					  int max_rate)
 164{
 165	return intel_dp_rate_limit_len(intel_dp->common_rates,
 166				       intel_dp->num_common_rates, max_rate);
 167}
 168
 169/* Theoretical max between source and sink */
 170static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 171{
 172	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 173}
 174
 175/* Theoretical max between source and sink */
 176static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 177{
 178	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 179	int source_max = dig_port->max_lanes;
 180	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 181	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 182	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 183
 184	if (lttpr_max)
 185		sink_max = min(sink_max, lttpr_max);
 186
 187	return min3(source_max, sink_max, fia_max);
 188}
 189
 190int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 191{
 192	return intel_dp->max_link_lane_count;
 193}
 194
 195int
 196intel_dp_link_required(int pixel_clock, int bpp)
 197{
 198	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 199	return DIV_ROUND_UP(pixel_clock * bpp, 8);
 200}
 201
 202int
 203intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 204{
 205	/* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 206	 * link rate that is generally expressed in Gbps. Since, 8 bits of data
 207	 * is transmitted every LS_Clk per lane, there is no need to account for
 208	 * the channel encoding that is done in the PHY layer here.
 209	 */
 210
 211	return max_link_clock * max_lanes;
 212}
 213
 214bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 215{
 216	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 217	struct intel_encoder *encoder = &intel_dig_port->base;
 218	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 219
 220	return DISPLAY_VER(dev_priv) >= 12 ||
 221		(DISPLAY_VER(dev_priv) == 11 &&
 222		 encoder->port != PORT_A);
 223}
 224
 225static int cnl_max_source_rate(struct intel_dp *intel_dp)
 226{
 227	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 228	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 229	enum port port = dig_port->base.port;
 230
 231	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 232
 233	/* Low voltage SKUs are limited to max of 5.4G */
 234	if (voltage == VOLTAGE_INFO_0_85V)
 235		return 540000;
 236
 237	/* For this SKU 8.1G is supported in all ports */
 238	if (IS_CNL_WITH_PORT_F(dev_priv))
 239		return 810000;
 240
 241	/* For other SKUs, max rate on ports A and D is 5.4G */
 242	if (port == PORT_A || port == PORT_D)
 243		return 540000;
 244
 245	return 810000;
 246}
 247
 248static int icl_max_source_rate(struct intel_dp *intel_dp)
 249{
 250	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 251	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 252	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 253
 254	if (intel_phy_is_combo(dev_priv, phy) &&
 255	    !intel_dp_is_edp(intel_dp))
 256		return 540000;
 257
 258	return 810000;
 259}
 260
 261static int ehl_max_source_rate(struct intel_dp *intel_dp)
 262{
 263	if (intel_dp_is_edp(intel_dp))
 264		return 540000;
 265
 266	return 810000;
 267}
 268
 269static void
 270intel_dp_set_source_rates(struct intel_dp *intel_dp)
 271{
 272	/* The values must be in increasing order */
 273	static const int cnl_rates[] = {
 274		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 275	};
 276	static const int bxt_rates[] = {
 277		162000, 216000, 243000, 270000, 324000, 432000, 540000
 278	};
 279	static const int skl_rates[] = {
 280		162000, 216000, 270000, 324000, 432000, 540000
 281	};
 282	static const int hsw_rates[] = {
 283		162000, 270000, 540000
 284	};
 285	static const int g4x_rates[] = {
 286		162000, 270000
 287	};
 288	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 289	struct intel_encoder *encoder = &dig_port->base;
 290	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 291	const int *source_rates;
 292	int size, max_rate = 0, vbt_max_rate;
 293
 294	/* This should only be done once */
 295	drm_WARN_ON(&dev_priv->drm,
 296		    intel_dp->source_rates || intel_dp->num_source_rates);
 297
 298	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
 299		source_rates = cnl_rates;
 300		size = ARRAY_SIZE(cnl_rates);
 301		if (DISPLAY_VER(dev_priv) == 10)
 302			max_rate = cnl_max_source_rate(intel_dp);
 303		else if (IS_JSL_EHL(dev_priv))
 304			max_rate = ehl_max_source_rate(intel_dp);
 305		else
 306			max_rate = icl_max_source_rate(intel_dp);
 307	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 308		source_rates = bxt_rates;
 309		size = ARRAY_SIZE(bxt_rates);
 310	} else if (DISPLAY_VER(dev_priv) == 9) {
 311		source_rates = skl_rates;
 312		size = ARRAY_SIZE(skl_rates);
 313	} else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 314		   IS_BROADWELL(dev_priv)) {
 315		source_rates = hsw_rates;
 316		size = ARRAY_SIZE(hsw_rates);
 317	} else {
 318		source_rates = g4x_rates;
 319		size = ARRAY_SIZE(g4x_rates);
 320	}
 321
 322	vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 323	if (max_rate && vbt_max_rate)
 324		max_rate = min(max_rate, vbt_max_rate);
 325	else if (vbt_max_rate)
 326		max_rate = vbt_max_rate;
 327
 328	if (max_rate)
 329		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 330
 331	intel_dp->source_rates = source_rates;
 332	intel_dp->num_source_rates = size;
 333}
 334
 335static int intersect_rates(const int *source_rates, int source_len,
 336			   const int *sink_rates, int sink_len,
 337			   int *common_rates)
 338{
 339	int i = 0, j = 0, k = 0;
 340
 341	while (i < source_len && j < sink_len) {
 342		if (source_rates[i] == sink_rates[j]) {
 343			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 344				return k;
 345			common_rates[k] = source_rates[i];
 346			++k;
 347			++i;
 348			++j;
 349		} else if (source_rates[i] < sink_rates[j]) {
 350			++i;
 351		} else {
 352			++j;
 353		}
 354	}
 355	return k;
 356}
 357
 358/* return index of rate in rates array, or -1 if not found */
 359static int intel_dp_rate_index(const int *rates, int len, int rate)
 360{
 361	int i;
 362
 363	for (i = 0; i < len; i++)
 364		if (rate == rates[i])
 365			return i;
 366
 367	return -1;
 368}
 369
 370static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 371{
 372	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 373
 374	drm_WARN_ON(&i915->drm,
 375		    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 376
 377	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 378						     intel_dp->num_source_rates,
 379						     intel_dp->sink_rates,
 380						     intel_dp->num_sink_rates,
 381						     intel_dp->common_rates);
 382
 383	/* Paranoia, there should always be something in common. */
 384	if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 385		intel_dp->common_rates[0] = 162000;
 386		intel_dp->num_common_rates = 1;
 387	}
 388}
 389
 390static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 391				       u8 lane_count)
 392{
 393	/*
 394	 * FIXME: we need to synchronize the current link parameters with
 395	 * hardware readout. Currently fast link training doesn't work on
 396	 * boot-up.
 397	 */
 398	if (link_rate == 0 ||
 399	    link_rate > intel_dp->max_link_rate)
 400		return false;
 401
 402	if (lane_count == 0 ||
 403	    lane_count > intel_dp_max_lane_count(intel_dp))
 404		return false;
 405
 406	return true;
 407}
 408
 409static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 410						     int link_rate,
 411						     u8 lane_count)
 412{
 413	const struct drm_display_mode *fixed_mode =
 414		intel_dp->attached_connector->panel.fixed_mode;
 415	int mode_rate, max_rate;
 416
 417	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 418	max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 419	if (mode_rate > max_rate)
 420		return false;
 421
 422	return true;
 423}
 424
 425int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 426					    int link_rate, u8 lane_count)
 427{
 428	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 429	int index;
 430
 431	/*
 432	 * TODO: Enable fallback on MST links once MST link compute can handle
 433	 * the fallback params.
 434	 */
 435	if (intel_dp->is_mst) {
 436		drm_err(&i915->drm, "Link Training Unsuccessful\n");
 437		return -1;
 438	}
 439
 440	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 441		drm_dbg_kms(&i915->drm,
 442			    "Retrying Link training for eDP with max parameters\n");
 443		intel_dp->use_max_params = true;
 444		return 0;
 445	}
 446
 447	index = intel_dp_rate_index(intel_dp->common_rates,
 448				    intel_dp->num_common_rates,
 449				    link_rate);
 450	if (index > 0) {
 451		if (intel_dp_is_edp(intel_dp) &&
 452		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 453							      intel_dp->common_rates[index - 1],
 454							      lane_count)) {
 455			drm_dbg_kms(&i915->drm,
 456				    "Retrying Link training for eDP with same parameters\n");
 457			return 0;
 458		}
 459		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 460		intel_dp->max_link_lane_count = lane_count;
 461	} else if (lane_count > 1) {
 462		if (intel_dp_is_edp(intel_dp) &&
 463		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 464							      intel_dp_max_common_rate(intel_dp),
 465							      lane_count >> 1)) {
 466			drm_dbg_kms(&i915->drm,
 467				    "Retrying Link training for eDP with same parameters\n");
 468			return 0;
 469		}
 470		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 471		intel_dp->max_link_lane_count = lane_count >> 1;
 472	} else {
 473		drm_err(&i915->drm, "Link Training Unsuccessful\n");
 474		return -1;
 475	}
 476
 477	return 0;
 478}
 479
 480u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 481{
 482	return div_u64(mul_u32_u32(mode_clock, 1000000U),
 483		       DP_DSC_FEC_OVERHEAD_FACTOR);
 484}
 485
 486static int
 487small_joiner_ram_size_bits(struct drm_i915_private *i915)
 488{
 489	if (DISPLAY_VER(i915) >= 11)
 490		return 7680 * 8;
 491	else
 492		return 6144 * 8;
 493}
 494
 495static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 496				       u32 link_clock, u32 lane_count,
 497				       u32 mode_clock, u32 mode_hdisplay,
 498				       bool bigjoiner,
 499				       u32 pipe_bpp)
 500{
 501	u32 bits_per_pixel, max_bpp_small_joiner_ram;
 502	int i;
 503
 504	/*
 505	 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 506	 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 507	 * for SST -> TimeSlotsPerMTP is 1,
 508	 * for MST -> TimeSlotsPerMTP has to be calculated
 509	 */
 510	bits_per_pixel = (link_clock * lane_count * 8) /
 511			 intel_dp_mode_to_fec_clock(mode_clock);
 512	drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 513
 514	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 515	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 516		mode_hdisplay;
 517
 518	if (bigjoiner)
 519		max_bpp_small_joiner_ram *= 2;
 520
 521	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 522		    max_bpp_small_joiner_ram);
 523
 524	/*
 525	 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 526	 * check, output bpp from small joiner RAM check)
 527	 */
 528	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 529
 530	if (bigjoiner) {
 531		u32 max_bpp_bigjoiner =
 532			i915->max_cdclk_freq * 48 /
 533			intel_dp_mode_to_fec_clock(mode_clock);
 534
 535		DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 536		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 537	}
 538
 539	/* Error out if the max bpp is less than smallest allowed valid bpp */
 540	if (bits_per_pixel < valid_dsc_bpp[0]) {
 541		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 542			    bits_per_pixel, valid_dsc_bpp[0]);
 543		return 0;
 544	}
 545
 546	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 547	if (DISPLAY_VER(i915) >= 13) {
 548		bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 549	} else {
 550		/* Find the nearest match in the array of known BPPs from VESA */
 551		for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 552			if (bits_per_pixel < valid_dsc_bpp[i + 1])
 553				break;
 554		}
 555		bits_per_pixel = valid_dsc_bpp[i];
 556	}
 557
 558	/*
 559	 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 560	 * fractional part is 0
 561	 */
 562	return bits_per_pixel << 4;
 563}
 564
 565static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 566				       int mode_clock, int mode_hdisplay,
 567				       bool bigjoiner)
 568{
 569	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 570	u8 min_slice_count, i;
 571	int max_slice_width;
 572
 573	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 574		min_slice_count = DIV_ROUND_UP(mode_clock,
 575					       DP_DSC_MAX_ENC_THROUGHPUT_0);
 576	else
 577		min_slice_count = DIV_ROUND_UP(mode_clock,
 578					       DP_DSC_MAX_ENC_THROUGHPUT_1);
 579
 580	max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 581	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 582		drm_dbg_kms(&i915->drm,
 583			    "Unsupported slice width %d by DP DSC Sink device\n",
 584			    max_slice_width);
 585		return 0;
 586	}
 587	/* Also take into account max slice width */
 588	min_slice_count = max_t(u8, min_slice_count,
 589				DIV_ROUND_UP(mode_hdisplay,
 590					     max_slice_width));
 591
 592	/* Find the closest match to the valid slice count values */
 593	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 594		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 595
 596		if (test_slice_count >
 597		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 598			break;
 599
 600		/* big joiner needs small joiner to be enabled */
 601		if (bigjoiner && test_slice_count < 4)
 602			continue;
 603
 604		if (min_slice_count <= test_slice_count)
 605			return test_slice_count;
 606	}
 607
 608	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 609		    min_slice_count);
 610	return 0;
 611}
 612
 613static enum intel_output_format
 614intel_dp_output_format(struct drm_connector *connector,
 615		       const struct drm_display_mode *mode)
 616{
 617	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 618	const struct drm_display_info *info = &connector->display_info;
 619
 620	if (!connector->ycbcr_420_allowed ||
 621	    !drm_mode_is_420_only(info, mode))
 622		return INTEL_OUTPUT_FORMAT_RGB;
 623
 624	if (intel_dp->dfp.rgb_to_ycbcr &&
 625	    intel_dp->dfp.ycbcr_444_to_420)
 626		return INTEL_OUTPUT_FORMAT_RGB;
 627
 628	if (intel_dp->dfp.ycbcr_444_to_420)
 629		return INTEL_OUTPUT_FORMAT_YCBCR444;
 630	else
 631		return INTEL_OUTPUT_FORMAT_YCBCR420;
 632}
 633
 634int intel_dp_min_bpp(enum intel_output_format output_format)
 635{
 636	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 637		return 6 * 3;
 638	else
 639		return 8 * 3;
 640}
 641
 642static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 643{
 644	/*
 645	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 646	 * format of the number of bytes per pixel will be half the number
 647	 * of bytes of RGB pixel.
 648	 */
 649	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 650		bpp /= 2;
 651
 652	return bpp;
 653}
 654
 655static int
 656intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 657			     const struct drm_display_mode *mode)
 658{
 659	enum intel_output_format output_format =
 660		intel_dp_output_format(connector, mode);
 661
 662	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 663}
 664
 665static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 666				  int hdisplay)
 667{
 668	/*
 669	 * Older platforms don't like hdisplay==4096 with DP.
 670	 *
 671	 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 672	 * and frame counter increment), but we don't get vblank interrupts,
 673	 * and the pipe underruns immediately. The link also doesn't seem
 674	 * to get trained properly.
 675	 *
 676	 * On CHV the vblank interrupts don't seem to disappear but
 677	 * otherwise the symptoms are similar.
 678	 *
 679	 * TODO: confirm the behaviour on HSW+
 680	 */
 681	return hdisplay == 4096 && !HAS_DDI(dev_priv);
 682}
 683
 684static enum drm_mode_status
 685intel_dp_mode_valid_downstream(struct intel_connector *connector,
 686			       const struct drm_display_mode *mode,
 687			       int target_clock)
 688{
 689	struct intel_dp *intel_dp = intel_attached_dp(connector);
 690	const struct drm_display_info *info = &connector->base.display_info;
 691	int tmds_clock;
 692
 693	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
 694	if (intel_dp->dfp.pcon_max_frl_bw) {
 695		int target_bw;
 696		int max_frl_bw;
 697		int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
 698
 699		target_bw = bpp * target_clock;
 700
 701		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 702
 703		/* converting bw from Gbps to Kbps*/
 704		max_frl_bw = max_frl_bw * 1000000;
 705
 706		if (target_bw > max_frl_bw)
 707			return MODE_CLOCK_HIGH;
 708
 709		return MODE_OK;
 710	}
 711
 712	if (intel_dp->dfp.max_dotclock &&
 713	    target_clock > intel_dp->dfp.max_dotclock)
 714		return MODE_CLOCK_HIGH;
 715
 716	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 717	tmds_clock = target_clock;
 718	if (drm_mode_is_420_only(info, mode))
 719		tmds_clock /= 2;
 720
 721	if (intel_dp->dfp.min_tmds_clock &&
 722	    tmds_clock < intel_dp->dfp.min_tmds_clock)
 723		return MODE_CLOCK_LOW;
 724	if (intel_dp->dfp.max_tmds_clock &&
 725	    tmds_clock > intel_dp->dfp.max_tmds_clock)
 726		return MODE_CLOCK_HIGH;
 727
 728	return MODE_OK;
 729}
 730
 731static enum drm_mode_status
 732intel_dp_mode_valid(struct drm_connector *connector,
 733		    struct drm_display_mode *mode)
 734{
 735	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 736	struct intel_connector *intel_connector = to_intel_connector(connector);
 737	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 738	struct drm_i915_private *dev_priv = to_i915(connector->dev);
 739	int target_clock = mode->clock;
 740	int max_rate, mode_rate, max_lanes, max_link_clock;
 741	int max_dotclk = dev_priv->max_dotclk_freq;
 742	u16 dsc_max_output_bpp = 0;
 743	u8 dsc_slice_count = 0;
 744	enum drm_mode_status status;
 745	bool dsc = false, bigjoiner = false;
 746
 747	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 748		return MODE_NO_DBLESCAN;
 749
 750	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 751		return MODE_H_ILLEGAL;
 752
 753	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 754		if (mode->hdisplay != fixed_mode->hdisplay)
 755			return MODE_PANEL;
 756
 757		if (mode->vdisplay != fixed_mode->vdisplay)
 758			return MODE_PANEL;
 759
 760		target_clock = fixed_mode->clock;
 761	}
 762
 763	if (mode->clock < 10000)
 764		return MODE_CLOCK_LOW;
 765
 766	if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 767	    intel_dp_can_bigjoiner(intel_dp)) {
 768		bigjoiner = true;
 769		max_dotclk *= 2;
 770	}
 771	if (target_clock > max_dotclk)
 772		return MODE_CLOCK_HIGH;
 773
 774	max_link_clock = intel_dp_max_link_rate(intel_dp);
 775	max_lanes = intel_dp_max_lane_count(intel_dp);
 776
 777	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 778	mode_rate = intel_dp_link_required(target_clock,
 779					   intel_dp_mode_min_output_bpp(connector, mode));
 780
 781	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 782		return MODE_H_ILLEGAL;
 783
 784	/*
 785	 * Output bpp is stored in 6.4 format so right shift by 4 to get the
 786	 * integer value since we support only integer values of bpp.
 787	 */
 788	if (DISPLAY_VER(dev_priv) >= 10 &&
 789	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 790		/*
 791		 * TBD pass the connector BPC,
 792		 * for now U8_MAX so that max BPC on that platform would be picked
 793		 */
 794		int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
 795
 796		if (intel_dp_is_edp(intel_dp)) {
 797			dsc_max_output_bpp =
 798				drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 799			dsc_slice_count =
 800				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 801								true);
 802		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 803			dsc_max_output_bpp =
 804				intel_dp_dsc_get_output_bpp(dev_priv,
 805							    max_link_clock,
 806							    max_lanes,
 807							    target_clock,
 808							    mode->hdisplay,
 809							    bigjoiner,
 810							    pipe_bpp) >> 4;
 811			dsc_slice_count =
 812				intel_dp_dsc_get_slice_count(intel_dp,
 813							     target_clock,
 814							     mode->hdisplay,
 815							     bigjoiner);
 816		}
 817
 818		dsc = dsc_max_output_bpp && dsc_slice_count;
 819	}
 820
 821	/*
 822	 * Big joiner configuration needs DSC for TGL which is not true for
 823	 * XE_LPD where uncompressed joiner is supported.
 824	 */
 825	if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
 826		return MODE_CLOCK_HIGH;
 827
 828	if (mode_rate > max_rate && !dsc)
 829		return MODE_CLOCK_HIGH;
 830
 831	status = intel_dp_mode_valid_downstream(intel_connector,
 832						mode, target_clock);
 833	if (status != MODE_OK)
 834		return status;
 835
 836	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 837}
 838
 839bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
 840{
 841	int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 842
 843	return max_rate >= 540000;
 844}
 845
 846bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
 847{
 848	int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 849
 850	return max_rate >= 810000;
 851}
 852
 853static void snprintf_int_array(char *str, size_t len,
 854			       const int *array, int nelem)
 855{
 856	int i;
 857
 858	str[0] = '\0';
 859
 860	for (i = 0; i < nelem; i++) {
 861		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
 862		if (r >= len)
 863			return;
 864		str += r;
 865		len -= r;
 866	}
 867}
 868
 869static void intel_dp_print_rates(struct intel_dp *intel_dp)
 870{
 871	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 872	char str[128]; /* FIXME: too big for stack? */
 873
 874	if (!drm_debug_enabled(DRM_UT_KMS))
 875		return;
 876
 877	snprintf_int_array(str, sizeof(str),
 878			   intel_dp->source_rates, intel_dp->num_source_rates);
 879	drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
 880
 881	snprintf_int_array(str, sizeof(str),
 882			   intel_dp->sink_rates, intel_dp->num_sink_rates);
 883	drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
 884
 885	snprintf_int_array(str, sizeof(str),
 886			   intel_dp->common_rates, intel_dp->num_common_rates);
 887	drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
 888}
 889
 890int
 891intel_dp_max_link_rate(struct intel_dp *intel_dp)
 892{
 893	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 894	int len;
 895
 896	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
 897	if (drm_WARN_ON(&i915->drm, len <= 0))
 898		return 162000;
 899
 900	return intel_dp->common_rates[len - 1];
 901}
 902
 903int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 904{
 905	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 906	int i = intel_dp_rate_index(intel_dp->sink_rates,
 907				    intel_dp->num_sink_rates, rate);
 908
 909	if (drm_WARN_ON(&i915->drm, i < 0))
 910		i = 0;
 911
 912	return i;
 913}
 914
 915void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 916			   u8 *link_bw, u8 *rate_select)
 917{
 918	/* eDP 1.4 rate select method. */
 919	if (intel_dp->use_rate_select) {
 920		*link_bw = 0;
 921		*rate_select =
 922			intel_dp_rate_select(intel_dp, port_clock);
 923	} else {
 924		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
 925		*rate_select = 0;
 926	}
 927}
 928
 929static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
 930					 const struct intel_crtc_state *pipe_config)
 931{
 932	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 933
 934	/* On TGL, FEC is supported on all Pipes */
 935	if (DISPLAY_VER(dev_priv) >= 12)
 936		return true;
 937
 938	if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
 939		return true;
 940
 941	return false;
 942}
 943
 944static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
 945				  const struct intel_crtc_state *pipe_config)
 946{
 947	return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
 948		drm_dp_sink_supports_fec(intel_dp->fec_capable);
 949}
 950
 951static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
 952				  const struct intel_crtc_state *crtc_state)
 953{
 954	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
 955		return false;
 956
 957	return intel_dsc_source_support(crtc_state) &&
 958		drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
 959}
 960
 961static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
 962				   const struct intel_crtc_state *crtc_state)
 963{
 964	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 965		(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
 966		 intel_dp->dfp.ycbcr_444_to_420);
 967}
 968
 969static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
 970				    const struct intel_crtc_state *crtc_state, int bpc)
 971{
 972	int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
 973
 974	if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
 975		clock /= 2;
 976
 977	return clock;
 978}
 979
 980static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
 981					   const struct intel_crtc_state *crtc_state, int bpc)
 982{
 983	int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
 984
 985	if (intel_dp->dfp.min_tmds_clock &&
 986	    tmds_clock < intel_dp->dfp.min_tmds_clock)
 987		return false;
 988
 989	if (intel_dp->dfp.max_tmds_clock &&
 990	    tmds_clock > intel_dp->dfp.max_tmds_clock)
 991		return false;
 992
 993	return true;
 994}
 995
 996static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
 997					      const struct intel_crtc_state *crtc_state,
 998					      int bpc)
 999{
1000
1001	return intel_hdmi_deep_color_possible(crtc_state, bpc,
1002					      intel_dp->has_hdmi_sink,
1003					      intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
1004		intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
1005}
1006
1007static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1008			    const struct intel_crtc_state *crtc_state)
1009{
1010	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1011	struct intel_connector *intel_connector = intel_dp->attached_connector;
1012	int bpp, bpc;
1013
1014	bpc = crtc_state->pipe_bpp / 3;
1015
1016	if (intel_dp->dfp.max_bpc)
1017		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1018
1019	if (intel_dp->dfp.min_tmds_clock) {
1020		for (; bpc >= 10; bpc -= 2) {
1021			if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1022				break;
1023		}
1024	}
1025
1026	bpp = bpc * 3;
1027	if (intel_dp_is_edp(intel_dp)) {
1028		/* Get bpp from vbt only for panels that dont have bpp in edid */
1029		if (intel_connector->base.display_info.bpc == 0 &&
1030		    dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1031			drm_dbg_kms(&dev_priv->drm,
1032				    "clamping bpp for eDP panel to BIOS-provided %i\n",
1033				    dev_priv->vbt.edp.bpp);
1034			bpp = dev_priv->vbt.edp.bpp;
1035		}
1036	}
1037
1038	return bpp;
1039}
1040
1041/* Adjust link config limits based on compliance test requests. */
1042void
1043intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1044				  struct intel_crtc_state *pipe_config,
1045				  struct link_config_limits *limits)
1046{
1047	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1048
1049	/* For DP Compliance we override the computed bpp for the pipe */
1050	if (intel_dp->compliance.test_data.bpc != 0) {
1051		int bpp = 3 * intel_dp->compliance.test_data.bpc;
1052
1053		limits->min_bpp = limits->max_bpp = bpp;
1054		pipe_config->dither_force_disable = bpp == 6 * 3;
1055
1056		drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1057	}
1058
1059	/* Use values requested by Compliance Test Request */
1060	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1061		int index;
1062
1063		/* Validate the compliance test data since max values
1064		 * might have changed due to link train fallback.
1065		 */
1066		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1067					       intel_dp->compliance.test_lane_count)) {
1068			index = intel_dp_rate_index(intel_dp->common_rates,
1069						    intel_dp->num_common_rates,
1070						    intel_dp->compliance.test_link_rate);
1071			if (index >= 0)
1072				limits->min_clock = limits->max_clock = index;
1073			limits->min_lane_count = limits->max_lane_count =
1074				intel_dp->compliance.test_lane_count;
1075		}
1076	}
1077}
1078
1079/* Optimize link config in order: max bpp, min clock, min lanes */
1080static int
1081intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1082				  struct intel_crtc_state *pipe_config,
1083				  const struct link_config_limits *limits)
1084{
1085	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1086	int bpp, clock, lane_count;
1087	int mode_rate, link_clock, link_avail;
1088
1089	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1090		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1091
1092		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1093						   output_bpp);
1094
1095		for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1096			for (lane_count = limits->min_lane_count;
1097			     lane_count <= limits->max_lane_count;
1098			     lane_count <<= 1) {
1099				link_clock = intel_dp->common_rates[clock];
1100				link_avail = intel_dp_max_data_rate(link_clock,
1101								    lane_count);
1102
1103				if (mode_rate <= link_avail) {
1104					pipe_config->lane_count = lane_count;
1105					pipe_config->pipe_bpp = bpp;
1106					pipe_config->port_clock = link_clock;
1107
1108					return 0;
1109				}
1110			}
1111		}
1112	}
1113
1114	return -EINVAL;
1115}
1116
1117static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1118{
1119	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1120	int i, num_bpc;
1121	u8 dsc_bpc[3] = {0};
1122	u8 dsc_max_bpc;
1123
1124	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1125	if (DISPLAY_VER(i915) >= 12)
1126		dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1127	else
1128		dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1129
1130	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1131						       dsc_bpc);
1132	for (i = 0; i < num_bpc; i++) {
1133		if (dsc_max_bpc >= dsc_bpc[i])
1134			return dsc_bpc[i] * 3;
1135	}
1136
1137	return 0;
1138}
1139
1140#define DSC_SUPPORTED_VERSION_MIN		1
1141
1142static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1143				       struct intel_crtc_state *crtc_state)
1144{
1145	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1146	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1147	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1148	u8 line_buf_depth;
1149	int ret;
1150
1151	/*
1152	 * RC_MODEL_SIZE is currently a constant across all configurations.
1153	 *
1154	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1155	 * DP_DSC_RC_BUF_SIZE for this.
1156	 */
1157	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1158
1159	/*
1160	 * Slice Height of 8 works for all currently available panels. So start
1161	 * with that if pic_height is an integral multiple of 8. Eventually add
1162	 * logic to try multiple slice heights.
1163	 */
1164	if (vdsc_cfg->pic_height % 8 == 0)
1165		vdsc_cfg->slice_height = 8;
1166	else if (vdsc_cfg->pic_height % 4 == 0)
1167		vdsc_cfg->slice_height = 4;
1168	else
1169		vdsc_cfg->slice_height = 2;
1170
1171	ret = intel_dsc_compute_params(encoder, crtc_state);
1172	if (ret)
1173		return ret;
1174
1175	vdsc_cfg->dsc_version_major =
1176		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1177		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1178	vdsc_cfg->dsc_version_minor =
1179		min(DSC_SUPPORTED_VERSION_MIN,
1180		    (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1181		     DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1182
1183	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1184		DP_DSC_RGB;
1185
1186	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1187	if (!line_buf_depth) {
1188		drm_dbg_kms(&i915->drm,
1189			    "DSC Sink Line Buffer Depth invalid\n");
1190		return -EINVAL;
1191	}
1192
1193	if (vdsc_cfg->dsc_version_minor == 2)
1194		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1195			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1196	else
1197		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1198			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1199
1200	vdsc_cfg->block_pred_enable =
1201		intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1202		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1203
1204	return drm_dsc_compute_rc_parameters(vdsc_cfg);
1205}
1206
1207static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1208				       struct intel_crtc_state *pipe_config,
1209				       struct drm_connector_state *conn_state,
1210				       struct link_config_limits *limits)
1211{
1212	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1213	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1214	const struct drm_display_mode *adjusted_mode =
1215		&pipe_config->hw.adjusted_mode;
1216	int pipe_bpp;
1217	int ret;
1218
1219	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1220		intel_dp_supports_fec(intel_dp, pipe_config);
1221
1222	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1223		return -EINVAL;
1224
1225	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1226
1227	/* Min Input BPC for ICL+ is 8 */
1228	if (pipe_bpp < 8 * 3) {
1229		drm_dbg_kms(&dev_priv->drm,
1230			    "No DSC support for less than 8bpc\n");
1231		return -EINVAL;
1232	}
1233
1234	/*
1235	 * For now enable DSC for max bpp, max link rate, max lane count.
1236	 * Optimize this later for the minimum possible link rate/lane count
1237	 * with DSC enabled for the requested mode.
1238	 */
1239	pipe_config->pipe_bpp = pipe_bpp;
1240	pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1241	pipe_config->lane_count = limits->max_lane_count;
1242
1243	if (intel_dp_is_edp(intel_dp)) {
1244		pipe_config->dsc.compressed_bpp =
1245			min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1246			      pipe_config->pipe_bpp);
1247		pipe_config->dsc.slice_count =
1248			drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1249							true);
1250	} else {
1251		u16 dsc_max_output_bpp;
1252		u8 dsc_dp_slice_count;
1253
1254		dsc_max_output_bpp =
1255			intel_dp_dsc_get_output_bpp(dev_priv,
1256						    pipe_config->port_clock,
1257						    pipe_config->lane_count,
1258						    adjusted_mode->crtc_clock,
1259						    adjusted_mode->crtc_hdisplay,
1260						    pipe_config->bigjoiner,
1261						    pipe_bpp);
1262		dsc_dp_slice_count =
1263			intel_dp_dsc_get_slice_count(intel_dp,
1264						     adjusted_mode->crtc_clock,
1265						     adjusted_mode->crtc_hdisplay,
1266						     pipe_config->bigjoiner);
1267		if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1268			drm_dbg_kms(&dev_priv->drm,
1269				    "Compressed BPP/Slice Count not supported\n");
1270			return -EINVAL;
1271		}
1272		pipe_config->dsc.compressed_bpp = min_t(u16,
1273							       dsc_max_output_bpp >> 4,
1274							       pipe_config->pipe_bpp);
1275		pipe_config->dsc.slice_count = dsc_dp_slice_count;
1276	}
1277	/*
1278	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1279	 * is greater than the maximum Cdclock and if slice count is even
1280	 * then we need to use 2 VDSC instances.
1281	 */
1282	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1283	    pipe_config->bigjoiner) {
1284		if (pipe_config->dsc.slice_count < 2) {
1285			drm_dbg_kms(&dev_priv->drm,
1286				    "Cannot split stream to use 2 VDSC instances\n");
1287			return -EINVAL;
1288		}
1289
1290		pipe_config->dsc.dsc_split = true;
1291	}
1292
1293	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1294	if (ret < 0) {
1295		drm_dbg_kms(&dev_priv->drm,
1296			    "Cannot compute valid DSC parameters for Input Bpp = %d "
1297			    "Compressed BPP = %d\n",
1298			    pipe_config->pipe_bpp,
1299			    pipe_config->dsc.compressed_bpp);
1300		return ret;
1301	}
1302
1303	pipe_config->dsc.compression_enable = true;
1304	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1305		    "Compressed Bpp = %d Slice Count = %d\n",
1306		    pipe_config->pipe_bpp,
1307		    pipe_config->dsc.compressed_bpp,
1308		    pipe_config->dsc.slice_count);
1309
1310	return 0;
1311}
1312
1313static int
1314intel_dp_compute_link_config(struct intel_encoder *encoder,
1315			     struct intel_crtc_state *pipe_config,
1316			     struct drm_connector_state *conn_state)
1317{
1318	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1319	const struct drm_display_mode *adjusted_mode =
1320		&pipe_config->hw.adjusted_mode;
1321	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1322	struct link_config_limits limits;
1323	int common_len;
1324	int ret;
1325
1326	common_len = intel_dp_common_len_rate_limit(intel_dp,
1327						    intel_dp->max_link_rate);
1328
1329	/* No common link rates between source and sink */
1330	drm_WARN_ON(encoder->base.dev, common_len <= 0);
1331
1332	limits.min_clock = 0;
1333	limits.max_clock = common_len - 1;
1334
1335	limits.min_lane_count = 1;
1336	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1337
1338	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1339	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1340
1341	if (intel_dp->use_max_params) {
1342		/*
1343		 * Use the maximum clock and number of lanes the eDP panel
1344		 * advertizes being capable of in case the initial fast
1345		 * optimal params failed us. The panels are generally
1346		 * designed to support only a single clock and lane
1347		 * configuration, and typically on older panels these
1348		 * values correspond to the native resolution of the panel.
1349		 */
1350		limits.min_lane_count = limits.max_lane_count;
1351		limits.min_clock = limits.max_clock;
1352	}
1353
1354	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1355
1356	drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1357		    "max rate %d max bpp %d pixel clock %iKHz\n",
1358		    limits.max_lane_count,
1359		    intel_dp->common_rates[limits.max_clock],
1360		    limits.max_bpp, adjusted_mode->crtc_clock);
1361
1362	if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
1363	     adjusted_mode->crtc_hdisplay > 5120) &&
1364	    intel_dp_can_bigjoiner(intel_dp))
1365		pipe_config->bigjoiner = true;
1366
1367	/*
1368	 * Optimize for slow and wide for everything, because there are some
1369	 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1370	 */
1371	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1372
1373	/*
1374	 * Pipe joiner needs compression upto display12 due to BW limitation. DG2
1375	 * onwards pipe joiner can be enabled without compression.
1376	 */
1377	drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1378	if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 &&
1379					      pipe_config->bigjoiner)) {
1380		ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1381						  conn_state, &limits);
1382		if (ret < 0)
1383			return ret;
1384	}
1385
1386	if (pipe_config->dsc.compression_enable) {
1387		drm_dbg_kms(&i915->drm,
1388			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1389			    pipe_config->lane_count, pipe_config->port_clock,
1390			    pipe_config->pipe_bpp,
1391			    pipe_config->dsc.compressed_bpp);
1392
1393		drm_dbg_kms(&i915->drm,
1394			    "DP link rate required %i available %i\n",
1395			    intel_dp_link_required(adjusted_mode->crtc_clock,
1396						   pipe_config->dsc.compressed_bpp),
1397			    intel_dp_max_data_rate(pipe_config->port_clock,
1398						   pipe_config->lane_count));
1399	} else {
1400		drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1401			    pipe_config->lane_count, pipe_config->port_clock,
1402			    pipe_config->pipe_bpp);
1403
1404		drm_dbg_kms(&i915->drm,
1405			    "DP link rate required %i available %i\n",
1406			    intel_dp_link_required(adjusted_mode->crtc_clock,
1407						   pipe_config->pipe_bpp),
1408			    intel_dp_max_data_rate(pipe_config->port_clock,
1409						   pipe_config->lane_count));
1410	}
1411	return 0;
1412}
1413
1414bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1415				  const struct drm_connector_state *conn_state)
1416{
1417	const struct intel_digital_connector_state *intel_conn_state =
1418		to_intel_digital_connector_state(conn_state);
1419	const struct drm_display_mode *adjusted_mode =
1420		&crtc_state->hw.adjusted_mode;
1421
1422	/*
1423	 * Our YCbCr output is always limited range.
1424	 * crtc_state->limited_color_range only applies to RGB,
1425	 * and it must never be set for YCbCr or we risk setting
1426	 * some conflicting bits in PIPECONF which will mess up
1427	 * the colors on the monitor.
1428	 */
1429	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1430		return false;
1431
1432	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1433		/*
1434		 * See:
1435		 * CEA-861-E - 5.1 Default Encoding Parameters
1436		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1437		 */
1438		return crtc_state->pipe_bpp != 18 &&
1439			drm_default_rgb_quant_range(adjusted_mode) ==
1440			HDMI_QUANTIZATION_RANGE_LIMITED;
1441	} else {
1442		return intel_conn_state->broadcast_rgb ==
1443			INTEL_BROADCAST_RGB_LIMITED;
1444	}
1445}
1446
1447static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1448				    enum port port)
1449{
1450	if (IS_G4X(dev_priv))
1451		return false;
1452	if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1453		return false;
1454
1455	return true;
1456}
1457
1458static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1459					     const struct drm_connector_state *conn_state,
1460					     struct drm_dp_vsc_sdp *vsc)
1461{
1462	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1463	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1464
1465	/*
1466	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1467	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1468	 * Colorimetry Format indication.
1469	 */
1470	vsc->revision = 0x5;
1471	vsc->length = 0x13;
1472
1473	/* DP 1.4a spec, Table 2-120 */
1474	switch (crtc_state->output_format) {
1475	case INTEL_OUTPUT_FORMAT_YCBCR444:
1476		vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1477		break;
1478	case INTEL_OUTPUT_FORMAT_YCBCR420:
1479		vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1480		break;
1481	case INTEL_OUTPUT_FORMAT_RGB:
1482	default:
1483		vsc->pixelformat = DP_PIXELFORMAT_RGB;
1484	}
1485
1486	switch (conn_state->colorspace) {
1487	case DRM_MODE_COLORIMETRY_BT709_YCC:
1488		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1489		break;
1490	case DRM_MODE_COLORIMETRY_XVYCC_601:
1491		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1492		break;
1493	case DRM_MODE_COLORIMETRY_XVYCC_709:
1494		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1495		break;
1496	case DRM_MODE_COLORIMETRY_SYCC_601:
1497		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1498		break;
1499	case DRM_MODE_COLORIMETRY_OPYCC_601:
1500		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1501		break;
1502	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1503		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1504		break;
1505	case DRM_MODE_COLORIMETRY_BT2020_RGB:
1506		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1507		break;
1508	case DRM_MODE_COLORIMETRY_BT2020_YCC:
1509		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1510		break;
1511	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1512	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1513		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1514		break;
1515	default:
1516		/*
1517		 * RGB->YCBCR color conversion uses the BT.709
1518		 * color space.
1519		 */
1520		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1521			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1522		else
1523			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1524		break;
1525	}
1526
1527	vsc->bpc = crtc_state->pipe_bpp / 3;
1528
1529	/* only RGB pixelformat supports 6 bpc */
1530	drm_WARN_ON(&dev_priv->drm,
1531		    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1532
1533	/* all YCbCr are always limited range */
1534	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1535	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1536}
1537
1538static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1539				     struct intel_crtc_state *crtc_state,
1540				     const struct drm_connector_state *conn_state)
1541{
1542	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1543
1544	/* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1545	if (crtc_state->has_psr)
1546		return;
1547
1548	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1549		return;
1550
1551	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1552	vsc->sdp_type = DP_SDP_VSC;
1553	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1554					 &crtc_state->infoframes.vsc);
1555}
1556
1557void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1558				  const struct intel_crtc_state *crtc_state,
1559				  const struct drm_connector_state *conn_state,
1560				  struct drm_dp_vsc_sdp *vsc)
1561{
1562	vsc->sdp_type = DP_SDP_VSC;
1563
1564	if (intel_dp->psr.psr2_enabled) {
1565		if (intel_dp->psr.colorimetry_support &&
1566		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1567			/* [PSR2, +Colorimetry] */
1568			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1569							 vsc);
1570		} else {
1571			/*
1572			 * [PSR2, -Colorimetry]
1573			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1574			 * 3D stereo + PSR/PSR2 + Y-coordinate.
1575			 */
1576			vsc->revision = 0x4;
1577			vsc->length = 0xe;
1578		}
1579	} else {
1580		/*
1581		 * [PSR1]
1582		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1583		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1584		 * higher).
1585		 */
1586		vsc->revision = 0x2;
1587		vsc->length = 0x8;
1588	}
1589}
1590
1591static void
1592intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1593					    struct intel_crtc_state *crtc_state,
1594					    const struct drm_connector_state *conn_state)
1595{
1596	int ret;
1597	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1598	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1599
1600	if (!conn_state->hdr_output_metadata)
1601		return;
1602
1603	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1604
1605	if (ret) {
1606		drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1607		return;
1608	}
1609
1610	crtc_state->infoframes.enable |=
1611		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1612}
1613
1614static void
1615intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
1616			     struct intel_crtc_state *pipe_config,
1617			     int output_bpp, bool constant_n)
1618{
1619	struct intel_connector *intel_connector = intel_dp->attached_connector;
1620	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1621	int pixel_clock;
1622
1623	if (pipe_config->vrr.enable)
1624		return;
1625
1626	/*
1627	 * DRRS and PSR can't be enable together, so giving preference to PSR
1628	 * as it allows more power-savings by complete shutting down display,
1629	 * so to guarantee this, intel_dp_drrs_compute_config() must be called
1630	 * after intel_psr_compute_config().
1631	 */
1632	if (pipe_config->has_psr)
1633		return;
1634
1635	if (!intel_connector->panel.downclock_mode ||
1636	    dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
1637		return;
1638
1639	pipe_config->has_drrs = true;
1640
1641	pixel_clock = intel_connector->panel.downclock_mode->clock;
1642	if (pipe_config->splitter.enable)
1643		pixel_clock /= pipe_config->splitter.link_count;
1644
1645	intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1646			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
1647			       constant_n, pipe_config->fec_enable);
1648
1649	/* FIXME: abstract this better */
1650	if (pipe_config->splitter.enable)
1651		pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
1652}
1653
1654int
1655intel_dp_compute_config(struct intel_encoder *encoder,
1656			struct intel_crtc_state *pipe_config,
1657			struct drm_connector_state *conn_state)
1658{
1659	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1660	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1661	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1662	enum port port = encoder->port;
1663	struct intel_connector *intel_connector = intel_dp->attached_connector;
1664	struct intel_digital_connector_state *intel_conn_state =
1665		to_intel_digital_connector_state(conn_state);
1666	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1667	int ret = 0, output_bpp;
1668
1669	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1670		pipe_config->has_pch_encoder = true;
1671
1672	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1673							    adjusted_mode);
1674
1675	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1676		ret = intel_pch_panel_fitting(pipe_config, conn_state);
1677		if (ret)
1678			return ret;
1679	}
1680
1681	if (!intel_dp_port_has_audio(dev_priv, port))
1682		pipe_config->has_audio = false;
1683	else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1684		pipe_config->has_audio = intel_dp->has_audio;
1685	else
1686		pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1687
1688	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1689		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1690				       adjusted_mode);
1691
1692		if (HAS_GMCH(dev_priv))
1693			ret = intel_gmch_panel_fitting(pipe_config, conn_state);
1694		else
1695			ret = intel_pch_panel_fitting(pipe_config, conn_state);
1696		if (ret)
1697			return ret;
1698	}
1699
1700	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1701		return -EINVAL;
1702
1703	if (HAS_GMCH(dev_priv) &&
1704	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1705		return -EINVAL;
1706
1707	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1708		return -EINVAL;
1709
1710	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1711		return -EINVAL;
1712
1713	ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1714	if (ret < 0)
1715		return ret;
1716
1717	pipe_config->limited_color_range =
1718		intel_dp_limited_color_range(pipe_config, conn_state);
1719
1720	if (pipe_config->dsc.compression_enable)
1721		output_bpp = pipe_config->dsc.compressed_bpp;
1722	else
1723		output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1724						 pipe_config->pipe_bpp);
1725
1726	if (intel_dp->mso_link_count) {
1727		int n = intel_dp->mso_link_count;
1728		int overlap = intel_dp->mso_pixel_overlap;
1729
1730		pipe_config->splitter.enable = true;
1731		pipe_config->splitter.link_count = n;
1732		pipe_config->splitter.pixel_overlap = overlap;
1733
1734		drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
1735			    n, overlap);
1736
1737		adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
1738		adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
1739		adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
1740		adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
1741		adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
1742		adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
1743		adjusted_mode->crtc_clock /= n;
1744	}
1745
1746	intel_link_compute_m_n(output_bpp,
1747			       pipe_config->lane_count,
1748			       adjusted_mode->crtc_clock,
1749			       pipe_config->port_clock,
1750			       &pipe_config->dp_m_n,
1751			       constant_n, pipe_config->fec_enable);
1752
1753	/* FIXME: abstract this better */
1754	if (pipe_config->splitter.enable)
1755		pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
1756
1757	if (!HAS_DDI(dev_priv))
1758		g4x_dp_set_clock(encoder, pipe_config);
1759
1760	intel_vrr_compute_config(pipe_config, conn_state);
1761	intel_psr_compute_config(intel_dp, pipe_config);
1762	intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1763				     constant_n);
1764	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1765	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1766
1767	return 0;
1768}
1769
1770void intel_dp_set_link_params(struct intel_dp *intel_dp,
1771			      int link_rate, int lane_count)
1772{
1773	intel_dp->link_trained = false;
1774	intel_dp->link_rate = link_rate;
1775	intel_dp->lane_count = lane_count;
1776}
1777
1778/* Enable backlight PWM and backlight PP control. */
1779void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1780			    const struct drm_connector_state *conn_state)
1781{
1782	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1783	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1784
1785	if (!intel_dp_is_edp(intel_dp))
1786		return;
1787
1788	drm_dbg_kms(&i915->drm, "\n");
1789
1790	intel_panel_enable_backlight(crtc_state, conn_state);
1791	intel_pps_backlight_on(intel_dp);
1792}
1793
1794/* Disable backlight PP control and backlight PWM. */
1795void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1796{
1797	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1798	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1799
1800	if (!intel_dp_is_edp(intel_dp))
1801		return;
1802
1803	drm_dbg_kms(&i915->drm, "\n");
1804
1805	intel_pps_backlight_off(intel_dp);
1806	intel_panel_disable_backlight(old_conn_state);
1807}
1808
1809static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
1810{
1811	/*
1812	 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
1813	 * be capable of signalling downstream hpd with a long pulse.
1814	 * Whether or not that means D3 is safe to use is not clear,
1815	 * but let's assume so until proven otherwise.
1816	 *
1817	 * FIXME should really check all downstream ports...
1818	 */
1819	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
1820		drm_dp_is_branch(intel_dp->dpcd) &&
1821		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
1822}
1823
1824void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1825					   const struct intel_crtc_state *crtc_state,
1826					   bool enable)
1827{
1828	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1829	int ret;
1830
1831	if (!crtc_state->dsc.compression_enable)
1832		return;
1833
1834	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
1835				 enable ? DP_DECOMPRESSION_EN : 0);
1836	if (ret < 0)
1837		drm_dbg_kms(&i915->drm,
1838			    "Failed to %s sink decompression state\n",
1839			    enabledisable(enable));
1840}
1841
1842static void
1843intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
1844{
1845	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1846	u8 oui[] = { 0x00, 0xaa, 0x01 };
1847	u8 buf[3] = { 0 };
1848
1849	/*
1850	 * During driver init, we want to be careful and avoid changing the source OUI if it's
1851	 * already set to what we want, so as to avoid clearing any state by accident
1852	 */
1853	if (careful) {
1854		if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
1855			drm_err(&i915->drm, "Failed to read source OUI\n");
1856
1857		if (memcmp(oui, buf, sizeof(oui)) == 0)
1858			return;
1859	}
1860
1861	if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
1862		drm_err(&i915->drm, "Failed to write source OUI\n");
1863}
1864
1865/* If the device supports it, try to set the power state appropriately */
1866void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
1867{
1868	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1869	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1870	int ret, i;
1871
1872	/* Should have a valid DPCD by this point */
1873	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1874		return;
1875
1876	if (mode != DP_SET_POWER_D0) {
1877		if (downstream_hpd_needs_d0(intel_dp))
1878			return;
1879
1880		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1881	} else {
1882		struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
1883
1884		lspcon_resume(dp_to_dig_port(intel_dp));
1885
1886		/* Write the source OUI as early as possible */
1887		if (intel_dp_is_edp(intel_dp))
1888			intel_edp_init_source_oui(intel_dp, false);
1889
1890		/*
1891		 * When turning on, we need to retry for 1ms to give the sink
1892		 * time to wake up.
1893		 */
1894		for (i = 0; i < 3; i++) {
1895			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1896			if (ret == 1)
1897				break;
1898			msleep(1);
1899		}
1900
1901		if (ret == 1 && lspcon->active)
1902			lspcon_wait_pcon_mode(lspcon);
1903	}
1904
1905	if (ret != 1)
1906		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
1907			    encoder->base.base.id, encoder->base.name,
1908			    mode == DP_SET_POWER_D0 ? "D0" : "D3");
1909}
1910
1911static bool
1912intel_dp_get_dpcd(struct intel_dp *intel_dp);
1913
1914/**
1915 * intel_dp_sync_state - sync the encoder state during init/resume
1916 * @encoder: intel encoder to sync
1917 * @crtc_state: state for the CRTC connected to the encoder
1918 *
1919 * Sync any state stored in the encoder wrt. HW state during driver init
1920 * and system resume.
1921 */
1922void intel_dp_sync_state(struct intel_encoder *encoder,
1923			 const struct intel_crtc_state *crtc_state)
1924{
1925	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1926
1927	/*
1928	 * Don't clobber DPCD if it's been already read out during output
1929	 * setup (eDP) or detect.
1930	 */
1931	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1932		intel_dp_get_dpcd(intel_dp);
1933
1934	intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
1935	intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
1936}
1937
1938bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
1939				    struct intel_crtc_state *crtc_state)
1940{
1941	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1942	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1943
1944	/*
1945	 * If BIOS has set an unsupported or non-standard link rate for some
1946	 * reason force an encoder recompute and full modeset.
1947	 */
1948	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
1949				crtc_state->port_clock) < 0) {
1950		drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
1951		crtc_state->uapi.connectors_changed = true;
1952		return false;
1953	}
1954
1955	/*
1956	 * FIXME hack to force full modeset when DSC is being used.
1957	 *
1958	 * As long as we do not have full state readout and config comparison
1959	 * of crtc_state->dsc, we have no way to ensure reliable fastset.
1960	 * Remove once we have readout for DSC.
1961	 */
1962	if (crtc_state->dsc.compression_enable) {
1963		drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
1964		crtc_state->uapi.mode_changed = true;
1965		return false;
1966	}
1967
1968	if (CAN_PSR(intel_dp)) {
1969		drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
1970		crtc_state->uapi.mode_changed = true;
1971		return false;
1972	}
1973
1974	return true;
1975}
1976
1977static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
1978{
1979	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1980
1981	/* Clear the cached register set to avoid using stale values */
1982
1983	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
1984
1985	if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
1986			     intel_dp->pcon_dsc_dpcd,
1987			     sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
1988		drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
1989			DP_PCON_DSC_ENCODER);
1990
1991	drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
1992		    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
1993}
1994
1995static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
1996{
1997	int bw_gbps[] = {9, 18, 24, 32, 40, 48};
1998	int i;
1999
2000	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2001		if (frl_bw_mask & (1 << i))
2002			return bw_gbps[i];
2003	}
2004	return 0;
2005}
2006
2007static int intel_dp_pcon_set_frl_mask(int max_frl)
2008{
2009	switch (max_frl) {
2010	case 48:
2011		return DP_PCON_FRL_BW_MASK_48GBPS;
2012	case 40:
2013		return DP_PCON_FRL_BW_MASK_40GBPS;
2014	case 32:
2015		return DP_PCON_FRL_BW_MASK_32GBPS;
2016	case 24:
2017		return DP_PCON_FRL_BW_MASK_24GBPS;
2018	case 18:
2019		return DP_PCON_FRL_BW_MASK_18GBPS;
2020	case 9:
2021		return DP_PCON_FRL_BW_MASK_9GBPS;
2022	}
2023
2024	return 0;
2025}
2026
2027static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2028{
2029	struct intel_connector *intel_connector = intel_dp->attached_connector;
2030	struct drm_connector *connector = &intel_connector->base;
2031	int max_frl_rate;
2032	int max_lanes, rate_per_lane;
2033	int max_dsc_lanes, dsc_rate_per_lane;
2034
2035	max_lanes = connector->display_info.hdmi.max_lanes;
2036	rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2037	max_frl_rate = max_lanes * rate_per_lane;
2038
2039	if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2040		max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2041		dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2042		if (max_dsc_lanes && dsc_rate_per_lane)
2043			max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2044	}
2045
2046	return max_frl_rate;
2047}
2048
2049static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2050{
2051#define TIMEOUT_FRL_READY_MS 500
2052#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2053
2054	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2055	int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2056	u8 max_frl_bw_mask = 0, frl_trained_mask;
2057	bool is_active;
2058
2059	ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2060	if (ret < 0)
2061		return ret;
2062
2063	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2064	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2065
2066	max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2067	drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2068
2069	max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2070
2071	if (max_frl_bw <= 0)
2072		return -EINVAL;
2073
2074	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2075	if (ret < 0)
2076		return ret;
2077	/* Wait for PCON to be FRL Ready */
2078	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2079
2080	if (!is_active)
2081		return -ETIMEDOUT;
2082
2083	max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2084	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2085					  DP_PCON_ENABLE_SEQUENTIAL_LINK);
2086	if (ret < 0)
2087		return ret;
2088	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2089					  DP_PCON_FRL_LINK_TRAIN_NORMAL);
2090	if (ret < 0)
2091		return ret;
2092	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2093	if (ret < 0)
2094		return ret;
2095	/*
2096	 * Wait for FRL to be completed
2097	 * Check if the HDMI Link is up and active.
2098	 */
2099	wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
2100
2101	if (!is_active)
2102		return -ETIMEDOUT;
2103
2104	/* Verify HDMI Link configuration shows FRL Mode */
2105	if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
2106	    DP_PCON_HDMI_MODE_FRL) {
2107		drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
2108		return -EINVAL;
2109	}
2110	drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
2111
2112	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2113	intel_dp->frl.is_trained = true;
2114	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2115
2116	return 0;
2117}
2118
2119static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2120{
2121	if (drm_dp_is_branch(intel_dp->dpcd) &&
2122	    intel_dp->has_hdmi_sink &&
2123	    intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2124		return true;
2125
2126	return false;
2127}
2128
2129void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2130{
2131	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2132
2133	/*
2134	 * Always go for FRL training if:
2135	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2136	 * -sink is HDMI2.1
2137	 */
2138	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2139	    !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2140	    intel_dp->frl.is_trained)
2141		return;
2142
2143	if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2144		int ret, mode;
2145
2146		drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2147		ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2148		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2149
2150		if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2151			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2152	} else {
2153		drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2154	}
2155}
2156
2157static int
2158intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2159{
2160	int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2161
2162	return intel_hdmi_dsc_get_slice_height(vactive);
2163}
2164
2165static int
2166intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2167			     const struct intel_crtc_state *crtc_state)
2168{
2169	struct intel_connector *intel_connector = intel_dp->attached_connector;
2170	struct drm_connector *connector = &intel_connector->base;
2171	int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2172	int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2173	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2174	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2175
2176	return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2177					     pcon_max_slice_width,
2178					     hdmi_max_slices, hdmi_throughput);
2179}
2180
2181static int
2182intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2183			  const struct intel_crtc_state *crtc_state,
2184			  int num_slices, int slice_width)
2185{
2186	struct intel_connector *intel_connector = intel_dp->attached_connector;
2187	struct drm_connector *connector = &intel_connector->base;
2188	int output_format = crtc_state->output_format;
2189	bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2190	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2191	int hdmi_max_chunk_bytes =
2192		connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2193
2194	return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2195				      num_slices, output_format, hdmi_all_bpp,
2196				      hdmi_max_chunk_bytes);
2197}
2198
2199void
2200intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2201			    const struct intel_crtc_state *crtc_state)
2202{
2203	u8 pps_param[6];
2204	int slice_height;
2205	int slice_width;
2206	int num_slices;
2207	int bits_per_pixel;
2208	int ret;
2209	struct intel_connector *intel_connector = intel_dp->attached_connector;
2210	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2211	struct drm_connector *connector;
2212	bool hdmi_is_dsc_1_2;
2213
2214	if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2215		return;
2216
2217	if (!intel_connector)
2218		return;
2219	connector = &intel_connector->base;
2220	hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2221
2222	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2223	    !hdmi_is_dsc_1_2)
2224		return;
2225
2226	slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2227	if (!slice_height)
2228		return;
2229
2230	num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2231	if (!num_slices)
2232		return;
2233
2234	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2235				   num_slices);
2236
2237	bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2238						   num_slices, slice_width);
2239	if (!bits_per_pixel)
2240		return;
2241
2242	pps_param[0] = slice_height & 0xFF;
2243	pps_param[1] = slice_height >> 8;
2244	pps_param[2] = slice_width & 0xFF;
2245	pps_param[3] = slice_width >> 8;
2246	pps_param[4] = bits_per_pixel & 0xFF;
2247	pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2248
2249	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2250	if (ret < 0)
2251		drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2252}
2253
2254void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2255					   const struct intel_crtc_state *crtc_state)
2256{
2257	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2258	u8 tmp;
2259
2260	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2261		return;
2262
2263	if (!drm_dp_is_branch(intel_dp->dpcd))
2264		return;
2265
2266	tmp = intel_dp->has_hdmi_sink ?
2267		DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2268
2269	if (drm_dp_dpcd_writeb(&intel_dp->aux,
2270			       DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2271		drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2272			    enabledisable(intel_dp->has_hdmi_sink));
2273
2274	tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2275		intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2276
2277	if (drm_dp_dpcd_writeb(&intel_dp->aux,
2278			       DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2279		drm_dbg_kms(&i915->drm,
2280			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2281			    enabledisable(intel_dp->dfp.ycbcr_444_to_420));
2282
2283	tmp = 0;
2284	if (intel_dp->dfp.rgb_to_ycbcr) {
2285		bool bt2020, bt709;
2286
2287		/*
2288		 * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2289		 * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2290		 *
2291		 */
2292		tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2293
2294		bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2295								   intel_dp->downstream_ports,
2296								   DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2297		bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2298								  intel_dp->downstream_ports,
2299								  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2300		switch (crtc_state->infoframes.vsc.colorimetry) {
2301		case DP_COLORIMETRY_BT2020_RGB:
2302		case DP_COLORIMETRY_BT2020_YCC:
2303			if (bt2020)
2304				tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2305			break;
2306		case DP_COLORIMETRY_BT709_YCC:
2307		case DP_COLORIMETRY_XVYCC_709:
2308			if (bt709)
2309				tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2310			break;
2311		default:
2312			break;
2313		}
2314	}
2315
2316	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2317		drm_dbg_kms(&i915->drm,
2318			   "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2319			   enabledisable(tmp));
2320}
2321
2322
2323bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2324{
2325	u8 dprx = 0;
2326
2327	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2328			      &dprx) != 1)
2329		return false;
2330	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2331}
2332
2333static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2334{
2335	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2336
2337	/*
2338	 * Clear the cached register set to avoid using stale values
2339	 * for the sinks that do not support DSC.
2340	 */
2341	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2342
2343	/* Clear fec_capable to avoid using stale values */
2344	intel_dp->fec_capable = 0;
2345
2346	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2347	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2348	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2349		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2350				     intel_dp->dsc_dpcd,
2351				     sizeof(intel_dp->dsc_dpcd)) < 0)
2352			drm_err(&i915->drm,
2353				"Failed to read DPCD register 0x%x\n",
2354				DP_DSC_SUPPORT);
2355
2356		drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2357			    (int)sizeof(intel_dp->dsc_dpcd),
2358			    intel_dp->dsc_dpcd);
2359
2360		/* FEC is supported only on DP 1.4 */
2361		if (!intel_dp_is_edp(intel_dp) &&
2362		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2363				      &intel_dp->fec_capable) < 0)
2364			drm_err(&i915->drm,
2365				"Failed to read FEC DPCD register\n");
2366
2367		drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2368			    intel_dp->fec_capable);
2369	}
2370}
2371
2372static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2373				     struct drm_display_mode *mode)
2374{
2375	struct intel_dp *intel_dp = intel_attached_dp(connector);
2376	struct drm_i915_private *i915 = to_i915(connector->base.dev);
2377	int n = intel_dp->mso_link_count;
2378	int overlap = intel_dp->mso_pixel_overlap;
2379
2380	if (!mode || !n)
2381		return;
2382
2383	mode->hdisplay = (mode->hdisplay - overlap) * n;
2384	mode->hsync_start = (mode->hsync_start - overlap) * n;
2385	mode->hsync_end = (mode->hsync_end - overlap) * n;
2386	mode->htotal = (mode->htotal - overlap) * n;
2387	mode->clock *= n;
2388
2389	drm_mode_set_name(mode);
2390
2391	drm_dbg_kms(&i915->drm,
2392		    "[CONNECTOR:%d:%s] using generated MSO mode: ",
2393		    connector->base.base.id, connector->base.name);
2394	drm_mode_debug_printmodeline(mode);
2395}
2396
2397static void intel_edp_mso_init(struct intel_dp *intel_dp)
2398{
2399	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2400	u8 mso;
2401
2402	if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2403		return;
2404
2405	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2406		drm_err(&i915->drm, "Failed to read MSO cap\n");
2407		return;
2408	}
2409
2410	/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2411	mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2412	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2413		drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2414		mso = 0;
2415	}
2416
2417	if (mso) {
2418		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
2419			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
2420		if (!HAS_MSO(i915)) {
2421			drm_err(&i915->drm, "No source MSO support, disabling\n");
2422			mso = 0;
2423		}
2424	}
2425
2426	intel_dp->mso_link_count = mso;
2427	intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
2428}
2429
2430static bool
2431intel_edp_init_dpcd(struct intel_dp *intel_dp)
2432{
2433	struct drm_i915_private *dev_priv =
2434		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2435
2436	/* this function is meant to be called only once */
2437	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2438
2439	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2440		return false;
2441
2442	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2443			 drm_dp_is_branch(intel_dp->dpcd));
2444
2445	/*
2446	 * Read the eDP display control registers.
2447	 *
2448	 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2449	 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2450	 * set, but require eDP 1.4+ detection (e.g. for supported link rates
2451	 * method). The display control registers should read zero if they're
2452	 * not supported anyway.
2453	 */
2454	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2455			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2456			     sizeof(intel_dp->edp_dpcd)) {
2457		drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2458			    (int)sizeof(intel_dp->edp_dpcd),
2459			    intel_dp->edp_dpcd);
2460
2461		intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
2462	}
2463
2464	/*
2465	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2466	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2467	 */
2468	intel_psr_init_dpcd(intel_dp);
2469
2470	/* Read the eDP 1.4+ supported link rates. */
2471	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2472		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2473		int i;
2474
2475		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2476				sink_rates, sizeof(sink_rates));
2477
2478		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2479			int val = le16_to_cpu(sink_rates[i]);
2480
2481			if (val == 0)
2482				break;
2483
2484			/* Value read multiplied by 200kHz gives the per-lane
2485			 * link rate in kHz. The source rates are, however,
2486			 * stored in terms of LS_Clk kHz. The full conversion
2487			 * back to symbols is
2488			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2489			 */
2490			intel_dp->sink_rates[i] = (val * 200) / 10;
2491		}
2492		intel_dp->num_sink_rates = i;
2493	}
2494
2495	/*
2496	 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2497	 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2498	 */
2499	if (intel_dp->num_sink_rates)
2500		intel_dp->use_rate_select = true;
2501	else
2502		intel_dp_set_sink_rates(intel_dp);
2503
2504	intel_dp_set_common_rates(intel_dp);
2505
2506	/* Read the eDP DSC DPCD registers */
2507	if (DISPLAY_VER(dev_priv) >= 10)
2508		intel_dp_get_dsc_sink_cap(intel_dp);
2509
2510	/*
2511	 * If needed, program our source OUI so we can make various Intel-specific AUX services
2512	 * available (such as HDR backlight controls)
2513	 */
2514	intel_edp_init_source_oui(intel_dp, true);
2515
2516	intel_edp_mso_init(intel_dp);
2517
2518	return true;
2519}
2520
2521static bool
2522intel_dp_has_sink_count(struct intel_dp *intel_dp)
2523{
2524	if (!intel_dp->attached_connector)
2525		return false;
2526
2527	return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2528					  intel_dp->dpcd,
2529					  &intel_dp->desc);
2530}
2531
2532static bool
2533intel_dp_get_dpcd(struct intel_dp *intel_dp)
2534{
2535	int ret;
2536
2537	if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2538		return false;
2539
2540	/*
2541	 * Don't clobber cached eDP rates. Also skip re-reading
2542	 * the OUI/ID since we know it won't change.
2543	 */
2544	if (!intel_dp_is_edp(intel_dp)) {
2545		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2546				 drm_dp_is_branch(intel_dp->dpcd));
2547
2548		intel_dp_set_sink_rates(intel_dp);
2549		intel_dp_set_common_rates(intel_dp);
2550	}
2551
2552	if (intel_dp_has_sink_count(intel_dp)) {
2553		ret = drm_dp_read_sink_count(&intel_dp->aux);
2554		if (ret < 0)
2555			return false;
2556
2557		/*
2558		 * Sink count can change between short pulse hpd hence
2559		 * a member variable in intel_dp will track any changes
2560		 * between short pulse interrupts.
2561		 */
2562		intel_dp->sink_count = ret;
2563
2564		/*
2565		 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2566		 * a dongle is present but no display. Unless we require to know
2567		 * if a dongle is present or not, we don't need to update
2568		 * downstream port information. So, an early return here saves
2569		 * time from performing other operations which are not required.
2570		 */
2571		if (!intel_dp->sink_count)
2572			return false;
2573	}
2574
2575	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2576					   intel_dp->downstream_ports) == 0;
2577}
2578
2579static bool
2580intel_dp_can_mst(struct intel_dp *intel_dp)
2581{
2582	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2583
2584	return i915->params.enable_dp_mst &&
2585		intel_dp->can_mst &&
2586		drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2587}
2588
2589static void
2590intel_dp_configure_mst(struct intel_dp *intel_dp)
2591{
2592	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2593	struct intel_encoder *encoder =
2594		&dp_to_dig_port(intel_dp)->base;
2595	bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2596
2597	drm_dbg_kms(&i915->drm,
2598		    "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2599		    encoder->base.base.id, encoder->base.name,
2600		    yesno(intel_dp->can_mst), yesno(sink_can_mst),
2601		    yesno(i915->params.enable_dp_mst));
2602
2603	if (!intel_dp->can_mst)
2604		return;
2605
2606	intel_dp->is_mst = sink_can_mst &&
2607		i915->params.enable_dp_mst;
2608
2609	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
2610					intel_dp->is_mst);
2611}
2612
2613static bool
2614intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2615{
2616	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
2617				sink_irq_vector, DP_DPRX_ESI_LEN) ==
2618		DP_DPRX_ESI_LEN;
2619}
2620
2621bool
2622intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
2623		       const struct drm_connector_state *conn_state)
2624{
2625	/*
2626	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
2627	 * of Color Encoding Format and Content Color Gamut], in order to
2628	 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
2629	 */
2630	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2631		return true;
2632
2633	switch (conn_state->colorspace) {
2634	case DRM_MODE_COLORIMETRY_SYCC_601:
2635	case DRM_MODE_COLORIMETRY_OPYCC_601:
2636	case DRM_MODE_COLORIMETRY_BT2020_YCC:
2637	case DRM_MODE_COLORIMETRY_BT2020_RGB:
2638	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2639		return true;
2640	default:
2641		break;
2642	}
2643
2644	return false;
2645}
2646
2647static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2648				     struct dp_sdp *sdp, size_t size)
2649{
2650	size_t length = sizeof(struct dp_sdp);
2651
2652	if (size < length)
2653		return -ENOSPC;
2654
2655	memset(sdp, 0, size);
2656
2657	/*
2658	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2659	 * VSC SDP Header Bytes
2660	 */
2661	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2662	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2663	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2664	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2665
2666	/*
2667	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
2668	 * per DP 1.4a spec.
2669	 */
2670	if (vsc->revision != 0x5)
2671		goto out;
2672
2673	/* VSC SDP Payload for DB16 through DB18 */
2674	/* Pixel Encoding and Colorimetry Formats  */
2675	sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2676	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2677
2678	switch (vsc->bpc) {
2679	case 6:
2680		/* 6bpc: 0x0 */
2681		break;
2682	case 8:
2683		sdp->db[17] = 0x1; /* DB17[3:0] */
2684		break;
2685	case 10:
2686		sdp->db[17] = 0x2;
2687		break;
2688	case 12:
2689		sdp->db[17] = 0x3;
2690		break;
2691	case 16:
2692		sdp->db[17] = 0x4;
2693		break;
2694	default:
2695		MISSING_CASE(vsc->bpc);
2696		break;
2697	}
2698	/* Dynamic Range and Component Bit Depth */
2699	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2700		sdp->db[17] |= 0x80;  /* DB17[7] */
2701
2702	/* Content Type */
2703	sdp->db[18] = vsc->content_type & 0x7;
2704
2705out:
2706	return length;
2707}
2708
2709static ssize_t
2710intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
2711					 struct dp_sdp *sdp,
2712					 size_t size)
2713{
2714	size_t length = sizeof(struct dp_sdp);
2715	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
2716	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2717	ssize_t len;
2718
2719	if (size < length)
2720		return -ENOSPC;
2721
2722	memset(sdp, 0, size);
2723
2724	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
2725	if (len < 0) {
2726		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
2727		return -ENOSPC;
2728	}
2729
2730	if (len != infoframe_size) {
2731		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
2732		return -ENOSPC;
2733	}
2734
2735	/*
2736	 * Set up the infoframe sdp packet for HDR static metadata.
2737	 * Prepare VSC Header for SU as per DP 1.4a spec,
2738	 * Table 2-100 and Table 2-101
2739	 */
2740
2741	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
2742	sdp->sdp_header.HB0 = 0;
2743	/*
2744	 * Packet Type 80h + Non-audio INFOFRAME Type value
2745	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
2746	 * - 80h + Non-audio INFOFRAME Type value
2747	 * - InfoFrame Type: 0x07
2748	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
2749	 */
2750	sdp->sdp_header.HB1 = drm_infoframe->type;
2751	/*
2752	 * Least Significant Eight Bits of (Data Byte Count – 1)
2753	 * infoframe_size - 1
2754	 */
2755	sdp->sdp_header.HB2 = 0x1D;
2756	/* INFOFRAME SDP Version Number */
2757	sdp->sdp_header.HB3 = (0x13 << 2);
2758	/* CTA Header Byte 2 (INFOFRAME Version Number) */
2759	sdp->db[0] = drm_infoframe->version;
2760	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2761	sdp->db[1] = drm_infoframe->length;
2762	/*
2763	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
2764	 * HDMI_INFOFRAME_HEADER_SIZE
2765	 */
2766	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
2767	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
2768	       HDMI_DRM_INFOFRAME_SIZE);
2769
2770	/*
2771	 * Size of DP infoframe sdp packet for HDR static metadata consists of
2772	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
2773	 * - Two Data Blocks: 2 bytes
2774	 *    CTA Header Byte2 (INFOFRAME Version Number)
2775	 *    CTA Header Byte3 (Length of INFOFRAME)
2776	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
2777	 *
2778	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
2779	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
2780	 * will pad rest of the size.
2781	 */
2782	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
2783}
2784
2785static void intel_write_dp_sdp(struct intel_encoder *encoder,
2786			       const struct intel_crtc_state *crtc_state,
2787			       unsigned int type)
2788{
2789	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2790	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2791	struct dp_sdp sdp = {};
2792	ssize_t len;
2793
2794	if ((crtc_state->infoframes.enable &
2795	     intel_hdmi_infoframe_enable(type)) == 0)
2796		return;
2797
2798	switch (type) {
2799	case DP_SDP_VSC:
2800		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
2801					    sizeof(sdp));
2802		break;
2803	case HDMI_PACKET_TYPE_GAMUT_METADATA:
2804		len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
2805							       &sdp, sizeof(sdp));
2806		break;
2807	default:
2808		MISSING_CASE(type);
2809		return;
2810	}
2811
2812	if (drm_WARN_ON(&dev_priv->drm, len < 0))
2813		return;
2814
2815	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
2816}
2817
2818void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
2819			    const struct intel_crtc_state *crtc_state,
2820			    struct drm_dp_vsc_sdp *vsc)
2821{
2822	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2823	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2824	struct dp_sdp sdp = {};
2825	ssize_t len;
2826
2827	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
2828
2829	if (drm_WARN_ON(&dev_priv->drm, len < 0))
2830		return;
2831
2832	dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
2833					&sdp, len);
2834}
2835
2836void intel_dp_set_infoframes(struct intel_encoder *encoder,
2837			     bool enable,
2838			     const struct intel_crtc_state *crtc_state,
2839			     const struct drm_connector_state *conn_state)
2840{
2841	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2842	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
2843	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
2844			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
2845			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
2846	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
2847
2848	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
2849	/* When PSR is enabled, this routine doesn't disable VSC DIP */
2850	if (!crtc_state->has_psr)
2851		val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
2852
2853	intel_de_write(dev_priv, reg, val);
2854	intel_de_posting_read(dev_priv, reg);
2855
2856	if (!enable)
2857		return;
2858
2859	/* When PSR is enabled, VSC SDP is handled by PSR routine */
2860	if (!crtc_state->has_psr)
2861		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
2862
2863	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
2864}
2865
2866static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
2867				   const void *buffer, size_t size)
2868{
2869	const struct dp_sdp *sdp = buffer;
2870
2871	if (size < sizeof(struct dp_sdp))
2872		return -EINVAL;
2873
2874	memset(vsc, 0, sizeof(*vsc));
2875
2876	if (sdp->sdp_header.HB0 != 0)
2877		return -EINVAL;
2878
2879	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
2880		return -EINVAL;
2881
2882	vsc->sdp_type = sdp->sdp_header.HB1;
2883	vsc->revision = sdp->sdp_header.HB2;
2884	vsc->length = sdp->sdp_header.HB3;
2885
2886	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
2887	    (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
2888		/*
2889		 * - HB2 = 0x2, HB3 = 0x8
2890		 *   VSC SDP supporting 3D stereo + PSR
2891		 * - HB2 = 0x4, HB3 = 0xe
2892		 *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
2893		 *   first scan line of the SU region (applies to eDP v1.4b
2894		 *   and higher).
2895		 */
2896		return 0;
2897	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
2898		/*
2899		 * - HB2 = 0x5, HB3 = 0x13
2900		 *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
2901		 *   Format.
2902		 */
2903		vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
2904		vsc->colorimetry = sdp->db[16] & 0xf;
2905		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
2906
2907		switch (sdp->db[17] & 0x7) {
2908		case 0x0:
2909			vsc->bpc = 6;
2910			break;
2911		case 0x1:
2912			vsc->bpc = 8;
2913			break;
2914		case 0x2:
2915			vsc->bpc = 10;
2916			break;
2917		case 0x3:
2918			vsc->bpc = 12;
2919			break;
2920		case 0x4:
2921			vsc->bpc = 16;
2922			break;
2923		default:
2924			MISSING_CASE(sdp->db[17] & 0x7);
2925			return -EINVAL;
2926		}
2927
2928		vsc->content_type = sdp->db[18] & 0x7;
2929	} else {
2930		return -EINVAL;
2931	}
2932
2933	return 0;
2934}
2935
2936static int
2937intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
2938					   const void *buffer, size_t size)
2939{
2940	int ret;
2941
2942	const struct dp_sdp *sdp = buffer;
2943
2944	if (size < sizeof(struct dp_sdp))
2945		return -EINVAL;
2946
2947	if (sdp->sdp_header.HB0 != 0)
2948		return -EINVAL;
2949
2950	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
2951		return -EINVAL;
2952
2953	/*
2954	 * Least Significant Eight Bits of (Data Byte Count – 1)
2955	 * 1Dh (i.e., Data Byte Count = 30 bytes).
2956	 */
2957	if (sdp->sdp_header.HB2 != 0x1D)
2958		return -EINVAL;
2959
2960	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
2961	if ((sdp->sdp_header.HB3 & 0x3) != 0)
2962		return -EINVAL;
2963
2964	/* INFOFRAME SDP Version Number */
2965	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
2966		return -EINVAL;
2967
2968	/* CTA Header Byte 2 (INFOFRAME Version Number) */
2969	if (sdp->db[0] != 1)
2970		return -EINVAL;
2971
2972	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2973	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
2974		return -EINVAL;
2975
2976	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
2977					     HDMI_DRM_INFOFRAME_SIZE);
2978
2979	return ret;
2980}
2981
2982static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
2983				  struct intel_crtc_state *crtc_state,
2984				  struct drm_dp_vsc_sdp *vsc)
2985{
2986	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2987	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2988	unsigned int type = DP_SDP_VSC;
2989	struct dp_sdp sdp = {};
2990	int ret;
2991
2992	/* When PSR is enabled, VSC SDP is handled by PSR routine */
2993	if (crtc_state->has_psr)
2994		return;
2995
2996	if ((crtc_state->infoframes.enable &
2997	     intel_hdmi_infoframe_enable(type)) == 0)
2998		return;
2999
3000	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3001
3002	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3003
3004	if (ret)
3005		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3006}
3007
3008static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3009						     struct intel_crtc_state *crtc_state,
3010						     struct hdmi_drm_infoframe *drm_infoframe)
3011{
3012	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3013	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3014	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3015	struct dp_sdp sdp = {};
3016	int ret;
3017
3018	if ((crtc_state->infoframes.enable &
3019	    intel_hdmi_infoframe_enable(type)) == 0)
3020		return;
3021
3022	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3023				 sizeof(sdp));
3024
3025	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3026							 sizeof(sdp));
3027
3028	if (ret)
3029		drm_dbg_kms(&dev_priv->drm,
3030			    "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3031}
3032
3033void intel_read_dp_sdp(struct intel_encoder *encoder,
3034		       struct intel_crtc_state *crtc_state,
3035		       unsigned int type)
3036{
3037	if (encoder->type != INTEL_OUTPUT_DDI)
3038		return;
3039
3040	switch (type) {
3041	case DP_SDP_VSC:
3042		intel_read_dp_vsc_sdp(encoder, crtc_state,
3043				      &crtc_state->infoframes.vsc);
3044		break;
3045	case HDMI_PACKET_TYPE_GAMUT_METADATA:
3046		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3047							 &crtc_state->infoframes.drm.drm);
3048		break;
3049	default:
3050		MISSING_CASE(type);
3051		break;
3052	}
3053}
3054
3055static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3056{
3057	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3058	int status = 0;
3059	int test_link_rate;
3060	u8 test_lane_count, test_link_bw;
3061	/* (DP CTS 1.2)
3062	 * 4.3.1.11
3063	 */
3064	/* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3065	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3066				   &test_lane_count);
3067
3068	if (status <= 0) {
3069		drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3070		return DP_TEST_NAK;
3071	}
3072	test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3073
3074	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3075				   &test_link_bw);
3076	if (status <= 0) {
3077		drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3078		return DP_TEST_NAK;
3079	}
3080	test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3081
3082	/* Validate the requested link rate and lane count */
3083	if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3084					test_lane_count))
3085		return DP_TEST_NAK;
3086
3087	intel_dp->compliance.test_lane_count = test_lane_count;
3088	intel_dp->compliance.test_link_rate = test_link_rate;
3089
3090	return DP_TEST_ACK;
3091}
3092
3093static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3094{
3095	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3096	u8 test_pattern;
3097	u8 test_misc;
3098	__be16 h_width, v_height;
3099	int status = 0;
3100
3101	/* Read the TEST_PATTERN (DP CTS 3.1.5) */
3102	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3103				   &test_pattern);
3104	if (status <= 0) {
3105		drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3106		return DP_TEST_NAK;
3107	}
3108	if (test_pattern != DP_COLOR_RAMP)
3109		return DP_TEST_NAK;
3110
3111	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3112				  &h_width, 2);
3113	if (status <= 0) {
3114		drm_dbg_kms(&i915->drm, "H Width read failed\n");
3115		return DP_TEST_NAK;
3116	}
3117
3118	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3119				  &v_height, 2);
3120	if (status <= 0) {
3121		drm_dbg_kms(&i915->drm, "V Height read failed\n");
3122		return DP_TEST_NAK;
3123	}
3124
3125	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3126				   &test_misc);
3127	if (status <= 0) {
3128		drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3129		return DP_TEST_NAK;
3130	}
3131	if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3132		return DP_TEST_NAK;
3133	if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3134		return DP_TEST_NAK;
3135	switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3136	case DP_TEST_BIT_DEPTH_6:
3137		intel_dp->compliance.test_data.bpc = 6;
3138		break;
3139	case DP_TEST_BIT_DEPTH_8:
3140		intel_dp->compliance.test_data.bpc = 8;
3141		break;
3142	default:
3143		return DP_TEST_NAK;
3144	}
3145
3146	intel_dp->compliance.test_data.video_pattern = test_pattern;
3147	intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3148	intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3149	/* Set test active flag here so userspace doesn't interrupt things */
3150	intel_dp->compliance.test_active = true;
3151
3152	return DP_TEST_ACK;
3153}
3154
3155static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3156{
3157	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3158	u8 test_result = DP_TEST_ACK;
3159	struct intel_connector *intel_connector = intel_dp->attached_connector;
3160	struct drm_connector *connector = &intel_connector->base;
3161
3162	if (intel_connector->detect_edid == NULL ||
3163	    connector->edid_corrupt ||
3164	    intel_dp->aux.i2c_defer_count > 6) {
3165		/* Check EDID read for NACKs, DEFERs and corruption
3166		 * (DP CTS 1.2 Core r1.1)
3167		 *    4.2.2.4 : Failed EDID read, I2C_NAK
3168		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
3169		 *    4.2.2.6 : EDID corruption detected
3170		 * Use failsafe mode for all cases
3171		 */
3172		if (intel_dp->aux.i2c_nack_count > 0 ||
3173			intel_dp->aux.i2c_defer_count > 0)
3174			drm_dbg_kms(&i915->drm,
3175				    "EDID read had %d NACKs, %d DEFERs\n",
3176				    intel_dp->aux.i2c_nack_count,
3177				    intel_dp->aux.i2c_defer_count);
3178		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3179	} else {
3180		struct edid *block = intel_connector->detect_edid;
3181
3182		/* We have to write the checksum
3183		 * of the last block read
3184		 */
3185		block += intel_connector->detect_edid->extensions;
3186
3187		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3188				       block->checksum) <= 0)
3189			drm_dbg_kms(&i915->drm,
3190				    "Failed to write EDID checksum\n");
3191
3192		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3193		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3194	}
3195
3196	/* Set test active flag here so userspace doesn't interrupt things */
3197	intel_dp->compliance.test_active = true;
3198
3199	return test_result;
3200}
3201
3202static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3203					const struct intel_crtc_state *crtc_state)
3204{
3205	struct drm_i915_private *dev_priv =
3206			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3207	struct drm_dp_phy_test_params *data =
3208			&intel_dp->compliance.test_data.phytest;
3209	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3210	enum pipe pipe = crtc->pipe;
3211	u32 pattern_val;
3212
3213	switch (data->phy_pattern) {
3214	case DP_PHY_TEST_PATTERN_NONE:
3215		DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
3216		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3217		break;
3218	case DP_PHY_TEST_PATTERN_D10_2:
3219		DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
3220		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3221			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3222		break;
3223	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3224		DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
3225		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3226			       DDI_DP_COMP_CTL_ENABLE |
3227			       DDI_DP_COMP_CTL_SCRAMBLED_0);
3228		break;
3229	case DP_PHY_TEST_PATTERN_PRBS7:
3230		DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
3231		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3232			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3233		break;
3234	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3235		/*
3236		 * FIXME: Ideally pattern should come from DPCD 0x250. As
3237		 * current firmware of DPR-100 could not set it, so hardcoding
3238		 * now for complaince test.
3239		 */
3240		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3241		pattern_val = 0x3e0f83e0;
3242		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3243		pattern_val = 0x0f83e0f8;
3244		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3245		pattern_val = 0x0000f83e;
3246		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3247		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3248			       DDI_DP_COMP_CTL_ENABLE |
3249			       DDI_DP_COMP_CTL_CUSTOM80);
3250		break;
3251	case DP_PHY_TEST_PATTERN_CP2520:
3252		/*
3253		 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3254		 * current firmware of DPR-100 could not set it, so hardcoding
3255		 * now for complaince test.
3256		 */
3257		DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
3258		pattern_val = 0xFB;
3259		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3260			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3261			       pattern_val);
3262		break;
3263	default:
3264		WARN(1, "Invalid Phy Test Pattern\n");
3265	}
3266}
3267
3268static void
3269intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3270				  const struct intel_crtc_state *crtc_state)
3271{
3272	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3273	struct drm_device *dev = dig_port->base.base.dev;
3274	struct drm_i915_private *dev_priv = to_i915(dev);
3275	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3276	enum pipe pipe = crtc->pipe;
3277	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3278
3279	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3280						 TRANS_DDI_FUNC_CTL(pipe));
3281	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3282	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3283
3284	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3285				      TGL_TRANS_DDI_PORT_MASK);
3286	trans_conf_value &= ~PIPECONF_ENABLE;
3287	dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3288
3289	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3290	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3291		       trans_ddi_func_ctl_value);
3292	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3293}
3294
3295static void
3296intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3297				 const struct intel_crtc_state *crtc_state)
3298{
3299	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3300	struct drm_device *dev = dig_port->base.base.dev;
3301	struct drm_i915_private *dev_priv = to_i915(dev);
3302	enum port port = dig_port->base.port;
3303	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3304	enum pipe pipe = crtc->pipe;
3305	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3306
3307	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3308						 TRANS_DDI_FUNC_CTL(pipe));
3309	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3310	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3311
3312	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3313				    TGL_TRANS_DDI_SELECT_PORT(port);
3314	trans_conf_value |= PIPECONF_ENABLE;
3315	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3316
3317	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3318	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3319	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3320		       trans_ddi_func_ctl_value);
3321}
3322
3323static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3324					 const struct intel_crtc_state *crtc_state)
3325{
3326	struct drm_dp_phy_test_params *data =
3327		&intel_dp->compliance.test_data.phytest;
3328	u8 link_status[DP_LINK_STATUS_SIZE];
3329
3330	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3331					     link_status) < 0) {
3332		DRM_DEBUG_KMS("failed to get link status\n");
3333		return;
3334	}
3335
3336	/* retrieve vswing & pre-emphasis setting */
3337	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3338				  link_status);
3339
3340	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3341
3342	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3343
3344	intel_dp_phy_pattern_update(intel_dp, crtc_state);
3345
3346	intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3347
3348	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3349				    link_status[DP_DPCD_REV]);
3350}
3351
3352static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3353{
3354	struct drm_dp_phy_test_params *data =
3355		&intel_dp->compliance.test_data.phytest;
3356
3357	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3358		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
3359		return DP_TEST_NAK;
3360	}
3361
3362	/* Set test active flag here so userspace doesn't interrupt things */
3363	intel_dp->compliance.test_active = true;
3364
3365	return DP_TEST_ACK;
3366}
3367
3368static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3369{
3370	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3371	u8 response = DP_TEST_NAK;
3372	u8 request = 0;
3373	int status;
3374
3375	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3376	if (status <= 0) {
3377		drm_dbg_kms(&i915->drm,
3378			    "Could not read test request from sink\n");
3379		goto update_status;
3380	}
3381
3382	switch (request) {
3383	case DP_TEST_LINK_TRAINING:
3384		drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3385		response = intel_dp_autotest_link_training(intel_dp);
3386		break;
3387	case DP_TEST_LINK_VIDEO_PATTERN:
3388		drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3389		response = intel_dp_autotest_video_pattern(intel_dp);
3390		break;
3391	case DP_TEST_LINK_EDID_READ:
3392		drm_dbg_kms(&i915->drm, "EDID test requested\n");
3393		response = intel_dp_autotest_edid(intel_dp);
3394		break;
3395	case DP_TEST_LINK_PHY_TEST_PATTERN:
3396		drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3397		response = intel_dp_autotest_phy_pattern(intel_dp);
3398		break;
3399	default:
3400		drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3401			    request);
3402		break;
3403	}
3404
3405	if (response & DP_TEST_ACK)
3406		intel_dp->compliance.test_type = request;
3407
3408update_status:
3409	status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3410	if (status <= 0)
3411		drm_dbg_kms(&i915->drm,
3412			    "Could not write test response to sink\n");
3413}
3414
3415static void
3416intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
3417{
3418		drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
3419
3420		if (esi[1] & DP_CP_IRQ) {
3421			intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3422			*handled = true;
3423		}
3424}
3425
3426/**
3427 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3428 * @intel_dp: Intel DP struct
3429 *
3430 * Read any pending MST interrupts, call MST core to handle these and ack the
3431 * interrupts. Check if the main and AUX link state is ok.
3432 *
3433 * Returns:
3434 * - %true if pending interrupts were serviced (or no interrupts were
3435 *   pending) w/o detecting an error condition.
3436 * - %false if an error condition - like AUX failure or a loss of link - is
3437 *   detected, which needs servicing from the hotplug work.
3438 */
3439static bool
3440intel_dp_check_mst_status(struct intel_dp *intel_dp)
3441{
3442	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3443	bool link_ok = true;
3444
3445	drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3446
3447	for (;;) {
3448		/*
3449		 * The +2 is because DP_DPRX_ESI_LEN is 14, but we then
3450		 * pass in "esi+10" to drm_dp_channel_eq_ok(), which
3451		 * takes a 6-byte array. So we actually need 16 bytes
3452		 * here.
3453		 *
3454		 * Somebody who knows what the limits actually are
3455		 * should check this, but for now this is at least
3456		 * harmless and avoids a valid compiler warning about
3457		 * using more of the array than we have allocated.
3458		 */
3459		u8 esi[DP_DPRX_ESI_LEN+2] = {};
3460		bool handled;
3461		int retry;
3462
3463		if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3464			drm_dbg_kms(&i915->drm,
3465				    "failed to get ESI - device may have failed\n");
3466			link_ok = false;
3467
3468			break;
3469		}
3470
3471		/* check link status - esi[10] = 0x200c */
3472		if (intel_dp->active_mst_links > 0 && link_ok &&
3473		    !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3474			drm_dbg_kms(&i915->drm,
3475				    "channel EQ not ok, retraining\n");
3476			link_ok = false;
3477		}
3478
3479		drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
3480
3481		intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
3482
3483		if (!handled)
3484			break;
3485
3486		for (retry = 0; retry < 3; retry++) {
3487			int wret;
3488
3489			wret = drm_dp_dpcd_write(&intel_dp->aux,
3490						 DP_SINK_COUNT_ESI+1,
3491						 &esi[1], 3);
3492			if (wret == 3)
3493				break;
3494		}
3495	}
3496
3497	return link_ok;
3498}
3499
3500static void
3501intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3502{
3503	bool is_active;
3504	u8 buf = 0;
3505
3506	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3507	if (intel_dp->frl.is_trained && !is_active) {
3508		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3509			return;
3510
3511		buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3512		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3513			return;
3514
3515		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3516
3517		/* Restart FRL training or fall back to TMDS mode */
3518		intel_dp_check_frl_training(intel_dp);
3519	}
3520}
3521
3522static bool
3523intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3524{
3525	u8 link_status[DP_LINK_STATUS_SIZE];
3526
3527	if (!intel_dp->link_trained)
3528		return false;
3529
3530	/*
3531	 * While PSR source HW is enabled, it will control main-link sending
3532	 * frames, enabling and disabling it so trying to do a retrain will fail
3533	 * as the link would or not be on or it could mix training patterns
3534	 * and frame data at the same time causing retrain to fail.
3535	 * Also when exiting PSR, HW will retrain the link anyways fixing
3536	 * any link status error.
3537	 */
3538	if (intel_psr_enabled(intel_dp))
3539		return false;
3540
3541	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3542					     link_status) < 0)
3543		return false;
3544
3545	/*
3546	 * Validate the cached values of intel_dp->link_rate and
3547	 * intel_dp->lane_count before attempting to retrain.
3548	 *
3549	 * FIXME would be nice to user the crtc state here, but since
3550	 * we need to call this from the short HPD handler that seems
3551	 * a bit hard.
3552	 */
3553	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3554					intel_dp->lane_count))
3555		return false;
3556
3557	/* Retrain if Channel EQ or CR not ok */
3558	return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3559}
3560
3561static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3562				   const struct drm_connector_state *conn_state)
3563{
3564	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3565	struct intel_encoder *encoder;
3566	enum pipe pipe;
3567
3568	if (!conn_state->best_encoder)
3569		return false;
3570
3571	/* SST */
3572	encoder = &dp_to_dig_port(intel_dp)->base;
3573	if (conn_state->best_encoder == &encoder->base)
3574		return true;
3575
3576	/* MST */
3577	for_each_pipe(i915, pipe) {
3578		encoder = &intel_dp->mst_encoders[pipe]->base;
3579		if (conn_state->best_encoder == &encoder->base)
3580			return true;
3581	}
3582
3583	return false;
3584}
3585
3586static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3587				      struct drm_modeset_acquire_ctx *ctx,
3588				      u32 *crtc_mask)
3589{
3590	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3591	struct drm_connector_list_iter conn_iter;
3592	struct intel_connector *connector;
3593	int ret = 0;
3594
3595	*crtc_mask = 0;
3596
3597	if (!intel_dp_needs_link_retrain(intel_dp))
3598		return 0;
3599
3600	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3601	for_each_intel_connector_iter(connector, &conn_iter) {
3602		struct drm_connector_state *conn_state =
3603			connector->base.state;
3604		struct intel_crtc_state *crtc_state;
3605		struct intel_crtc *crtc;
3606
3607		if (!intel_dp_has_connector(intel_dp, conn_state))
3608			continue;
3609
3610		crtc = to_intel_crtc(conn_state->crtc);
3611		if (!crtc)
3612			continue;
3613
3614		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3615		if (ret)
3616			break;
3617
3618		crtc_state = to_intel_crtc_state(crtc->base.state);
3619
3620		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3621
3622		if (!crtc_state->hw.active)
3623			continue;
3624
3625		if (conn_state->commit &&
3626		    !try_wait_for_completion(&conn_state->commit->hw_done))
3627			continue;
3628
3629		*crtc_mask |= drm_crtc_mask(&crtc->base);
3630	}
3631	drm_connector_list_iter_end(&conn_iter);
3632
3633	if (!intel_dp_needs_link_retrain(intel_dp))
3634		*crtc_mask = 0;
3635
3636	return ret;
3637}
3638
3639static bool intel_dp_is_connected(struct intel_dp *intel_dp)
3640{
3641	struct intel_connector *connector = intel_dp->attached_connector;
3642
3643	return connector->base.status == connector_status_connected ||
3644		intel_dp->is_mst;
3645}
3646
3647int intel_dp_retrain_link(struct intel_encoder *encoder,
3648			  struct drm_modeset_acquire_ctx *ctx)
3649{
3650	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3651	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3652	struct intel_crtc *crtc;
3653	u32 crtc_mask;
3654	int ret;
3655
3656	if (!intel_dp_is_connected(intel_dp))
3657		return 0;
3658
3659	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3660			       ctx);
3661	if (ret)
3662		return ret;
3663
3664	ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
3665	if (ret)
3666		return ret;
3667
3668	if (crtc_mask == 0)
3669		return 0;
3670
3671	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
3672		    encoder->base.base.id, encoder->base.name);
3673
3674	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3675		const struct intel_crtc_state *crtc_state =
3676			to_intel_crtc_state(crtc->base.state);
3677
3678		/* Suppress underruns caused by re-training */
3679		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3680		if (crtc_state->has_pch_encoder)
3681			intel_set_pch_fifo_underrun_reporting(dev_priv,
3682							      intel_crtc_pch_transcoder(crtc), false);
3683	}
3684
3685	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3686		const struct intel_crtc_state *crtc_state =
3687			to_intel_crtc_state(crtc->base.state);
3688
3689		/* retrain on the MST master transcoder */
3690		if (DISPLAY_VER(dev_priv) >= 12 &&
3691		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3692		    !intel_dp_mst_is_master_trans(crtc_state))
3693			continue;
3694
3695		intel_dp_check_frl_training(intel_dp);
3696		intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
3697		intel_dp_start_link_train(intel_dp, crtc_state);
3698		intel_dp_stop_link_train(intel_dp, crtc_state);
3699		break;
3700	}
3701
3702	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3703		const struct intel_crtc_state *crtc_state =
3704			to_intel_crtc_state(crtc->base.state);
3705
3706		/* Keep underrun reporting disabled until things are stable */
3707		intel_wait_for_vblank(dev_priv, crtc->pipe);
3708
3709		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3710		if (crtc_state->has_pch_encoder)
3711			intel_set_pch_fifo_underrun_reporting(dev_priv,
3712							      intel_crtc_pch_transcoder(crtc), true);
3713	}
3714
3715	return 0;
3716}
3717
3718static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
3719				  struct drm_modeset_acquire_ctx *ctx,
3720				  u32 *crtc_mask)
3721{
3722	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3723	struct drm_connector_list_iter conn_iter;
3724	struct intel_connector *connector;
3725	int ret = 0;
3726
3727	*crtc_mask = 0;
3728
3729	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3730	for_each_intel_connector_iter(connector, &conn_iter) {
3731		struct drm_connector_state *conn_state =
3732			connector->base.state;
3733		struct intel_crtc_state *crtc_state;
3734		struct intel_crtc *crtc;
3735
3736		if (!intel_dp_has_connector(intel_dp, conn_state))
3737			continue;
3738
3739		crtc = to_intel_crtc(conn_state->crtc);
3740		if (!crtc)
3741			continue;
3742
3743		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3744		if (ret)
3745			break;
3746
3747		crtc_state = to_intel_crtc_state(crtc->base.state);
3748
3749		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3750
3751		if (!crtc_state->hw.active)
3752			continue;
3753
3754		if (conn_state->commit &&
3755		    !try_wait_for_completion(&conn_state->commit->hw_done))
3756			continue;
3757
3758		*crtc_mask |= drm_crtc_mask(&crtc->base);
3759	}
3760	drm_connector_list_iter_end(&conn_iter);
3761
3762	return ret;
3763}
3764
3765static int intel_dp_do_phy_test(struct intel_encoder *encoder,
3766				struct drm_modeset_acquire_ctx *ctx)
3767{
3768	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3769	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3770	struct intel_crtc *crtc;
3771	u32 crtc_mask;
3772	int ret;
3773
3774	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3775			       ctx);
3776	if (ret)
3777		return ret;
3778
3779	ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
3780	if (ret)
3781		return ret;
3782
3783	if (crtc_mask == 0)
3784		return 0;
3785
3786	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
3787		    encoder->base.base.id, encoder->base.name);
3788
3789	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3790		const struct intel_crtc_state *crtc_state =
3791			to_intel_crtc_state(crtc->base.state);
3792
3793		/* test on the MST master transcoder */
3794		if (DISPLAY_VER(dev_priv) >= 12 &&
3795		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3796		    !intel_dp_mst_is_master_trans(crtc_state))
3797			continue;
3798
3799		intel_dp_process_phy_request(intel_dp, crtc_state);
3800		break;
3801	}
3802
3803	return 0;
3804}
3805
3806void intel_dp_phy_test(struct intel_encoder *encoder)
3807{
3808	struct drm_modeset_acquire_ctx ctx;
3809	int ret;
3810
3811	drm_modeset_acquire_init(&ctx, 0);
3812
3813	for (;;) {
3814		ret = intel_dp_do_phy_test(encoder, &ctx);
3815
3816		if (ret == -EDEADLK) {
3817			drm_modeset_backoff(&ctx);
3818			continue;
3819		}
3820
3821		break;
3822	}
3823
3824	drm_modeset_drop_locks(&ctx);
3825	drm_modeset_acquire_fini(&ctx);
3826	drm_WARN(encoder->base.dev, ret,
3827		 "Acquiring modeset locks failed with %i\n", ret);
3828}
3829
3830static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
3831{
3832	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3833	u8 val;
3834
3835	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3836		return;
3837
3838	if (drm_dp_dpcd_readb(&intel_dp->aux,
3839			      DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
3840		return;
3841
3842	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
3843
3844	if (val & DP_AUTOMATED_TEST_REQUEST)
3845		intel_dp_handle_test_request(intel_dp);
3846
3847	if (val & DP_CP_IRQ)
3848		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3849
3850	if (val & DP_SINK_SPECIFIC_IRQ)
3851		drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
3852}
3853
3854static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
3855{
3856	u8 val;
3857
3858	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3859		return;
3860
3861	if (drm_dp_dpcd_readb(&intel_dp->aux,
3862			      DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
3863		return;
3864
3865	if (drm_dp_dpcd_writeb(&intel_dp->aux,
3866			       DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
3867		return;
3868
3869	if (val & HDMI_LINK_STATUS_CHANGED)
3870		intel_dp_handle_hdmi_link_status_change(intel_dp);
3871}
3872
3873/*
3874 * According to DP spec
3875 * 5.1.2:
3876 *  1. Read DPCD
3877 *  2. Configure link according to Receiver Capabilities
3878 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3879 *  4. Check link status on receipt of hot-plug interrupt
3880 *
3881 * intel_dp_short_pulse -  handles short pulse interrupts
3882 * when full detection is not required.
3883 * Returns %true if short pulse is handled and full detection
3884 * is NOT required and %false otherwise.
3885 */
3886static bool
3887intel_dp_short_pulse(struct intel_dp *intel_dp)
3888{
3889	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3890	u8 old_sink_count = intel_dp->sink_count;
3891	bool ret;
3892
3893	/*
3894	 * Clearing compliance test variables to allow capturing
3895	 * of values for next automated test request.
3896	 */
3897	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
3898
3899	/*
3900	 * Now read the DPCD to see if it's actually running
3901	 * If the current value of sink count doesn't match with
3902	 * the value that was stored earlier or dpcd read failed
3903	 * we need to do full detection
3904	 */
3905	ret = intel_dp_get_dpcd(intel_dp);
3906
3907	if ((old_sink_count != intel_dp->sink_count) || !ret) {
3908		/* No need to proceed if we are going to do full detect */
3909		return false;
3910	}
3911
3912	intel_dp_check_device_service_irq(intel_dp);
3913	intel_dp_check_link_service_irq(intel_dp);
3914
3915	/* Handle CEC interrupts, if any */
3916	drm_dp_cec_irq(&intel_dp->aux);
3917
3918	/* defer to the hotplug work for link retraining if needed */
3919	if (intel_dp_needs_link_retrain(intel_dp))
3920		return false;
3921
3922	intel_psr_short_pulse(intel_dp);
3923
3924	switch (intel_dp->compliance.test_type) {
3925	case DP_TEST_LINK_TRAINING:
3926		drm_dbg_kms(&dev_priv->drm,
3927			    "Link Training Compliance Test requested\n");
3928		/* Send a Hotplug Uevent to userspace to start modeset */
3929		drm_kms_helper_hotplug_event(&dev_priv->drm);
3930		break;
3931	case DP_TEST_LINK_PHY_TEST_PATTERN:
3932		drm_dbg_kms(&dev_priv->drm,
3933			    "PHY test pattern Compliance Test requested\n");
3934		/*
3935		 * Schedule long hpd to do the test
3936		 *
3937		 * FIXME get rid of the ad-hoc phy test modeset code
3938		 * and properly incorporate it into the normal modeset.
3939		 */
3940		return false;
3941	}
3942
3943	return true;
3944}
3945
3946/* XXX this is probably wrong for multiple downstream ports */
3947static enum drm_connector_status
3948intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3949{
3950	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3951	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3952	u8 *dpcd = intel_dp->dpcd;
3953	u8 type;
3954
3955	if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
3956		return connector_status_connected;
3957
3958	lspcon_resume(dig_port);
3959
3960	if (!intel_dp_get_dpcd(intel_dp))
3961		return connector_status_disconnected;
3962
3963	/* if there's no downstream port, we're done */
3964	if (!drm_dp_is_branch(dpcd))
3965		return connector_status_connected;
3966
3967	/* If we're HPD-aware, SINK_COUNT changes dynamically */
3968	if (intel_dp_has_sink_count(intel_dp) &&
3969	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3970		return intel_dp->sink_count ?
3971		connector_status_connected : connector_status_disconnected;
3972	}
3973
3974	if (intel_dp_can_mst(intel_dp))
3975		return connector_status_connected;
3976
3977	/* If no HPD, poke DDC gently */
3978	if (drm_probe_ddc(&intel_dp->aux.ddc))
3979		return connector_status_connected;
3980
3981	/* Well we tried, say unknown for unreliable port types */
3982	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3983		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3984		if (type == DP_DS_PORT_TYPE_VGA ||
3985		    type == DP_DS_PORT_TYPE_NON_EDID)
3986			return connector_status_unknown;
3987	} else {
3988		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3989			DP_DWN_STRM_PORT_TYPE_MASK;
3990		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3991		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
3992			return connector_status_unknown;
3993	}
3994
3995	/* Anything else is out of spec, warn and ignore */
3996	drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
3997	return connector_status_disconnected;
3998}
3999
4000static enum drm_connector_status
4001edp_detect(struct intel_dp *intel_dp)
4002{
4003	return connector_status_connected;
4004}
4005
4006/*
4007 * intel_digital_port_connected - is the specified port connected?
4008 * @encoder: intel_encoder
4009 *
4010 * In cases where there's a connector physically connected but it can't be used
4011 * by our hardware we also return false, since the rest of the driver should
4012 * pretty much treat the port as disconnected. This is relevant for type-C
4013 * (starting on ICL) where there's ownership involved.
4014 *
4015 * Return %true if port is connected, %false otherwise.
4016 */
4017bool intel_digital_port_connected(struct intel_encoder *encoder)
4018{
4019	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4020	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4021	bool is_connected = false;
4022	intel_wakeref_t wakeref;
4023
4024	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4025		is_connected = dig_port->connected(encoder);
4026
4027	return is_connected;
4028}
4029
4030static struct edid *
4031intel_dp_get_edid(struct intel_dp *intel_dp)
4032{
4033	struct intel_connector *intel_connector = intel_dp->attached_connector;
4034
4035	/* use cached edid if we have one */
4036	if (intel_connector->edid) {
4037		/* invalid edid */
4038		if (IS_ERR(intel_connector->edid))
4039			return NULL;
4040
4041		return drm_edid_duplicate(intel_connector->edid);
4042	} else
4043		return drm_get_edid(&intel_connector->base,
4044				    &intel_dp->aux.ddc);
4045}
4046
4047static void
4048intel_dp_update_dfp(struct intel_dp *intel_dp,
4049		    const struct edid *edid)
4050{
4051	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4052	struct intel_connector *connector = intel_dp->attached_connector;
4053
4054	intel_dp->dfp.max_bpc =
4055		drm_dp_downstream_max_bpc(intel_dp->dpcd,
4056					  intel_dp->downstream_ports, edid);
4057
4058	intel_dp->dfp.max_dotclock =
4059		drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4060					       intel_dp->downstream_ports);
4061
4062	intel_dp->dfp.min_tmds_clock =
4063		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4064						 intel_dp->downstream_ports,
4065						 edid);
4066	intel_dp->dfp.max_tmds_clock =
4067		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4068						 intel_dp->downstream_ports,
4069						 edid);
4070
4071	intel_dp->dfp.pcon_max_frl_bw =
4072		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4073					   intel_dp->downstream_ports);
4074
4075	drm_dbg_kms(&i915->drm,
4076		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4077		    connector->base.base.id, connector->base.name,
4078		    intel_dp->dfp.max_bpc,
4079		    intel_dp->dfp.max_dotclock,
4080		    intel_dp->dfp.min_tmds_clock,
4081		    intel_dp->dfp.max_tmds_clock,
4082		    intel_dp->dfp.pcon_max_frl_bw);
4083
4084	intel_dp_get_pcon_dsc_cap(intel_dp);
4085}
4086
4087static void
4088intel_dp_update_420(struct intel_dp *intel_dp)
4089{
4090	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4091	struct intel_connector *connector = intel_dp->attached_connector;
4092	bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4093
4094	/* No YCbCr output support on gmch platforms */
4095	if (HAS_GMCH(i915))
4096		return;
4097
4098	/*
4099	 * ILK doesn't seem capable of DP YCbCr output. The
4100	 * displayed image is severly corrupted. SNB+ is fine.
4101	 */
4102	if (IS_IRONLAKE(i915))
4103		return;
4104
4105	is_branch = drm_dp_is_branch(intel_dp->dpcd);
4106	ycbcr_420_passthrough =
4107		drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4108						  intel_dp->downstream_ports);
4109	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4110	ycbcr_444_to_420 =
4111		dp_to_dig_port(intel_dp)->lspcon.active ||
4112		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4113							intel_dp->downstream_ports);
4114	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4115								 intel_dp->downstream_ports,
4116								 DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
4117								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
4118								 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
4119
4120	if (DISPLAY_VER(i915) >= 11) {
4121		/* Let PCON convert from RGB->YCbCr if possible */
4122		if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4123			intel_dp->dfp.rgb_to_ycbcr = true;
4124			intel_dp->dfp.ycbcr_444_to_420 = true;
4125			connector->base.ycbcr_420_allowed = true;
4126		} else {
4127		/* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4128			intel_dp->dfp.ycbcr_444_to_420 =
4129				ycbcr_444_to_420 && !ycbcr_420_passthrough;
4130
4131			connector->base.ycbcr_420_allowed =
4132				!is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4133		}
4134	} else {
4135		/* 4:4:4->4:2:0 conversion is the only way */
4136		intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4137
4138		connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4139	}
4140
4141	drm_dbg_kms(&i915->drm,
4142		    "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4143		    connector->base.base.id, connector->base.name,
4144		    yesno(intel_dp->dfp.rgb_to_ycbcr),
4145		    yesno(connector->base.ycbcr_420_allowed),
4146		    yesno(intel_dp->dfp.ycbcr_444_to_420));
4147}
4148
4149static void
4150intel_dp_set_edid(struct intel_dp *intel_dp)
4151{
4152	struct intel_connector *connector = intel_dp->attached_connector;
4153	struct edid *edid;
4154
4155	intel_dp_unset_edid(intel_dp);
4156	edid = intel_dp_get_edid(intel_dp);
4157	connector->detect_edid = edid;
4158
4159	intel_dp_update_dfp(intel_dp, edid);
4160	intel_dp_update_420(intel_dp);
4161
4162	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4163		intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4164		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4165	}
4166
4167	drm_dp_cec_set_edid(&intel_dp->aux, edid);
4168}
4169
4170static void
4171intel_dp_unset_edid(struct intel_dp *intel_dp)
4172{
4173	struct intel_connector *connector = intel_dp->attached_connector;
4174
4175	drm_dp_cec_unset_edid(&intel_dp->aux);
4176	kfree(connector->detect_edid);
4177	connector->detect_edid = NULL;
4178
4179	intel_dp->has_hdmi_sink = false;
4180	intel_dp->has_audio = false;
4181
4182	intel_dp->dfp.max_bpc = 0;
4183	intel_dp->dfp.max_dotclock = 0;
4184	intel_dp->dfp.min_tmds_clock = 0;
4185	intel_dp->dfp.max_tmds_clock = 0;
4186
4187	intel_dp->dfp.pcon_max_frl_bw = 0;
4188
4189	intel_dp->dfp.ycbcr_444_to_420 = false;
4190	connector->base.ycbcr_420_allowed = false;
4191}
4192
4193static int
4194intel_dp_detect(struct drm_connector *connector,
4195		struct drm_modeset_acquire_ctx *ctx,
4196		bool force)
4197{
4198	struct drm_i915_private *dev_priv = to_i915(connector->dev);
4199	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4200	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4201	struct intel_encoder *encoder = &dig_port->base;
4202	enum drm_connector_status status;
4203
4204	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4205		    connector->base.id, connector->name);
4206	drm_WARN_ON(&dev_priv->drm,
4207		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4208
4209	if (!INTEL_DISPLAY_ENABLED(dev_priv))
4210		return connector_status_disconnected;
4211
4212	/* Can't disconnect eDP */
4213	if (intel_dp_is_edp(intel_dp))
4214		status = edp_detect(intel_dp);
4215	else if (intel_digital_port_connected(encoder))
4216		status = intel_dp_detect_dpcd(intel_dp);
4217	else
4218		status = connector_status_disconnected;
4219
4220	if (status == connector_status_disconnected) {
4221		memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4222		memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4223
4224		if (intel_dp->is_mst) {
4225			drm_dbg_kms(&dev_priv->drm,
4226				    "MST device may have disappeared %d vs %d\n",
4227				    intel_dp->is_mst,
4228				    intel_dp->mst_mgr.mst_state);
4229			intel_dp->is_mst = false;
4230			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4231							intel_dp->is_mst);
4232		}
4233
4234		goto out;
4235	}
4236
4237	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4238	if (DISPLAY_VER(dev_priv) >= 11)
4239		intel_dp_get_dsc_sink_cap(intel_dp);
4240
4241	intel_dp_configure_mst(intel_dp);
4242
4243	/*
4244	 * TODO: Reset link params when switching to MST mode, until MST
4245	 * supports link training fallback params.
4246	 */
4247	if (intel_dp->reset_link_params || intel_dp->is_mst) {
4248		/* Initial max link lane count */
4249		intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4250
4251		/* Initial max link rate */
4252		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4253
4254		intel_dp->reset_link_params = false;
4255	}
4256
4257	intel_dp_print_rates(intel_dp);
4258
4259	if (intel_dp->is_mst) {
4260		/*
4261		 * If we are in MST mode then this connector
4262		 * won't appear connected or have anything
4263		 * with EDID on it
4264		 */
4265		status = connector_status_disconnected;
4266		goto out;
4267	}
4268
4269	/*
4270	 * Some external monitors do not signal loss of link synchronization
4271	 * with an IRQ_HPD, so force a link status check.
4272	 */
4273	if (!intel_dp_is_edp(intel_dp)) {
4274		int ret;
4275
4276		ret = intel_dp_retrain_link(encoder, ctx);
4277		if (ret)
4278			return ret;
4279	}
4280
4281	/*
4282	 * Clearing NACK and defer counts to get their exact values
4283	 * while reading EDID which are required by Compliance tests
4284	 * 4.2.2.4 and 4.2.2.5
4285	 */
4286	intel_dp->aux.i2c_nack_count = 0;
4287	intel_dp->aux.i2c_defer_count = 0;
4288
4289	intel_dp_set_edid(intel_dp);
4290	if (intel_dp_is_edp(intel_dp) ||
4291	    to_intel_connector(connector)->detect_edid)
4292		status = connector_status_connected;
4293
4294	intel_dp_check_device_service_irq(intel_dp);
4295
4296out:
4297	if (status != connector_status_connected && !intel_dp->is_mst)
4298		intel_dp_unset_edid(intel_dp);
4299
4300	/*
4301	 * Make sure the refs for power wells enabled during detect are
4302	 * dropped to avoid a new detect cycle triggered by HPD polling.
4303	 */
4304	intel_display_power_flush_work(dev_priv);
4305
4306	if (!intel_dp_is_edp(intel_dp))
4307		drm_dp_set_subconnector_property(connector,
4308						 status,
4309						 intel_dp->dpcd,
4310						 intel_dp->downstream_ports);
4311	return status;
4312}
4313
4314static void
4315intel_dp_force(struct drm_connector *connector)
4316{
4317	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4318	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4319	struct intel_encoder *intel_encoder = &dig_port->base;
4320	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4321	enum intel_display_power_domain aux_domain =
4322		intel_aux_power_domain(dig_port);
4323	intel_wakeref_t wakeref;
4324
4325	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4326		    connector->base.id, connector->name);
4327	intel_dp_unset_edid(intel_dp);
4328
4329	if (connector->status != connector_status_connected)
4330		return;
4331
4332	wakeref = intel_display_power_get(dev_priv, aux_domain);
4333
4334	intel_dp_set_edid(intel_dp);
4335
4336	intel_display_power_put(dev_priv, aux_domain, wakeref);
4337}
4338
4339static int intel_dp_get_modes(struct drm_connector *connector)
4340{
4341	struct intel_connector *intel_connector = to_intel_connector(connector);
4342	struct edid *edid;
4343	int num_modes = 0;
4344
4345	edid = intel_connector->detect_edid;
4346	if (edid) {
4347		num_modes = intel_connector_update_modes(connector, edid);
4348
4349		if (intel_vrr_is_capable(connector))
4350			drm_connector_set_vrr_capable_property(connector,
4351							       true);
4352	}
4353
4354	/* Also add fixed mode, which may or may not be present in EDID */
4355	if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
4356	    intel_connector->panel.fixed_mode) {
4357		struct drm_display_mode *mode;
4358
4359		mode = drm_mode_duplicate(connector->dev,
4360					  intel_connector->panel.fixed_mode);
4361		if (mode) {
4362			drm_mode_probed_add(connector, mode);
4363			num_modes++;
4364		}
4365	}
4366
4367	if (num_modes)
4368		return num_modes;
4369
4370	if (!edid) {
4371		struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4372		struct drm_display_mode *mode;
4373
4374		mode = drm_dp_downstream_mode(connector->dev,
4375					      intel_dp->dpcd,
4376					      intel_dp->downstream_ports);
4377		if (mode) {
4378			drm_mode_probed_add(connector, mode);
4379			num_modes++;
4380		}
4381	}
4382
4383	return num_modes;
4384}
4385
4386static int
4387intel_dp_connector_register(struct drm_connector *connector)
4388{
4389	struct drm_i915_private *i915 = to_i915(connector->dev);
4390	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4391	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4392	struct intel_lspcon *lspcon = &dig_port->lspcon;
4393	int ret;
4394
4395	ret = intel_connector_register(connector);
4396	if (ret)
4397		return ret;
4398
4399	drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4400		    intel_dp->aux.name, connector->kdev->kobj.name);
4401
4402	intel_dp->aux.dev = connector->kdev;
4403	ret = drm_dp_aux_register(&intel_dp->aux);
4404	if (!ret)
4405		drm_dp_cec_register_connector(&intel_dp->aux, connector);
4406
4407	if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4408		return ret;
4409
4410	/*
4411	 * ToDo: Clean this up to handle lspcon init and resume more
4412	 * efficiently and streamlined.
4413	 */
4414	if (lspcon_init(dig_port)) {
4415		lspcon_detect_hdr_capability(lspcon);
4416		if (lspcon->hdr_supported)
4417			drm_object_attach_property(&connector->base,
4418						   connector->dev->mode_config.hdr_output_metadata_property,
4419						   0);
4420	}
4421
4422	return ret;
4423}
4424
4425static void
4426intel_dp_connector_unregister(struct drm_connector *connector)
4427{
4428	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4429
4430	drm_dp_cec_unregister_connector(&intel_dp->aux);
4431	drm_dp_aux_unregister(&intel_dp->aux);
4432	intel_connector_unregister(connector);
4433}
4434
4435void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4436{
4437	struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4438	struct intel_dp *intel_dp = &dig_port->dp;
4439
4440	intel_dp_mst_encoder_cleanup(dig_port);
4441
4442	intel_pps_vdd_off_sync(intel_dp);
4443
4444	intel_dp_aux_fini(intel_dp);
4445}
4446
4447void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4448{
4449	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4450
4451	intel_pps_vdd_off_sync(intel_dp);
4452}
4453
4454void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4455{
4456	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4457
4458	intel_pps_wait_power_cycle(intel_dp);
4459}
4460
4461static int intel_modeset_tile_group(struct intel_atomic_state *state,
4462				    int tile_group_id)
4463{
4464	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4465	struct drm_connector_list_iter conn_iter;
4466	struct drm_connector *connector;
4467	int ret = 0;
4468
4469	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4470	drm_for_each_connector_iter(connector, &conn_iter) {
4471		struct drm_connector_state *conn_state;
4472		struct intel_crtc_state *crtc_state;
4473		struct intel_crtc *crtc;
4474
4475		if (!connector->has_tile ||
4476		    connector->tile_group->id != tile_group_id)
4477			continue;
4478
4479		conn_state = drm_atomic_get_connector_state(&state->base,
4480							    connector);
4481		if (IS_ERR(conn_state)) {
4482			ret = PTR_ERR(conn_state);
4483			break;
4484		}
4485
4486		crtc = to_intel_crtc(conn_state->crtc);
4487
4488		if (!crtc)
4489			continue;
4490
4491		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4492		crtc_state->uapi.mode_changed = true;
4493
4494		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4495		if (ret)
4496			break;
4497	}
4498	drm_connector_list_iter_end(&conn_iter);
4499
4500	return ret;
4501}
4502
4503static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4504{
4505	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4506	struct intel_crtc *crtc;
4507
4508	if (transcoders == 0)
4509		return 0;
4510
4511	for_each_intel_crtc(&dev_priv->drm, crtc) {
4512		struct intel_crtc_state *crtc_state;
4513		int ret;
4514
4515		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4516		if (IS_ERR(crtc_state))
4517			return PTR_ERR(crtc_state);
4518
4519		if (!crtc_state->hw.enable)
4520			continue;
4521
4522		if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4523			continue;
4524
4525		crtc_state->uapi.mode_changed = true;
4526
4527		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4528		if (ret)
4529			return ret;
4530
4531		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4532		if (ret)
4533			return ret;
4534
4535		transcoders &= ~BIT(crtc_state->cpu_transcoder);
4536	}
4537
4538	drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4539
4540	return 0;
4541}
4542
4543static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4544				      struct drm_connector *connector)
4545{
4546	const struct drm_connector_state *old_conn_state =
4547		drm_atomic_get_old_connector_state(&state->base, connector);
4548	const struct intel_crtc_state *old_crtc_state;
4549	struct intel_crtc *crtc;
4550	u8 transcoders;
4551
4552	crtc = to_intel_crtc(old_conn_state->crtc);
4553	if (!crtc)
4554		return 0;
4555
4556	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4557
4558	if (!old_crtc_state->hw.active)
4559		return 0;
4560
4561	transcoders = old_crtc_state->sync_mode_slaves_mask;
4562	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4563		transcoders |= BIT(old_crtc_state->master_transcoder);
4564
4565	return intel_modeset_affected_transcoders(state,
4566						  transcoders);
4567}
4568
4569static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4570					   struct drm_atomic_state *_state)
4571{
4572	struct drm_i915_private *dev_priv = to_i915(conn->dev);
4573	struct intel_atomic_state *state = to_intel_atomic_state(_state);
4574	int ret;
4575
4576	ret = intel_digital_connector_atomic_check(conn, &state->base);
4577	if (ret)
4578		return ret;
4579
4580	/*
4581	 * We don't enable port sync on BDW due to missing w/as and
4582	 * due to not having adjusted the modeset sequence appropriately.
4583	 */
4584	if (DISPLAY_VER(dev_priv) < 9)
4585		return 0;
4586
4587	if (!intel_connector_needs_modeset(state, conn))
4588		return 0;
4589
4590	if (conn->has_tile) {
4591		ret = intel_modeset_tile_group(state, conn->tile_group->id);
4592		if (ret)
4593			return ret;
4594	}
4595
4596	return intel_modeset_synced_crtcs(state, conn);
4597}
4598
4599static const struct drm_connector_funcs intel_dp_connector_funcs = {
4600	.force = intel_dp_force,
4601	.fill_modes = drm_helper_probe_single_connector_modes,
4602	.atomic_get_property = intel_digital_connector_atomic_get_property,
4603	.atomic_set_property = intel_digital_connector_atomic_set_property,
4604	.late_register = intel_dp_connector_register,
4605	.early_unregister = intel_dp_connector_unregister,
4606	.destroy = intel_connector_destroy,
4607	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4608	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
4609};
4610
4611static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4612	.detect_ctx = intel_dp_detect,
4613	.get_modes = intel_dp_get_modes,
4614	.mode_valid = intel_dp_mode_valid,
4615	.atomic_check = intel_dp_connector_atomic_check,
4616};
4617
4618enum irqreturn
4619intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
4620{
4621	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4622	struct intel_dp *intel_dp = &dig_port->dp;
4623
4624	if (dig_port->base.type == INTEL_OUTPUT_EDP &&
4625	    (long_hpd || !intel_pps_have_power(intel_dp))) {
4626		/*
4627		 * vdd off can generate a long/short pulse on eDP which
4628		 * would require vdd on to handle it, and thus we
4629		 * would end up in an endless cycle of
4630		 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
4631		 */
4632		drm_dbg_kms(&i915->drm,
4633			    "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
4634			    long_hpd ? "long" : "short",
4635			    dig_port->base.base.base.id,
4636			    dig_port->base.base.name);
4637		return IRQ_HANDLED;
4638	}
4639
4640	drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
4641		    dig_port->base.base.base.id,
4642		    dig_port->base.base.name,
4643		    long_hpd ? "long" : "short");
4644
4645	if (long_hpd) {
4646		intel_dp->reset_link_params = true;
4647		return IRQ_NONE;
4648	}
4649
4650	if (intel_dp->is_mst) {
4651		if (!intel_dp_check_mst_status(intel_dp))
4652			return IRQ_NONE;
4653	} else if (!intel_dp_short_pulse(intel_dp)) {
4654		return IRQ_NONE;
4655	}
4656
4657	return IRQ_HANDLED;
4658}
4659
4660/* check the VBT to see whether the eDP is on another port */
4661bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
4662{
4663	/*
4664	 * eDP not supported on g4x. so bail out early just
4665	 * for a bit extra safety in case the VBT is bonkers.
4666	 */
4667	if (DISPLAY_VER(dev_priv) < 5)
4668		return false;
4669
4670	if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
4671		return true;
4672
4673	return intel_bios_is_port_edp(dev_priv, port);
4674}
4675
4676static void
4677intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4678{
4679	struct drm_i915_private *dev_priv = to_i915(connector->dev);
4680	enum port port = dp_to_dig_port(intel_dp)->base.port;
4681
4682	if (!intel_dp_is_edp(intel_dp))
4683		drm_connector_attach_dp_subconnector_property(connector);
4684
4685	if (!IS_G4X(dev_priv) && port != PORT_A)
4686		intel_attach_force_audio_property(connector);
4687
4688	intel_attach_broadcast_rgb_property(connector);
4689	if (HAS_GMCH(dev_priv))
4690		drm_connector_attach_max_bpc_property(connector, 6, 10);
4691	else if (DISPLAY_VER(dev_priv) >= 5)
4692		drm_connector_attach_max_bpc_property(connector, 6, 12);
4693
4694	/* Register HDMI colorspace for case of lspcon */
4695	if (intel_bios_is_lspcon_present(dev_priv, port)) {
4696		drm_connector_attach_content_type_property(connector);
4697		intel_attach_hdmi_colorspace_property(connector);
4698	} else {
4699		intel_attach_dp_colorspace_property(connector);
4700	}
4701
4702	if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
4703		drm_object_attach_property(&connector->base,
4704					   connector->dev->mode_config.hdr_output_metadata_property,
4705					   0);
4706
4707	if (intel_dp_is_edp(intel_dp)) {
4708		u32 allowed_scalers;
4709
4710		allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
4711		if (!HAS_GMCH(dev_priv))
4712			allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
4713
4714		drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
4715
4716		connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
4717
4718	}
4719
4720	if (HAS_VRR(dev_priv))
4721		drm_connector_attach_vrr_capable_property(connector);
4722}
4723
4724/**
4725 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4726 * @dev_priv: i915 device
4727 * @crtc_state: a pointer to the active intel_crtc_state
4728 * @refresh_rate: RR to be programmed
4729 *
4730 * This function gets called when refresh rate (RR) has to be changed from
4731 * one frequency to another. Switches can be between high and low RR
4732 * supported by the panel or to any other RR based on media playback (in
4733 * this case, RR value needs to be passed from user space).
4734 *
4735 * The caller of this function needs to take a lock on dev_priv->drrs.
4736 */
4737static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
4738				    const struct intel_crtc_state *crtc_state,
4739				    int refresh_rate)
4740{
4741	struct intel_dp *intel_dp = dev_priv->drrs.dp;
4742	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4743	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4744
4745	if (refresh_rate <= 0) {
4746		drm_dbg_kms(&dev_priv->drm,
4747			    "Refresh rate should be positive non-zero.\n");
4748		return;
4749	}
4750
4751	if (intel_dp == NULL) {
4752		drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
4753		return;
4754	}
4755
4756	if (!intel_crtc) {
4757		drm_dbg_kms(&dev_priv->drm,
4758			    "DRRS: intel_crtc not initialized\n");
4759		return;
4760	}
4761
4762	if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4763		drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
4764		return;
4765	}
4766
4767	if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
4768			refresh_rate)
4769		index = DRRS_LOW_RR;
4770
4771	if (index == dev_priv->drrs.refresh_rate_type) {
4772		drm_dbg_kms(&dev_priv->drm,
4773			    "DRRS requested for previously set RR...ignoring\n");
4774		return;
4775	}
4776
4777	if (!crtc_state->hw.active) {
4778		drm_dbg_kms(&dev_priv->drm,
4779			    "eDP encoder disabled. CRTC not Active\n");
4780		return;
4781	}
4782
4783	if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
4784		switch (index) {
4785		case DRRS_HIGH_RR:
4786			intel_dp_set_m_n(crtc_state, M1_N1);
4787			break;
4788		case DRRS_LOW_RR:
4789			intel_dp_set_m_n(crtc_state, M2_N2);
4790			break;
4791		case DRRS_MAX_RR:
4792		default:
4793			drm_err(&dev_priv->drm,
4794				"Unsupported refreshrate type\n");
4795		}
4796	} else if (DISPLAY_VER(dev_priv) > 6) {
4797		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
4798		u32 val;
4799
4800		val = intel_de_read(dev_priv, reg);
4801		if (index > DRRS_HIGH_RR) {
4802			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4803				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4804			else
4805				val |= PIPECONF_EDP_RR_MODE_SWITCH;
4806		} else {
4807			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4808				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4809			else
4810				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4811		}
4812		intel_de_write(dev_priv, reg, val);
4813	}
4814
4815	dev_priv->drrs.refresh_rate_type = index;
4816
4817	drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
4818		    refresh_rate);
4819}
4820
4821static void
4822intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
4823{
4824	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4825
4826	dev_priv->drrs.busy_frontbuffer_bits = 0;
4827	dev_priv->drrs.dp = intel_dp;
4828}
4829
4830/**
4831 * intel_edp_drrs_enable - init drrs struct if supported
4832 * @intel_dp: DP struct
4833 * @crtc_state: A pointer to the active crtc state.
4834 *
4835 * Initializes frontbuffer_bits and drrs.dp
4836 */
4837void intel_edp_drrs_enable(struct intel_dp *intel_dp,
4838			   const struct intel_crtc_state *crtc_state)
4839{
4840	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4841
4842	if (!crtc_state->has_drrs)
4843		return;
4844
4845	drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
4846
4847	mutex_lock(&dev_priv->drrs.mutex);
4848
4849	if (dev_priv->drrs.dp) {
4850		drm_warn(&dev_priv->drm, "DRRS already enabled\n");
4851		goto unlock;
4852	}
4853
4854	intel_edp_drrs_enable_locked(intel_dp);
4855
4856unlock:
4857	mutex_unlock(&dev_priv->drrs.mutex);
4858}
4859
4860static void
4861intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
4862			      const struct intel_crtc_state *crtc_state)
4863{
4864	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4865
4866	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4867		int refresh;
4868
4869		refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
4870		intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
4871	}
4872
4873	dev_priv->drrs.dp = NULL;
4874}
4875
4876/**
4877 * intel_edp_drrs_disable - Disable DRRS
4878 * @intel_dp: DP struct
4879 * @old_crtc_state: Pointer to old crtc_state.
4880 *
4881 */
4882void intel_edp_drrs_disable(struct intel_dp *intel_dp,
4883			    const struct intel_crtc_state *old_crtc_state)
4884{
4885	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4886
4887	if (!old_crtc_state->has_drrs)
4888		return;
4889
4890	mutex_lock(&dev_priv->drrs.mutex);
4891	if (!dev_priv->drrs.dp) {
4892		mutex_unlock(&dev_priv->drrs.mutex);
4893		return;
4894	}
4895
4896	intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
4897	mutex_unlock(&dev_priv->drrs.mutex);
4898
4899	cancel_delayed_work_sync(&dev_priv->drrs.work);
4900}
4901
4902/**
4903 * intel_edp_drrs_update - Update DRRS state
4904 * @intel_dp: Intel DP
4905 * @crtc_state: new CRTC state
4906 *
4907 * This function will update DRRS states, disabling or enabling DRRS when
4908 * executing fastsets. For full modeset, intel_edp_drrs_disable() and
4909 * intel_edp_drrs_enable() should be called instead.
4910 */
4911void
4912intel_edp_drrs_update(struct intel_dp *intel_dp,
4913		      const struct intel_crtc_state *crtc_state)
4914{
4915	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4916
4917	if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
4918		return;
4919
4920	mutex_lock(&dev_priv->drrs.mutex);
4921
4922	/* New state matches current one? */
4923	if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
4924		goto unlock;
4925
4926	if (crtc_state->has_drrs)
4927		intel_edp_drrs_enable_locked(intel_dp);
4928	else
4929		intel_edp_drrs_disable_locked(intel_dp, crtc_state);
4930
4931unlock:
4932	mutex_unlock(&dev_priv->drrs.mutex);
4933}
4934
4935static void intel_edp_drrs_downclock_work(struct work_struct *work)
4936{
4937	struct drm_i915_private *dev_priv =
4938		container_of(work, typeof(*dev_priv), drrs.work.work);
4939	struct intel_dp *intel_dp;
4940
4941	mutex_lock(&dev_priv->drrs.mutex);
4942
4943	intel_dp = dev_priv->drrs.dp;
4944
4945	if (!intel_dp)
4946		goto unlock;
4947
4948	/*
4949	 * The delayed work can race with an invalidate hence we need to
4950	 * recheck.
4951	 */
4952
4953	if (dev_priv->drrs.busy_frontbuffer_bits)
4954		goto unlock;
4955
4956	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
4957		struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4958
4959		intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
4960			drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
4961	}
4962
4963unlock:
4964	mutex_unlock(&dev_priv->drrs.mutex);
4965}
4966
4967/**
4968 * intel_edp_drrs_invalidate - Disable Idleness DRRS
4969 * @dev_priv: i915 device
4970 * @frontbuffer_bits: frontbuffer plane tracking bits
4971 *
4972 * This function gets called everytime rendering on the given planes start.
4973 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
4974 *
4975 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4976 */
4977void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
4978			       unsigned int frontbuffer_bits)
4979{
4980	struct intel_dp *intel_dp;
4981	struct drm_crtc *crtc;
4982	enum pipe pipe;
4983
4984	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
4985		return;
4986
4987	cancel_delayed_work(&dev_priv->drrs.work);
4988
4989	mutex_lock(&dev_priv->drrs.mutex);
4990
4991	intel_dp = dev_priv->drrs.dp;
4992	if (!intel_dp) {
4993		mutex_unlock(&dev_priv->drrs.mutex);
4994		return;
4995	}
4996
4997	crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4998	pipe = to_intel_crtc(crtc)->pipe;
4999
5000	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5001	dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5002
5003	/* invalidate means busy screen hence upclock */
5004	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5005		intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5006					drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5007
5008	mutex_unlock(&dev_priv->drrs.mutex);
5009}
5010
5011/**
5012 * intel_edp_drrs_flush - Restart Idleness DRRS
5013 * @dev_priv: i915 device
5014 * @frontbuffer_bits: frontbuffer plane tracking bits
5015 *
5016 * This function gets called every time rendering on the given planes has
5017 * completed or flip on a crtc is completed. So DRRS should be upclocked
5018 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5019 * if no other planes are dirty.
5020 *
5021 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5022 */
5023void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5024			  unsigned int frontbuffer_bits)
5025{
5026	struct intel_dp *intel_dp;
5027	struct drm_crtc *crtc;
5028	enum pipe pipe;
5029
5030	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5031		return;
5032
5033	cancel_delayed_work(&dev_priv->drrs.work);
5034
5035	mutex_lock(&dev_priv->drrs.mutex);
5036
5037	intel_dp = dev_priv->drrs.dp;
5038	if (!intel_dp) {
5039		mutex_unlock(&dev_priv->drrs.mutex);
5040		return;
5041	}
5042
5043	crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5044	pipe = to_intel_crtc(crtc)->pipe;
5045
5046	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5047	dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5048
5049	/* flush means busy screen hence upclock */
5050	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5051		intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5052					drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5053
5054	/*
5055	 * flush also means no more activity hence schedule downclock, if all
5056	 * other fbs are quiescent too
5057	 */
5058	if (!dev_priv->drrs.busy_frontbuffer_bits)
5059		schedule_delayed_work(&dev_priv->drrs.work,
5060				msecs_to_jiffies(1000));
5061	mutex_unlock(&dev_priv->drrs.mutex);
5062}
5063
5064/**
5065 * DOC: Display Refresh Rate Switching (DRRS)
5066 *
5067 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5068 * which enables swtching between low and high refresh rates,
5069 * dynamically, based on the usage scenario. This feature is applicable
5070 * for internal panels.
5071 *
5072 * Indication that the panel supports DRRS is given by the panel EDID, which
5073 * would list multiple refresh rates for one resolution.
5074 *
5075 * DRRS is of 2 types - static and seamless.
5076 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5077 * (may appear as a blink on screen) and is used in dock-undock scenario.
5078 * Seamless DRRS involves changing RR without any visual effect to the user
5079 * and can be used during normal system usage. This is done by programming
5080 * certain registers.
5081 *
5082 * Support for static/seamless DRRS may be indicated in the VBT based on
5083 * inputs from the panel spec.
5084 *
5085 * DRRS saves power by switching to low RR based on usage scenarios.
5086 *
5087 * The implementation is based on frontbuffer tracking implementation.  When
5088 * there is a disturbance on the screen triggered by user activity or a periodic
5089 * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5090 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5091 * made.
5092 *
5093 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5094 * and intel_edp_drrs_flush() are called.
5095 *
5096 * DRRS can be further extended to support other internal panels and also
5097 * the scenario of video playback wherein RR is set based on the rate
5098 * requested by userspace.
5099 */
5100
5101/**
5102 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5103 * @connector: eDP connector
5104 * @fixed_mode: preferred mode of panel
5105 *
5106 * This function is  called only once at driver load to initialize basic
5107 * DRRS stuff.
5108 *
5109 * Returns:
5110 * Downclock mode if panel supports it, else return NULL.
5111 * DRRS support is determined by the presence of downclock mode (apart
5112 * from VBT setting).
5113 */
5114static struct drm_display_mode *
5115intel_dp_drrs_init(struct intel_connector *connector,
5116		   struct drm_display_mode *fixed_mode)
5117{
5118	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5119	struct drm_display_mode *downclock_mode = NULL;
5120
5121	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5122	mutex_init(&dev_priv->drrs.mutex);
5123
5124	if (DISPLAY_VER(dev_priv) <= 6) {
5125		drm_dbg_kms(&dev_priv->drm,
5126			    "DRRS supported for Gen7 and above\n");
5127		return NULL;
5128	}
5129
5130	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5131		drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
5132		return NULL;
5133	}
5134
5135	downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
5136	if (!downclock_mode) {
5137		drm_dbg_kms(&dev_priv->drm,
5138			    "Downclock mode is not found. DRRS not supported\n");
5139		return NULL;
5140	}
5141
5142	dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5143
5144	dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5145	drm_dbg_kms(&dev_priv->drm,
5146		    "seamless DRRS supported for eDP panel.\n");
5147	return downclock_mode;
5148}
5149
5150static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5151				     struct intel_connector *intel_connector)
5152{
5153	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5154	struct drm_device *dev = &dev_priv->drm;
5155	struct drm_connector *connector = &intel_connector->base;
5156	struct drm_display_mode *fixed_mode = NULL;
5157	struct drm_display_mode *downclock_mode = NULL;
5158	bool has_dpcd;
5159	enum pipe pipe = INVALID_PIPE;
5160	struct edid *edid;
5161
5162	if (!intel_dp_is_edp(intel_dp))
5163		return true;
5164
5165	/*
5166	 * On IBX/CPT we may get here with LVDS already registered. Since the
5167	 * driver uses the only internal power sequencer available for both
5168	 * eDP and LVDS bail out early in this case to prevent interfering
5169	 * with an already powered-on LVDS power sequencer.
5170	 */
5171	if (intel_get_lvds_encoder(dev_priv)) {
5172		drm_WARN_ON(dev,
5173			    !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5174		drm_info(&dev_priv->drm,
5175			 "LVDS was detected, not registering eDP\n");
5176
5177		return false;
5178	}
5179
5180	intel_pps_init(intel_dp);
5181
5182	/* Cache DPCD and EDID for edp. */
5183	has_dpcd = intel_edp_init_dpcd(intel_dp);
5184
5185	if (!has_dpcd) {
5186		/* if this fails, presume the device is a ghost */
5187		drm_info(&dev_priv->drm,
5188			 "failed to retrieve link info, disabling eDP\n");
5189		goto out_vdd_off;
5190	}
5191
5192	mutex_lock(&dev->mode_config.mutex);
5193	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5194	if (edid) {
5195		if (drm_add_edid_modes(connector, edid)) {
5196			drm_connector_update_edid_property(connector, edid);
5197		} else {
5198			kfree(edid);
5199			edid = ERR_PTR(-EINVAL);
5200		}
5201	} else {
5202		edid = ERR_PTR(-ENOENT);
5203	}
5204	intel_connector->edid = edid;
5205
5206	fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
5207	if (fixed_mode)
5208		downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
5209
5210	/* multiply the mode clock and horizontal timings for MSO */
5211	intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5212	intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
5213
5214	/* fallback to VBT if available for eDP */
5215	if (!fixed_mode)
5216		fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
5217	mutex_unlock(&dev->mode_config.mutex);
5218
5219	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5220		/*
5221		 * Figure out the current pipe for the initial backlight setup.
5222		 * If the current pipe isn't valid, try the PPS pipe, and if that
5223		 * fails just assume pipe A.
5224		 */
5225		pipe = vlv_active_pipe(intel_dp);
5226
5227		if (pipe != PIPE_A && pipe != PIPE_B)
5228			pipe = intel_dp->pps.pps_pipe;
5229
5230		if (pipe != PIPE_A && pipe != PIPE_B)
5231			pipe = PIPE_A;
5232
5233		drm_dbg_kms(&dev_priv->drm,
5234			    "using pipe %c for initial backlight setup\n",
5235			    pipe_name(pipe));
5236	}
5237
5238	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5239	intel_connector->panel.backlight.power = intel_pps_backlight_power;
5240	intel_panel_setup_backlight(connector, pipe);
5241
5242	if (fixed_mode) {
5243		drm_connector_set_panel_orientation_with_quirk(connector,
5244				dev_priv->vbt.orientation,
5245				fixed_mode->hdisplay, fixed_mode->vdisplay);
5246	}
5247
5248	return true;
5249
5250out_vdd_off:
5251	intel_pps_vdd_off_sync(intel_dp);
5252
5253	return false;
5254}
5255
5256static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5257{
5258	struct intel_connector *intel_connector;
5259	struct drm_connector *connector;
5260
5261	intel_connector = container_of(work, typeof(*intel_connector),
5262				       modeset_retry_work);
5263	connector = &intel_connector->base;
5264	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5265		      connector->name);
5266
5267	/* Grab the locks before changing connector property*/
5268	mutex_lock(&connector->dev->mode_config.mutex);
5269	/* Set connector link status to BAD and send a Uevent to notify
5270	 * userspace to do a modeset.
5271	 */
5272	drm_connector_set_link_status_property(connector,
5273					       DRM_MODE_LINK_STATUS_BAD);
5274	mutex_unlock(&connector->dev->mode_config.mutex);
5275	/* Send Hotplug uevent so userspace can reprobe */
5276	drm_kms_helper_hotplug_event(connector->dev);
5277}
5278
5279bool
5280intel_dp_init_connector(struct intel_digital_port *dig_port,
5281			struct intel_connector *intel_connector)
5282{
5283	struct drm_connector *connector = &intel_connector->base;
5284	struct intel_dp *intel_dp = &dig_port->dp;
5285	struct intel_encoder *intel_encoder = &dig_port->base;
5286	struct drm_device *dev = intel_encoder->base.dev;
5287	struct drm_i915_private *dev_priv = to_i915(dev);
5288	enum port port = intel_encoder->port;
5289	enum phy phy = intel_port_to_phy(dev_priv, port);
5290	int type;
5291
5292	/* Initialize the work for modeset in case of link train failure */
5293	INIT_WORK(&intel_connector->modeset_retry_work,
5294		  intel_dp_modeset_retry_work_fn);
5295
5296	if (drm_WARN(dev, dig_port->max_lanes < 1,
5297		     "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5298		     dig_port->max_lanes, intel_encoder->base.base.id,
5299		     intel_encoder->base.name))
5300		return false;
5301
5302	intel_dp_set_source_rates(intel_dp);
5303
5304	intel_dp->reset_link_params = true;
5305	intel_dp->pps.pps_pipe = INVALID_PIPE;
5306	intel_dp->pps.active_pipe = INVALID_PIPE;
5307
5308	/* Preserve the current hw state. */
5309	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5310	intel_dp->attached_connector = intel_connector;
5311
5312	if (intel_dp_is_port_edp(dev_priv, port)) {
5313		/*
5314		 * Currently we don't support eDP on TypeC ports, although in
5315		 * theory it could work on TypeC legacy ports.
5316		 */
5317		drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5318		type = DRM_MODE_CONNECTOR_eDP;
5319	} else {
5320		type = DRM_MODE_CONNECTOR_DisplayPort;
5321	}
5322
5323	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5324		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5325
5326	/*
5327	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5328	 * for DP the encoder type can be set by the caller to
5329	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5330	 */
5331	if (type == DRM_MODE_CONNECTOR_eDP)
5332		intel_encoder->type = INTEL_OUTPUT_EDP;
5333
5334	/* eDP only on port B and/or C on vlv/chv */
5335	if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5336			      IS_CHERRYVIEW(dev_priv)) &&
5337			intel_dp_is_edp(intel_dp) &&
5338			port != PORT_B && port != PORT_C))
5339		return false;
5340
5341	drm_dbg_kms(&dev_priv->drm,
5342		    "Adding %s connector on [ENCODER:%d:%s]\n",
5343		    type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5344		    intel_encoder->base.base.id, intel_encoder->base.name);
5345
5346	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5347	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5348
5349	if (!HAS_GMCH(dev_priv))
5350		connector->interlace_allowed = true;
5351	connector->doublescan_allowed = 0;
5352
5353	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5354
5355	intel_dp_aux_init(intel_dp);
5356
5357	intel_connector_attach_encoder(intel_connector, intel_encoder);
5358
5359	if (HAS_DDI(dev_priv))
5360		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5361	else
5362		intel_connector->get_hw_state = intel_connector_get_hw_state;
5363
5364	/* init MST on ports that can support it */
5365	intel_dp_mst_encoder_init(dig_port,
5366				  intel_connector->base.base.id);
5367
5368	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5369		intel_dp_aux_fini(intel_dp);
5370		intel_dp_mst_encoder_cleanup(dig_port);
5371		goto fail;
5372	}
5373
5374	intel_dp_add_properties(intel_dp, connector);
5375
5376	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5377		int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5378		if (ret)
5379			drm_dbg_kms(&dev_priv->drm,
5380				    "HDCP init failed, skipping.\n");
5381	}
5382
5383	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5384	 * 0xd.  Failure to do so will result in spurious interrupts being
5385	 * generated on the port when a cable is not attached.
5386	 */
5387	if (IS_G45(dev_priv)) {
5388		u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5389		intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5390			       (temp & ~0xf) | 0xd);
5391	}
5392
5393	intel_dp->frl.is_trained = false;
5394	intel_dp->frl.trained_rate_gbps = 0;
5395
5396	intel_psr_init(intel_dp);
5397
5398	return true;
5399
5400fail:
5401	drm_connector_cleanup(connector);
5402
5403	return false;
5404}
5405
5406void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5407{
5408	struct intel_encoder *encoder;
5409
5410	if (!HAS_DISPLAY(dev_priv))
5411		return;
5412
5413	for_each_intel_encoder(&dev_priv->drm, encoder) {
5414		struct intel_dp *intel_dp;
5415
5416		if (encoder->type != INTEL_OUTPUT_DDI)
5417			continue;
5418
5419		intel_dp = enc_to_intel_dp(encoder);
5420
5421		if (!intel_dp->can_mst)
5422			continue;
5423
5424		if (intel_dp->is_mst)
5425			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5426	}
5427}
5428
5429void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5430{
5431	struct intel_encoder *encoder;
5432
5433	if (!HAS_DISPLAY(dev_priv))
5434		return;
5435
5436	for_each_intel_encoder(&dev_priv->drm, encoder) {
5437		struct intel_dp *intel_dp;
5438		int ret;
5439
5440		if (encoder->type != INTEL_OUTPUT_DDI)
5441			continue;
5442
5443		intel_dp = enc_to_intel_dp(encoder);
5444
5445		if (!intel_dp->can_mst)
5446			continue;
5447
5448		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5449						     true);
5450		if (ret) {
5451			intel_dp->is_mst = false;
5452			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5453							false);
5454		}
5455	}
5456}