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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_psp.h"
25#include "amdgpu_ucode.h"
26#include "soc15_common.h"
27#include "psp_v13_0.h"
28
29#include "mp/mp_13_0_2_offset.h"
30#include "mp/mp_13_0_2_sh_mask.h"
31
32MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
33MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
34MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
35MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
36MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
37
38static int psp_v13_0_init_microcode(struct psp_context *psp)
39{
40 struct amdgpu_device *adev = psp->adev;
41 const char *chip_name;
42 int err = 0;
43
44 switch (adev->asic_type) {
45 case CHIP_ALDEBARAN:
46 chip_name = "aldebaran";
47 break;
48 case CHIP_YELLOW_CARP:
49 chip_name = "yellow_carp";
50 break;
51 default:
52 BUG();
53 }
54 switch (adev->asic_type) {
55 case CHIP_ALDEBARAN:
56 err = psp_init_sos_microcode(psp, chip_name);
57 if (err)
58 return err;
59 err = psp_init_ta_microcode(&adev->psp, chip_name);
60 if (err)
61 return err;
62 break;
63 case CHIP_YELLOW_CARP:
64 err = psp_init_asd_microcode(psp, chip_name);
65 if (err)
66 return err;
67 err = psp_init_toc_microcode(psp, chip_name);
68 if (err)
69 return err;
70 err = psp_init_ta_microcode(psp, chip_name);
71 if (err)
72 return err;
73 break;
74 default:
75 BUG();
76 }
77
78 return 0;
79}
80
81static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
82{
83 struct amdgpu_device *adev = psp->adev;
84 uint32_t sol_reg;
85
86 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
87
88 return sol_reg != 0x0;
89}
90
91static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
92{
93 struct amdgpu_device *adev = psp->adev;
94
95 int ret;
96 int retry_loop;
97
98 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
99 /* Wait for bootloader to signify that is
100 ready having bit 31 of C2PMSG_35 set to 1 */
101 ret = psp_wait_for(psp,
102 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
103 0x80000000,
104 0x80000000,
105 false);
106
107 if (ret == 0)
108 return 0;
109 }
110
111 return ret;
112}
113
114static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
115{
116 int ret;
117 uint32_t psp_gfxdrv_command_reg = 0;
118 struct amdgpu_device *adev = psp->adev;
119
120 /* Check tOS sign of life register to confirm sys driver and sOS
121 * are already been loaded.
122 */
123 if (psp_v13_0_is_sos_alive(psp))
124 return 0;
125
126 ret = psp_v13_0_wait_for_bootloader(psp);
127 if (ret)
128 return ret;
129
130 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
131
132 /* Copy PSP KDB binary to memory */
133 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
134
135 /* Provide the PSP KDB to bootloader */
136 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
137 (uint32_t)(psp->fw_pri_mc_addr >> 20));
138 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
139 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
140 psp_gfxdrv_command_reg);
141
142 ret = psp_v13_0_wait_for_bootloader(psp);
143
144 return ret;
145}
146
147static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
148{
149 int ret;
150 uint32_t psp_gfxdrv_command_reg = 0;
151 struct amdgpu_device *adev = psp->adev;
152
153 /* Check sOS sign of life register to confirm sys driver and sOS
154 * are already been loaded.
155 */
156 if (psp_v13_0_is_sos_alive(psp))
157 return 0;
158
159 ret = psp_v13_0_wait_for_bootloader(psp);
160 if (ret)
161 return ret;
162
163 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
164
165 /* Copy PSP System Driver binary to memory */
166 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
167
168 /* Provide the sys driver to bootloader */
169 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
170 (uint32_t)(psp->fw_pri_mc_addr >> 20));
171 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
172 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
173 psp_gfxdrv_command_reg);
174
175 /* there might be handshake issue with hardware which needs delay */
176 mdelay(20);
177
178 ret = psp_v13_0_wait_for_bootloader(psp);
179
180 return ret;
181}
182
183static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
184{
185 int ret;
186 unsigned int psp_gfxdrv_command_reg = 0;
187 struct amdgpu_device *adev = psp->adev;
188
189 /* Check sOS sign of life register to confirm sys driver and sOS
190 * are already been loaded.
191 */
192 if (psp_v13_0_is_sos_alive(psp))
193 return 0;
194
195 ret = psp_v13_0_wait_for_bootloader(psp);
196 if (ret)
197 return ret;
198
199 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
200
201 /* Copy Secure OS binary to PSP memory */
202 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
203
204 /* Provide the PSP secure OS to bootloader */
205 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
206 (uint32_t)(psp->fw_pri_mc_addr >> 20));
207 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
208 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
209 psp_gfxdrv_command_reg);
210
211 /* there might be handshake issue with hardware which needs delay */
212 mdelay(20);
213 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
214 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
215 0, true);
216
217 return ret;
218}
219
220static int psp_v13_0_ring_init(struct psp_context *psp,
221 enum psp_ring_type ring_type)
222{
223 int ret = 0;
224 struct psp_ring *ring;
225 struct amdgpu_device *adev = psp->adev;
226
227 ring = &psp->km_ring;
228
229 ring->ring_type = ring_type;
230
231 /* allocate 4k Page of Local Frame Buffer memory for ring */
232 ring->ring_size = 0x1000;
233 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
234 AMDGPU_GEM_DOMAIN_VRAM,
235 &adev->firmware.rbuf,
236 &ring->ring_mem_mc_addr,
237 (void **)&ring->ring_mem);
238 if (ret) {
239 ring->ring_size = 0;
240 return ret;
241 }
242
243 return 0;
244}
245
246static int psp_v13_0_ring_stop(struct psp_context *psp,
247 enum psp_ring_type ring_type)
248{
249 int ret = 0;
250 struct amdgpu_device *adev = psp->adev;
251
252 if (amdgpu_sriov_vf(adev)) {
253 /* Write the ring destroy command*/
254 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
255 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
256 /* there might be handshake issue with hardware which needs delay */
257 mdelay(20);
258 /* Wait for response flag (bit 31) */
259 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
260 0x80000000, 0x80000000, false);
261 } else {
262 /* Write the ring destroy command*/
263 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
264 GFX_CTRL_CMD_ID_DESTROY_RINGS);
265 /* there might be handshake issue with hardware which needs delay */
266 mdelay(20);
267 /* Wait for response flag (bit 31) */
268 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
269 0x80000000, 0x80000000, false);
270 }
271
272 return ret;
273}
274
275static int psp_v13_0_ring_create(struct psp_context *psp,
276 enum psp_ring_type ring_type)
277{
278 int ret = 0;
279 unsigned int psp_ring_reg = 0;
280 struct psp_ring *ring = &psp->km_ring;
281 struct amdgpu_device *adev = psp->adev;
282
283 if (amdgpu_sriov_vf(adev)) {
284 ret = psp_v13_0_ring_stop(psp, ring_type);
285 if (ret) {
286 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
287 return ret;
288 }
289
290 /* Write low address of the ring to C2PMSG_102 */
291 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
292 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
293 /* Write high address of the ring to C2PMSG_103 */
294 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
295 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
296
297 /* Write the ring initialization command to C2PMSG_101 */
298 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
299 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
300
301 /* there might be handshake issue with hardware which needs delay */
302 mdelay(20);
303
304 /* Wait for response flag (bit 31) in C2PMSG_101 */
305 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
306 0x80000000, 0x8000FFFF, false);
307
308 } else {
309 /* Wait for sOS ready for ring creation */
310 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
311 0x80000000, 0x80000000, false);
312 if (ret) {
313 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
314 return ret;
315 }
316
317 /* Write low address of the ring to C2PMSG_69 */
318 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
319 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
320 /* Write high address of the ring to C2PMSG_70 */
321 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
322 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
323 /* Write size of ring to C2PMSG_71 */
324 psp_ring_reg = ring->ring_size;
325 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
326 /* Write the ring initialization command to C2PMSG_64 */
327 psp_ring_reg = ring_type;
328 psp_ring_reg = psp_ring_reg << 16;
329 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
330
331 /* there might be handshake issue with hardware which needs delay */
332 mdelay(20);
333
334 /* Wait for response flag (bit 31) in C2PMSG_64 */
335 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
336 0x80000000, 0x8000FFFF, false);
337 }
338
339 return ret;
340}
341
342static int psp_v13_0_ring_destroy(struct psp_context *psp,
343 enum psp_ring_type ring_type)
344{
345 int ret = 0;
346 struct psp_ring *ring = &psp->km_ring;
347 struct amdgpu_device *adev = psp->adev;
348
349 ret = psp_v13_0_ring_stop(psp, ring_type);
350 if (ret)
351 DRM_ERROR("Fail to stop psp ring\n");
352
353 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
354 &ring->ring_mem_mc_addr,
355 (void **)&ring->ring_mem);
356
357 return ret;
358}
359
360static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
361{
362 uint32_t data;
363 struct amdgpu_device *adev = psp->adev;
364
365 if (amdgpu_sriov_vf(adev))
366 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
367 else
368 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
369
370 return data;
371}
372
373static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
374{
375 struct amdgpu_device *adev = psp->adev;
376
377 if (amdgpu_sriov_vf(adev)) {
378 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
379 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
380 GFX_CTRL_CMD_ID_CONSUME_CMD);
381 } else
382 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
383}
384
385static const struct psp_funcs psp_v13_0_funcs = {
386 .init_microcode = psp_v13_0_init_microcode,
387 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
388 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
389 .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
390 .ring_init = psp_v13_0_ring_init,
391 .ring_create = psp_v13_0_ring_create,
392 .ring_stop = psp_v13_0_ring_stop,
393 .ring_destroy = psp_v13_0_ring_destroy,
394 .ring_get_wptr = psp_v13_0_ring_get_wptr,
395 .ring_set_wptr = psp_v13_0_ring_set_wptr,
396};
397
398void psp_v13_0_set_psp_funcs(struct psp_context *psp)
399{
400 psp->funcs = &psp_v13_0_funcs;
401}