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1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/gpio/gpio.h>
3#include <dt-bindings/interrupt-controller/irq.h>
4
5#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
6
7/ {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "marvell,dove";
11 model = "Marvell Armada 88AP510 SoC";
12 interrupt-parent = <&intc>;
13
14 aliases {
15 gpio0 = &gpio0;
16 gpio1 = &gpio1;
17 gpio2 = &gpio2;
18 };
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu0: cpu@0 {
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
26 device_type = "cpu";
27 next-level-cache = <&l2>;
28 reg = <0>;
29 };
30 };
31
32 l2: l2-cache {
33 compatible = "marvell,tauros2-cache";
34 marvell,tauros2-cache-features = <0>;
35 };
36
37 gpu-subsystem {
38 compatible = "marvell,dove-gpu-subsystem";
39 cores = <&gpu>;
40 status = "disabled";
41 };
42
43 i2c-mux {
44 compatible = "i2c-mux-pinctrl";
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 i2c-parent = <&i2c>;
49
50 pinctrl-names = "i2c0", "i2c1", "i2c2";
51 pinctrl-0 = <&pmx_i2cmux_0>;
52 pinctrl-1 = <&pmx_i2cmux_1>;
53 pinctrl-2 = <&pmx_i2cmux_2>;
54
55 i2c0: i2c@0 {
56 reg = <0>;
57 #address-cells = <1>;
58 #size-cells = <0>;
59 status = "okay";
60 };
61
62 i2c1: i2c@1 {
63 reg = <1>;
64 #address-cells = <1>;
65 #size-cells = <0>;
66 /* Requires pmx_i2c1 on i2c controller node */
67 status = "disabled";
68 };
69
70 i2c2: i2c@2 {
71 reg = <2>;
72 #address-cells = <1>;
73 #size-cells = <0>;
74 /* Requires pmx_i2c2 on i2c controller node */
75 status = "disabled";
76 };
77 };
78
79 mbus {
80 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
81 #address-cells = <2>;
82 #size-cells = <1>;
83 controller = <&mbusc>;
84 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
85 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
86
87 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
88 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
89 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
90 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
91 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
92
93 pcie: pcie {
94 compatible = "marvell,dove-pcie";
95 status = "disabled";
96 device_type = "pci";
97 #address-cells = <3>;
98 #size-cells = <2>;
99
100 msi-parent = <&intc>;
101 bus-range = <0x00 0xff>;
102
103 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
104 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
105 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
106 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
107 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
108 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
109
110 pcie0: pcie@1 {
111 device_type = "pci";
112 status = "disabled";
113 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
114 reg = <0x0800 0 0 0 0>;
115 clocks = <&gate_clk 4>;
116 marvell,pcie-port = <0>;
117
118 #address-cells = <3>;
119 #size-cells = <2>;
120 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
121 0x81000000 0 0 0x81000000 0x1 0 1 0>;
122 bus-range = <0x00 0xff>;
123
124 #interrupt-cells = <1>;
125 interrupt-map-mask = <0 0 0 0>;
126 interrupt-map = <0 0 0 0 &intc 16>;
127 };
128
129 pcie1: pcie@2 {
130 device_type = "pci";
131 status = "disabled";
132 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
133 reg = <0x1000 0 0 0 0>;
134 clocks = <&gate_clk 5>;
135 marvell,pcie-port = <1>;
136
137 #address-cells = <3>;
138 #size-cells = <2>;
139 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
140 0x81000000 0 0 0x81000000 0x2 0 1 0>;
141 bus-range = <0x00 0xff>;
142
143 #interrupt-cells = <1>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &intc 18>;
146 };
147 };
148
149 internal-regs {
150 compatible = "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
153 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
154 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
155 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
156 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
157
158 spi0: spi@10600 {
159 compatible = "marvell,orion-spi";
160 #address-cells = <1>;
161 #size-cells = <0>;
162 cell-index = <0>;
163 interrupts = <6>;
164 reg = <0x10600 0x28>;
165 clocks = <&core_clk 0>;
166 pinctrl-0 = <&pmx_spi0>;
167 pinctrl-names = "default";
168 status = "disabled";
169 };
170
171 i2c: i2c@11000 {
172 compatible = "marvell,mv64xxx-i2c";
173 reg = <0x11000 0x20>;
174 #address-cells = <1>;
175 #size-cells = <0>;
176 interrupts = <11>;
177 clock-frequency = <400000>;
178 clocks = <&core_clk 0>;
179 status = "okay";
180 };
181
182 uart0: serial@12000 {
183 compatible = "ns16550a";
184 reg = <0x12000 0x100>;
185 reg-shift = <2>;
186 interrupts = <7>;
187 clocks = <&core_clk 0>;
188 status = "disabled";
189 };
190
191 uart1: serial@12100 {
192 compatible = "ns16550a";
193 reg = <0x12100 0x100>;
194 reg-shift = <2>;
195 interrupts = <8>;
196 clocks = <&core_clk 0>;
197 pinctrl-0 = <&pmx_uart1>;
198 pinctrl-names = "default";
199 status = "disabled";
200 };
201
202 uart2: serial@12200 {
203 compatible = "ns16550a";
204 reg = <0x12200 0x100>;
205 reg-shift = <2>;
206 interrupts = <9>;
207 clocks = <&core_clk 0>;
208 status = "disabled";
209 };
210
211 uart3: serial@12300 {
212 compatible = "ns16550a";
213 reg = <0x12300 0x100>;
214 reg-shift = <2>;
215 interrupts = <10>;
216 clocks = <&core_clk 0>;
217 status = "disabled";
218 };
219
220 spi1: spi@14600 {
221 compatible = "marvell,orion-spi";
222 #address-cells = <1>;
223 #size-cells = <0>;
224 cell-index = <1>;
225 interrupts = <5>;
226 reg = <0x14600 0x28>;
227 clocks = <&core_clk 0>;
228 status = "disabled";
229 };
230
231 mbusc: mbus-ctrl@20000 {
232 compatible = "marvell,mbus-controller";
233 reg = <0x20000 0x80>, <0x800100 0x8>;
234 };
235
236 sysc: system-ctrl@20000 {
237 compatible = "marvell,orion-system-controller";
238 reg = <0x20000 0x110>;
239 };
240
241 bridge_intc: bridge-interrupt-ctrl@20110 {
242 compatible = "marvell,orion-bridge-intc";
243 interrupt-controller;
244 #interrupt-cells = <1>;
245 reg = <0x20110 0x8>;
246 interrupts = <0>;
247 marvell,#interrupts = <5>;
248 };
249
250 intc: interrupt-controller@20200 {
251 compatible = "marvell,orion-intc";
252 interrupt-controller;
253 #interrupt-cells = <1>;
254 reg = <0x20200 0x10>, <0x20210 0x10>;
255 };
256
257 timer: timer@20300 {
258 compatible = "marvell,orion-timer";
259 reg = <0x20300 0x20>;
260 interrupt-parent = <&bridge_intc>;
261 interrupts = <1>, <2>;
262 clocks = <&core_clk 0>;
263 };
264
265 watchdog@20300 {
266 compatible = "marvell,orion-wdt";
267 reg = <0x20300 0x28>, <0x20108 0x4>;
268 interrupt-parent = <&bridge_intc>;
269 interrupts = <3>;
270 clocks = <&core_clk 0>;
271 };
272
273 crypto: crypto-engine@30000 {
274 compatible = "marvell,dove-crypto";
275 reg = <0x30000 0x10000>;
276 reg-names = "regs";
277 interrupts = <31>;
278 clocks = <&gate_clk 15>;
279 marvell,crypto-srams = <&crypto_sram>;
280 marvell,crypto-sram-size = <0x800>;
281 status = "okay";
282 };
283
284 ehci0: usb-host@50000 {
285 compatible = "marvell,orion-ehci";
286 reg = <0x50000 0x1000>;
287 interrupts = <24>;
288 clocks = <&gate_clk 0>;
289 status = "okay";
290 };
291
292 ehci1: usb-host@51000 {
293 compatible = "marvell,orion-ehci";
294 reg = <0x51000 0x1000>;
295 interrupts = <25>;
296 clocks = <&gate_clk 1>;
297 status = "okay";
298 };
299
300 xor0: dma-engine@60800 {
301 compatible = "marvell,orion-xor";
302 reg = <0x60800 0x100
303 0x60a00 0x100>;
304 clocks = <&gate_clk 23>;
305 status = "okay";
306
307 channel0 {
308 interrupts = <39>;
309 dmacap,memcpy;
310 dmacap,xor;
311 };
312
313 channel1 {
314 interrupts = <40>;
315 dmacap,memcpy;
316 dmacap,xor;
317 };
318 };
319
320 xor1: dma-engine@60900 {
321 compatible = "marvell,orion-xor";
322 reg = <0x60900 0x100
323 0x60b00 0x100>;
324 clocks = <&gate_clk 24>;
325 status = "okay";
326
327 channel0 {
328 interrupts = <42>;
329 dmacap,memcpy;
330 dmacap,xor;
331 };
332
333 channel1 {
334 interrupts = <43>;
335 dmacap,memcpy;
336 dmacap,xor;
337 };
338 };
339
340 sdio1: sdio-host@90000 {
341 compatible = "marvell,dove-sdhci";
342 reg = <0x90000 0x100>;
343 interrupts = <36>, <38>;
344 clocks = <&gate_clk 9>;
345 pinctrl-0 = <&pmx_sdio1>;
346 pinctrl-names = "default";
347 status = "disabled";
348 };
349
350 eth: ethernet-ctrl@72000 {
351 compatible = "marvell,orion-eth";
352 #address-cells = <1>;
353 #size-cells = <0>;
354 reg = <0x72000 0x4000>;
355 clocks = <&gate_clk 2>;
356 marvell,tx-checksum-limit = <1600>;
357 status = "disabled";
358
359 ethernet-port@0 {
360 compatible = "marvell,orion-eth-port";
361 reg = <0>;
362 interrupts = <29>;
363 /* overwrite MAC address in bootloader */
364 local-mac-address = [00 00 00 00 00 00];
365 phy-handle = <ðphy>;
366 };
367 };
368
369 mdio: mdio-bus@72004 {
370 compatible = "marvell,orion-mdio";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 reg = <0x72004 0x84>;
374 interrupts = <30>;
375 clocks = <&gate_clk 2>;
376 status = "disabled";
377
378 ethphy: ethernet-phy {
379 /* set phy address in board file */
380 };
381 };
382
383 sdio0: sdio-host@92000 {
384 compatible = "marvell,dove-sdhci";
385 reg = <0x92000 0x100>;
386 interrupts = <35>, <37>;
387 clocks = <&gate_clk 8>;
388 pinctrl-0 = <&pmx_sdio0>;
389 pinctrl-names = "default";
390 status = "disabled";
391 };
392
393 sata0: sata-host@a0000 {
394 compatible = "marvell,orion-sata";
395 reg = <0xa0000 0x2400>;
396 interrupts = <62>;
397 clocks = <&gate_clk 3>;
398 phys = <&sata_phy0>;
399 phy-names = "port0";
400 nr-ports = <1>;
401 status = "disabled";
402 };
403
404 sata_phy0: sata-phy@a2000 {
405 compatible = "marvell,mvebu-sata-phy";
406 reg = <0xa2000 0x0334>;
407 clocks = <&gate_clk 3>;
408 clock-names = "sata";
409 #phy-cells = <0>;
410 status = "ok";
411 };
412
413 audio0: audio-controller@b0000 {
414 compatible = "marvell,dove-audio";
415 reg = <0xb0000 0x2210>;
416 interrupts = <19>, <20>;
417 clocks = <&gate_clk 12>;
418 clock-names = "internal";
419 status = "disabled";
420 };
421
422 audio1: audio-controller@b4000 {
423 compatible = "marvell,dove-audio";
424 reg = <0xb4000 0x2210>;
425 interrupts = <21>, <22>;
426 clocks = <&gate_clk 13>;
427 clock-names = "internal";
428 status = "disabled";
429 };
430
431 pmu: power-management@d0000 {
432 compatible = "marvell,dove-pmu", "simple-bus";
433 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
434 ranges = <0x00000000 0x000d0000 0x8000
435 0x00008000 0x000d8000 0x8000>;
436 interrupts = <33>;
437 interrupt-controller;
438 #address-cells = <1>;
439 #size-cells = <1>;
440 #interrupt-cells = <1>;
441 #reset-cells = <1>;
442
443 domains {
444 vpu_domain: vpu-domain {
445 #power-domain-cells = <0>;
446 marvell,pmu_pwr_mask = <0x00000008>;
447 marvell,pmu_iso_mask = <0x00000001>;
448 resets = <&pmu 16>;
449 };
450
451 gpu_domain: gpu-domain {
452 #power-domain-cells = <0>;
453 marvell,pmu_pwr_mask = <0x00000004>;
454 marvell,pmu_iso_mask = <0x00000002>;
455 resets = <&pmu 18>;
456 };
457 };
458
459 thermal: thermal-diode@1c {
460 compatible = "marvell,dove-thermal";
461 reg = <0x001c 0x0c>, <0x005c 0x08>;
462 };
463
464 gate_clk: clock-gating-ctrl@38 {
465 compatible = "marvell,dove-gating-clock";
466 reg = <0x0038 0x4>;
467 clocks = <&core_clk 0>;
468 #clock-cells = <1>;
469 };
470
471 divider_clk: core-clock@64 {
472 compatible = "marvell,dove-divider-clock";
473 reg = <0x0064 0x8>;
474 #clock-cells = <1>;
475 };
476
477 pinctrl: pin-ctrl@200 {
478 compatible = "marvell,dove-pinctrl";
479 reg = <0x0200 0x14>,
480 <0x0440 0x04>;
481 clocks = <&gate_clk 22>;
482
483 pmx_gpio_0: pmx-gpio-0 {
484 marvell,pins = "mpp0";
485 marvell,function = "gpio";
486 };
487
488 pmx_gpio_1: pmx-gpio-1 {
489 marvell,pins = "mpp1";
490 marvell,function = "gpio";
491 };
492
493 pmx_gpio_2: pmx-gpio-2 {
494 marvell,pins = "mpp2";
495 marvell,function = "gpio";
496 };
497
498 pmx_gpio_3: pmx-gpio-3 {
499 marvell,pins = "mpp3";
500 marvell,function = "gpio";
501 };
502
503 pmx_gpio_4: pmx-gpio-4 {
504 marvell,pins = "mpp4";
505 marvell,function = "gpio";
506 };
507
508 pmx_gpio_5: pmx-gpio-5 {
509 marvell,pins = "mpp5";
510 marvell,function = "gpio";
511 };
512
513 pmx_gpio_6: pmx-gpio-6 {
514 marvell,pins = "mpp6";
515 marvell,function = "gpio";
516 };
517
518 pmx_gpio_7: pmx-gpio-7 {
519 marvell,pins = "mpp7";
520 marvell,function = "gpio";
521 };
522
523 pmx_gpio_8: pmx-gpio-8 {
524 marvell,pins = "mpp8";
525 marvell,function = "gpio";
526 };
527
528 pmx_gpio_9: pmx-gpio-9 {
529 marvell,pins = "mpp9";
530 marvell,function = "gpio";
531 };
532
533 pmx_pcie1_clkreq: pmx-pcie1-clkreq {
534 marvell,pins = "mpp9";
535 marvell,function = "pex1";
536 };
537
538 pmx_gpio_10: pmx-gpio-10 {
539 marvell,pins = "mpp10";
540 marvell,function = "gpio";
541 };
542
543 pmx_gpio_11: pmx-gpio-11 {
544 marvell,pins = "mpp11";
545 marvell,function = "gpio";
546 };
547
548 pmx_pcie0_clkreq: pmx-pcie0-clkreq {
549 marvell,pins = "mpp11";
550 marvell,function = "pex0";
551 };
552
553 pmx_gpio_12: pmx-gpio-12 {
554 marvell,pins = "mpp12";
555 marvell,function = "gpio";
556 };
557
558 pmx_gpio_13: pmx-gpio-13 {
559 marvell,pins = "mpp13";
560 marvell,function = "gpio";
561 };
562
563 pmx_audio1_extclk: pmx-audio1-extclk {
564 marvell,pins = "mpp13";
565 marvell,function = "audio1";
566 };
567
568 pmx_gpio_14: pmx-gpio-14 {
569 marvell,pins = "mpp14";
570 marvell,function = "gpio";
571 };
572
573 pmx_gpio_15: pmx-gpio-15 {
574 marvell,pins = "mpp15";
575 marvell,function = "gpio";
576 };
577
578 pmx_gpio_16: pmx-gpio-16 {
579 marvell,pins = "mpp16";
580 marvell,function = "gpio";
581 };
582
583 pmx_gpio_17: pmx-gpio-17 {
584 marvell,pins = "mpp17";
585 marvell,function = "gpio";
586 };
587
588 pmx_gpio_18: pmx-gpio-18 {
589 marvell,pins = "mpp18";
590 marvell,function = "gpio";
591 };
592
593 pmx_gpio_19: pmx-gpio-19 {
594 marvell,pins = "mpp19";
595 marvell,function = "gpio";
596 };
597
598 pmx_gpio_20: pmx-gpio-20 {
599 marvell,pins = "mpp20";
600 marvell,function = "gpio";
601 };
602
603 pmx_gpio_21: pmx-gpio-21 {
604 marvell,pins = "mpp21";
605 marvell,function = "gpio";
606 };
607
608 pmx_camera: pmx-camera {
609 marvell,pins = "mpp_camera";
610 marvell,function = "camera";
611 };
612
613 pmx_camera_gpio: pmx-camera-gpio {
614 marvell,pins = "mpp_camera";
615 marvell,function = "gpio";
616 };
617
618 pmx_sdio0: pmx-sdio0 {
619 marvell,pins = "mpp_sdio0";
620 marvell,function = "sdio0";
621 };
622
623 pmx_sdio0_gpio: pmx-sdio0-gpio {
624 marvell,pins = "mpp_sdio0";
625 marvell,function = "gpio";
626 };
627
628 pmx_sdio1: pmx-sdio1 {
629 marvell,pins = "mpp_sdio1";
630 marvell,function = "sdio1";
631 };
632
633 pmx_sdio1_gpio: pmx-sdio1-gpio {
634 marvell,pins = "mpp_sdio1";
635 marvell,function = "gpio";
636 };
637
638 pmx_audio1_gpio: pmx-audio1-gpio {
639 marvell,pins = "mpp_audio1";
640 marvell,function = "gpio";
641 };
642
643 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
644 marvell,pins = "mpp_audio1";
645 marvell,function = "i2s1/spdifo";
646 };
647
648 pmx_spi0: pmx-spi0 {
649 marvell,pins = "mpp_spi0";
650 marvell,function = "spi0";
651 };
652
653 pmx_spi0_gpio: pmx-spi0-gpio {
654 marvell,pins = "mpp_spi0";
655 marvell,function = "gpio";
656 };
657
658 pmx_spi1_4_7: pmx-spi1-4-7 {
659 marvell,pins = "mpp4", "mpp5",
660 "mpp6", "mpp7";
661 marvell,function = "spi1";
662 };
663
664 pmx_spi1_20_23: pmx-spi1-20-23 {
665 marvell,pins = "mpp20", "mpp21",
666 "mpp22", "mpp23";
667 marvell,function = "spi1";
668 };
669
670 pmx_uart1: pmx-uart1 {
671 marvell,pins = "mpp_uart1";
672 marvell,function = "uart1";
673 };
674
675 pmx_uart1_gpio: pmx-uart1-gpio {
676 marvell,pins = "mpp_uart1";
677 marvell,function = "gpio";
678 };
679
680 pmx_nand: pmx-nand {
681 marvell,pins = "mpp_nand";
682 marvell,function = "nand";
683 };
684
685 pmx_nand_gpo: pmx-nand-gpo {
686 marvell,pins = "mpp_nand";
687 marvell,function = "gpo";
688 };
689
690 pmx_i2c1: pmx-i2c1 {
691 marvell,pins = "mpp17", "mpp19";
692 marvell,function = "twsi";
693 };
694
695 pmx_i2c2: pmx-i2c2 {
696 marvell,pins = "mpp_audio1";
697 marvell,function = "twsi";
698 };
699
700 pmx_ssp_i2c2: pmx-ssp-i2c2 {
701 marvell,pins = "mpp_audio1";
702 marvell,function = "ssp/twsi";
703 };
704
705 pmx_i2cmux_0: pmx-i2cmux-0 {
706 marvell,pins = "twsi";
707 marvell,function = "twsi-opt1";
708 };
709
710 pmx_i2cmux_1: pmx-i2cmux-1 {
711 marvell,pins = "twsi";
712 marvell,function = "twsi-opt2";
713 };
714
715 pmx_i2cmux_2: pmx-i2cmux-2 {
716 marvell,pins = "twsi";
717 marvell,function = "twsi-opt3";
718 };
719 };
720
721 core_clk: core-clocks@214 {
722 compatible = "marvell,dove-core-clock";
723 reg = <0x0214 0x4>;
724 #clock-cells = <1>;
725 };
726
727 gpio0: gpio-ctrl@400 {
728 compatible = "marvell,orion-gpio";
729 #gpio-cells = <2>;
730 gpio-controller;
731 reg = <0x0400 0x20>;
732 ngpios = <32>;
733 interrupt-controller;
734 #interrupt-cells = <2>;
735 interrupt-parent = <&intc>;
736 interrupts = <12>, <13>, <14>, <60>;
737 };
738
739 gpio1: gpio-ctrl@420 {
740 compatible = "marvell,orion-gpio";
741 #gpio-cells = <2>;
742 gpio-controller;
743 reg = <0x0420 0x20>;
744 ngpios = <32>;
745 interrupt-controller;
746 #interrupt-cells = <2>;
747 interrupt-parent = <&intc>;
748 interrupts = <61>;
749 };
750
751 rtc: real-time-clock@8500 {
752 compatible = "marvell,orion-rtc";
753 reg = <0x8500 0x20>;
754 interrupts = <5>;
755 };
756 };
757
758 gconf: global-config@e802c {
759 compatible = "marvell,dove-global-config",
760 "syscon";
761 reg = <0xe802c 0x14>;
762 };
763
764 gpio2: gpio-ctrl@e8400 {
765 compatible = "marvell,orion-gpio";
766 #gpio-cells = <2>;
767 gpio-controller;
768 reg = <0xe8400 0x0c>;
769 ngpios = <8>;
770 };
771
772 lcd1: lcd-controller@810000 {
773 compatible = "marvell,dove-lcd";
774 reg = <0x810000 0x1000>;
775 interrupts = <46>;
776 status = "disabled";
777 };
778
779 lcd0: lcd-controller@820000 {
780 compatible = "marvell,dove-lcd";
781 reg = <0x820000 0x1000>;
782 interrupts = <47>;
783 status = "disabled";
784 };
785
786 crypto_sram: sram@ffffe000 {
787 compatible = "mmio-sram";
788 reg = <0xffffe000 0x800>;
789 clocks = <&gate_clk 15>;
790 #address-cells = <1>;
791 #size-cells = <1>;
792 };
793
794 gpu: gpu@840000 {
795 clocks = <÷r_clk 1>;
796 clock-names = "core";
797 compatible = "vivante,gc";
798 interrupts = <48>;
799 power-domains = <&gpu_domain>;
800 reg = <0x840000 0x4000>;
801 status = "disabled";
802 };
803 };
804 };
805};