Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for DBRI sound chip found on Sparcs.
4 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
5 *
6 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
7 *
8 * Based entirely upon drivers/sbus/audio/dbri.c which is:
9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
10 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
11 *
12 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
13 * on Sun SPARCStation 10, 20, LX and Voyager models.
14 *
15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
16 * data time multiplexer with ISDN support (aka T7259)
17 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
18 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
19 * Documentation:
20 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
21 * Sparc Technology Business (courtesy of Sun Support)
22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
23 * available from the Lucent (formerly AT&T microelectronics) home
24 * page.
25 * - https://www.freesoft.org/Linux/DBRI/
26 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
27 * Interfaces: CHI, Audio In & Out, 2 bits parallel
28 * Documentation: from the Crystal Semiconductor home page.
29 *
30 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
31 * memory and a serial device (long pipes, no. 0-15) or between two serial
32 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
33 * device (short pipes).
34 * A timeslot defines the bit-offset and no. of bits read from a serial device.
35 * The timeslots are linked to 6 circular lists, one for each direction for
36 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
37 * (the second one is a monitor/tee pipe, valid only for serial input).
38 *
39 * The mmcodec is connected via the CHI bus and needs the data & some
40 * parameters (volume, output selection) time multiplexed in 8 byte
41 * chunks. It also has a control mode, which serves for audio format setting.
42 *
43 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
44 * the same CHI bus, so I thought perhaps it is possible to use the on-board
45 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
46 * audio devices. But the SUN HW group decided against it, at least on my
47 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
48 * connected.
49 *
50 * I've tried to stick to the following function naming conventions:
51 * snd_* ALSA stuff
52 * cs4215_* CS4215 codec specific stuff
53 * dbri_* DBRI high-level stuff
54 * other DBRI low-level stuff
55 */
56
57#include <linux/interrupt.h>
58#include <linux/delay.h>
59#include <linux/irq.h>
60#include <linux/io.h>
61#include <linux/dma-mapping.h>
62#include <linux/gfp.h>
63
64#include <sound/core.h>
65#include <sound/pcm.h>
66#include <sound/pcm_params.h>
67#include <sound/info.h>
68#include <sound/control.h>
69#include <sound/initval.h>
70
71#include <linux/of.h>
72#include <linux/of_device.h>
73#include <linux/atomic.h>
74#include <linux/module.h>
75
76MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
77MODULE_DESCRIPTION("Sun DBRI");
78MODULE_LICENSE("GPL");
79
80static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
81static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
82/* Enable this card */
83static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
84
85module_param_array(index, int, NULL, 0444);
86MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
87module_param_array(id, charp, NULL, 0444);
88MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
89module_param_array(enable, bool, NULL, 0444);
90MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
91
92#undef DBRI_DEBUG
93
94#define D_INT (1<<0)
95#define D_GEN (1<<1)
96#define D_CMD (1<<2)
97#define D_MM (1<<3)
98#define D_USR (1<<4)
99#define D_DESC (1<<5)
100
101static int dbri_debug;
102module_param(dbri_debug, int, 0644);
103MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
104
105#ifdef DBRI_DEBUG
106static const char * const cmds[] = {
107 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
108 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
109};
110
111#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
112
113#else
114#define dprintk(a, x...) do { } while (0)
115
116#endif /* DBRI_DEBUG */
117
118#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
119 (intr << 27) | \
120 value)
121
122/***************************************************************************
123 CS4215 specific definitions and structures
124****************************************************************************/
125
126struct cs4215 {
127 __u8 data[4]; /* Data mode: Time slots 5-8 */
128 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
129 __u8 onboard;
130 __u8 offset; /* Bit offset from frame sync to time slot 1 */
131 volatile __u32 status;
132 volatile __u32 version;
133 __u8 precision; /* In bits, either 8 or 16 */
134 __u8 channels; /* 1 or 2 */
135};
136
137/*
138 * Control mode first
139 */
140
141/* Time Slot 1, Status register */
142#define CS4215_CLB (1<<2) /* Control Latch Bit */
143#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
144 /* 0: line: 2.8V, speaker 8V */
145#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
146#define CS4215_RSRVD_1 (1<<5)
147
148/* Time Slot 2, Data Format Register */
149#define CS4215_DFR_LINEAR16 0
150#define CS4215_DFR_ULAW 1
151#define CS4215_DFR_ALAW 2
152#define CS4215_DFR_LINEAR8 3
153#define CS4215_DFR_STEREO (1<<2)
154static struct {
155 unsigned short freq;
156 unsigned char xtal;
157 unsigned char csval;
158} CS4215_FREQ[] = {
159 { 8000, (1 << 4), (0 << 3) },
160 { 16000, (1 << 4), (1 << 3) },
161 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
162 { 32000, (1 << 4), (3 << 3) },
163 /* { NA, (1 << 4), (4 << 3) }, */
164 /* { NA, (1 << 4), (5 << 3) }, */
165 { 48000, (1 << 4), (6 << 3) },
166 { 9600, (1 << 4), (7 << 3) },
167 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
168 { 11025, (2 << 4), (1 << 3) },
169 { 18900, (2 << 4), (2 << 3) },
170 { 22050, (2 << 4), (3 << 3) },
171 { 37800, (2 << 4), (4 << 3) },
172 { 44100, (2 << 4), (5 << 3) },
173 { 33075, (2 << 4), (6 << 3) },
174 { 6615, (2 << 4), (7 << 3) },
175 { 0, 0, 0}
176};
177
178#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
179
180#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
181
182/* Time Slot 3, Serial Port Control register */
183#define CS4215_XEN (1<<0) /* 0: Enable serial output */
184#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
185#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
186#define CS4215_BSEL_128 (1<<2)
187#define CS4215_BSEL_256 (2<<2)
188#define CS4215_MCK_MAST (0<<4) /* Master clock */
189#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
190#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
191#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
192#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
193
194/* Time Slot 4, Test Register */
195#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
196#define CS4215_ENL (1<<1) /* Enable Loopback Testing */
197
198/* Time Slot 5, Parallel Port Register */
199/* Read only here and the same as the in data mode */
200
201/* Time Slot 6, Reserved */
202
203/* Time Slot 7, Version Register */
204#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
205
206/* Time Slot 8, Reserved */
207
208/*
209 * Data mode
210 */
211/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
212
213/* Time Slot 5, Output Setting */
214#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
215#define CS4215_LE (1<<6) /* Line Out Enable */
216#define CS4215_HE (1<<7) /* Headphone Enable */
217
218/* Time Slot 6, Output Setting */
219#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
220#define CS4215_SE (1<<6) /* Speaker Enable */
221#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
222
223/* Time Slot 7, Input Setting */
224#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
225#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
226#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
227#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
228#define CS4215_PIO1 (1<<7)
229
230/* Time Slot 8, Input Setting */
231#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
232#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
233
234/***************************************************************************
235 DBRI specific definitions and structures
236****************************************************************************/
237
238/* DBRI main registers */
239#define REG0 0x00 /* Status and Control */
240#define REG1 0x04 /* Mode and Interrupt */
241#define REG2 0x08 /* Parallel IO */
242#define REG3 0x0c /* Test */
243#define REG8 0x20 /* Command Queue Pointer */
244#define REG9 0x24 /* Interrupt Queue Pointer */
245
246#define DBRI_NO_CMDS 64
247#define DBRI_INT_BLK 64
248#define DBRI_NO_DESCS 64
249#define DBRI_NO_PIPES 32
250#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
251
252#define DBRI_REC 0
253#define DBRI_PLAY 1
254#define DBRI_NO_STREAMS 2
255
256/* One transmit/receive descriptor */
257/* When ba != 0 descriptor is used */
258struct dbri_mem {
259 volatile __u32 word1;
260 __u32 ba; /* Transmit/Receive Buffer Address */
261 __u32 nda; /* Next Descriptor Address */
262 volatile __u32 word4;
263};
264
265/* This structure is in a DMA region where it can accessed by both
266 * the CPU and the DBRI
267 */
268struct dbri_dma {
269 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
270 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
271 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
272};
273
274#define dbri_dma_off(member, elem) \
275 ((u32)(unsigned long) \
276 (&(((struct dbri_dma *)0)->member[elem])))
277
278enum in_or_out { PIPEinput, PIPEoutput };
279
280struct dbri_pipe {
281 u32 sdp; /* SDP command word */
282 int nextpipe; /* Next pipe in linked list */
283 int length; /* Length of timeslot (bits) */
284 int first_desc; /* Index of first descriptor */
285 int desc; /* Index of active descriptor */
286 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
287};
288
289/* Per stream (playback or record) information */
290struct dbri_streaminfo {
291 struct snd_pcm_substream *substream;
292 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
293 int size; /* Size of DMA buffer */
294 size_t offset; /* offset in user buffer */
295 int pipe; /* Data pipe used */
296 int left_gain; /* mixer elements */
297 int right_gain;
298};
299
300/* This structure holds the information for both chips (DBRI & CS4215) */
301struct snd_dbri {
302 int regs_size, irq; /* Needed for unload */
303 struct platform_device *op; /* OF device info */
304 spinlock_t lock;
305
306 struct dbri_dma *dma; /* Pointer to our DMA block */
307 dma_addr_t dma_dvma; /* DBRI visible DMA address */
308
309 void __iomem *regs; /* dbri HW regs */
310 int dbri_irqp; /* intr queue pointer */
311
312 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
313 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
314 spinlock_t cmdlock; /* Protects cmd queue accesses */
315 s32 *cmdptr; /* Pointer to the last queued cmd */
316
317 int chi_bpf;
318
319 struct cs4215 mm; /* mmcodec special info */
320 /* per stream (playback/record) info */
321 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
322};
323
324#define DBRI_MAX_VOLUME 63 /* Output volume */
325#define DBRI_MAX_GAIN 15 /* Input gain */
326
327/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
328#define D_P (1<<15) /* Program command & queue pointer valid */
329#define D_G (1<<14) /* Allow 4-Word SBus Burst */
330#define D_S (1<<13) /* Allow 16-Word SBus Burst */
331#define D_E (1<<12) /* Allow 8-Word SBus Burst */
332#define D_X (1<<7) /* Sanity Timer Disable */
333#define D_T (1<<6) /* Permit activation of the TE interface */
334#define D_N (1<<5) /* Permit activation of the NT interface */
335#define D_C (1<<4) /* Permit activation of the CHI interface */
336#define D_F (1<<3) /* Force Sanity Timer Time-Out */
337#define D_D (1<<2) /* Disable Master Mode */
338#define D_H (1<<1) /* Halt for Analysis */
339#define D_R (1<<0) /* Soft Reset */
340
341/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
342#define D_LITTLE_END (1<<8) /* Byte Order */
343#define D_BIG_END (0<<8) /* Byte Order */
344#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
345#define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
346#define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
347#define D_MBE (1<<1) /* Burst Error on SBus (read only) */
348#define D_IR (1<<0) /* Interrupt Indicator (read only) */
349
350/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
351#define D_ENPIO3 (1<<7) /* Enable Pin 3 */
352#define D_ENPIO2 (1<<6) /* Enable Pin 2 */
353#define D_ENPIO1 (1<<5) /* Enable Pin 1 */
354#define D_ENPIO0 (1<<4) /* Enable Pin 0 */
355#define D_ENPIO (0xf0) /* Enable all the pins */
356#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
357#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
358#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
359#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
360
361/* DBRI Commands (Page 20) */
362#define D_WAIT 0x0 /* Stop execution */
363#define D_PAUSE 0x1 /* Flush long pipes */
364#define D_JUMP 0x2 /* New command queue */
365#define D_IIQ 0x3 /* Initialize Interrupt Queue */
366#define D_REX 0x4 /* Report command execution via interrupt */
367#define D_SDP 0x5 /* Setup Data Pipe */
368#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
369#define D_DTS 0x7 /* Define Time Slot */
370#define D_SSP 0x8 /* Set short Data Pipe */
371#define D_CHI 0x9 /* Set CHI Global Mode */
372#define D_NT 0xa /* NT Command */
373#define D_TE 0xb /* TE Command */
374#define D_CDEC 0xc /* Codec setup */
375#define D_TEST 0xd /* No comment */
376#define D_CDM 0xe /* CHI Data mode command */
377
378/* Special bits for some commands */
379#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
380
381/* Setup Data Pipe */
382/* IRM */
383#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
384#define D_SDP_CHANGE (2<<18) /* Report any changes */
385#define D_SDP_EVERY (3<<18) /* Report any changes */
386#define D_SDP_EOL (1<<17) /* EOL interrupt enable */
387#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
388
389/* Pipe data MODE */
390#define D_SDP_MEM (0<<13) /* To/from memory */
391#define D_SDP_HDLC (2<<13)
392#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
393#define D_SDP_SER (4<<13) /* Serial to serial */
394#define D_SDP_FIXED (6<<13) /* Short only */
395#define D_SDP_MODE(v) ((v)&(7<<13))
396
397#define D_SDP_TO_SER (1<<12) /* Direction */
398#define D_SDP_FROM_SER (0<<12) /* Direction */
399#define D_SDP_MSB (1<<11) /* Bit order within Byte */
400#define D_SDP_LSB (0<<11) /* Bit order within Byte */
401#define D_SDP_P (1<<10) /* Pointer Valid */
402#define D_SDP_A (1<<8) /* Abort */
403#define D_SDP_C (1<<7) /* Clear */
404
405/* Define Time Slot */
406#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
407#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
408#define D_DTS_INS (1<<15) /* Insert Time Slot */
409#define D_DTS_DEL (0<<15) /* Delete Time Slot */
410#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
411#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
412
413/* Time Slot defines */
414#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
415#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
416#define D_TS_DI (1<<13) /* Data Invert */
417#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
418#define D_TS_MONITOR (2<<10) /* Monitor pipe */
419#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
420#define D_TS_ANCHOR (7<<10) /* Starting short pipes */
421#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
422#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
423
424/* Concentration Highway Interface Modes */
425#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
426#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
427#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
428#define D_CHI_OD (1<<13) /* Open Drain Enable */
429#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
430#define D_CHI_FD (1<<11) /* Frame Drive */
431#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
432
433/* NT: These are here for completeness */
434#define D_NT_FBIT (1<<17) /* Frame Bit */
435#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
436#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
437#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
438#define D_NT_ISNT (1<<13) /* Configure interface as NT */
439#define D_NT_FT (1<<12) /* Fixed Timing */
440#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
441#define D_NT_IFA (1<<10) /* Inhibit Final Activation */
442#define D_NT_ACT (1<<9) /* Activate Interface */
443#define D_NT_MFE (1<<8) /* Multiframe Enable */
444#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
445#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
446#define D_NT_FACT (1<<1) /* Force Activation */
447#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
448
449/* Codec Setup */
450#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
451#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
452#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
453
454/* Test */
455#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
456#define D_TEST_SIZE(v) ((v)<<11) /* */
457#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
458#define D_TEST_PROC 0x6 /* Microprocessor test */
459#define D_TEST_SER 0x7 /* Serial-Controller test */
460#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
461#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
462#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
463#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
464#define D_TEST_DUMP 0xe /* ROM Dump */
465
466/* CHI Data Mode */
467#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
468#define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
469#define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
470#define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
471#define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
472#define D_CDM_REN (1 << 0) /* Receive Highway Enable */
473
474/* The Interrupts */
475#define D_INTR_BRDY 1 /* Buffer Ready for processing */
476#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
477#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
478#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
479#define D_INTR_EOL 5 /* End of List */
480#define D_INTR_CMDI 6 /* Command has bean read */
481#define D_INTR_XCMP 8 /* Transmission of frame complete */
482#define D_INTR_SBRI 9 /* BRI status change info */
483#define D_INTR_FXDT 10 /* Fixed data change */
484#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
485#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
486#define D_INTR_DBYT 12 /* Dropped by frame slip */
487#define D_INTR_RBYT 13 /* Repeated by frame slip */
488#define D_INTR_LINT 14 /* Lost Interrupt */
489#define D_INTR_UNDR 15 /* DMA underrun */
490
491#define D_INTR_TE 32
492#define D_INTR_NT 34
493#define D_INTR_CHI 36
494#define D_INTR_CMD 38
495
496#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
497#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
498#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
499#define D_INTR_GETVAL(v) ((v) & 0xffff)
500#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
501
502#define D_P_0 0 /* TE receive anchor */
503#define D_P_1 1 /* TE transmit anchor */
504#define D_P_2 2 /* NT transmit anchor */
505#define D_P_3 3 /* NT receive anchor */
506#define D_P_4 4 /* CHI send data */
507#define D_P_5 5 /* CHI receive data */
508#define D_P_6 6 /* */
509#define D_P_7 7 /* */
510#define D_P_8 8 /* */
511#define D_P_9 9 /* */
512#define D_P_10 10 /* */
513#define D_P_11 11 /* */
514#define D_P_12 12 /* */
515#define D_P_13 13 /* */
516#define D_P_14 14 /* */
517#define D_P_15 15 /* */
518#define D_P_16 16 /* CHI anchor pipe */
519#define D_P_17 17 /* CHI send */
520#define D_P_18 18 /* CHI receive */
521#define D_P_19 19 /* CHI receive */
522#define D_P_20 20 /* CHI receive */
523#define D_P_21 21 /* */
524#define D_P_22 22 /* */
525#define D_P_23 23 /* */
526#define D_P_24 24 /* */
527#define D_P_25 25 /* */
528#define D_P_26 26 /* */
529#define D_P_27 27 /* */
530#define D_P_28 28 /* */
531#define D_P_29 29 /* */
532#define D_P_30 30 /* */
533#define D_P_31 31 /* */
534
535/* Transmit descriptor defines */
536#define DBRI_TD_F (1 << 31) /* End of Frame */
537#define DBRI_TD_D (1 << 30) /* Do not append CRC */
538#define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
539#define DBRI_TD_B (1 << 15) /* Final interrupt */
540#define DBRI_TD_M (1 << 14) /* Marker interrupt */
541#define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
542#define DBRI_TD_FCNT(v) (v) /* Flag Count */
543#define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
544#define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
545#define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
546#define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
547 /* Maximum buffer size per TD: almost 8KB */
548#define DBRI_TD_MAXCNT ((1 << 13) - 4)
549
550/* Receive descriptor defines */
551#define DBRI_RD_F (1 << 31) /* End of Frame */
552#define DBRI_RD_C (1 << 30) /* Completed buffer */
553#define DBRI_RD_B (1 << 15) /* Final interrupt */
554#define DBRI_RD_M (1 << 14) /* Marker interrupt */
555#define DBRI_RD_BCNT(v) (v) /* Buffer size */
556#define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
557#define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
558#define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
559#define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
560#define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
561#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
562
563/* stream_info[] access */
564/* Translate the ALSA direction into the array index */
565#define DBRI_STREAMNO(substream) \
566 (substream->stream == \
567 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
568
569/* Return a pointer to dbri_streaminfo */
570#define DBRI_STREAM(dbri, substream) \
571 &dbri->stream_info[DBRI_STREAMNO(substream)]
572
573/*
574 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
575 * So we have to reverse the bits. Note: not all bit lengths are supported
576 */
577static __u32 reverse_bytes(__u32 b, int len)
578{
579 switch (len) {
580 case 32:
581 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
582 fallthrough;
583 case 16:
584 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
585 fallthrough;
586 case 8:
587 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
588 fallthrough;
589 case 4:
590 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
591 fallthrough;
592 case 2:
593 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
594 case 1:
595 case 0:
596 break;
597 default:
598 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
599 }
600
601 return b;
602}
603
604/*
605****************************************************************************
606************** DBRI initialization and command synchronization *************
607****************************************************************************
608
609Commands are sent to the DBRI by building a list of them in memory,
610then writing the address of the first list item to DBRI register 8.
611The list is terminated with a WAIT command, which generates a
612CPU interrupt to signal completion.
613
614Since the DBRI can run in parallel with the CPU, several means of
615synchronization present themselves. The method implemented here uses
616the dbri_cmdwait() to wait for execution of batch of sent commands.
617
618A circular command buffer is used here. A new command is being added
619while another can be executed. The scheme works by adding two WAIT commands
620after each sent batch of commands. When the next batch is prepared it is
621added after the WAIT commands then the WAITs are replaced with single JUMP
622command to the new batch. Then the DBRI is forced to reread the last WAIT
623command (replaced by the JUMP by then). If the DBRI is still executing
624previous commands the request to reread the WAIT command is ignored.
625
626Every time a routine wants to write commands to the DBRI, it must
627first call dbri_cmdlock() and get pointer to a free space in
628dbri->dma->cmd buffer. After this, the commands can be written to
629the buffer, and dbri_cmdsend() is called with the final pointer value
630to send them to the DBRI.
631
632*/
633
634#define MAXLOOPS 20
635/*
636 * Wait for the current command string to execute
637 */
638static void dbri_cmdwait(struct snd_dbri *dbri)
639{
640 int maxloops = MAXLOOPS;
641 unsigned long flags;
642
643 /* Delay if previous commands are still being processed */
644 spin_lock_irqsave(&dbri->lock, flags);
645 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
646 spin_unlock_irqrestore(&dbri->lock, flags);
647 msleep_interruptible(1);
648 spin_lock_irqsave(&dbri->lock, flags);
649 }
650 spin_unlock_irqrestore(&dbri->lock, flags);
651
652 if (maxloops == 0)
653 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
654 else
655 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
656 MAXLOOPS - maxloops - 1);
657}
658/*
659 * Lock the command queue and return pointer to space for len cmd words
660 * It locks the cmdlock spinlock.
661 */
662static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
663{
664 u32 dvma_addr = (u32)dbri->dma_dvma;
665
666 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
667 len += 2;
668 spin_lock(&dbri->cmdlock);
669 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
670 return dbri->cmdptr + 2;
671 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
672 return dbri->dma->cmd;
673 else
674 printk(KERN_ERR "DBRI: no space for commands.");
675
676 return NULL;
677}
678
679/*
680 * Send prepared cmd string. It works by writing a JUMP cmd into
681 * the last WAIT cmd and force DBRI to reread the cmd.
682 * The JUMP cmd points to the new cmd string.
683 * It also releases the cmdlock spinlock.
684 *
685 * Lock must be held before calling this.
686 */
687static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
688{
689 u32 dvma_addr = (u32)dbri->dma_dvma;
690 s32 tmp, addr;
691 static int wait_id = 0;
692
693 wait_id++;
694 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
695 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
696 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
697
698 /* Replace the last command with JUMP */
699 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32);
700 *(dbri->cmdptr+1) = addr;
701 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
702
703#ifdef DBRI_DEBUG
704 if (cmd > dbri->cmdptr) {
705 s32 *ptr;
706
707 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
708 dprintk(D_CMD, "cmd: %lx:%08x\n",
709 (unsigned long)ptr, *ptr);
710 } else {
711 s32 *ptr = dbri->cmdptr;
712
713 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
714 ptr++;
715 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
716 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
717 dprintk(D_CMD, "cmd: %lx:%08x\n",
718 (unsigned long)ptr, *ptr);
719 }
720#endif
721
722 /* Reread the last command */
723 tmp = sbus_readl(dbri->regs + REG0);
724 tmp |= D_P;
725 sbus_writel(tmp, dbri->regs + REG0);
726
727 dbri->cmdptr = cmd;
728 spin_unlock(&dbri->cmdlock);
729}
730
731/* Lock must be held when calling this */
732static void dbri_reset(struct snd_dbri *dbri)
733{
734 int i;
735 u32 tmp;
736
737 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
738 sbus_readl(dbri->regs + REG0),
739 sbus_readl(dbri->regs + REG2),
740 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
741
742 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
743 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
744 udelay(10);
745
746 /* A brute approach - DBRI falls back to working burst size by itself
747 * On SS20 D_S does not work, so do not try so high. */
748 tmp = sbus_readl(dbri->regs + REG0);
749 tmp |= D_G | D_E;
750 tmp &= ~D_S;
751 sbus_writel(tmp, dbri->regs + REG0);
752}
753
754/* Lock must not be held before calling this */
755static void dbri_initialize(struct snd_dbri *dbri)
756{
757 u32 dvma_addr = (u32)dbri->dma_dvma;
758 s32 *cmd;
759 u32 dma_addr;
760 unsigned long flags;
761 int n;
762
763 spin_lock_irqsave(&dbri->lock, flags);
764
765 dbri_reset(dbri);
766
767 /* Initialize pipes */
768 for (n = 0; n < DBRI_NO_PIPES; n++)
769 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
770
771 spin_lock_init(&dbri->cmdlock);
772 /*
773 * Initialize the interrupt ring buffer.
774 */
775 dma_addr = dvma_addr + dbri_dma_off(intr, 0);
776 dbri->dma->intr[0] = dma_addr;
777 dbri->dbri_irqp = 1;
778 /*
779 * Set up the interrupt queue
780 */
781 spin_lock(&dbri->cmdlock);
782 cmd = dbri->cmdptr = dbri->dma->cmd;
783 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
784 *(cmd++) = dma_addr;
785 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
786 dbri->cmdptr = cmd;
787 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
788 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
789 dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
790 sbus_writel(dma_addr, dbri->regs + REG8);
791 spin_unlock(&dbri->cmdlock);
792
793 spin_unlock_irqrestore(&dbri->lock, flags);
794 dbri_cmdwait(dbri);
795}
796
797/*
798****************************************************************************
799************************** DBRI data pipe management ***********************
800****************************************************************************
801
802While DBRI control functions use the command and interrupt buffers, the
803main data path takes the form of data pipes, which can be short (command
804and interrupt driven), or long (attached to DMA buffers). These functions
805provide a rudimentary means of setting up and managing the DBRI's pipes,
806but the calling functions have to make sure they respect the pipes' linked
807list ordering, among other things. The transmit and receive functions
808here interface closely with the transmit and receive interrupt code.
809
810*/
811static inline int pipe_active(struct snd_dbri *dbri, int pipe)
812{
813 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
814}
815
816/* reset_pipe(dbri, pipe)
817 *
818 * Called on an in-use pipe to clear anything being transmitted or received
819 * Lock must be held before calling this.
820 */
821static void reset_pipe(struct snd_dbri *dbri, int pipe)
822{
823 int sdp;
824 int desc;
825 s32 *cmd;
826
827 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
828 printk(KERN_ERR "DBRI: reset_pipe called with "
829 "illegal pipe number\n");
830 return;
831 }
832
833 sdp = dbri->pipes[pipe].sdp;
834 if (sdp == 0) {
835 printk(KERN_ERR "DBRI: reset_pipe called "
836 "on uninitialized pipe\n");
837 return;
838 }
839
840 cmd = dbri_cmdlock(dbri, 3);
841 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
842 *(cmd++) = 0;
843 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
844 dbri_cmdsend(dbri, cmd, 3);
845
846 desc = dbri->pipes[pipe].first_desc;
847 if (desc >= 0)
848 do {
849 dbri->dma->desc[desc].ba = 0;
850 dbri->dma->desc[desc].nda = 0;
851 desc = dbri->next_desc[desc];
852 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
853
854 dbri->pipes[pipe].desc = -1;
855 dbri->pipes[pipe].first_desc = -1;
856}
857
858/*
859 * Lock must be held before calling this.
860 */
861static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
862{
863 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
864 printk(KERN_ERR "DBRI: setup_pipe called "
865 "with illegal pipe number\n");
866 return;
867 }
868
869 if ((sdp & 0xf800) != sdp) {
870 printk(KERN_ERR "DBRI: setup_pipe called "
871 "with strange SDP value\n");
872 /* sdp &= 0xf800; */
873 }
874
875 /* If this is a fixed receive pipe, arrange for an interrupt
876 * every time its data changes
877 */
878 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
879 sdp |= D_SDP_CHANGE;
880
881 sdp |= D_PIPE(pipe);
882 dbri->pipes[pipe].sdp = sdp;
883 dbri->pipes[pipe].desc = -1;
884 dbri->pipes[pipe].first_desc = -1;
885
886 reset_pipe(dbri, pipe);
887}
888
889/*
890 * Lock must be held before calling this.
891 */
892static void link_time_slot(struct snd_dbri *dbri, int pipe,
893 int prevpipe, int nextpipe,
894 int length, int cycle)
895{
896 s32 *cmd;
897 int val;
898
899 if (pipe < 0 || pipe > DBRI_MAX_PIPE
900 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
901 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
902 printk(KERN_ERR
903 "DBRI: link_time_slot called with illegal pipe number\n");
904 return;
905 }
906
907 if (dbri->pipes[pipe].sdp == 0
908 || dbri->pipes[prevpipe].sdp == 0
909 || dbri->pipes[nextpipe].sdp == 0) {
910 printk(KERN_ERR "DBRI: link_time_slot called "
911 "on uninitialized pipe\n");
912 return;
913 }
914
915 dbri->pipes[prevpipe].nextpipe = pipe;
916 dbri->pipes[pipe].nextpipe = nextpipe;
917 dbri->pipes[pipe].length = length;
918
919 cmd = dbri_cmdlock(dbri, 4);
920
921 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
922 /* Deal with CHI special case:
923 * "If transmission on edges 0 or 1 is desired, then cycle n
924 * (where n = # of bit times per frame...) must be used."
925 * - DBRI data sheet, page 11
926 */
927 if (prevpipe == 16 && cycle == 0)
928 cycle = dbri->chi_bpf;
929
930 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
931 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
932 *(cmd++) = 0;
933 *(cmd++) =
934 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
935 } else {
936 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
937 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
938 *(cmd++) =
939 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
940 *(cmd++) = 0;
941 }
942 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
943
944 dbri_cmdsend(dbri, cmd, 4);
945}
946
947#if 0
948/*
949 * Lock must be held before calling this.
950 */
951static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
952 enum in_or_out direction, int prevpipe,
953 int nextpipe)
954{
955 s32 *cmd;
956 int val;
957
958 if (pipe < 0 || pipe > DBRI_MAX_PIPE
959 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
960 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
961 printk(KERN_ERR
962 "DBRI: unlink_time_slot called with illegal pipe number\n");
963 return;
964 }
965
966 cmd = dbri_cmdlock(dbri, 4);
967
968 if (direction == PIPEinput) {
969 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
970 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
971 *(cmd++) = D_TS_NEXT(nextpipe);
972 *(cmd++) = 0;
973 } else {
974 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
975 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
976 *(cmd++) = 0;
977 *(cmd++) = D_TS_NEXT(nextpipe);
978 }
979 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
980
981 dbri_cmdsend(dbri, cmd, 4);
982}
983#endif
984
985/* xmit_fixed() / recv_fixed()
986 *
987 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
988 * expected to change much, and which we don't need to buffer.
989 * The DBRI only interrupts us when the data changes (receive pipes),
990 * or only changes the data when this function is called (transmit pipes).
991 * Only short pipes (numbers 16-31) can be used in fixed data mode.
992 *
993 * These function operate on a 32-bit field, no matter how large
994 * the actual time slot is. The interrupt handler takes care of bit
995 * ordering and alignment. An 8-bit time slot will always end up
996 * in the low-order 8 bits, filled either MSB-first or LSB-first,
997 * depending on the settings passed to setup_pipe().
998 *
999 * Lock must not be held before calling it.
1000 */
1001static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
1002{
1003 s32 *cmd;
1004 unsigned long flags;
1005
1006 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1007 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1008 return;
1009 }
1010
1011 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1012 printk(KERN_ERR "DBRI: xmit_fixed: "
1013 "Uninitialized pipe %d\n", pipe);
1014 return;
1015 }
1016
1017 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1018 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1019 return;
1020 }
1021
1022 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1023 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1024 pipe);
1025 return;
1026 }
1027
1028 /* DBRI short pipes always transmit LSB first */
1029
1030 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1031 data = reverse_bytes(data, dbri->pipes[pipe].length);
1032
1033 cmd = dbri_cmdlock(dbri, 3);
1034
1035 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1036 *(cmd++) = data;
1037 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1038
1039 spin_lock_irqsave(&dbri->lock, flags);
1040 dbri_cmdsend(dbri, cmd, 3);
1041 spin_unlock_irqrestore(&dbri->lock, flags);
1042 dbri_cmdwait(dbri);
1043
1044}
1045
1046static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1047{
1048 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1049 printk(KERN_ERR "DBRI: recv_fixed called with "
1050 "illegal pipe number\n");
1051 return;
1052 }
1053
1054 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1055 printk(KERN_ERR "DBRI: recv_fixed called on "
1056 "non-fixed pipe %d\n", pipe);
1057 return;
1058 }
1059
1060 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1061 printk(KERN_ERR "DBRI: recv_fixed called on "
1062 "transmit pipe %d\n", pipe);
1063 return;
1064 }
1065
1066 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1067}
1068
1069/* setup_descs()
1070 *
1071 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1072 * with a DMA buffer.
1073 *
1074 * Only pipe numbers 0-15 can be used in this mode.
1075 *
1076 * This function takes a stream number pointing to a data buffer,
1077 * and work by building chains of descriptors which identify the
1078 * data buffers. Buffers too large for a single descriptor will
1079 * be spread across multiple descriptors.
1080 *
1081 * All descriptors create a ring buffer.
1082 *
1083 * Lock must be held before calling this.
1084 */
1085static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1086{
1087 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1088 u32 dvma_addr = (u32)dbri->dma_dvma;
1089 __u32 dvma_buffer;
1090 int desc;
1091 int len;
1092 int first_desc = -1;
1093 int last_desc = -1;
1094
1095 if (info->pipe < 0 || info->pipe > 15) {
1096 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1097 return -2;
1098 }
1099
1100 if (dbri->pipes[info->pipe].sdp == 0) {
1101 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1102 info->pipe);
1103 return -2;
1104 }
1105
1106 dvma_buffer = info->dvma_buffer;
1107 len = info->size;
1108
1109 if (streamno == DBRI_PLAY) {
1110 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1111 printk(KERN_ERR "DBRI: setup_descs: "
1112 "Called on receive pipe %d\n", info->pipe);
1113 return -2;
1114 }
1115 } else {
1116 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1117 printk(KERN_ERR
1118 "DBRI: setup_descs: Called on transmit pipe %d\n",
1119 info->pipe);
1120 return -2;
1121 }
1122 /* Should be able to queue multiple buffers
1123 * to receive on a pipe
1124 */
1125 if (pipe_active(dbri, info->pipe)) {
1126 printk(KERN_ERR "DBRI: recv_on_pipe: "
1127 "Called on active pipe %d\n", info->pipe);
1128 return -2;
1129 }
1130
1131 /* Make sure buffer size is multiple of four */
1132 len &= ~3;
1133 }
1134
1135 /* Free descriptors if pipe has any */
1136 desc = dbri->pipes[info->pipe].first_desc;
1137 if (desc >= 0)
1138 do {
1139 dbri->dma->desc[desc].ba = 0;
1140 dbri->dma->desc[desc].nda = 0;
1141 desc = dbri->next_desc[desc];
1142 } while (desc != -1 &&
1143 desc != dbri->pipes[info->pipe].first_desc);
1144
1145 dbri->pipes[info->pipe].desc = -1;
1146 dbri->pipes[info->pipe].first_desc = -1;
1147
1148 desc = 0;
1149 while (len > 0) {
1150 int mylen;
1151
1152 for (; desc < DBRI_NO_DESCS; desc++) {
1153 if (!dbri->dma->desc[desc].ba)
1154 break;
1155 }
1156
1157 if (desc == DBRI_NO_DESCS) {
1158 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1159 return -1;
1160 }
1161
1162 if (len > DBRI_TD_MAXCNT)
1163 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1164 else
1165 mylen = len;
1166
1167 if (mylen > period)
1168 mylen = period;
1169
1170 dbri->next_desc[desc] = -1;
1171 dbri->dma->desc[desc].ba = dvma_buffer;
1172 dbri->dma->desc[desc].nda = 0;
1173
1174 if (streamno == DBRI_PLAY) {
1175 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1176 dbri->dma->desc[desc].word4 = 0;
1177 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1178 } else {
1179 dbri->dma->desc[desc].word1 = 0;
1180 dbri->dma->desc[desc].word4 =
1181 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1182 }
1183
1184 if (first_desc == -1)
1185 first_desc = desc;
1186 else {
1187 dbri->next_desc[last_desc] = desc;
1188 dbri->dma->desc[last_desc].nda =
1189 dvma_addr + dbri_dma_off(desc, desc);
1190 }
1191
1192 last_desc = desc;
1193 dvma_buffer += mylen;
1194 len -= mylen;
1195 }
1196
1197 if (first_desc == -1 || last_desc == -1) {
1198 printk(KERN_ERR "DBRI: setup_descs: "
1199 " Not enough descriptors available\n");
1200 return -1;
1201 }
1202
1203 dbri->dma->desc[last_desc].nda =
1204 dvma_addr + dbri_dma_off(desc, first_desc);
1205 dbri->next_desc[last_desc] = first_desc;
1206 dbri->pipes[info->pipe].first_desc = first_desc;
1207 dbri->pipes[info->pipe].desc = first_desc;
1208
1209#ifdef DBRI_DEBUG
1210 for (desc = first_desc; desc != -1;) {
1211 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1212 desc,
1213 dbri->dma->desc[desc].word1,
1214 dbri->dma->desc[desc].ba,
1215 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1216 desc = dbri->next_desc[desc];
1217 if (desc == first_desc)
1218 break;
1219 }
1220#endif
1221 return 0;
1222}
1223
1224/*
1225****************************************************************************
1226************************** DBRI - CHI interface ****************************
1227****************************************************************************
1228
1229The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1230multiplexed serial interface which the DBRI can operate in either master
1231(give clock/frame sync) or slave (take clock/frame sync) mode.
1232
1233*/
1234
1235enum master_or_slave { CHImaster, CHIslave };
1236
1237/*
1238 * Lock must not be held before calling it.
1239 */
1240static void reset_chi(struct snd_dbri *dbri,
1241 enum master_or_slave master_or_slave,
1242 int bits_per_frame)
1243{
1244 s32 *cmd;
1245 int val;
1246
1247 /* Set CHI Anchor: Pipe 16 */
1248
1249 cmd = dbri_cmdlock(dbri, 4);
1250 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1251 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1252 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1253 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1254 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1255 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1256 dbri_cmdsend(dbri, cmd, 4);
1257
1258 dbri->pipes[16].sdp = 1;
1259 dbri->pipes[16].nextpipe = 16;
1260
1261 cmd = dbri_cmdlock(dbri, 4);
1262
1263 if (master_or_slave == CHIslave) {
1264 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1265 *
1266 * CHICM = 0 (slave mode, 8 kHz frame rate)
1267 * IR = give immediate CHI status interrupt
1268 * EN = give CHI status interrupt upon change
1269 */
1270 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1271 } else {
1272 /* Setup DBRI for CHI Master - generate clock, FS
1273 *
1274 * BPF = bits per 8 kHz frame
1275 * 12.288 MHz / CHICM_divisor = clock rate
1276 * FD = 1 - drive CHIFS on rising edge of CHICK
1277 */
1278 int clockrate = bits_per_frame * 8;
1279 int divisor = 12288 / clockrate;
1280
1281 if (divisor > 255 || divisor * clockrate != 12288)
1282 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1283 "in setup_chi\n");
1284
1285 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1286 | D_CHI_BPF(bits_per_frame));
1287 }
1288
1289 dbri->chi_bpf = bits_per_frame;
1290
1291 /* CHI Data Mode
1292 *
1293 * RCE = 0 - receive on falling edge of CHICK
1294 * XCE = 1 - transmit on rising edge of CHICK
1295 * XEN = 1 - enable transmitter
1296 * REN = 1 - enable receiver
1297 */
1298
1299 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1300 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1301 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1302
1303 dbri_cmdsend(dbri, cmd, 4);
1304}
1305
1306/*
1307****************************************************************************
1308*********************** CS4215 audio codec management **********************
1309****************************************************************************
1310
1311In the standard SPARC audio configuration, the CS4215 codec is attached
1312to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1313
1314 * Lock must not be held before calling it.
1315
1316*/
1317static void cs4215_setup_pipes(struct snd_dbri *dbri)
1318{
1319 unsigned long flags;
1320
1321 spin_lock_irqsave(&dbri->lock, flags);
1322 /*
1323 * Data mode:
1324 * Pipe 4: Send timeslots 1-4 (audio data)
1325 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1326 * Pipe 6: Receive timeslots 1-4 (audio data)
1327 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1328 * interrupt, and the rest of the data (slot 5 and 8) is
1329 * not relevant for us (only for doublechecking).
1330 *
1331 * Control mode:
1332 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1333 * Pipe 18: Receive timeslot 1 (clb).
1334 * Pipe 19: Receive timeslot 7 (version).
1335 */
1336
1337 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1338 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1339 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1340 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1341
1342 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1343 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1344 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1345 spin_unlock_irqrestore(&dbri->lock, flags);
1346
1347 dbri_cmdwait(dbri);
1348}
1349
1350static int cs4215_init_data(struct cs4215 *mm)
1351{
1352 /*
1353 * No action, memory resetting only.
1354 *
1355 * Data Time Slot 5-8
1356 * Speaker,Line and Headphone enable. Gain set to the half.
1357 * Input is mike.
1358 */
1359 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1360 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1361 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1362 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1363
1364 /*
1365 * Control Time Slot 1-4
1366 * 0: Default I/O voltage scale
1367 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1368 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1369 * 3: Tests disabled
1370 */
1371 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1372 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1373 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1374 mm->ctrl[3] = 0;
1375
1376 mm->status = 0;
1377 mm->version = 0xff;
1378 mm->precision = 8; /* For ULAW */
1379 mm->channels = 1;
1380
1381 return 0;
1382}
1383
1384static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1385{
1386 if (muted) {
1387 dbri->mm.data[0] |= 63;
1388 dbri->mm.data[1] |= 63;
1389 dbri->mm.data[2] &= ~15;
1390 dbri->mm.data[3] &= ~15;
1391 } else {
1392 /* Start by setting the playback attenuation. */
1393 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1394 int left_gain = info->left_gain & 0x3f;
1395 int right_gain = info->right_gain & 0x3f;
1396
1397 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1398 dbri->mm.data[1] &= ~0x3f;
1399 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1400 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1401
1402 /* Now set the recording gain. */
1403 info = &dbri->stream_info[DBRI_REC];
1404 left_gain = info->left_gain & 0xf;
1405 right_gain = info->right_gain & 0xf;
1406 dbri->mm.data[2] |= CS4215_LG(left_gain);
1407 dbri->mm.data[3] |= CS4215_RG(right_gain);
1408 }
1409
1410 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1411}
1412
1413/*
1414 * Set the CS4215 to data mode.
1415 */
1416static void cs4215_open(struct snd_dbri *dbri)
1417{
1418 int data_width;
1419 u32 tmp;
1420 unsigned long flags;
1421
1422 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1423 dbri->mm.channels, dbri->mm.precision);
1424
1425 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1426 * to make sure this takes. This avoids clicking noises.
1427 */
1428
1429 cs4215_setdata(dbri, 1);
1430 udelay(125);
1431
1432 /*
1433 * Data mode:
1434 * Pipe 4: Send timeslots 1-4 (audio data)
1435 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1436 * Pipe 6: Receive timeslots 1-4 (audio data)
1437 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1438 * interrupt, and the rest of the data (slot 5 and 8) is
1439 * not relevant for us (only for doublechecking).
1440 *
1441 * Just like in control mode, the time slots are all offset by eight
1442 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1443 * even if it's the CHI master. Don't ask me...
1444 */
1445 spin_lock_irqsave(&dbri->lock, flags);
1446 tmp = sbus_readl(dbri->regs + REG0);
1447 tmp &= ~(D_C); /* Disable CHI */
1448 sbus_writel(tmp, dbri->regs + REG0);
1449
1450 /* Switch CS4215 to data mode - set PIO3 to 1 */
1451 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1452 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1453
1454 reset_chi(dbri, CHIslave, 128);
1455
1456 /* Note: this next doesn't work for 8-bit stereo, because the two
1457 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1458 * (See CS4215 datasheet Fig 15)
1459 *
1460 * DBRI non-contiguous mode would be required to make this work.
1461 */
1462 data_width = dbri->mm.channels * dbri->mm.precision;
1463
1464 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1465 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1466 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1467 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1468
1469 /* FIXME: enable CHI after _setdata? */
1470 tmp = sbus_readl(dbri->regs + REG0);
1471 tmp |= D_C; /* Enable CHI */
1472 sbus_writel(tmp, dbri->regs + REG0);
1473 spin_unlock_irqrestore(&dbri->lock, flags);
1474
1475 cs4215_setdata(dbri, 0);
1476}
1477
1478/*
1479 * Send the control information (i.e. audio format)
1480 */
1481static int cs4215_setctrl(struct snd_dbri *dbri)
1482{
1483 int i, val;
1484 u32 tmp;
1485 unsigned long flags;
1486
1487 /* FIXME - let the CPU do something useful during these delays */
1488
1489 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1490 * to make sure this takes. This avoids clicking noises.
1491 */
1492 cs4215_setdata(dbri, 1);
1493 udelay(125);
1494
1495 /*
1496 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1497 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1498 */
1499 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1500 sbus_writel(val, dbri->regs + REG2);
1501 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1502 udelay(34);
1503
1504 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1505 * operate as CHI master, supplying clocking and frame synchronization.
1506 *
1507 * In Data mode, however, the CS4215 must be CHI master to insure
1508 * that its data stream is synchronous with its codec.
1509 *
1510 * The upshot of all this? We start by putting the DBRI into master
1511 * mode, program the CS4215 in Control mode, then switch the CS4215
1512 * into Data mode and put the DBRI into slave mode. Various timing
1513 * requirements must be observed along the way.
1514 *
1515 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1516 * others?), the addressing of the CS4215's time slots is
1517 * offset by eight bits, so we add eight to all the "cycle"
1518 * values in the Define Time Slot (DTS) commands. This is
1519 * done in hardware by a TI 248 that delays the DBRI->4215
1520 * frame sync signal by eight clock cycles. Anybody know why?
1521 */
1522 spin_lock_irqsave(&dbri->lock, flags);
1523 tmp = sbus_readl(dbri->regs + REG0);
1524 tmp &= ~D_C; /* Disable CHI */
1525 sbus_writel(tmp, dbri->regs + REG0);
1526
1527 reset_chi(dbri, CHImaster, 128);
1528
1529 /*
1530 * Control mode:
1531 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1532 * Pipe 18: Receive timeslot 1 (clb).
1533 * Pipe 19: Receive timeslot 7 (version).
1534 */
1535
1536 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1537 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1538 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1539 spin_unlock_irqrestore(&dbri->lock, flags);
1540
1541 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1542 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1543 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1544
1545 spin_lock_irqsave(&dbri->lock, flags);
1546 tmp = sbus_readl(dbri->regs + REG0);
1547 tmp |= D_C; /* Enable CHI */
1548 sbus_writel(tmp, dbri->regs + REG0);
1549 spin_unlock_irqrestore(&dbri->lock, flags);
1550
1551 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1552 msleep_interruptible(1);
1553
1554 if (i == 0) {
1555 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1556 dbri->mm.status);
1557 return -1;
1558 }
1559
1560 /* Disable changes to our copy of the version number, as we are about
1561 * to leave control mode.
1562 */
1563 recv_fixed(dbri, 19, NULL);
1564
1565 /* Terminate CS4215 control mode - data sheet says
1566 * "Set CLB=1 and send two more frames of valid control info"
1567 */
1568 dbri->mm.ctrl[0] |= CS4215_CLB;
1569 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1570
1571 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1572 udelay(250);
1573
1574 cs4215_setdata(dbri, 0);
1575
1576 return 0;
1577}
1578
1579/*
1580 * Setup the codec with the sampling rate, audio format and number of
1581 * channels.
1582 * As part of the process we resend the settings for the data
1583 * timeslots as well.
1584 */
1585static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1586 snd_pcm_format_t format, unsigned int channels)
1587{
1588 int freq_idx;
1589 int ret = 0;
1590
1591 /* Lookup index for this rate */
1592 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1593 if (CS4215_FREQ[freq_idx].freq == rate)
1594 break;
1595 }
1596 if (CS4215_FREQ[freq_idx].freq != rate) {
1597 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1598 return -1;
1599 }
1600
1601 switch (format) {
1602 case SNDRV_PCM_FORMAT_MU_LAW:
1603 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1604 dbri->mm.precision = 8;
1605 break;
1606 case SNDRV_PCM_FORMAT_A_LAW:
1607 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1608 dbri->mm.precision = 8;
1609 break;
1610 case SNDRV_PCM_FORMAT_U8:
1611 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1612 dbri->mm.precision = 8;
1613 break;
1614 case SNDRV_PCM_FORMAT_S16_BE:
1615 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1616 dbri->mm.precision = 16;
1617 break;
1618 default:
1619 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1620 return -1;
1621 }
1622
1623 /* Add rate parameters */
1624 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1625 dbri->mm.ctrl[2] = CS4215_XCLK |
1626 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1627
1628 dbri->mm.channels = channels;
1629 if (channels == 2)
1630 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1631
1632 ret = cs4215_setctrl(dbri);
1633 if (ret == 0)
1634 cs4215_open(dbri); /* set codec to data mode */
1635
1636 return ret;
1637}
1638
1639/*
1640 *
1641 */
1642static int cs4215_init(struct snd_dbri *dbri)
1643{
1644 u32 reg2 = sbus_readl(dbri->regs + REG2);
1645 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1646
1647 /* Look for the cs4215 chips */
1648 if (reg2 & D_PIO2) {
1649 dprintk(D_MM, "Onboard CS4215 detected\n");
1650 dbri->mm.onboard = 1;
1651 }
1652 if (reg2 & D_PIO0) {
1653 dprintk(D_MM, "Speakerbox detected\n");
1654 dbri->mm.onboard = 0;
1655
1656 if (reg2 & D_PIO2) {
1657 printk(KERN_INFO "DBRI: Using speakerbox / "
1658 "ignoring onboard mmcodec.\n");
1659 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1660 }
1661 }
1662
1663 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1664 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1665 return -EIO;
1666 }
1667
1668 cs4215_setup_pipes(dbri);
1669 cs4215_init_data(&dbri->mm);
1670
1671 /* Enable capture of the status & version timeslots. */
1672 recv_fixed(dbri, 18, &dbri->mm.status);
1673 recv_fixed(dbri, 19, &dbri->mm.version);
1674
1675 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1676 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1677 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1678 dbri->mm.offset);
1679 return -EIO;
1680 }
1681 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1682
1683 return 0;
1684}
1685
1686/*
1687****************************************************************************
1688*************************** DBRI interrupt handler *************************
1689****************************************************************************
1690
1691The DBRI communicates with the CPU mainly via a circular interrupt
1692buffer. When an interrupt is signaled, the CPU walks through the
1693buffer and calls dbri_process_one_interrupt() for each interrupt word.
1694Complicated interrupts are handled by dedicated functions (which
1695appear first in this file). Any pending interrupts can be serviced by
1696calling dbri_process_interrupt_buffer(), which works even if the CPU's
1697interrupts are disabled.
1698
1699*/
1700
1701/* xmit_descs()
1702 *
1703 * Starts transmitting the current TD's for recording/playing.
1704 * For playback, ALSA has filled the DMA memory with new data (we hope).
1705 */
1706static void xmit_descs(struct snd_dbri *dbri)
1707{
1708 struct dbri_streaminfo *info;
1709 u32 dvma_addr;
1710 s32 *cmd;
1711 unsigned long flags;
1712 int first_td;
1713
1714 if (dbri == NULL)
1715 return; /* Disabled */
1716
1717 dvma_addr = (u32)dbri->dma_dvma;
1718 info = &dbri->stream_info[DBRI_REC];
1719 spin_lock_irqsave(&dbri->lock, flags);
1720
1721 if (info->pipe >= 0) {
1722 first_td = dbri->pipes[info->pipe].first_desc;
1723
1724 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1725
1726 /* Stream could be closed by the time we run. */
1727 if (first_td >= 0) {
1728 cmd = dbri_cmdlock(dbri, 2);
1729 *(cmd++) = DBRI_CMD(D_SDP, 0,
1730 dbri->pipes[info->pipe].sdp
1731 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1732 *(cmd++) = dvma_addr +
1733 dbri_dma_off(desc, first_td);
1734 dbri_cmdsend(dbri, cmd, 2);
1735
1736 /* Reset our admin of the pipe. */
1737 dbri->pipes[info->pipe].desc = first_td;
1738 }
1739 }
1740
1741 info = &dbri->stream_info[DBRI_PLAY];
1742
1743 if (info->pipe >= 0) {
1744 first_td = dbri->pipes[info->pipe].first_desc;
1745
1746 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1747
1748 /* Stream could be closed by the time we run. */
1749 if (first_td >= 0) {
1750 cmd = dbri_cmdlock(dbri, 2);
1751 *(cmd++) = DBRI_CMD(D_SDP, 0,
1752 dbri->pipes[info->pipe].sdp
1753 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1754 *(cmd++) = dvma_addr +
1755 dbri_dma_off(desc, first_td);
1756 dbri_cmdsend(dbri, cmd, 2);
1757
1758 /* Reset our admin of the pipe. */
1759 dbri->pipes[info->pipe].desc = first_td;
1760 }
1761 }
1762
1763 spin_unlock_irqrestore(&dbri->lock, flags);
1764}
1765
1766/* transmission_complete_intr()
1767 *
1768 * Called by main interrupt handler when DBRI signals transmission complete
1769 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1770 *
1771 * Walks through the pipe's list of transmit buffer descriptors and marks
1772 * them as available. Stops when the first descriptor is found without
1773 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1774 *
1775 * The DMA buffers are not released. They form a ring buffer and
1776 * they are filled by ALSA while others are transmitted by DMA.
1777 *
1778 */
1779
1780static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1781{
1782 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1783 int td = dbri->pipes[pipe].desc;
1784 int status;
1785
1786 while (td >= 0) {
1787 if (td >= DBRI_NO_DESCS) {
1788 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1789 return;
1790 }
1791
1792 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1793 if (!(status & DBRI_TD_TBC))
1794 break;
1795
1796 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1797
1798 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1799 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1800
1801 td = dbri->next_desc[td];
1802 dbri->pipes[pipe].desc = td;
1803 }
1804
1805 /* Notify ALSA */
1806 spin_unlock(&dbri->lock);
1807 snd_pcm_period_elapsed(info->substream);
1808 spin_lock(&dbri->lock);
1809}
1810
1811static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1812{
1813 struct dbri_streaminfo *info;
1814 int rd = dbri->pipes[pipe].desc;
1815 s32 status;
1816
1817 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1818 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1819 return;
1820 }
1821
1822 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1823 status = dbri->dma->desc[rd].word1;
1824 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1825
1826 info = &dbri->stream_info[DBRI_REC];
1827 info->offset += DBRI_RD_CNT(status);
1828
1829 /* FIXME: Check status */
1830
1831 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1832 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1833
1834 /* Notify ALSA */
1835 spin_unlock(&dbri->lock);
1836 snd_pcm_period_elapsed(info->substream);
1837 spin_lock(&dbri->lock);
1838}
1839
1840static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1841{
1842 int val = D_INTR_GETVAL(x);
1843 int channel = D_INTR_GETCHAN(x);
1844 int command = D_INTR_GETCMD(x);
1845 int code = D_INTR_GETCODE(x);
1846#ifdef DBRI_DEBUG
1847 int rval = D_INTR_GETRVAL(x);
1848#endif
1849
1850 if (channel == D_INTR_CMD) {
1851 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1852 cmds[command], val);
1853 } else {
1854 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1855 channel, code, rval);
1856 }
1857
1858 switch (code) {
1859 case D_INTR_CMDI:
1860 if (command != D_WAIT)
1861 printk(KERN_ERR "DBRI: Command read interrupt\n");
1862 break;
1863 case D_INTR_BRDY:
1864 reception_complete_intr(dbri, channel);
1865 break;
1866 case D_INTR_XCMP:
1867 case D_INTR_MINT:
1868 transmission_complete_intr(dbri, channel);
1869 break;
1870 case D_INTR_UNDR:
1871 /* UNDR - Transmission underrun
1872 * resend SDP command with clear pipe bit (C) set
1873 */
1874 {
1875 /* FIXME: do something useful in case of underrun */
1876 printk(KERN_ERR "DBRI: Underrun error\n");
1877#if 0
1878 s32 *cmd;
1879 int pipe = channel;
1880 int td = dbri->pipes[pipe].desc;
1881
1882 dbri->dma->desc[td].word4 = 0;
1883 cmd = dbri_cmdlock(dbri, NoGetLock);
1884 *(cmd++) = DBRI_CMD(D_SDP, 0,
1885 dbri->pipes[pipe].sdp
1886 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1887 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1888 dbri_cmdsend(dbri, cmd);
1889#endif
1890 }
1891 break;
1892 case D_INTR_FXDT:
1893 /* FXDT - Fixed data change */
1894 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1895 val = reverse_bytes(val, dbri->pipes[channel].length);
1896
1897 if (dbri->pipes[channel].recv_fixed_ptr)
1898 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1899 break;
1900 default:
1901 if (channel != D_INTR_CMD)
1902 printk(KERN_WARNING
1903 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1904 }
1905}
1906
1907/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1908 * buffer until it finds a zero word (indicating nothing more to do
1909 * right now). Non-zero words require processing and are handed off
1910 * to dbri_process_one_interrupt AFTER advancing the pointer.
1911 */
1912static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1913{
1914 s32 x;
1915
1916 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1917 dbri->dma->intr[dbri->dbri_irqp] = 0;
1918 dbri->dbri_irqp++;
1919 if (dbri->dbri_irqp == DBRI_INT_BLK)
1920 dbri->dbri_irqp = 1;
1921
1922 dbri_process_one_interrupt(dbri, x);
1923 }
1924}
1925
1926static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1927{
1928 struct snd_dbri *dbri = dev_id;
1929 static int errcnt = 0;
1930 int x;
1931
1932 if (dbri == NULL)
1933 return IRQ_NONE;
1934 spin_lock(&dbri->lock);
1935
1936 /*
1937 * Read it, so the interrupt goes away.
1938 */
1939 x = sbus_readl(dbri->regs + REG1);
1940
1941 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1942 u32 tmp;
1943
1944 if (x & D_MRR)
1945 printk(KERN_ERR
1946 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1947 x);
1948 if (x & D_MLE)
1949 printk(KERN_ERR
1950 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1951 x);
1952 if (x & D_LBG)
1953 printk(KERN_ERR
1954 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1955 if (x & D_MBE)
1956 printk(KERN_ERR
1957 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1958
1959 /* Some of these SBus errors cause the chip's SBus circuitry
1960 * to be disabled, so just re-enable and try to keep going.
1961 *
1962 * The only one I've seen is MRR, which will be triggered
1963 * if you let a transmit pipe underrun, then try to CDP it.
1964 *
1965 * If these things persist, we reset the chip.
1966 */
1967 if ((++errcnt) % 10 == 0) {
1968 dprintk(D_INT, "Interrupt errors exceeded.\n");
1969 dbri_reset(dbri);
1970 } else {
1971 tmp = sbus_readl(dbri->regs + REG0);
1972 tmp &= ~(D_D);
1973 sbus_writel(tmp, dbri->regs + REG0);
1974 }
1975 }
1976
1977 dbri_process_interrupt_buffer(dbri);
1978
1979 spin_unlock(&dbri->lock);
1980
1981 return IRQ_HANDLED;
1982}
1983
1984/****************************************************************************
1985 PCM Interface
1986****************************************************************************/
1987static const struct snd_pcm_hardware snd_dbri_pcm_hw = {
1988 .info = SNDRV_PCM_INFO_MMAP |
1989 SNDRV_PCM_INFO_INTERLEAVED |
1990 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1991 SNDRV_PCM_INFO_MMAP_VALID |
1992 SNDRV_PCM_INFO_BATCH,
1993 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1994 SNDRV_PCM_FMTBIT_A_LAW |
1995 SNDRV_PCM_FMTBIT_U8 |
1996 SNDRV_PCM_FMTBIT_S16_BE,
1997 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1998 .rate_min = 5512,
1999 .rate_max = 48000,
2000 .channels_min = 1,
2001 .channels_max = 2,
2002 .buffer_bytes_max = 64 * 1024,
2003 .period_bytes_min = 1,
2004 .period_bytes_max = DBRI_TD_MAXCNT,
2005 .periods_min = 1,
2006 .periods_max = 1024,
2007};
2008
2009static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
2010 struct snd_pcm_hw_rule *rule)
2011{
2012 struct snd_interval *c = hw_param_interval(params,
2013 SNDRV_PCM_HW_PARAM_CHANNELS);
2014 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2015 struct snd_mask fmt;
2016
2017 snd_mask_any(&fmt);
2018 if (c->min > 1) {
2019 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2020 return snd_mask_refine(f, &fmt);
2021 }
2022 return 0;
2023}
2024
2025static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2026 struct snd_pcm_hw_rule *rule)
2027{
2028 struct snd_interval *c = hw_param_interval(params,
2029 SNDRV_PCM_HW_PARAM_CHANNELS);
2030 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2031 struct snd_interval ch;
2032
2033 snd_interval_any(&ch);
2034 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2035 ch.min = 1;
2036 ch.max = 1;
2037 ch.integer = 1;
2038 return snd_interval_refine(c, &ch);
2039 }
2040 return 0;
2041}
2042
2043static int snd_dbri_open(struct snd_pcm_substream *substream)
2044{
2045 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2046 struct snd_pcm_runtime *runtime = substream->runtime;
2047 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2048 unsigned long flags;
2049
2050 dprintk(D_USR, "open audio output.\n");
2051 runtime->hw = snd_dbri_pcm_hw;
2052
2053 spin_lock_irqsave(&dbri->lock, flags);
2054 info->substream = substream;
2055 info->offset = 0;
2056 info->dvma_buffer = 0;
2057 info->pipe = -1;
2058 spin_unlock_irqrestore(&dbri->lock, flags);
2059
2060 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2061 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2062 -1);
2063 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2064 snd_hw_rule_channels, NULL,
2065 SNDRV_PCM_HW_PARAM_CHANNELS,
2066 -1);
2067
2068 cs4215_open(dbri);
2069
2070 return 0;
2071}
2072
2073static int snd_dbri_close(struct snd_pcm_substream *substream)
2074{
2075 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2076 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2077
2078 dprintk(D_USR, "close audio output.\n");
2079 info->substream = NULL;
2080 info->offset = 0;
2081
2082 return 0;
2083}
2084
2085static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2086 struct snd_pcm_hw_params *hw_params)
2087{
2088 struct snd_pcm_runtime *runtime = substream->runtime;
2089 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2090 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2091 int direction;
2092 int ret;
2093
2094 /* set sampling rate, audio format and number of channels */
2095 ret = cs4215_prepare(dbri, params_rate(hw_params),
2096 params_format(hw_params),
2097 params_channels(hw_params));
2098 if (ret != 0)
2099 return ret;
2100
2101 /* hw_params can get called multiple times. Only map the DMA once.
2102 */
2103 if (info->dvma_buffer == 0) {
2104 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2105 direction = DMA_TO_DEVICE;
2106 else
2107 direction = DMA_FROM_DEVICE;
2108
2109 info->dvma_buffer =
2110 dma_map_single(&dbri->op->dev,
2111 runtime->dma_area,
2112 params_buffer_bytes(hw_params),
2113 direction);
2114 }
2115
2116 direction = params_buffer_bytes(hw_params);
2117 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2118 direction, info->dvma_buffer);
2119 return 0;
2120}
2121
2122static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2123{
2124 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2125 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2126 int direction;
2127
2128 dprintk(D_USR, "hw_free.\n");
2129
2130 /* hw_free can get called multiple times. Only unmap the DMA once.
2131 */
2132 if (info->dvma_buffer) {
2133 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2134 direction = DMA_TO_DEVICE;
2135 else
2136 direction = DMA_FROM_DEVICE;
2137
2138 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2139 substream->runtime->buffer_size, direction);
2140 info->dvma_buffer = 0;
2141 }
2142 if (info->pipe != -1) {
2143 reset_pipe(dbri, info->pipe);
2144 info->pipe = -1;
2145 }
2146
2147 return 0;
2148}
2149
2150static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2151{
2152 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2153 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2154 int ret;
2155
2156 info->size = snd_pcm_lib_buffer_bytes(substream);
2157 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2158 info->pipe = 4; /* Send pipe */
2159 else
2160 info->pipe = 6; /* Receive pipe */
2161
2162 spin_lock_irq(&dbri->lock);
2163 info->offset = 0;
2164
2165 /* Setup the all the transmit/receive descriptors to cover the
2166 * whole DMA buffer.
2167 */
2168 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2169 snd_pcm_lib_period_bytes(substream));
2170
2171 spin_unlock_irq(&dbri->lock);
2172
2173 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2174 return ret;
2175}
2176
2177static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2178{
2179 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2180 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2181 int ret = 0;
2182
2183 switch (cmd) {
2184 case SNDRV_PCM_TRIGGER_START:
2185 dprintk(D_USR, "start audio, period is %d bytes\n",
2186 (int)snd_pcm_lib_period_bytes(substream));
2187 /* Re-submit the TDs. */
2188 xmit_descs(dbri);
2189 break;
2190 case SNDRV_PCM_TRIGGER_STOP:
2191 dprintk(D_USR, "stop audio.\n");
2192 reset_pipe(dbri, info->pipe);
2193 break;
2194 default:
2195 ret = -EINVAL;
2196 }
2197
2198 return ret;
2199}
2200
2201static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2202{
2203 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2204 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2205 snd_pcm_uframes_t ret;
2206
2207 ret = bytes_to_frames(substream->runtime, info->offset)
2208 % substream->runtime->buffer_size;
2209 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2210 ret, substream->runtime->buffer_size);
2211 return ret;
2212}
2213
2214static const struct snd_pcm_ops snd_dbri_ops = {
2215 .open = snd_dbri_open,
2216 .close = snd_dbri_close,
2217 .hw_params = snd_dbri_hw_params,
2218 .hw_free = snd_dbri_hw_free,
2219 .prepare = snd_dbri_prepare,
2220 .trigger = snd_dbri_trigger,
2221 .pointer = snd_dbri_pointer,
2222};
2223
2224static int snd_dbri_pcm(struct snd_card *card)
2225{
2226 struct snd_pcm *pcm;
2227 int err;
2228
2229 err = snd_pcm_new(card,
2230 /* ID */ "sun_dbri",
2231 /* device */ 0,
2232 /* playback count */ 1,
2233 /* capture count */ 1, &pcm);
2234 if (err < 0)
2235 return err;
2236
2237 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2238 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2239
2240 pcm->private_data = card->private_data;
2241 pcm->info_flags = 0;
2242 strcpy(pcm->name, card->shortname);
2243
2244 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
2245 NULL, 64 * 1024, 64 * 1024);
2246 return 0;
2247}
2248
2249/*****************************************************************************
2250 Mixer interface
2251*****************************************************************************/
2252
2253static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2254 struct snd_ctl_elem_info *uinfo)
2255{
2256 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2257 uinfo->count = 2;
2258 uinfo->value.integer.min = 0;
2259 if (kcontrol->private_value == DBRI_PLAY)
2260 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2261 else
2262 uinfo->value.integer.max = DBRI_MAX_GAIN;
2263 return 0;
2264}
2265
2266static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2267 struct snd_ctl_elem_value *ucontrol)
2268{
2269 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2270 struct dbri_streaminfo *info;
2271
2272 if (snd_BUG_ON(!dbri))
2273 return -EINVAL;
2274 info = &dbri->stream_info[kcontrol->private_value];
2275
2276 ucontrol->value.integer.value[0] = info->left_gain;
2277 ucontrol->value.integer.value[1] = info->right_gain;
2278 return 0;
2279}
2280
2281static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2282 struct snd_ctl_elem_value *ucontrol)
2283{
2284 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2285 struct dbri_streaminfo *info =
2286 &dbri->stream_info[kcontrol->private_value];
2287 unsigned int vol[2];
2288 int changed = 0;
2289
2290 vol[0] = ucontrol->value.integer.value[0];
2291 vol[1] = ucontrol->value.integer.value[1];
2292 if (kcontrol->private_value == DBRI_PLAY) {
2293 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2294 return -EINVAL;
2295 } else {
2296 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2297 return -EINVAL;
2298 }
2299
2300 if (info->left_gain != vol[0]) {
2301 info->left_gain = vol[0];
2302 changed = 1;
2303 }
2304 if (info->right_gain != vol[1]) {
2305 info->right_gain = vol[1];
2306 changed = 1;
2307 }
2308 if (changed) {
2309 /* First mute outputs, and wait 1/8000 sec (125 us)
2310 * to make sure this takes. This avoids clicking noises.
2311 */
2312 cs4215_setdata(dbri, 1);
2313 udelay(125);
2314 cs4215_setdata(dbri, 0);
2315 }
2316 return changed;
2317}
2318
2319static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2320 struct snd_ctl_elem_info *uinfo)
2321{
2322 int mask = (kcontrol->private_value >> 16) & 0xff;
2323
2324 uinfo->type = (mask == 1) ?
2325 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2326 uinfo->count = 1;
2327 uinfo->value.integer.min = 0;
2328 uinfo->value.integer.max = mask;
2329 return 0;
2330}
2331
2332static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2333 struct snd_ctl_elem_value *ucontrol)
2334{
2335 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2336 int elem = kcontrol->private_value & 0xff;
2337 int shift = (kcontrol->private_value >> 8) & 0xff;
2338 int mask = (kcontrol->private_value >> 16) & 0xff;
2339 int invert = (kcontrol->private_value >> 24) & 1;
2340
2341 if (snd_BUG_ON(!dbri))
2342 return -EINVAL;
2343
2344 if (elem < 4)
2345 ucontrol->value.integer.value[0] =
2346 (dbri->mm.data[elem] >> shift) & mask;
2347 else
2348 ucontrol->value.integer.value[0] =
2349 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2350
2351 if (invert == 1)
2352 ucontrol->value.integer.value[0] =
2353 mask - ucontrol->value.integer.value[0];
2354 return 0;
2355}
2356
2357static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2358 struct snd_ctl_elem_value *ucontrol)
2359{
2360 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2361 int elem = kcontrol->private_value & 0xff;
2362 int shift = (kcontrol->private_value >> 8) & 0xff;
2363 int mask = (kcontrol->private_value >> 16) & 0xff;
2364 int invert = (kcontrol->private_value >> 24) & 1;
2365 int changed = 0;
2366 unsigned short val;
2367
2368 if (snd_BUG_ON(!dbri))
2369 return -EINVAL;
2370
2371 val = (ucontrol->value.integer.value[0] & mask);
2372 if (invert == 1)
2373 val = mask - val;
2374 val <<= shift;
2375
2376 if (elem < 4) {
2377 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2378 ~(mask << shift)) | val;
2379 changed = (val != dbri->mm.data[elem]);
2380 } else {
2381 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2382 ~(mask << shift)) | val;
2383 changed = (val != dbri->mm.ctrl[elem - 4]);
2384 }
2385
2386 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2387 "mixer-value=%ld, mm-value=0x%x\n",
2388 mask, changed, ucontrol->value.integer.value[0],
2389 dbri->mm.data[elem & 3]);
2390
2391 if (changed) {
2392 /* First mute outputs, and wait 1/8000 sec (125 us)
2393 * to make sure this takes. This avoids clicking noises.
2394 */
2395 cs4215_setdata(dbri, 1);
2396 udelay(125);
2397 cs4215_setdata(dbri, 0);
2398 }
2399 return changed;
2400}
2401
2402/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2403 timeslots. Shift is the bit offset in the timeslot, mask defines the
2404 number of bits. invert is a boolean for use with attenuation.
2405 */
2406#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2407{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2408 .info = snd_cs4215_info_single, \
2409 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2410 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2411 ((invert) << 24) },
2412
2413static const struct snd_kcontrol_new dbri_controls[] = {
2414 {
2415 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2416 .name = "Playback Volume",
2417 .info = snd_cs4215_info_volume,
2418 .get = snd_cs4215_get_volume,
2419 .put = snd_cs4215_put_volume,
2420 .private_value = DBRI_PLAY,
2421 },
2422 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2423 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2424 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2425 {
2426 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2427 .name = "Capture Volume",
2428 .info = snd_cs4215_info_volume,
2429 .get = snd_cs4215_get_volume,
2430 .put = snd_cs4215_put_volume,
2431 .private_value = DBRI_REC,
2432 },
2433 /* FIXME: mic/line switch */
2434 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2435 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2436 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2437 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2438};
2439
2440static int snd_dbri_mixer(struct snd_card *card)
2441{
2442 int idx, err;
2443 struct snd_dbri *dbri;
2444
2445 if (snd_BUG_ON(!card || !card->private_data))
2446 return -EINVAL;
2447 dbri = card->private_data;
2448
2449 strcpy(card->mixername, card->shortname);
2450
2451 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2452 err = snd_ctl_add(card,
2453 snd_ctl_new1(&dbri_controls[idx], dbri));
2454 if (err < 0)
2455 return err;
2456 }
2457
2458 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2459 dbri->stream_info[idx].left_gain = 0;
2460 dbri->stream_info[idx].right_gain = 0;
2461 }
2462
2463 return 0;
2464}
2465
2466/****************************************************************************
2467 /proc interface
2468****************************************************************************/
2469static void dbri_regs_read(struct snd_info_entry *entry,
2470 struct snd_info_buffer *buffer)
2471{
2472 struct snd_dbri *dbri = entry->private_data;
2473
2474 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2475 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2476 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2477 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2478}
2479
2480#ifdef DBRI_DEBUG
2481static void dbri_debug_read(struct snd_info_entry *entry,
2482 struct snd_info_buffer *buffer)
2483{
2484 struct snd_dbri *dbri = entry->private_data;
2485 int pipe;
2486 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2487
2488 for (pipe = 0; pipe < 32; pipe++) {
2489 if (pipe_active(dbri, pipe)) {
2490 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2491 snd_iprintf(buffer,
2492 "Pipe %d: %s SDP=0x%x desc=%d, "
2493 "len=%d next %d\n",
2494 pipe,
2495 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2496 "input",
2497 pptr->sdp, pptr->desc,
2498 pptr->length, pptr->nextpipe);
2499 }
2500 }
2501}
2502#endif
2503
2504static void snd_dbri_proc(struct snd_card *card)
2505{
2506 struct snd_dbri *dbri = card->private_data;
2507
2508 snd_card_ro_proc_new(card, "regs", dbri, dbri_regs_read);
2509#ifdef DBRI_DEBUG
2510 snd_card_ro_proc_new(card, "debug", dbri, dbri_debug_read);
2511#endif
2512}
2513
2514/*
2515****************************************************************************
2516**************************** Initialization ********************************
2517****************************************************************************
2518*/
2519static void snd_dbri_free(struct snd_dbri *dbri);
2520
2521static int snd_dbri_create(struct snd_card *card,
2522 struct platform_device *op,
2523 int irq, int dev)
2524{
2525 struct snd_dbri *dbri = card->private_data;
2526 int err;
2527
2528 spin_lock_init(&dbri->lock);
2529 dbri->op = op;
2530 dbri->irq = irq;
2531
2532 dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma),
2533 &dbri->dma_dvma, GFP_KERNEL);
2534 if (!dbri->dma)
2535 return -ENOMEM;
2536
2537 dprintk(D_GEN, "DMA Cmd Block 0x%p (%pad)\n",
2538 dbri->dma, dbri->dma_dvma);
2539
2540 /* Map the registers into memory. */
2541 dbri->regs_size = resource_size(&op->resource[0]);
2542 dbri->regs = of_ioremap(&op->resource[0], 0,
2543 dbri->regs_size, "DBRI Registers");
2544 if (!dbri->regs) {
2545 printk(KERN_ERR "DBRI: could not allocate registers\n");
2546 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2547 (void *)dbri->dma, dbri->dma_dvma);
2548 return -EIO;
2549 }
2550
2551 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2552 "DBRI audio", dbri);
2553 if (err) {
2554 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2555 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2556 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2557 (void *)dbri->dma, dbri->dma_dvma);
2558 return err;
2559 }
2560
2561 /* Do low level initialization of the DBRI and CS4215 chips */
2562 dbri_initialize(dbri);
2563 err = cs4215_init(dbri);
2564 if (err) {
2565 snd_dbri_free(dbri);
2566 return err;
2567 }
2568
2569 return 0;
2570}
2571
2572static void snd_dbri_free(struct snd_dbri *dbri)
2573{
2574 dprintk(D_GEN, "snd_dbri_free\n");
2575 dbri_reset(dbri);
2576
2577 if (dbri->irq)
2578 free_irq(dbri->irq, dbri);
2579
2580 if (dbri->regs)
2581 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2582
2583 if (dbri->dma)
2584 dma_free_coherent(&dbri->op->dev,
2585 sizeof(struct dbri_dma),
2586 (void *)dbri->dma, dbri->dma_dvma);
2587}
2588
2589static int dbri_probe(struct platform_device *op)
2590{
2591 struct snd_dbri *dbri;
2592 struct resource *rp;
2593 struct snd_card *card;
2594 static int dev = 0;
2595 int irq;
2596 int err;
2597
2598 if (dev >= SNDRV_CARDS)
2599 return -ENODEV;
2600 if (!enable[dev]) {
2601 dev++;
2602 return -ENOENT;
2603 }
2604
2605 irq = op->archdata.irqs[0];
2606 if (irq <= 0) {
2607 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2608 return -ENODEV;
2609 }
2610
2611 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
2612 sizeof(struct snd_dbri), &card);
2613 if (err < 0)
2614 return err;
2615
2616 strcpy(card->driver, "DBRI");
2617 strcpy(card->shortname, "Sun DBRI");
2618 rp = &op->resource[0];
2619 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2620 card->shortname,
2621 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2622
2623 err = snd_dbri_create(card, op, irq, dev);
2624 if (err < 0) {
2625 snd_card_free(card);
2626 return err;
2627 }
2628
2629 dbri = card->private_data;
2630 err = snd_dbri_pcm(card);
2631 if (err < 0)
2632 goto _err;
2633
2634 err = snd_dbri_mixer(card);
2635 if (err < 0)
2636 goto _err;
2637
2638 /* /proc file handling */
2639 snd_dbri_proc(card);
2640 dev_set_drvdata(&op->dev, card);
2641
2642 err = snd_card_register(card);
2643 if (err < 0)
2644 goto _err;
2645
2646 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2647 dev, dbri->regs,
2648 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2649 dev++;
2650
2651 return 0;
2652
2653_err:
2654 snd_dbri_free(dbri);
2655 snd_card_free(card);
2656 return err;
2657}
2658
2659static int dbri_remove(struct platform_device *op)
2660{
2661 struct snd_card *card = dev_get_drvdata(&op->dev);
2662
2663 snd_dbri_free(card->private_data);
2664 snd_card_free(card);
2665
2666 return 0;
2667}
2668
2669static const struct of_device_id dbri_match[] = {
2670 {
2671 .name = "SUNW,DBRIe",
2672 },
2673 {
2674 .name = "SUNW,DBRIf",
2675 },
2676 {},
2677};
2678
2679MODULE_DEVICE_TABLE(of, dbri_match);
2680
2681static struct platform_driver dbri_sbus_driver = {
2682 .driver = {
2683 .name = "dbri",
2684 .of_match_table = dbri_match,
2685 },
2686 .probe = dbri_probe,
2687 .remove = dbri_remove,
2688};
2689
2690module_platform_driver(dbri_sbus_driver);
1/*
2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
4 *
5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
6 *
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
10 *
11 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCStation 10, 20, LX and Voyager models.
13 *
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
18 * Documentation:
19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
20 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
22 * available from the Lucent (formerly AT&T microelectronics) home
23 * page.
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
28 *
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
30 * memory and a serial device (long pipes, no. 0-15) or between two serial
31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
32 * device (short pipes).
33 * A timeslot defines the bit-offset and no. of bits read from a serial device.
34 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
37 *
38 * The mmcodec is connected via the CHI bus and needs the data & some
39 * parameters (volume, output selection) time multiplexed in 8 byte
40 * chunks. It also has a control mode, which serves for audio format setting.
41 *
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
43 * the same CHI bus, so I thought perhaps it is possible to use the on-board
44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
45 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * connected.
48 *
49 * I've tried to stick to the following function naming conventions:
50 * snd_* ALSA stuff
51 * cs4215_* CS4215 codec specific stuff
52 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
54 */
55
56#include <linux/interrupt.h>
57#include <linux/delay.h>
58#include <linux/irq.h>
59#include <linux/io.h>
60#include <linux/dma-mapping.h>
61#include <linux/gfp.h>
62
63#include <sound/core.h>
64#include <sound/pcm.h>
65#include <sound/pcm_params.h>
66#include <sound/info.h>
67#include <sound/control.h>
68#include <sound/initval.h>
69
70#include <linux/of.h>
71#include <linux/of_device.h>
72#include <linux/atomic.h>
73
74MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
75MODULE_DESCRIPTION("Sun DBRI");
76MODULE_LICENSE("GPL");
77MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
78
79static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
80static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
81/* Enable this card */
82static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
83
84module_param_array(index, int, NULL, 0444);
85MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
86module_param_array(id, charp, NULL, 0444);
87MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
88module_param_array(enable, bool, NULL, 0444);
89MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
90
91#undef DBRI_DEBUG
92
93#define D_INT (1<<0)
94#define D_GEN (1<<1)
95#define D_CMD (1<<2)
96#define D_MM (1<<3)
97#define D_USR (1<<4)
98#define D_DESC (1<<5)
99
100static int dbri_debug;
101module_param(dbri_debug, int, 0644);
102MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
103
104#ifdef DBRI_DEBUG
105static char *cmds[] = {
106 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
107 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
108};
109
110#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
111
112#else
113#define dprintk(a, x...) do { } while (0)
114
115#endif /* DBRI_DEBUG */
116
117#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
118 (intr << 27) | \
119 value)
120
121/***************************************************************************
122 CS4215 specific definitions and structures
123****************************************************************************/
124
125struct cs4215 {
126 __u8 data[4]; /* Data mode: Time slots 5-8 */
127 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
128 __u8 onboard;
129 __u8 offset; /* Bit offset from frame sync to time slot 1 */
130 volatile __u32 status;
131 volatile __u32 version;
132 __u8 precision; /* In bits, either 8 or 16 */
133 __u8 channels; /* 1 or 2 */
134};
135
136/*
137 * Control mode first
138 */
139
140/* Time Slot 1, Status register */
141#define CS4215_CLB (1<<2) /* Control Latch Bit */
142#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
143 /* 0: line: 2.8V, speaker 8V */
144#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
145#define CS4215_RSRVD_1 (1<<5)
146
147/* Time Slot 2, Data Format Register */
148#define CS4215_DFR_LINEAR16 0
149#define CS4215_DFR_ULAW 1
150#define CS4215_DFR_ALAW 2
151#define CS4215_DFR_LINEAR8 3
152#define CS4215_DFR_STEREO (1<<2)
153static struct {
154 unsigned short freq;
155 unsigned char xtal;
156 unsigned char csval;
157} CS4215_FREQ[] = {
158 { 8000, (1 << 4), (0 << 3) },
159 { 16000, (1 << 4), (1 << 3) },
160 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
161 { 32000, (1 << 4), (3 << 3) },
162 /* { NA, (1 << 4), (4 << 3) }, */
163 /* { NA, (1 << 4), (5 << 3) }, */
164 { 48000, (1 << 4), (6 << 3) },
165 { 9600, (1 << 4), (7 << 3) },
166 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
167 { 11025, (2 << 4), (1 << 3) },
168 { 18900, (2 << 4), (2 << 3) },
169 { 22050, (2 << 4), (3 << 3) },
170 { 37800, (2 << 4), (4 << 3) },
171 { 44100, (2 << 4), (5 << 3) },
172 { 33075, (2 << 4), (6 << 3) },
173 { 6615, (2 << 4), (7 << 3) },
174 { 0, 0, 0}
175};
176
177#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
178
179#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
180
181/* Time Slot 3, Serial Port Control register */
182#define CS4215_XEN (1<<0) /* 0: Enable serial output */
183#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
184#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
185#define CS4215_BSEL_128 (1<<2)
186#define CS4215_BSEL_256 (2<<2)
187#define CS4215_MCK_MAST (0<<4) /* Master clock */
188#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
189#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
190#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
191#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
192
193/* Time Slot 4, Test Register */
194#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
195#define CS4215_ENL (1<<1) /* Enable Loopback Testing */
196
197/* Time Slot 5, Parallel Port Register */
198/* Read only here and the same as the in data mode */
199
200/* Time Slot 6, Reserved */
201
202/* Time Slot 7, Version Register */
203#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
204
205/* Time Slot 8, Reserved */
206
207/*
208 * Data mode
209 */
210/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
211
212/* Time Slot 5, Output Setting */
213#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
214#define CS4215_LE (1<<6) /* Line Out Enable */
215#define CS4215_HE (1<<7) /* Headphone Enable */
216
217/* Time Slot 6, Output Setting */
218#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
219#define CS4215_SE (1<<6) /* Speaker Enable */
220#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
221
222/* Time Slot 7, Input Setting */
223#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
224#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
225#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
226#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
227#define CS4215_PIO1 (1<<7)
228
229/* Time Slot 8, Input Setting */
230#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
231#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
232
233/***************************************************************************
234 DBRI specific definitions and structures
235****************************************************************************/
236
237/* DBRI main registers */
238#define REG0 0x00 /* Status and Control */
239#define REG1 0x04 /* Mode and Interrupt */
240#define REG2 0x08 /* Parallel IO */
241#define REG3 0x0c /* Test */
242#define REG8 0x20 /* Command Queue Pointer */
243#define REG9 0x24 /* Interrupt Queue Pointer */
244
245#define DBRI_NO_CMDS 64
246#define DBRI_INT_BLK 64
247#define DBRI_NO_DESCS 64
248#define DBRI_NO_PIPES 32
249#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
250
251#define DBRI_REC 0
252#define DBRI_PLAY 1
253#define DBRI_NO_STREAMS 2
254
255/* One transmit/receive descriptor */
256/* When ba != 0 descriptor is used */
257struct dbri_mem {
258 volatile __u32 word1;
259 __u32 ba; /* Transmit/Receive Buffer Address */
260 __u32 nda; /* Next Descriptor Address */
261 volatile __u32 word4;
262};
263
264/* This structure is in a DMA region where it can accessed by both
265 * the CPU and the DBRI
266 */
267struct dbri_dma {
268 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
269 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
270 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
271};
272
273#define dbri_dma_off(member, elem) \
274 ((u32)(unsigned long) \
275 (&(((struct dbri_dma *)0)->member[elem])))
276
277enum in_or_out { PIPEinput, PIPEoutput };
278
279struct dbri_pipe {
280 u32 sdp; /* SDP command word */
281 int nextpipe; /* Next pipe in linked list */
282 int length; /* Length of timeslot (bits) */
283 int first_desc; /* Index of first descriptor */
284 int desc; /* Index of active descriptor */
285 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
286};
287
288/* Per stream (playback or record) information */
289struct dbri_streaminfo {
290 struct snd_pcm_substream *substream;
291 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
292 int size; /* Size of DMA buffer */
293 size_t offset; /* offset in user buffer */
294 int pipe; /* Data pipe used */
295 int left_gain; /* mixer elements */
296 int right_gain;
297};
298
299/* This structure holds the information for both chips (DBRI & CS4215) */
300struct snd_dbri {
301 int regs_size, irq; /* Needed for unload */
302 struct platform_device *op; /* OF device info */
303 spinlock_t lock;
304
305 struct dbri_dma *dma; /* Pointer to our DMA block */
306 u32 dma_dvma; /* DBRI visible DMA address */
307
308 void __iomem *regs; /* dbri HW regs */
309 int dbri_irqp; /* intr queue pointer */
310
311 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
312 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
313 spinlock_t cmdlock; /* Protects cmd queue accesses */
314 s32 *cmdptr; /* Pointer to the last queued cmd */
315
316 int chi_bpf;
317
318 struct cs4215 mm; /* mmcodec special info */
319 /* per stream (playback/record) info */
320 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
321};
322
323#define DBRI_MAX_VOLUME 63 /* Output volume */
324#define DBRI_MAX_GAIN 15 /* Input gain */
325
326/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
327#define D_P (1<<15) /* Program command & queue pointer valid */
328#define D_G (1<<14) /* Allow 4-Word SBus Burst */
329#define D_S (1<<13) /* Allow 16-Word SBus Burst */
330#define D_E (1<<12) /* Allow 8-Word SBus Burst */
331#define D_X (1<<7) /* Sanity Timer Disable */
332#define D_T (1<<6) /* Permit activation of the TE interface */
333#define D_N (1<<5) /* Permit activation of the NT interface */
334#define D_C (1<<4) /* Permit activation of the CHI interface */
335#define D_F (1<<3) /* Force Sanity Timer Time-Out */
336#define D_D (1<<2) /* Disable Master Mode */
337#define D_H (1<<1) /* Halt for Analysis */
338#define D_R (1<<0) /* Soft Reset */
339
340/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
341#define D_LITTLE_END (1<<8) /* Byte Order */
342#define D_BIG_END (0<<8) /* Byte Order */
343#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
344#define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
345#define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
346#define D_MBE (1<<1) /* Burst Error on SBus (read only) */
347#define D_IR (1<<0) /* Interrupt Indicator (read only) */
348
349/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
350#define D_ENPIO3 (1<<7) /* Enable Pin 3 */
351#define D_ENPIO2 (1<<6) /* Enable Pin 2 */
352#define D_ENPIO1 (1<<5) /* Enable Pin 1 */
353#define D_ENPIO0 (1<<4) /* Enable Pin 0 */
354#define D_ENPIO (0xf0) /* Enable all the pins */
355#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
356#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
357#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
358#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
359
360/* DBRI Commands (Page 20) */
361#define D_WAIT 0x0 /* Stop execution */
362#define D_PAUSE 0x1 /* Flush long pipes */
363#define D_JUMP 0x2 /* New command queue */
364#define D_IIQ 0x3 /* Initialize Interrupt Queue */
365#define D_REX 0x4 /* Report command execution via interrupt */
366#define D_SDP 0x5 /* Setup Data Pipe */
367#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
368#define D_DTS 0x7 /* Define Time Slot */
369#define D_SSP 0x8 /* Set short Data Pipe */
370#define D_CHI 0x9 /* Set CHI Global Mode */
371#define D_NT 0xa /* NT Command */
372#define D_TE 0xb /* TE Command */
373#define D_CDEC 0xc /* Codec setup */
374#define D_TEST 0xd /* No comment */
375#define D_CDM 0xe /* CHI Data mode command */
376
377/* Special bits for some commands */
378#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
379
380/* Setup Data Pipe */
381/* IRM */
382#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
383#define D_SDP_CHANGE (2<<18) /* Report any changes */
384#define D_SDP_EVERY (3<<18) /* Report any changes */
385#define D_SDP_EOL (1<<17) /* EOL interrupt enable */
386#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
387
388/* Pipe data MODE */
389#define D_SDP_MEM (0<<13) /* To/from memory */
390#define D_SDP_HDLC (2<<13)
391#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
392#define D_SDP_SER (4<<13) /* Serial to serial */
393#define D_SDP_FIXED (6<<13) /* Short only */
394#define D_SDP_MODE(v) ((v)&(7<<13))
395
396#define D_SDP_TO_SER (1<<12) /* Direction */
397#define D_SDP_FROM_SER (0<<12) /* Direction */
398#define D_SDP_MSB (1<<11) /* Bit order within Byte */
399#define D_SDP_LSB (0<<11) /* Bit order within Byte */
400#define D_SDP_P (1<<10) /* Pointer Valid */
401#define D_SDP_A (1<<8) /* Abort */
402#define D_SDP_C (1<<7) /* Clear */
403
404/* Define Time Slot */
405#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
406#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
407#define D_DTS_INS (1<<15) /* Insert Time Slot */
408#define D_DTS_DEL (0<<15) /* Delete Time Slot */
409#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
410#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
411
412/* Time Slot defines */
413#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
414#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
415#define D_TS_DI (1<<13) /* Data Invert */
416#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
417#define D_TS_MONITOR (2<<10) /* Monitor pipe */
418#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
419#define D_TS_ANCHOR (7<<10) /* Starting short pipes */
420#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
421#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
422
423/* Concentration Highway Interface Modes */
424#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
425#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
426#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
427#define D_CHI_OD (1<<13) /* Open Drain Enable */
428#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
429#define D_CHI_FD (1<<11) /* Frame Drive */
430#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
431
432/* NT: These are here for completeness */
433#define D_NT_FBIT (1<<17) /* Frame Bit */
434#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
435#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
436#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
437#define D_NT_ISNT (1<<13) /* Configure interface as NT */
438#define D_NT_FT (1<<12) /* Fixed Timing */
439#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
440#define D_NT_IFA (1<<10) /* Inhibit Final Activation */
441#define D_NT_ACT (1<<9) /* Activate Interface */
442#define D_NT_MFE (1<<8) /* Multiframe Enable */
443#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
444#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
445#define D_NT_FACT (1<<1) /* Force Activation */
446#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
447
448/* Codec Setup */
449#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
450#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
451#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
452
453/* Test */
454#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
455#define D_TEST_SIZE(v) ((v)<<11) /* */
456#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
457#define D_TEST_PROC 0x6 /* Microprocessor test */
458#define D_TEST_SER 0x7 /* Serial-Controller test */
459#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
460#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
461#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
462#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
463#define D_TEST_DUMP 0xe /* ROM Dump */
464
465/* CHI Data Mode */
466#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
467#define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
468#define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
469#define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
470#define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
471#define D_CDM_REN (1 << 0) /* Receive Highway Enable */
472
473/* The Interrupts */
474#define D_INTR_BRDY 1 /* Buffer Ready for processing */
475#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
476#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
477#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
478#define D_INTR_EOL 5 /* End of List */
479#define D_INTR_CMDI 6 /* Command has bean read */
480#define D_INTR_XCMP 8 /* Transmission of frame complete */
481#define D_INTR_SBRI 9 /* BRI status change info */
482#define D_INTR_FXDT 10 /* Fixed data change */
483#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
484#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
485#define D_INTR_DBYT 12 /* Dropped by frame slip */
486#define D_INTR_RBYT 13 /* Repeated by frame slip */
487#define D_INTR_LINT 14 /* Lost Interrupt */
488#define D_INTR_UNDR 15 /* DMA underrun */
489
490#define D_INTR_TE 32
491#define D_INTR_NT 34
492#define D_INTR_CHI 36
493#define D_INTR_CMD 38
494
495#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
496#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
497#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
498#define D_INTR_GETVAL(v) ((v) & 0xffff)
499#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
500
501#define D_P_0 0 /* TE receive anchor */
502#define D_P_1 1 /* TE transmit anchor */
503#define D_P_2 2 /* NT transmit anchor */
504#define D_P_3 3 /* NT receive anchor */
505#define D_P_4 4 /* CHI send data */
506#define D_P_5 5 /* CHI receive data */
507#define D_P_6 6 /* */
508#define D_P_7 7 /* */
509#define D_P_8 8 /* */
510#define D_P_9 9 /* */
511#define D_P_10 10 /* */
512#define D_P_11 11 /* */
513#define D_P_12 12 /* */
514#define D_P_13 13 /* */
515#define D_P_14 14 /* */
516#define D_P_15 15 /* */
517#define D_P_16 16 /* CHI anchor pipe */
518#define D_P_17 17 /* CHI send */
519#define D_P_18 18 /* CHI receive */
520#define D_P_19 19 /* CHI receive */
521#define D_P_20 20 /* CHI receive */
522#define D_P_21 21 /* */
523#define D_P_22 22 /* */
524#define D_P_23 23 /* */
525#define D_P_24 24 /* */
526#define D_P_25 25 /* */
527#define D_P_26 26 /* */
528#define D_P_27 27 /* */
529#define D_P_28 28 /* */
530#define D_P_29 29 /* */
531#define D_P_30 30 /* */
532#define D_P_31 31 /* */
533
534/* Transmit descriptor defines */
535#define DBRI_TD_F (1 << 31) /* End of Frame */
536#define DBRI_TD_D (1 << 30) /* Do not append CRC */
537#define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
538#define DBRI_TD_B (1 << 15) /* Final interrupt */
539#define DBRI_TD_M (1 << 14) /* Marker interrupt */
540#define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
541#define DBRI_TD_FCNT(v) (v) /* Flag Count */
542#define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
543#define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
544#define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
545#define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
546 /* Maximum buffer size per TD: almost 8KB */
547#define DBRI_TD_MAXCNT ((1 << 13) - 4)
548
549/* Receive descriptor defines */
550#define DBRI_RD_F (1 << 31) /* End of Frame */
551#define DBRI_RD_C (1 << 30) /* Completed buffer */
552#define DBRI_RD_B (1 << 15) /* Final interrupt */
553#define DBRI_RD_M (1 << 14) /* Marker interrupt */
554#define DBRI_RD_BCNT(v) (v) /* Buffer size */
555#define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
556#define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
557#define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
558#define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
559#define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
560#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
561
562/* stream_info[] access */
563/* Translate the ALSA direction into the array index */
564#define DBRI_STREAMNO(substream) \
565 (substream->stream == \
566 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
567
568/* Return a pointer to dbri_streaminfo */
569#define DBRI_STREAM(dbri, substream) \
570 &dbri->stream_info[DBRI_STREAMNO(substream)]
571
572/*
573 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
574 * So we have to reverse the bits. Note: not all bit lengths are supported
575 */
576static __u32 reverse_bytes(__u32 b, int len)
577{
578 switch (len) {
579 case 32:
580 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
581 case 16:
582 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
583 case 8:
584 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
585 case 4:
586 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
587 case 2:
588 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
589 case 1:
590 case 0:
591 break;
592 default:
593 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
594 };
595
596 return b;
597}
598
599/*
600****************************************************************************
601************** DBRI initialization and command synchronization *************
602****************************************************************************
603
604Commands are sent to the DBRI by building a list of them in memory,
605then writing the address of the first list item to DBRI register 8.
606The list is terminated with a WAIT command, which generates a
607CPU interrupt to signal completion.
608
609Since the DBRI can run in parallel with the CPU, several means of
610synchronization present themselves. The method implemented here uses
611the dbri_cmdwait() to wait for execution of batch of sent commands.
612
613A circular command buffer is used here. A new command is being added
614while another can be executed. The scheme works by adding two WAIT commands
615after each sent batch of commands. When the next batch is prepared it is
616added after the WAIT commands then the WAITs are replaced with single JUMP
617command to the new batch. The the DBRI is forced to reread the last WAIT
618command (replaced by the JUMP by then). If the DBRI is still executing
619previous commands the request to reread the WAIT command is ignored.
620
621Every time a routine wants to write commands to the DBRI, it must
622first call dbri_cmdlock() and get pointer to a free space in
623dbri->dma->cmd buffer. After this, the commands can be written to
624the buffer, and dbri_cmdsend() is called with the final pointer value
625to send them to the DBRI.
626
627*/
628
629#define MAXLOOPS 20
630/*
631 * Wait for the current command string to execute
632 */
633static void dbri_cmdwait(struct snd_dbri *dbri)
634{
635 int maxloops = MAXLOOPS;
636 unsigned long flags;
637
638 /* Delay if previous commands are still being processed */
639 spin_lock_irqsave(&dbri->lock, flags);
640 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
641 spin_unlock_irqrestore(&dbri->lock, flags);
642 msleep_interruptible(1);
643 spin_lock_irqsave(&dbri->lock, flags);
644 }
645 spin_unlock_irqrestore(&dbri->lock, flags);
646
647 if (maxloops == 0)
648 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
649 else
650 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
651 MAXLOOPS - maxloops - 1);
652}
653/*
654 * Lock the command queue and return pointer to space for len cmd words
655 * It locks the cmdlock spinlock.
656 */
657static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
658{
659 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
660 len += 2;
661 spin_lock(&dbri->cmdlock);
662 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
663 return dbri->cmdptr + 2;
664 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
665 return dbri->dma->cmd;
666 else
667 printk(KERN_ERR "DBRI: no space for commands.");
668
669 return NULL;
670}
671
672/*
673 * Send prepared cmd string. It works by writing a JUMP cmd into
674 * the last WAIT cmd and force DBRI to reread the cmd.
675 * The JUMP cmd points to the new cmd string.
676 * It also releases the cmdlock spinlock.
677 *
678 * Lock must be held before calling this.
679 */
680static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
681{
682 s32 tmp, addr;
683 static int wait_id = 0;
684
685 wait_id++;
686 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
687 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
688 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
689
690 /* Replace the last command with JUMP */
691 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
692 *(dbri->cmdptr+1) = addr;
693 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
694
695#ifdef DBRI_DEBUG
696 if (cmd > dbri->cmdptr) {
697 s32 *ptr;
698
699 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
700 dprintk(D_CMD, "cmd: %lx:%08x\n",
701 (unsigned long)ptr, *ptr);
702 } else {
703 s32 *ptr = dbri->cmdptr;
704
705 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
706 ptr++;
707 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
708 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
709 dprintk(D_CMD, "cmd: %lx:%08x\n",
710 (unsigned long)ptr, *ptr);
711 }
712#endif
713
714 /* Reread the last command */
715 tmp = sbus_readl(dbri->regs + REG0);
716 tmp |= D_P;
717 sbus_writel(tmp, dbri->regs + REG0);
718
719 dbri->cmdptr = cmd;
720 spin_unlock(&dbri->cmdlock);
721}
722
723/* Lock must be held when calling this */
724static void dbri_reset(struct snd_dbri *dbri)
725{
726 int i;
727 u32 tmp;
728
729 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
730 sbus_readl(dbri->regs + REG0),
731 sbus_readl(dbri->regs + REG2),
732 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
733
734 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
735 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
736 udelay(10);
737
738 /* A brute approach - DBRI falls back to working burst size by itself
739 * On SS20 D_S does not work, so do not try so high. */
740 tmp = sbus_readl(dbri->regs + REG0);
741 tmp |= D_G | D_E;
742 tmp &= ~D_S;
743 sbus_writel(tmp, dbri->regs + REG0);
744}
745
746/* Lock must not be held before calling this */
747static void __devinit dbri_initialize(struct snd_dbri *dbri)
748{
749 s32 *cmd;
750 u32 dma_addr;
751 unsigned long flags;
752 int n;
753
754 spin_lock_irqsave(&dbri->lock, flags);
755
756 dbri_reset(dbri);
757
758 /* Initialize pipes */
759 for (n = 0; n < DBRI_NO_PIPES; n++)
760 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
761
762 spin_lock_init(&dbri->cmdlock);
763 /*
764 * Initialize the interrupt ring buffer.
765 */
766 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
767 dbri->dma->intr[0] = dma_addr;
768 dbri->dbri_irqp = 1;
769 /*
770 * Set up the interrupt queue
771 */
772 spin_lock(&dbri->cmdlock);
773 cmd = dbri->cmdptr = dbri->dma->cmd;
774 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
775 *(cmd++) = dma_addr;
776 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
777 dbri->cmdptr = cmd;
778 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
779 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
780 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
781 sbus_writel(dma_addr, dbri->regs + REG8);
782 spin_unlock(&dbri->cmdlock);
783
784 spin_unlock_irqrestore(&dbri->lock, flags);
785 dbri_cmdwait(dbri);
786}
787
788/*
789****************************************************************************
790************************** DBRI data pipe management ***********************
791****************************************************************************
792
793While DBRI control functions use the command and interrupt buffers, the
794main data path takes the form of data pipes, which can be short (command
795and interrupt driven), or long (attached to DMA buffers). These functions
796provide a rudimentary means of setting up and managing the DBRI's pipes,
797but the calling functions have to make sure they respect the pipes' linked
798list ordering, among other things. The transmit and receive functions
799here interface closely with the transmit and receive interrupt code.
800
801*/
802static inline int pipe_active(struct snd_dbri *dbri, int pipe)
803{
804 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
805}
806
807/* reset_pipe(dbri, pipe)
808 *
809 * Called on an in-use pipe to clear anything being transmitted or received
810 * Lock must be held before calling this.
811 */
812static void reset_pipe(struct snd_dbri *dbri, int pipe)
813{
814 int sdp;
815 int desc;
816 s32 *cmd;
817
818 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
819 printk(KERN_ERR "DBRI: reset_pipe called with "
820 "illegal pipe number\n");
821 return;
822 }
823
824 sdp = dbri->pipes[pipe].sdp;
825 if (sdp == 0) {
826 printk(KERN_ERR "DBRI: reset_pipe called "
827 "on uninitialized pipe\n");
828 return;
829 }
830
831 cmd = dbri_cmdlock(dbri, 3);
832 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
833 *(cmd++) = 0;
834 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
835 dbri_cmdsend(dbri, cmd, 3);
836
837 desc = dbri->pipes[pipe].first_desc;
838 if (desc >= 0)
839 do {
840 dbri->dma->desc[desc].ba = 0;
841 dbri->dma->desc[desc].nda = 0;
842 desc = dbri->next_desc[desc];
843 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
844
845 dbri->pipes[pipe].desc = -1;
846 dbri->pipes[pipe].first_desc = -1;
847}
848
849/*
850 * Lock must be held before calling this.
851 */
852static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
853{
854 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
855 printk(KERN_ERR "DBRI: setup_pipe called "
856 "with illegal pipe number\n");
857 return;
858 }
859
860 if ((sdp & 0xf800) != sdp) {
861 printk(KERN_ERR "DBRI: setup_pipe called "
862 "with strange SDP value\n");
863 /* sdp &= 0xf800; */
864 }
865
866 /* If this is a fixed receive pipe, arrange for an interrupt
867 * every time its data changes
868 */
869 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
870 sdp |= D_SDP_CHANGE;
871
872 sdp |= D_PIPE(pipe);
873 dbri->pipes[pipe].sdp = sdp;
874 dbri->pipes[pipe].desc = -1;
875 dbri->pipes[pipe].first_desc = -1;
876
877 reset_pipe(dbri, pipe);
878}
879
880/*
881 * Lock must be held before calling this.
882 */
883static void link_time_slot(struct snd_dbri *dbri, int pipe,
884 int prevpipe, int nextpipe,
885 int length, int cycle)
886{
887 s32 *cmd;
888 int val;
889
890 if (pipe < 0 || pipe > DBRI_MAX_PIPE
891 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
892 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
893 printk(KERN_ERR
894 "DBRI: link_time_slot called with illegal pipe number\n");
895 return;
896 }
897
898 if (dbri->pipes[pipe].sdp == 0
899 || dbri->pipes[prevpipe].sdp == 0
900 || dbri->pipes[nextpipe].sdp == 0) {
901 printk(KERN_ERR "DBRI: link_time_slot called "
902 "on uninitialized pipe\n");
903 return;
904 }
905
906 dbri->pipes[prevpipe].nextpipe = pipe;
907 dbri->pipes[pipe].nextpipe = nextpipe;
908 dbri->pipes[pipe].length = length;
909
910 cmd = dbri_cmdlock(dbri, 4);
911
912 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
913 /* Deal with CHI special case:
914 * "If transmission on edges 0 or 1 is desired, then cycle n
915 * (where n = # of bit times per frame...) must be used."
916 * - DBRI data sheet, page 11
917 */
918 if (prevpipe == 16 && cycle == 0)
919 cycle = dbri->chi_bpf;
920
921 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
922 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
923 *(cmd++) = 0;
924 *(cmd++) =
925 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
926 } else {
927 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
928 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
929 *(cmd++) =
930 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
931 *(cmd++) = 0;
932 }
933 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
934
935 dbri_cmdsend(dbri, cmd, 4);
936}
937
938#if 0
939/*
940 * Lock must be held before calling this.
941 */
942static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
943 enum in_or_out direction, int prevpipe,
944 int nextpipe)
945{
946 s32 *cmd;
947 int val;
948
949 if (pipe < 0 || pipe > DBRI_MAX_PIPE
950 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
951 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
952 printk(KERN_ERR
953 "DBRI: unlink_time_slot called with illegal pipe number\n");
954 return;
955 }
956
957 cmd = dbri_cmdlock(dbri, 4);
958
959 if (direction == PIPEinput) {
960 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
961 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
962 *(cmd++) = D_TS_NEXT(nextpipe);
963 *(cmd++) = 0;
964 } else {
965 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
966 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
967 *(cmd++) = 0;
968 *(cmd++) = D_TS_NEXT(nextpipe);
969 }
970 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
971
972 dbri_cmdsend(dbri, cmd, 4);
973}
974#endif
975
976/* xmit_fixed() / recv_fixed()
977 *
978 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
979 * expected to change much, and which we don't need to buffer.
980 * The DBRI only interrupts us when the data changes (receive pipes),
981 * or only changes the data when this function is called (transmit pipes).
982 * Only short pipes (numbers 16-31) can be used in fixed data mode.
983 *
984 * These function operate on a 32-bit field, no matter how large
985 * the actual time slot is. The interrupt handler takes care of bit
986 * ordering and alignment. An 8-bit time slot will always end up
987 * in the low-order 8 bits, filled either MSB-first or LSB-first,
988 * depending on the settings passed to setup_pipe().
989 *
990 * Lock must not be held before calling it.
991 */
992static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
993{
994 s32 *cmd;
995 unsigned long flags;
996
997 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
998 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
999 return;
1000 }
1001
1002 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1003 printk(KERN_ERR "DBRI: xmit_fixed: "
1004 "Uninitialized pipe %d\n", pipe);
1005 return;
1006 }
1007
1008 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1009 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1010 return;
1011 }
1012
1013 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1014 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1015 pipe);
1016 return;
1017 }
1018
1019 /* DBRI short pipes always transmit LSB first */
1020
1021 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1022 data = reverse_bytes(data, dbri->pipes[pipe].length);
1023
1024 cmd = dbri_cmdlock(dbri, 3);
1025
1026 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1027 *(cmd++) = data;
1028 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1029
1030 spin_lock_irqsave(&dbri->lock, flags);
1031 dbri_cmdsend(dbri, cmd, 3);
1032 spin_unlock_irqrestore(&dbri->lock, flags);
1033 dbri_cmdwait(dbri);
1034
1035}
1036
1037static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1038{
1039 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1040 printk(KERN_ERR "DBRI: recv_fixed called with "
1041 "illegal pipe number\n");
1042 return;
1043 }
1044
1045 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1046 printk(KERN_ERR "DBRI: recv_fixed called on "
1047 "non-fixed pipe %d\n", pipe);
1048 return;
1049 }
1050
1051 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1052 printk(KERN_ERR "DBRI: recv_fixed called on "
1053 "transmit pipe %d\n", pipe);
1054 return;
1055 }
1056
1057 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1058}
1059
1060/* setup_descs()
1061 *
1062 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1063 * with a DMA buffer.
1064 *
1065 * Only pipe numbers 0-15 can be used in this mode.
1066 *
1067 * This function takes a stream number pointing to a data buffer,
1068 * and work by building chains of descriptors which identify the
1069 * data buffers. Buffers too large for a single descriptor will
1070 * be spread across multiple descriptors.
1071 *
1072 * All descriptors create a ring buffer.
1073 *
1074 * Lock must be held before calling this.
1075 */
1076static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1077{
1078 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1079 __u32 dvma_buffer;
1080 int desc;
1081 int len;
1082 int first_desc = -1;
1083 int last_desc = -1;
1084
1085 if (info->pipe < 0 || info->pipe > 15) {
1086 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1087 return -2;
1088 }
1089
1090 if (dbri->pipes[info->pipe].sdp == 0) {
1091 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1092 info->pipe);
1093 return -2;
1094 }
1095
1096 dvma_buffer = info->dvma_buffer;
1097 len = info->size;
1098
1099 if (streamno == DBRI_PLAY) {
1100 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1101 printk(KERN_ERR "DBRI: setup_descs: "
1102 "Called on receive pipe %d\n", info->pipe);
1103 return -2;
1104 }
1105 } else {
1106 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1107 printk(KERN_ERR
1108 "DBRI: setup_descs: Called on transmit pipe %d\n",
1109 info->pipe);
1110 return -2;
1111 }
1112 /* Should be able to queue multiple buffers
1113 * to receive on a pipe
1114 */
1115 if (pipe_active(dbri, info->pipe)) {
1116 printk(KERN_ERR "DBRI: recv_on_pipe: "
1117 "Called on active pipe %d\n", info->pipe);
1118 return -2;
1119 }
1120
1121 /* Make sure buffer size is multiple of four */
1122 len &= ~3;
1123 }
1124
1125 /* Free descriptors if pipe has any */
1126 desc = dbri->pipes[info->pipe].first_desc;
1127 if (desc >= 0)
1128 do {
1129 dbri->dma->desc[desc].ba = 0;
1130 dbri->dma->desc[desc].nda = 0;
1131 desc = dbri->next_desc[desc];
1132 } while (desc != -1 &&
1133 desc != dbri->pipes[info->pipe].first_desc);
1134
1135 dbri->pipes[info->pipe].desc = -1;
1136 dbri->pipes[info->pipe].first_desc = -1;
1137
1138 desc = 0;
1139 while (len > 0) {
1140 int mylen;
1141
1142 for (; desc < DBRI_NO_DESCS; desc++) {
1143 if (!dbri->dma->desc[desc].ba)
1144 break;
1145 }
1146
1147 if (desc == DBRI_NO_DESCS) {
1148 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1149 return -1;
1150 }
1151
1152 if (len > DBRI_TD_MAXCNT)
1153 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1154 else
1155 mylen = len;
1156
1157 if (mylen > period)
1158 mylen = period;
1159
1160 dbri->next_desc[desc] = -1;
1161 dbri->dma->desc[desc].ba = dvma_buffer;
1162 dbri->dma->desc[desc].nda = 0;
1163
1164 if (streamno == DBRI_PLAY) {
1165 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1166 dbri->dma->desc[desc].word4 = 0;
1167 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1168 } else {
1169 dbri->dma->desc[desc].word1 = 0;
1170 dbri->dma->desc[desc].word4 =
1171 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1172 }
1173
1174 if (first_desc == -1)
1175 first_desc = desc;
1176 else {
1177 dbri->next_desc[last_desc] = desc;
1178 dbri->dma->desc[last_desc].nda =
1179 dbri->dma_dvma + dbri_dma_off(desc, desc);
1180 }
1181
1182 last_desc = desc;
1183 dvma_buffer += mylen;
1184 len -= mylen;
1185 }
1186
1187 if (first_desc == -1 || last_desc == -1) {
1188 printk(KERN_ERR "DBRI: setup_descs: "
1189 " Not enough descriptors available\n");
1190 return -1;
1191 }
1192
1193 dbri->dma->desc[last_desc].nda =
1194 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1195 dbri->next_desc[last_desc] = first_desc;
1196 dbri->pipes[info->pipe].first_desc = first_desc;
1197 dbri->pipes[info->pipe].desc = first_desc;
1198
1199#ifdef DBRI_DEBUG
1200 for (desc = first_desc; desc != -1;) {
1201 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1202 desc,
1203 dbri->dma->desc[desc].word1,
1204 dbri->dma->desc[desc].ba,
1205 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1206 desc = dbri->next_desc[desc];
1207 if (desc == first_desc)
1208 break;
1209 }
1210#endif
1211 return 0;
1212}
1213
1214/*
1215****************************************************************************
1216************************** DBRI - CHI interface ****************************
1217****************************************************************************
1218
1219The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1220multiplexed serial interface which the DBRI can operate in either master
1221(give clock/frame sync) or slave (take clock/frame sync) mode.
1222
1223*/
1224
1225enum master_or_slave { CHImaster, CHIslave };
1226
1227/*
1228 * Lock must not be held before calling it.
1229 */
1230static void reset_chi(struct snd_dbri *dbri,
1231 enum master_or_slave master_or_slave,
1232 int bits_per_frame)
1233{
1234 s32 *cmd;
1235 int val;
1236
1237 /* Set CHI Anchor: Pipe 16 */
1238
1239 cmd = dbri_cmdlock(dbri, 4);
1240 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1241 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1242 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1243 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1244 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1245 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1246 dbri_cmdsend(dbri, cmd, 4);
1247
1248 dbri->pipes[16].sdp = 1;
1249 dbri->pipes[16].nextpipe = 16;
1250
1251 cmd = dbri_cmdlock(dbri, 4);
1252
1253 if (master_or_slave == CHIslave) {
1254 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1255 *
1256 * CHICM = 0 (slave mode, 8 kHz frame rate)
1257 * IR = give immediate CHI status interrupt
1258 * EN = give CHI status interrupt upon change
1259 */
1260 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1261 } else {
1262 /* Setup DBRI for CHI Master - generate clock, FS
1263 *
1264 * BPF = bits per 8 kHz frame
1265 * 12.288 MHz / CHICM_divisor = clock rate
1266 * FD = 1 - drive CHIFS on rising edge of CHICK
1267 */
1268 int clockrate = bits_per_frame * 8;
1269 int divisor = 12288 / clockrate;
1270
1271 if (divisor > 255 || divisor * clockrate != 12288)
1272 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1273 "in setup_chi\n");
1274
1275 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1276 | D_CHI_BPF(bits_per_frame));
1277 }
1278
1279 dbri->chi_bpf = bits_per_frame;
1280
1281 /* CHI Data Mode
1282 *
1283 * RCE = 0 - receive on falling edge of CHICK
1284 * XCE = 1 - transmit on rising edge of CHICK
1285 * XEN = 1 - enable transmitter
1286 * REN = 1 - enable receiver
1287 */
1288
1289 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1290 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1291 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1292
1293 dbri_cmdsend(dbri, cmd, 4);
1294}
1295
1296/*
1297****************************************************************************
1298*********************** CS4215 audio codec management **********************
1299****************************************************************************
1300
1301In the standard SPARC audio configuration, the CS4215 codec is attached
1302to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1303
1304 * Lock must not be held before calling it.
1305
1306*/
1307static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri)
1308{
1309 unsigned long flags;
1310
1311 spin_lock_irqsave(&dbri->lock, flags);
1312 /*
1313 * Data mode:
1314 * Pipe 4: Send timeslots 1-4 (audio data)
1315 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1316 * Pipe 6: Receive timeslots 1-4 (audio data)
1317 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1318 * interrupt, and the rest of the data (slot 5 and 8) is
1319 * not relevant for us (only for doublechecking).
1320 *
1321 * Control mode:
1322 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1323 * Pipe 18: Receive timeslot 1 (clb).
1324 * Pipe 19: Receive timeslot 7 (version).
1325 */
1326
1327 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1328 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1329 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1330 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1331
1332 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1333 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1334 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1335 spin_unlock_irqrestore(&dbri->lock, flags);
1336
1337 dbri_cmdwait(dbri);
1338}
1339
1340static __devinit int cs4215_init_data(struct cs4215 *mm)
1341{
1342 /*
1343 * No action, memory resetting only.
1344 *
1345 * Data Time Slot 5-8
1346 * Speaker,Line and Headphone enable. Gain set to the half.
1347 * Input is mike.
1348 */
1349 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1350 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1351 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1352 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1353
1354 /*
1355 * Control Time Slot 1-4
1356 * 0: Default I/O voltage scale
1357 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1358 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1359 * 3: Tests disabled
1360 */
1361 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1362 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1363 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1364 mm->ctrl[3] = 0;
1365
1366 mm->status = 0;
1367 mm->version = 0xff;
1368 mm->precision = 8; /* For ULAW */
1369 mm->channels = 1;
1370
1371 return 0;
1372}
1373
1374static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1375{
1376 if (muted) {
1377 dbri->mm.data[0] |= 63;
1378 dbri->mm.data[1] |= 63;
1379 dbri->mm.data[2] &= ~15;
1380 dbri->mm.data[3] &= ~15;
1381 } else {
1382 /* Start by setting the playback attenuation. */
1383 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1384 int left_gain = info->left_gain & 0x3f;
1385 int right_gain = info->right_gain & 0x3f;
1386
1387 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1388 dbri->mm.data[1] &= ~0x3f;
1389 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1390 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1391
1392 /* Now set the recording gain. */
1393 info = &dbri->stream_info[DBRI_REC];
1394 left_gain = info->left_gain & 0xf;
1395 right_gain = info->right_gain & 0xf;
1396 dbri->mm.data[2] |= CS4215_LG(left_gain);
1397 dbri->mm.data[3] |= CS4215_RG(right_gain);
1398 }
1399
1400 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1401}
1402
1403/*
1404 * Set the CS4215 to data mode.
1405 */
1406static void cs4215_open(struct snd_dbri *dbri)
1407{
1408 int data_width;
1409 u32 tmp;
1410 unsigned long flags;
1411
1412 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1413 dbri->mm.channels, dbri->mm.precision);
1414
1415 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1416 * to make sure this takes. This avoids clicking noises.
1417 */
1418
1419 cs4215_setdata(dbri, 1);
1420 udelay(125);
1421
1422 /*
1423 * Data mode:
1424 * Pipe 4: Send timeslots 1-4 (audio data)
1425 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1426 * Pipe 6: Receive timeslots 1-4 (audio data)
1427 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1428 * interrupt, and the rest of the data (slot 5 and 8) is
1429 * not relevant for us (only for doublechecking).
1430 *
1431 * Just like in control mode, the time slots are all offset by eight
1432 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1433 * even if it's the CHI master. Don't ask me...
1434 */
1435 spin_lock_irqsave(&dbri->lock, flags);
1436 tmp = sbus_readl(dbri->regs + REG0);
1437 tmp &= ~(D_C); /* Disable CHI */
1438 sbus_writel(tmp, dbri->regs + REG0);
1439
1440 /* Switch CS4215 to data mode - set PIO3 to 1 */
1441 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1442 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1443
1444 reset_chi(dbri, CHIslave, 128);
1445
1446 /* Note: this next doesn't work for 8-bit stereo, because the two
1447 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1448 * (See CS4215 datasheet Fig 15)
1449 *
1450 * DBRI non-contiguous mode would be required to make this work.
1451 */
1452 data_width = dbri->mm.channels * dbri->mm.precision;
1453
1454 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1455 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1456 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1457 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1458
1459 /* FIXME: enable CHI after _setdata? */
1460 tmp = sbus_readl(dbri->regs + REG0);
1461 tmp |= D_C; /* Enable CHI */
1462 sbus_writel(tmp, dbri->regs + REG0);
1463 spin_unlock_irqrestore(&dbri->lock, flags);
1464
1465 cs4215_setdata(dbri, 0);
1466}
1467
1468/*
1469 * Send the control information (i.e. audio format)
1470 */
1471static int cs4215_setctrl(struct snd_dbri *dbri)
1472{
1473 int i, val;
1474 u32 tmp;
1475 unsigned long flags;
1476
1477 /* FIXME - let the CPU do something useful during these delays */
1478
1479 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1480 * to make sure this takes. This avoids clicking noises.
1481 */
1482 cs4215_setdata(dbri, 1);
1483 udelay(125);
1484
1485 /*
1486 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1487 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1488 */
1489 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1490 sbus_writel(val, dbri->regs + REG2);
1491 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1492 udelay(34);
1493
1494 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1495 * operate as CHI master, supplying clocking and frame synchronization.
1496 *
1497 * In Data mode, however, the CS4215 must be CHI master to insure
1498 * that its data stream is synchronous with its codec.
1499 *
1500 * The upshot of all this? We start by putting the DBRI into master
1501 * mode, program the CS4215 in Control mode, then switch the CS4215
1502 * into Data mode and put the DBRI into slave mode. Various timing
1503 * requirements must be observed along the way.
1504 *
1505 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1506 * others?), the addressing of the CS4215's time slots is
1507 * offset by eight bits, so we add eight to all the "cycle"
1508 * values in the Define Time Slot (DTS) commands. This is
1509 * done in hardware by a TI 248 that delays the DBRI->4215
1510 * frame sync signal by eight clock cycles. Anybody know why?
1511 */
1512 spin_lock_irqsave(&dbri->lock, flags);
1513 tmp = sbus_readl(dbri->regs + REG0);
1514 tmp &= ~D_C; /* Disable CHI */
1515 sbus_writel(tmp, dbri->regs + REG0);
1516
1517 reset_chi(dbri, CHImaster, 128);
1518
1519 /*
1520 * Control mode:
1521 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1522 * Pipe 18: Receive timeslot 1 (clb).
1523 * Pipe 19: Receive timeslot 7 (version).
1524 */
1525
1526 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1527 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1528 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1529 spin_unlock_irqrestore(&dbri->lock, flags);
1530
1531 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1532 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1533 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1534
1535 spin_lock_irqsave(&dbri->lock, flags);
1536 tmp = sbus_readl(dbri->regs + REG0);
1537 tmp |= D_C; /* Enable CHI */
1538 sbus_writel(tmp, dbri->regs + REG0);
1539 spin_unlock_irqrestore(&dbri->lock, flags);
1540
1541 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1542 msleep_interruptible(1);
1543
1544 if (i == 0) {
1545 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1546 dbri->mm.status);
1547 return -1;
1548 }
1549
1550 /* Disable changes to our copy of the version number, as we are about
1551 * to leave control mode.
1552 */
1553 recv_fixed(dbri, 19, NULL);
1554
1555 /* Terminate CS4215 control mode - data sheet says
1556 * "Set CLB=1 and send two more frames of valid control info"
1557 */
1558 dbri->mm.ctrl[0] |= CS4215_CLB;
1559 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1560
1561 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1562 udelay(250);
1563
1564 cs4215_setdata(dbri, 0);
1565
1566 return 0;
1567}
1568
1569/*
1570 * Setup the codec with the sampling rate, audio format and number of
1571 * channels.
1572 * As part of the process we resend the settings for the data
1573 * timeslots as well.
1574 */
1575static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1576 snd_pcm_format_t format, unsigned int channels)
1577{
1578 int freq_idx;
1579 int ret = 0;
1580
1581 /* Lookup index for this rate */
1582 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1583 if (CS4215_FREQ[freq_idx].freq == rate)
1584 break;
1585 }
1586 if (CS4215_FREQ[freq_idx].freq != rate) {
1587 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1588 return -1;
1589 }
1590
1591 switch (format) {
1592 case SNDRV_PCM_FORMAT_MU_LAW:
1593 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1594 dbri->mm.precision = 8;
1595 break;
1596 case SNDRV_PCM_FORMAT_A_LAW:
1597 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1598 dbri->mm.precision = 8;
1599 break;
1600 case SNDRV_PCM_FORMAT_U8:
1601 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1602 dbri->mm.precision = 8;
1603 break;
1604 case SNDRV_PCM_FORMAT_S16_BE:
1605 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1606 dbri->mm.precision = 16;
1607 break;
1608 default:
1609 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1610 return -1;
1611 }
1612
1613 /* Add rate parameters */
1614 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1615 dbri->mm.ctrl[2] = CS4215_XCLK |
1616 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1617
1618 dbri->mm.channels = channels;
1619 if (channels == 2)
1620 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1621
1622 ret = cs4215_setctrl(dbri);
1623 if (ret == 0)
1624 cs4215_open(dbri); /* set codec to data mode */
1625
1626 return ret;
1627}
1628
1629/*
1630 *
1631 */
1632static __devinit int cs4215_init(struct snd_dbri *dbri)
1633{
1634 u32 reg2 = sbus_readl(dbri->regs + REG2);
1635 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1636
1637 /* Look for the cs4215 chips */
1638 if (reg2 & D_PIO2) {
1639 dprintk(D_MM, "Onboard CS4215 detected\n");
1640 dbri->mm.onboard = 1;
1641 }
1642 if (reg2 & D_PIO0) {
1643 dprintk(D_MM, "Speakerbox detected\n");
1644 dbri->mm.onboard = 0;
1645
1646 if (reg2 & D_PIO2) {
1647 printk(KERN_INFO "DBRI: Using speakerbox / "
1648 "ignoring onboard mmcodec.\n");
1649 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1650 }
1651 }
1652
1653 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1654 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1655 return -EIO;
1656 }
1657
1658 cs4215_setup_pipes(dbri);
1659 cs4215_init_data(&dbri->mm);
1660
1661 /* Enable capture of the status & version timeslots. */
1662 recv_fixed(dbri, 18, &dbri->mm.status);
1663 recv_fixed(dbri, 19, &dbri->mm.version);
1664
1665 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1666 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1667 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1668 dbri->mm.offset);
1669 return -EIO;
1670 }
1671 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1672
1673 return 0;
1674}
1675
1676/*
1677****************************************************************************
1678*************************** DBRI interrupt handler *************************
1679****************************************************************************
1680
1681The DBRI communicates with the CPU mainly via a circular interrupt
1682buffer. When an interrupt is signaled, the CPU walks through the
1683buffer and calls dbri_process_one_interrupt() for each interrupt word.
1684Complicated interrupts are handled by dedicated functions (which
1685appear first in this file). Any pending interrupts can be serviced by
1686calling dbri_process_interrupt_buffer(), which works even if the CPU's
1687interrupts are disabled.
1688
1689*/
1690
1691/* xmit_descs()
1692 *
1693 * Starts transmitting the current TD's for recording/playing.
1694 * For playback, ALSA has filled the DMA memory with new data (we hope).
1695 */
1696static void xmit_descs(struct snd_dbri *dbri)
1697{
1698 struct dbri_streaminfo *info;
1699 s32 *cmd;
1700 unsigned long flags;
1701 int first_td;
1702
1703 if (dbri == NULL)
1704 return; /* Disabled */
1705
1706 info = &dbri->stream_info[DBRI_REC];
1707 spin_lock_irqsave(&dbri->lock, flags);
1708
1709 if (info->pipe >= 0) {
1710 first_td = dbri->pipes[info->pipe].first_desc;
1711
1712 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1713
1714 /* Stream could be closed by the time we run. */
1715 if (first_td >= 0) {
1716 cmd = dbri_cmdlock(dbri, 2);
1717 *(cmd++) = DBRI_CMD(D_SDP, 0,
1718 dbri->pipes[info->pipe].sdp
1719 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1720 *(cmd++) = dbri->dma_dvma +
1721 dbri_dma_off(desc, first_td);
1722 dbri_cmdsend(dbri, cmd, 2);
1723
1724 /* Reset our admin of the pipe. */
1725 dbri->pipes[info->pipe].desc = first_td;
1726 }
1727 }
1728
1729 info = &dbri->stream_info[DBRI_PLAY];
1730
1731 if (info->pipe >= 0) {
1732 first_td = dbri->pipes[info->pipe].first_desc;
1733
1734 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1735
1736 /* Stream could be closed by the time we run. */
1737 if (first_td >= 0) {
1738 cmd = dbri_cmdlock(dbri, 2);
1739 *(cmd++) = DBRI_CMD(D_SDP, 0,
1740 dbri->pipes[info->pipe].sdp
1741 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1742 *(cmd++) = dbri->dma_dvma +
1743 dbri_dma_off(desc, first_td);
1744 dbri_cmdsend(dbri, cmd, 2);
1745
1746 /* Reset our admin of the pipe. */
1747 dbri->pipes[info->pipe].desc = first_td;
1748 }
1749 }
1750
1751 spin_unlock_irqrestore(&dbri->lock, flags);
1752}
1753
1754/* transmission_complete_intr()
1755 *
1756 * Called by main interrupt handler when DBRI signals transmission complete
1757 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1758 *
1759 * Walks through the pipe's list of transmit buffer descriptors and marks
1760 * them as available. Stops when the first descriptor is found without
1761 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1762 *
1763 * The DMA buffers are not released. They form a ring buffer and
1764 * they are filled by ALSA while others are transmitted by DMA.
1765 *
1766 */
1767
1768static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1769{
1770 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1771 int td = dbri->pipes[pipe].desc;
1772 int status;
1773
1774 while (td >= 0) {
1775 if (td >= DBRI_NO_DESCS) {
1776 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1777 return;
1778 }
1779
1780 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1781 if (!(status & DBRI_TD_TBC))
1782 break;
1783
1784 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1785
1786 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1787 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1788
1789 td = dbri->next_desc[td];
1790 dbri->pipes[pipe].desc = td;
1791 }
1792
1793 /* Notify ALSA */
1794 spin_unlock(&dbri->lock);
1795 snd_pcm_period_elapsed(info->substream);
1796 spin_lock(&dbri->lock);
1797}
1798
1799static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1800{
1801 struct dbri_streaminfo *info;
1802 int rd = dbri->pipes[pipe].desc;
1803 s32 status;
1804
1805 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1806 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1807 return;
1808 }
1809
1810 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1811 status = dbri->dma->desc[rd].word1;
1812 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1813
1814 info = &dbri->stream_info[DBRI_REC];
1815 info->offset += DBRI_RD_CNT(status);
1816
1817 /* FIXME: Check status */
1818
1819 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1820 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1821
1822 /* Notify ALSA */
1823 spin_unlock(&dbri->lock);
1824 snd_pcm_period_elapsed(info->substream);
1825 spin_lock(&dbri->lock);
1826}
1827
1828static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1829{
1830 int val = D_INTR_GETVAL(x);
1831 int channel = D_INTR_GETCHAN(x);
1832 int command = D_INTR_GETCMD(x);
1833 int code = D_INTR_GETCODE(x);
1834#ifdef DBRI_DEBUG
1835 int rval = D_INTR_GETRVAL(x);
1836#endif
1837
1838 if (channel == D_INTR_CMD) {
1839 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1840 cmds[command], val);
1841 } else {
1842 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1843 channel, code, rval);
1844 }
1845
1846 switch (code) {
1847 case D_INTR_CMDI:
1848 if (command != D_WAIT)
1849 printk(KERN_ERR "DBRI: Command read interrupt\n");
1850 break;
1851 case D_INTR_BRDY:
1852 reception_complete_intr(dbri, channel);
1853 break;
1854 case D_INTR_XCMP:
1855 case D_INTR_MINT:
1856 transmission_complete_intr(dbri, channel);
1857 break;
1858 case D_INTR_UNDR:
1859 /* UNDR - Transmission underrun
1860 * resend SDP command with clear pipe bit (C) set
1861 */
1862 {
1863 /* FIXME: do something useful in case of underrun */
1864 printk(KERN_ERR "DBRI: Underrun error\n");
1865#if 0
1866 s32 *cmd;
1867 int pipe = channel;
1868 int td = dbri->pipes[pipe].desc;
1869
1870 dbri->dma->desc[td].word4 = 0;
1871 cmd = dbri_cmdlock(dbri, NoGetLock);
1872 *(cmd++) = DBRI_CMD(D_SDP, 0,
1873 dbri->pipes[pipe].sdp
1874 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1875 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1876 dbri_cmdsend(dbri, cmd);
1877#endif
1878 }
1879 break;
1880 case D_INTR_FXDT:
1881 /* FXDT - Fixed data change */
1882 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1883 val = reverse_bytes(val, dbri->pipes[channel].length);
1884
1885 if (dbri->pipes[channel].recv_fixed_ptr)
1886 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1887 break;
1888 default:
1889 if (channel != D_INTR_CMD)
1890 printk(KERN_WARNING
1891 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1892 }
1893}
1894
1895/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1896 * buffer until it finds a zero word (indicating nothing more to do
1897 * right now). Non-zero words require processing and are handed off
1898 * to dbri_process_one_interrupt AFTER advancing the pointer.
1899 */
1900static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1901{
1902 s32 x;
1903
1904 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1905 dbri->dma->intr[dbri->dbri_irqp] = 0;
1906 dbri->dbri_irqp++;
1907 if (dbri->dbri_irqp == DBRI_INT_BLK)
1908 dbri->dbri_irqp = 1;
1909
1910 dbri_process_one_interrupt(dbri, x);
1911 }
1912}
1913
1914static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1915{
1916 struct snd_dbri *dbri = dev_id;
1917 static int errcnt = 0;
1918 int x;
1919
1920 if (dbri == NULL)
1921 return IRQ_NONE;
1922 spin_lock(&dbri->lock);
1923
1924 /*
1925 * Read it, so the interrupt goes away.
1926 */
1927 x = sbus_readl(dbri->regs + REG1);
1928
1929 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1930 u32 tmp;
1931
1932 if (x & D_MRR)
1933 printk(KERN_ERR
1934 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1935 x);
1936 if (x & D_MLE)
1937 printk(KERN_ERR
1938 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1939 x);
1940 if (x & D_LBG)
1941 printk(KERN_ERR
1942 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1943 if (x & D_MBE)
1944 printk(KERN_ERR
1945 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1946
1947 /* Some of these SBus errors cause the chip's SBus circuitry
1948 * to be disabled, so just re-enable and try to keep going.
1949 *
1950 * The only one I've seen is MRR, which will be triggered
1951 * if you let a transmit pipe underrun, then try to CDP it.
1952 *
1953 * If these things persist, we reset the chip.
1954 */
1955 if ((++errcnt) % 10 == 0) {
1956 dprintk(D_INT, "Interrupt errors exceeded.\n");
1957 dbri_reset(dbri);
1958 } else {
1959 tmp = sbus_readl(dbri->regs + REG0);
1960 tmp &= ~(D_D);
1961 sbus_writel(tmp, dbri->regs + REG0);
1962 }
1963 }
1964
1965 dbri_process_interrupt_buffer(dbri);
1966
1967 spin_unlock(&dbri->lock);
1968
1969 return IRQ_HANDLED;
1970}
1971
1972/****************************************************************************
1973 PCM Interface
1974****************************************************************************/
1975static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1976 .info = SNDRV_PCM_INFO_MMAP |
1977 SNDRV_PCM_INFO_INTERLEAVED |
1978 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1979 SNDRV_PCM_INFO_MMAP_VALID |
1980 SNDRV_PCM_INFO_BATCH,
1981 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1982 SNDRV_PCM_FMTBIT_A_LAW |
1983 SNDRV_PCM_FMTBIT_U8 |
1984 SNDRV_PCM_FMTBIT_S16_BE,
1985 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1986 .rate_min = 5512,
1987 .rate_max = 48000,
1988 .channels_min = 1,
1989 .channels_max = 2,
1990 .buffer_bytes_max = 64 * 1024,
1991 .period_bytes_min = 1,
1992 .period_bytes_max = DBRI_TD_MAXCNT,
1993 .periods_min = 1,
1994 .periods_max = 1024,
1995};
1996
1997static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
1998 struct snd_pcm_hw_rule *rule)
1999{
2000 struct snd_interval *c = hw_param_interval(params,
2001 SNDRV_PCM_HW_PARAM_CHANNELS);
2002 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2003 struct snd_mask fmt;
2004
2005 snd_mask_any(&fmt);
2006 if (c->min > 1) {
2007 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2008 return snd_mask_refine(f, &fmt);
2009 }
2010 return 0;
2011}
2012
2013static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2014 struct snd_pcm_hw_rule *rule)
2015{
2016 struct snd_interval *c = hw_param_interval(params,
2017 SNDRV_PCM_HW_PARAM_CHANNELS);
2018 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2019 struct snd_interval ch;
2020
2021 snd_interval_any(&ch);
2022 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2023 ch.min = 1;
2024 ch.max = 1;
2025 ch.integer = 1;
2026 return snd_interval_refine(c, &ch);
2027 }
2028 return 0;
2029}
2030
2031static int snd_dbri_open(struct snd_pcm_substream *substream)
2032{
2033 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2034 struct snd_pcm_runtime *runtime = substream->runtime;
2035 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2036 unsigned long flags;
2037
2038 dprintk(D_USR, "open audio output.\n");
2039 runtime->hw = snd_dbri_pcm_hw;
2040
2041 spin_lock_irqsave(&dbri->lock, flags);
2042 info->substream = substream;
2043 info->offset = 0;
2044 info->dvma_buffer = 0;
2045 info->pipe = -1;
2046 spin_unlock_irqrestore(&dbri->lock, flags);
2047
2048 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2049 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2050 -1);
2051 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2052 snd_hw_rule_channels, NULL,
2053 SNDRV_PCM_HW_PARAM_CHANNELS,
2054 -1);
2055
2056 cs4215_open(dbri);
2057
2058 return 0;
2059}
2060
2061static int snd_dbri_close(struct snd_pcm_substream *substream)
2062{
2063 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2064 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2065
2066 dprintk(D_USR, "close audio output.\n");
2067 info->substream = NULL;
2068 info->offset = 0;
2069
2070 return 0;
2071}
2072
2073static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2074 struct snd_pcm_hw_params *hw_params)
2075{
2076 struct snd_pcm_runtime *runtime = substream->runtime;
2077 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2078 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2079 int direction;
2080 int ret;
2081
2082 /* set sampling rate, audio format and number of channels */
2083 ret = cs4215_prepare(dbri, params_rate(hw_params),
2084 params_format(hw_params),
2085 params_channels(hw_params));
2086 if (ret != 0)
2087 return ret;
2088
2089 if ((ret = snd_pcm_lib_malloc_pages(substream,
2090 params_buffer_bytes(hw_params))) < 0) {
2091 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2092 return ret;
2093 }
2094
2095 /* hw_params can get called multiple times. Only map the DMA once.
2096 */
2097 if (info->dvma_buffer == 0) {
2098 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2099 direction = DMA_TO_DEVICE;
2100 else
2101 direction = DMA_FROM_DEVICE;
2102
2103 info->dvma_buffer =
2104 dma_map_single(&dbri->op->dev,
2105 runtime->dma_area,
2106 params_buffer_bytes(hw_params),
2107 direction);
2108 }
2109
2110 direction = params_buffer_bytes(hw_params);
2111 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2112 direction, info->dvma_buffer);
2113 return 0;
2114}
2115
2116static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2117{
2118 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2119 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2120 int direction;
2121
2122 dprintk(D_USR, "hw_free.\n");
2123
2124 /* hw_free can get called multiple times. Only unmap the DMA once.
2125 */
2126 if (info->dvma_buffer) {
2127 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2128 direction = DMA_TO_DEVICE;
2129 else
2130 direction = DMA_FROM_DEVICE;
2131
2132 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2133 substream->runtime->buffer_size, direction);
2134 info->dvma_buffer = 0;
2135 }
2136 if (info->pipe != -1) {
2137 reset_pipe(dbri, info->pipe);
2138 info->pipe = -1;
2139 }
2140
2141 return snd_pcm_lib_free_pages(substream);
2142}
2143
2144static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2145{
2146 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2147 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2148 int ret;
2149
2150 info->size = snd_pcm_lib_buffer_bytes(substream);
2151 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2152 info->pipe = 4; /* Send pipe */
2153 else
2154 info->pipe = 6; /* Receive pipe */
2155
2156 spin_lock_irq(&dbri->lock);
2157 info->offset = 0;
2158
2159 /* Setup the all the transmit/receive descriptors to cover the
2160 * whole DMA buffer.
2161 */
2162 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2163 snd_pcm_lib_period_bytes(substream));
2164
2165 spin_unlock_irq(&dbri->lock);
2166
2167 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2168 return ret;
2169}
2170
2171static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2172{
2173 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2174 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2175 int ret = 0;
2176
2177 switch (cmd) {
2178 case SNDRV_PCM_TRIGGER_START:
2179 dprintk(D_USR, "start audio, period is %d bytes\n",
2180 (int)snd_pcm_lib_period_bytes(substream));
2181 /* Re-submit the TDs. */
2182 xmit_descs(dbri);
2183 break;
2184 case SNDRV_PCM_TRIGGER_STOP:
2185 dprintk(D_USR, "stop audio.\n");
2186 reset_pipe(dbri, info->pipe);
2187 break;
2188 default:
2189 ret = -EINVAL;
2190 }
2191
2192 return ret;
2193}
2194
2195static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2196{
2197 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2198 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2199 snd_pcm_uframes_t ret;
2200
2201 ret = bytes_to_frames(substream->runtime, info->offset)
2202 % substream->runtime->buffer_size;
2203 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2204 ret, substream->runtime->buffer_size);
2205 return ret;
2206}
2207
2208static struct snd_pcm_ops snd_dbri_ops = {
2209 .open = snd_dbri_open,
2210 .close = snd_dbri_close,
2211 .ioctl = snd_pcm_lib_ioctl,
2212 .hw_params = snd_dbri_hw_params,
2213 .hw_free = snd_dbri_hw_free,
2214 .prepare = snd_dbri_prepare,
2215 .trigger = snd_dbri_trigger,
2216 .pointer = snd_dbri_pointer,
2217};
2218
2219static int __devinit snd_dbri_pcm(struct snd_card *card)
2220{
2221 struct snd_pcm *pcm;
2222 int err;
2223
2224 if ((err = snd_pcm_new(card,
2225 /* ID */ "sun_dbri",
2226 /* device */ 0,
2227 /* playback count */ 1,
2228 /* capture count */ 1, &pcm)) < 0)
2229 return err;
2230
2231 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2232 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2233
2234 pcm->private_data = card->private_data;
2235 pcm->info_flags = 0;
2236 strcpy(pcm->name, card->shortname);
2237
2238 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2239 SNDRV_DMA_TYPE_CONTINUOUS,
2240 snd_dma_continuous_data(GFP_KERNEL),
2241 64 * 1024, 64 * 1024)) < 0)
2242 return err;
2243
2244 return 0;
2245}
2246
2247/*****************************************************************************
2248 Mixer interface
2249*****************************************************************************/
2250
2251static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2252 struct snd_ctl_elem_info *uinfo)
2253{
2254 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2255 uinfo->count = 2;
2256 uinfo->value.integer.min = 0;
2257 if (kcontrol->private_value == DBRI_PLAY)
2258 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2259 else
2260 uinfo->value.integer.max = DBRI_MAX_GAIN;
2261 return 0;
2262}
2263
2264static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2265 struct snd_ctl_elem_value *ucontrol)
2266{
2267 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2268 struct dbri_streaminfo *info;
2269
2270 if (snd_BUG_ON(!dbri))
2271 return -EINVAL;
2272 info = &dbri->stream_info[kcontrol->private_value];
2273
2274 ucontrol->value.integer.value[0] = info->left_gain;
2275 ucontrol->value.integer.value[1] = info->right_gain;
2276 return 0;
2277}
2278
2279static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2280 struct snd_ctl_elem_value *ucontrol)
2281{
2282 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2283 struct dbri_streaminfo *info =
2284 &dbri->stream_info[kcontrol->private_value];
2285 unsigned int vol[2];
2286 int changed = 0;
2287
2288 vol[0] = ucontrol->value.integer.value[0];
2289 vol[1] = ucontrol->value.integer.value[1];
2290 if (kcontrol->private_value == DBRI_PLAY) {
2291 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2292 return -EINVAL;
2293 } else {
2294 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2295 return -EINVAL;
2296 }
2297
2298 if (info->left_gain != vol[0]) {
2299 info->left_gain = vol[0];
2300 changed = 1;
2301 }
2302 if (info->right_gain != vol[1]) {
2303 info->right_gain = vol[1];
2304 changed = 1;
2305 }
2306 if (changed) {
2307 /* First mute outputs, and wait 1/8000 sec (125 us)
2308 * to make sure this takes. This avoids clicking noises.
2309 */
2310 cs4215_setdata(dbri, 1);
2311 udelay(125);
2312 cs4215_setdata(dbri, 0);
2313 }
2314 return changed;
2315}
2316
2317static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2318 struct snd_ctl_elem_info *uinfo)
2319{
2320 int mask = (kcontrol->private_value >> 16) & 0xff;
2321
2322 uinfo->type = (mask == 1) ?
2323 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2324 uinfo->count = 1;
2325 uinfo->value.integer.min = 0;
2326 uinfo->value.integer.max = mask;
2327 return 0;
2328}
2329
2330static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2331 struct snd_ctl_elem_value *ucontrol)
2332{
2333 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2334 int elem = kcontrol->private_value & 0xff;
2335 int shift = (kcontrol->private_value >> 8) & 0xff;
2336 int mask = (kcontrol->private_value >> 16) & 0xff;
2337 int invert = (kcontrol->private_value >> 24) & 1;
2338
2339 if (snd_BUG_ON(!dbri))
2340 return -EINVAL;
2341
2342 if (elem < 4)
2343 ucontrol->value.integer.value[0] =
2344 (dbri->mm.data[elem] >> shift) & mask;
2345 else
2346 ucontrol->value.integer.value[0] =
2347 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2348
2349 if (invert == 1)
2350 ucontrol->value.integer.value[0] =
2351 mask - ucontrol->value.integer.value[0];
2352 return 0;
2353}
2354
2355static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2356 struct snd_ctl_elem_value *ucontrol)
2357{
2358 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2359 int elem = kcontrol->private_value & 0xff;
2360 int shift = (kcontrol->private_value >> 8) & 0xff;
2361 int mask = (kcontrol->private_value >> 16) & 0xff;
2362 int invert = (kcontrol->private_value >> 24) & 1;
2363 int changed = 0;
2364 unsigned short val;
2365
2366 if (snd_BUG_ON(!dbri))
2367 return -EINVAL;
2368
2369 val = (ucontrol->value.integer.value[0] & mask);
2370 if (invert == 1)
2371 val = mask - val;
2372 val <<= shift;
2373
2374 if (elem < 4) {
2375 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2376 ~(mask << shift)) | val;
2377 changed = (val != dbri->mm.data[elem]);
2378 } else {
2379 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2380 ~(mask << shift)) | val;
2381 changed = (val != dbri->mm.ctrl[elem - 4]);
2382 }
2383
2384 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2385 "mixer-value=%ld, mm-value=0x%x\n",
2386 mask, changed, ucontrol->value.integer.value[0],
2387 dbri->mm.data[elem & 3]);
2388
2389 if (changed) {
2390 /* First mute outputs, and wait 1/8000 sec (125 us)
2391 * to make sure this takes. This avoids clicking noises.
2392 */
2393 cs4215_setdata(dbri, 1);
2394 udelay(125);
2395 cs4215_setdata(dbri, 0);
2396 }
2397 return changed;
2398}
2399
2400/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2401 timeslots. Shift is the bit offset in the timeslot, mask defines the
2402 number of bits. invert is a boolean for use with attenuation.
2403 */
2404#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2405{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2406 .info = snd_cs4215_info_single, \
2407 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2408 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2409 ((invert) << 24) },
2410
2411static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2412 {
2413 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2414 .name = "Playback Volume",
2415 .info = snd_cs4215_info_volume,
2416 .get = snd_cs4215_get_volume,
2417 .put = snd_cs4215_put_volume,
2418 .private_value = DBRI_PLAY,
2419 },
2420 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2421 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2422 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2423 {
2424 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2425 .name = "Capture Volume",
2426 .info = snd_cs4215_info_volume,
2427 .get = snd_cs4215_get_volume,
2428 .put = snd_cs4215_put_volume,
2429 .private_value = DBRI_REC,
2430 },
2431 /* FIXME: mic/line switch */
2432 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2433 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2434 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2435 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2436};
2437
2438static int __devinit snd_dbri_mixer(struct snd_card *card)
2439{
2440 int idx, err;
2441 struct snd_dbri *dbri;
2442
2443 if (snd_BUG_ON(!card || !card->private_data))
2444 return -EINVAL;
2445 dbri = card->private_data;
2446
2447 strcpy(card->mixername, card->shortname);
2448
2449 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2450 err = snd_ctl_add(card,
2451 snd_ctl_new1(&dbri_controls[idx], dbri));
2452 if (err < 0)
2453 return err;
2454 }
2455
2456 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2457 dbri->stream_info[idx].left_gain = 0;
2458 dbri->stream_info[idx].right_gain = 0;
2459 }
2460
2461 return 0;
2462}
2463
2464/****************************************************************************
2465 /proc interface
2466****************************************************************************/
2467static void dbri_regs_read(struct snd_info_entry *entry,
2468 struct snd_info_buffer *buffer)
2469{
2470 struct snd_dbri *dbri = entry->private_data;
2471
2472 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2473 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2474 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2475 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2476}
2477
2478#ifdef DBRI_DEBUG
2479static void dbri_debug_read(struct snd_info_entry *entry,
2480 struct snd_info_buffer *buffer)
2481{
2482 struct snd_dbri *dbri = entry->private_data;
2483 int pipe;
2484 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2485
2486 for (pipe = 0; pipe < 32; pipe++) {
2487 if (pipe_active(dbri, pipe)) {
2488 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2489 snd_iprintf(buffer,
2490 "Pipe %d: %s SDP=0x%x desc=%d, "
2491 "len=%d next %d\n",
2492 pipe,
2493 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2494 "input",
2495 pptr->sdp, pptr->desc,
2496 pptr->length, pptr->nextpipe);
2497 }
2498 }
2499}
2500#endif
2501
2502static void __devinit snd_dbri_proc(struct snd_card *card)
2503{
2504 struct snd_dbri *dbri = card->private_data;
2505 struct snd_info_entry *entry;
2506
2507 if (!snd_card_proc_new(card, "regs", &entry))
2508 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2509
2510#ifdef DBRI_DEBUG
2511 if (!snd_card_proc_new(card, "debug", &entry)) {
2512 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2513 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2514 }
2515#endif
2516}
2517
2518/*
2519****************************************************************************
2520**************************** Initialization ********************************
2521****************************************************************************
2522*/
2523static void snd_dbri_free(struct snd_dbri *dbri);
2524
2525static int __devinit snd_dbri_create(struct snd_card *card,
2526 struct platform_device *op,
2527 int irq, int dev)
2528{
2529 struct snd_dbri *dbri = card->private_data;
2530 int err;
2531
2532 spin_lock_init(&dbri->lock);
2533 dbri->op = op;
2534 dbri->irq = irq;
2535
2536 dbri->dma = dma_alloc_coherent(&op->dev,
2537 sizeof(struct dbri_dma),
2538 &dbri->dma_dvma, GFP_ATOMIC);
2539 if (!dbri->dma)
2540 return -ENOMEM;
2541 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2542
2543 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2544 dbri->dma, dbri->dma_dvma);
2545
2546 /* Map the registers into memory. */
2547 dbri->regs_size = resource_size(&op->resource[0]);
2548 dbri->regs = of_ioremap(&op->resource[0], 0,
2549 dbri->regs_size, "DBRI Registers");
2550 if (!dbri->regs) {
2551 printk(KERN_ERR "DBRI: could not allocate registers\n");
2552 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2553 (void *)dbri->dma, dbri->dma_dvma);
2554 return -EIO;
2555 }
2556
2557 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2558 "DBRI audio", dbri);
2559 if (err) {
2560 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2561 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2562 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2563 (void *)dbri->dma, dbri->dma_dvma);
2564 return err;
2565 }
2566
2567 /* Do low level initialization of the DBRI and CS4215 chips */
2568 dbri_initialize(dbri);
2569 err = cs4215_init(dbri);
2570 if (err) {
2571 snd_dbri_free(dbri);
2572 return err;
2573 }
2574
2575 return 0;
2576}
2577
2578static void snd_dbri_free(struct snd_dbri *dbri)
2579{
2580 dprintk(D_GEN, "snd_dbri_free\n");
2581 dbri_reset(dbri);
2582
2583 if (dbri->irq)
2584 free_irq(dbri->irq, dbri);
2585
2586 if (dbri->regs)
2587 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2588
2589 if (dbri->dma)
2590 dma_free_coherent(&dbri->op->dev,
2591 sizeof(struct dbri_dma),
2592 (void *)dbri->dma, dbri->dma_dvma);
2593}
2594
2595static int __devinit dbri_probe(struct platform_device *op)
2596{
2597 struct snd_dbri *dbri;
2598 struct resource *rp;
2599 struct snd_card *card;
2600 static int dev = 0;
2601 int irq;
2602 int err;
2603
2604 if (dev >= SNDRV_CARDS)
2605 return -ENODEV;
2606 if (!enable[dev]) {
2607 dev++;
2608 return -ENOENT;
2609 }
2610
2611 irq = op->archdata.irqs[0];
2612 if (irq <= 0) {
2613 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2614 return -ENODEV;
2615 }
2616
2617 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2618 sizeof(struct snd_dbri), &card);
2619 if (err < 0)
2620 return err;
2621
2622 strcpy(card->driver, "DBRI");
2623 strcpy(card->shortname, "Sun DBRI");
2624 rp = &op->resource[0];
2625 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2626 card->shortname,
2627 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2628
2629 err = snd_dbri_create(card, op, irq, dev);
2630 if (err < 0) {
2631 snd_card_free(card);
2632 return err;
2633 }
2634
2635 dbri = card->private_data;
2636 err = snd_dbri_pcm(card);
2637 if (err < 0)
2638 goto _err;
2639
2640 err = snd_dbri_mixer(card);
2641 if (err < 0)
2642 goto _err;
2643
2644 /* /proc file handling */
2645 snd_dbri_proc(card);
2646 dev_set_drvdata(&op->dev, card);
2647
2648 err = snd_card_register(card);
2649 if (err < 0)
2650 goto _err;
2651
2652 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2653 dev, dbri->regs,
2654 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2655 dev++;
2656
2657 return 0;
2658
2659_err:
2660 snd_dbri_free(dbri);
2661 snd_card_free(card);
2662 return err;
2663}
2664
2665static int __devexit dbri_remove(struct platform_device *op)
2666{
2667 struct snd_card *card = dev_get_drvdata(&op->dev);
2668
2669 snd_dbri_free(card->private_data);
2670 snd_card_free(card);
2671
2672 dev_set_drvdata(&op->dev, NULL);
2673
2674 return 0;
2675}
2676
2677static const struct of_device_id dbri_match[] = {
2678 {
2679 .name = "SUNW,DBRIe",
2680 },
2681 {
2682 .name = "SUNW,DBRIf",
2683 },
2684 {},
2685};
2686
2687MODULE_DEVICE_TABLE(of, dbri_match);
2688
2689static struct platform_driver dbri_sbus_driver = {
2690 .driver = {
2691 .name = "dbri",
2692 .owner = THIS_MODULE,
2693 .of_match_table = dbri_match,
2694 },
2695 .probe = dbri_probe,
2696 .remove = __devexit_p(dbri_remove),
2697};
2698
2699/* Probe for the dbri chip and then attach the driver. */
2700static int __init dbri_init(void)
2701{
2702 return platform_driver_register(&dbri_sbus_driver);
2703}
2704
2705static void __exit dbri_exit(void)
2706{
2707 platform_driver_unregister(&dbri_sbus_driver);
2708}
2709
2710module_init(dbri_init);
2711module_exit(dbri_exit);