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1/*
2 * Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * EXYNOS3250 - CPU PMU (Power Management Unit) support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/soc/samsung/exynos-regs-pmu.h>
13#include <linux/soc/samsung/exynos-pmu.h>
14
15#include "exynos-pmu.h"
16
17static struct exynos_pmu_conf exynos3250_pmu_config[] = {
18 /* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */
19 { EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
20 { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
21 { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
22 { EXYNOS3_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
23 { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
24 { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
25 { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
26 { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
27 { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
28 { EXYNOS3_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
29 { EXYNOS3_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x3} },
30 { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
31 { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
32 { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
33 { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
34 { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
35 { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
36 { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
37 { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
38 { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
39 { EXYNOS3_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
40 { EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
41 { EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
42 { EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
43 { EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
44 { EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
45 { EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
46 { EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
47 { EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
48 { EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
49 { EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
50 { EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
51 { EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
52 { EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
53 { EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
54 { EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
55 { EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
56 { EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
57 { EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
58 { EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
59 { EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
60 { EXYNOS3_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
61 { EXYNOS3_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
62 { EXYNOS3_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
63 { EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
64 { EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
65 { EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
66 { EXYNOS3_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
67 { EXYNOS3_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
68 { EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
69 { EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
70 { EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
71 { EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
72 { EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
73 { EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
74 { EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
75 { EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
76 { EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
77 { EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
78 { EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
79 { EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
80 { EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
81 { EXYNOS3_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
82 { EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
83 { EXYNOS3_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
84 { EXYNOS3_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
85 { EXYNOS3_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
86 { EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
87 { EXYNOS3_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
88 { EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
89 { EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
90 { EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
91 { EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
92 { EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
93 { EXYNOS3_CAM_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
94 { EXYNOS3_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
95 { EXYNOS3_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
96 { EXYNOS3_LCD0_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
97 { EXYNOS3_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
98 { EXYNOS3_MAUDIO_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
99 { EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
100 { PMU_TABLE_END,},
101};
102
103static unsigned int const exynos3250_list_feed[] = {
104 EXYNOS3_ARM_CORE_OPTION(0),
105 EXYNOS3_ARM_CORE_OPTION(1),
106 EXYNOS3_ARM_CORE_OPTION(2),
107 EXYNOS3_ARM_CORE_OPTION(3),
108 EXYNOS3_ARM_COMMON_OPTION,
109 EXYNOS3_TOP_PWR_OPTION,
110 EXYNOS3_CORE_TOP_PWR_OPTION,
111 S5P_CAM_OPTION,
112 S5P_MFC_OPTION,
113 S5P_G3D_OPTION,
114 S5P_LCD0_OPTION,
115 S5P_ISP_OPTION,
116};
117
118static void exynos3250_powerdown_conf_extra(enum sys_powerdown mode)
119{
120 unsigned int i;
121 unsigned int tmp;
122
123 /* Enable only SC_FEEDBACK */
124 for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) {
125 tmp = pmu_raw_readl(exynos3250_list_feed[i]);
126 tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER);
127 tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK;
128 pmu_raw_writel(tmp, exynos3250_list_feed[i]);
129 }
130
131 if (mode != SYS_SLEEP)
132 return;
133
134 pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION);
135 pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION);
136 pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION);
137 pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION,
138 EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);
139}
140
141static void exynos3250_pmu_init(void)
142{
143 unsigned int value;
144
145 /*
146 * To prevent from issuing new bus request form L2 memory system
147 * If core status is power down, should be set '1' to L2 power down
148 */
149 value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION);
150 value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
151 pmu_raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);
152
153 /* Enable USE_STANDBY_WFI for all CORE */
154 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
155
156 /*
157 * Set PSHOLD port for output high
158 */
159 value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
160 value |= S5P_PS_HOLD_OUTPUT_HIGH;
161 pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
162
163 /*
164 * Enable signal for PSHOLD port
165 */
166 value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
167 value |= S5P_PS_HOLD_EN;
168 pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
169}
170
171const struct exynos_pmu_data exynos3250_pmu_data = {
172 .pmu_config = exynos3250_pmu_config,
173 .pmu_init = exynos3250_pmu_init,
174 .powerdown_conf_extra = exynos3250_powerdown_conf_extra,
175};