1/*
 2 * This header provides constants clk index STMicroelectronics
 3 * STiH418 SoC.
 4 */
 5#ifndef _DT_BINDINGS_CLK_STIH418
 6#define _DT_BINDINGS_CLK_STIH418
 7
 8#include "stih410-clks.h"
 9
10/* STiH418 introduces new clock outputs compared to STiH410 */
11
12/* CLOCKGEN C0 */
13#define CLK_PROC_BDISP_0        14
14#define CLK_PROC_BDISP_1        15
15#define CLK_TX_ICN_1            23
16#define CLK_ETH_PHYREF          27
17#define CLK_PP_HEVC             35
18#define CLK_CLUST_HEVC          36
19#define CLK_HWPE_HEVC           37
20#define CLK_FC_HEVC             38
21#define CLK_PROC_MIXER		39
22#define CLK_PROC_SC		40
23#define CLK_AVSP_HEVC		41
24
25/* CLOCKGEN D2 */
26#undef CLK_PIX_PIP
27#undef CLK_PIX_GDP1
28#undef CLK_PIX_GDP2
29#undef CLK_PIX_GDP3
30#undef CLK_PIX_GDP4
31
32#define CLK_TMDS_HDMI_DIV2	5
33#define CLK_VP9			47
34#endif

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * This header provides constants clk index STMicroelectronics
 4 * STiH418 SoC.
 5 */
 6#ifndef _DT_BINDINGS_CLK_STIH418
 7#define _DT_BINDINGS_CLK_STIH418
 8
 9#include "stih410-clks.h"
10
11/* STiH418 introduces new clock outputs compared to STiH410 */
12
13/* CLOCKGEN C0 */
14#define CLK_PROC_BDISP_0        14
15#define CLK_PROC_BDISP_1        15
16#define CLK_TX_ICN_1            23
17#define CLK_ETH_PHYREF          27
18#define CLK_PP_HEVC             35
19#define CLK_CLUST_HEVC          36
20#define CLK_HWPE_HEVC           37
21#define CLK_FC_HEVC             38
22#define CLK_PROC_MIXER		39
23#define CLK_PROC_SC		40
24#define CLK_AVSP_HEVC		41
25
26/* CLOCKGEN D2 */
27#undef CLK_PIX_PIP
28#undef CLK_PIX_GDP1
29#undef CLK_PIX_GDP2
30#undef CLK_PIX_GDP3
31#undef CLK_PIX_GDP4
32
33#define CLK_TMDS_HDMI_DIV2	5
34#define CLK_VP9			47
35#endif