Loading...
Note: File does not exist in v4.6.
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <asm/amd_nb.h>
14#include <linux/acpi.h>
15#include <linux/bitfield.h>
16#include <linux/bits.h>
17#include <linux/debugfs.h>
18#include <linux/delay.h>
19#include <linux/io.h>
20#include <linux/iopoll.h>
21#include <linux/limits.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/platform_device.h>
25#include <linux/rtc.h>
26#include <linux/serio.h>
27#include <linux/suspend.h>
28#include <linux/seq_file.h>
29#include <linux/uaccess.h>
30
31#include "pmc.h"
32
33/* SMU communication registers */
34#define AMD_PMC_REGISTER_RESPONSE 0x980
35#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
36
37/* PMC Scratch Registers */
38#define AMD_PMC_SCRATCH_REG_CZN 0x94
39#define AMD_PMC_SCRATCH_REG_YC 0xD14
40#define AMD_PMC_SCRATCH_REG_1AH 0xF14
41
42/* STB Registers */
43#define AMD_PMC_STB_PMI_0 0x03E30600
44#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
45#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
46#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
47#define AMD_PMC_STB_DUMMY_PC 0xC6000007
48
49/* STB S2D(Spill to DRAM) has different message port offset */
50#define AMD_S2D_REGISTER_MESSAGE 0xA20
51#define AMD_S2D_REGISTER_RESPONSE 0xA80
52#define AMD_S2D_REGISTER_ARGUMENT 0xA88
53
54/* STB Spill to DRAM Parameters */
55#define S2D_TELEMETRY_BYTES_MAX 0x100000U
56#define S2D_RSVD_RAM_SPACE 0x100000
57#define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
58
59/* STB Spill to DRAM Message Definition */
60#define STB_FORCE_FLUSH_DATA 0xCF
61
62/* Base address of SMU for mapping physical address to virtual address */
63#define AMD_PMC_MAPPING_SIZE 0x01000
64#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
65#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
66#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
67#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
68#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
69
70/* SMU Response Codes */
71#define AMD_PMC_RESULT_OK 0x01
72#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
73#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
74#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
75#define AMD_PMC_RESULT_FAILED 0xFF
76
77/* FCH SSC Registers */
78#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
79#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
80#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
81#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
82#define FCH_SSC_MAPPING_SIZE 0x800
83#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
84#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
85
86/* SMU Message Definations */
87#define SMU_MSG_GETSMUVERSION 0x02
88#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
89#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
90#define SMU_MSG_LOG_START 0x06
91#define SMU_MSG_LOG_RESET 0x07
92#define SMU_MSG_LOG_DUMP_DATA 0x08
93#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
94
95#define PMC_MSG_DELAY_MIN_US 50
96#define RESPONSE_REGISTER_LOOP_MAX 20000
97
98#define DELAY_MIN_US 2000
99#define DELAY_MAX_US 3000
100#define FIFO_SIZE 4096
101
102enum amd_pmc_def {
103 MSG_TEST = 0x01,
104 MSG_OS_HINT_PCO,
105 MSG_OS_HINT_RN,
106};
107
108enum s2d_arg {
109 S2D_TELEMETRY_SIZE = 0x01,
110 S2D_PHYS_ADDR_LOW,
111 S2D_PHYS_ADDR_HIGH,
112 S2D_NUM_SAMPLES,
113 S2D_DRAM_SIZE,
114};
115
116struct amd_pmc_stb_v2_data {
117 size_t size;
118 u8 data[] __counted_by(size);
119};
120
121struct amd_pmc_bit_map {
122 const char *name;
123 u32 bit_mask;
124};
125
126static const struct amd_pmc_bit_map soc15_ip_blk[] = {
127 {"DISPLAY", BIT(0)},
128 {"CPU", BIT(1)},
129 {"GFX", BIT(2)},
130 {"VDD", BIT(3)},
131 {"ACP", BIT(4)},
132 {"VCN", BIT(5)},
133 {"ISP", BIT(6)},
134 {"NBIO", BIT(7)},
135 {"DF", BIT(8)},
136 {"USB3_0", BIT(9)},
137 {"USB3_1", BIT(10)},
138 {"LAPIC", BIT(11)},
139 {"USB3_2", BIT(12)},
140 {"USB3_3", BIT(13)},
141 {"USB3_4", BIT(14)},
142 {"USB4_0", BIT(15)},
143 {"USB4_1", BIT(16)},
144 {"MPM", BIT(17)},
145 {"JPEG", BIT(18)},
146 {"IPU", BIT(19)},
147 {"UMSCH", BIT(20)},
148 {"VPE", BIT(21)},
149 {}
150};
151
152static bool enable_stb;
153module_param(enable_stb, bool, 0644);
154MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
155
156static bool disable_workarounds;
157module_param(disable_workarounds, bool, 0644);
158MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
159
160static bool dump_custom_stb;
161module_param(dump_custom_stb, bool, 0644);
162MODULE_PARM_DESC(dump_custom_stb, "Enable to dump full STB buffer");
163
164static struct amd_pmc_dev pmc;
165static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
166static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
167static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
168
169static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
170{
171 return ioread32(dev->regbase + reg_offset);
172}
173
174static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
175{
176 iowrite32(val, dev->regbase + reg_offset);
177}
178
179struct smu_metrics {
180 u32 table_version;
181 u32 hint_count;
182 u32 s0i3_last_entry_status;
183 u32 timein_s0i2;
184 u64 timeentering_s0i3_lastcapture;
185 u64 timeentering_s0i3_totaltime;
186 u64 timeto_resume_to_os_lastcapture;
187 u64 timeto_resume_to_os_totaltime;
188 u64 timein_s0i3_lastcapture;
189 u64 timein_s0i3_totaltime;
190 u64 timein_swdrips_lastcapture;
191 u64 timein_swdrips_totaltime;
192 u64 timecondition_notmet_lastcapture[32];
193 u64 timecondition_notmet_totaltime[32];
194} __packed;
195
196static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
197{
198 struct amd_pmc_dev *dev = filp->f_inode->i_private;
199 u32 size = FIFO_SIZE * sizeof(u32);
200 u32 *buf;
201 int rc;
202
203 buf = kzalloc(size, GFP_KERNEL);
204 if (!buf)
205 return -ENOMEM;
206
207 rc = amd_pmc_read_stb(dev, buf);
208 if (rc) {
209 kfree(buf);
210 return rc;
211 }
212
213 filp->private_data = buf;
214 return rc;
215}
216
217static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
218 loff_t *pos)
219{
220 if (!filp->private_data)
221 return -EINVAL;
222
223 return simple_read_from_buffer(buf, size, pos, filp->private_data,
224 FIFO_SIZE * sizeof(u32));
225}
226
227static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
228{
229 kfree(filp->private_data);
230 return 0;
231}
232
233static const struct file_operations amd_pmc_stb_debugfs_fops = {
234 .owner = THIS_MODULE,
235 .open = amd_pmc_stb_debugfs_open,
236 .read = amd_pmc_stb_debugfs_read,
237 .release = amd_pmc_stb_debugfs_release,
238};
239
240/* Enhanced STB Firmware Reporting Mechanism */
241static int amd_pmc_stb_handle_efr(struct file *filp)
242{
243 struct amd_pmc_dev *dev = filp->f_inode->i_private;
244 struct amd_pmc_stb_v2_data *stb_data_arr;
245 u32 fsize;
246
247 fsize = dev->dram_size - S2D_RSVD_RAM_SPACE;
248 stb_data_arr = kmalloc(struct_size(stb_data_arr, data, fsize), GFP_KERNEL);
249 if (!stb_data_arr)
250 return -ENOMEM;
251
252 stb_data_arr->size = fsize;
253 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr, fsize);
254 filp->private_data = stb_data_arr;
255
256 return 0;
257}
258
259static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
260{
261 struct amd_pmc_dev *dev = filp->f_inode->i_private;
262 u32 fsize, num_samples, val, stb_rdptr_offset = 0;
263 struct amd_pmc_stb_v2_data *stb_data_arr;
264 int ret;
265
266 /* Write dummy postcode while reading the STB buffer */
267 ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
268 if (ret)
269 dev_err(dev->dev, "error writing to STB: %d\n", ret);
270
271 /* Spill to DRAM num_samples uses separate SMU message port */
272 dev->msg_port = 1;
273
274 ret = amd_pmc_send_cmd(dev, 0, &val, STB_FORCE_FLUSH_DATA, 1);
275 if (ret)
276 dev_dbg_once(dev->dev, "S2D force flush not supported: %d\n", ret);
277
278 /*
279 * We have a custom stb size and the PMFW is supposed to give
280 * the enhanced dram size. Note that we land here only for the
281 * platforms that support enhanced dram size reporting.
282 */
283 if (dump_custom_stb)
284 return amd_pmc_stb_handle_efr(filp);
285
286 /* Get the num_samples to calculate the last push location */
287 ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true);
288 /* Clear msg_port for other SMU operation */
289 dev->msg_port = 0;
290 if (ret) {
291 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
292 return ret;
293 }
294
295 fsize = min(num_samples, S2D_TELEMETRY_BYTES_MAX);
296 stb_data_arr = kmalloc(struct_size(stb_data_arr, data, fsize), GFP_KERNEL);
297 if (!stb_data_arr)
298 return -ENOMEM;
299
300 stb_data_arr->size = fsize;
301
302 /*
303 * Start capturing data from the last push location.
304 * This is for general cases, where the stb limits
305 * are meant for standard usage.
306 */
307 if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
308 /* First read oldest data starting 1 behind last write till end of ringbuffer */
309 stb_rdptr_offset = num_samples % S2D_TELEMETRY_BYTES_MAX;
310 fsize = S2D_TELEMETRY_BYTES_MAX - stb_rdptr_offset;
311
312 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr + stb_rdptr_offset, fsize);
313 /* Second copy the newer samples from offset 0 - last write */
314 memcpy_fromio(stb_data_arr->data + fsize, dev->stb_virt_addr, stb_rdptr_offset);
315 } else {
316 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr, fsize);
317 }
318
319 filp->private_data = stb_data_arr;
320
321 return 0;
322}
323
324static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
325 loff_t *pos)
326{
327 struct amd_pmc_stb_v2_data *data = filp->private_data;
328
329 return simple_read_from_buffer(buf, size, pos, data->data, data->size);
330}
331
332static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
333{
334 kfree(filp->private_data);
335 return 0;
336}
337
338static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
339 .owner = THIS_MODULE,
340 .open = amd_pmc_stb_debugfs_open_v2,
341 .read = amd_pmc_stb_debugfs_read_v2,
342 .release = amd_pmc_stb_debugfs_release_v2,
343};
344
345static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
346{
347 switch (dev->cpu_id) {
348 case AMD_CPU_ID_PCO:
349 case AMD_CPU_ID_RN:
350 case AMD_CPU_ID_YC:
351 case AMD_CPU_ID_CB:
352 dev->num_ips = 12;
353 dev->s2d_msg_id = 0xBE;
354 dev->smu_msg = 0x538;
355 break;
356 case AMD_CPU_ID_PS:
357 dev->num_ips = 21;
358 dev->s2d_msg_id = 0x85;
359 dev->smu_msg = 0x538;
360 break;
361 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
362 dev->num_ips = 22;
363 dev->s2d_msg_id = 0xDE;
364 dev->smu_msg = 0x938;
365 break;
366 }
367}
368
369static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
370{
371 if (dev->cpu_id == AMD_CPU_ID_PCO) {
372 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
373 return -EINVAL;
374 }
375
376 /* Get Active devices list from SMU */
377 if (!dev->active_ips)
378 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);
379
380 /* Get dram address */
381 if (!dev->smu_virt_addr) {
382 u32 phys_addr_low, phys_addr_hi;
383 u64 smu_phys_addr;
384
385 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);
386 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);
387 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
388
389 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
390 sizeof(struct smu_metrics));
391 if (!dev->smu_virt_addr)
392 return -ENOMEM;
393 }
394
395 /* Start the logging */
396 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);
397 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);
398
399 return 0;
400}
401
402static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
403{
404 if (!pdev->smu_virt_addr) {
405 int ret = amd_pmc_setup_smu_logging(pdev);
406
407 if (ret)
408 return ret;
409 }
410
411 if (pdev->cpu_id == AMD_CPU_ID_PCO)
412 return -ENODEV;
413 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
414 return 0;
415}
416
417static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
418{
419 struct smu_metrics table;
420
421 if (get_metrics_table(pdev, &table))
422 return;
423
424 if (!table.s0i3_last_entry_status)
425 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
426 pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
427 table.timein_s0i3_lastcapture : 0);
428}
429
430static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
431{
432 int rc;
433 u32 val;
434
435 if (dev->cpu_id == AMD_CPU_ID_PCO)
436 return -ENODEV;
437
438 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);
439 if (rc)
440 return rc;
441
442 dev->smu_program = (val >> 24) & GENMASK(7, 0);
443 dev->major = (val >> 16) & GENMASK(7, 0);
444 dev->minor = (val >> 8) & GENMASK(7, 0);
445 dev->rev = (val >> 0) & GENMASK(7, 0);
446
447 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
448 dev->smu_program, dev->major, dev->minor, dev->rev);
449
450 return 0;
451}
452
453static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
454 char *buf)
455{
456 struct amd_pmc_dev *dev = dev_get_drvdata(d);
457
458 if (!dev->major) {
459 int rc = amd_pmc_get_smu_version(dev);
460
461 if (rc)
462 return rc;
463 }
464 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
465}
466
467static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
468 char *buf)
469{
470 struct amd_pmc_dev *dev = dev_get_drvdata(d);
471
472 if (!dev->major) {
473 int rc = amd_pmc_get_smu_version(dev);
474
475 if (rc)
476 return rc;
477 }
478 return sysfs_emit(buf, "%u\n", dev->smu_program);
479}
480
481static DEVICE_ATTR_RO(smu_fw_version);
482static DEVICE_ATTR_RO(smu_program);
483
484static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
485{
486 struct device *dev = kobj_to_dev(kobj);
487 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
488
489 if (pdev->cpu_id == AMD_CPU_ID_PCO)
490 return 0;
491 return 0444;
492}
493
494static struct attribute *pmc_attrs[] = {
495 &dev_attr_smu_fw_version.attr,
496 &dev_attr_smu_program.attr,
497 NULL,
498};
499
500static struct attribute_group pmc_attr_group = {
501 .attrs = pmc_attrs,
502 .is_visible = pmc_attr_is_visible,
503};
504
505static const struct attribute_group *pmc_groups[] = {
506 &pmc_attr_group,
507 NULL,
508};
509
510static int smu_fw_info_show(struct seq_file *s, void *unused)
511{
512 struct amd_pmc_dev *dev = s->private;
513 struct smu_metrics table;
514 int idx;
515
516 if (get_metrics_table(dev, &table))
517 return -EINVAL;
518
519 seq_puts(s, "\n=== SMU Statistics ===\n");
520 seq_printf(s, "Table Version: %d\n", table.table_version);
521 seq_printf(s, "Hint Count: %d\n", table.hint_count);
522 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
523 "Unknown/Fail");
524 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
525 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
526 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
527 table.timeto_resume_to_os_lastcapture);
528
529 seq_puts(s, "\n=== Active time (in us) ===\n");
530 for (idx = 0 ; idx < dev->num_ips ; idx++) {
531 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
532 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
533 table.timecondition_notmet_lastcapture[idx]);
534 }
535
536 return 0;
537}
538DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
539
540static int s0ix_stats_show(struct seq_file *s, void *unused)
541{
542 struct amd_pmc_dev *dev = s->private;
543 u64 entry_time, exit_time, residency;
544
545 /* Use FCH registers to get the S0ix stats */
546 if (!dev->fch_virt_addr) {
547 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
548 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
549 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
550
551 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
552 if (!dev->fch_virt_addr)
553 return -ENOMEM;
554 }
555
556 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
557 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
558
559 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
560 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
561
562 /* It's in 48MHz. We need to convert it */
563 residency = exit_time - entry_time;
564 do_div(residency, 48);
565
566 seq_puts(s, "=== S0ix statistics ===\n");
567 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
568 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
569 seq_printf(s, "Residency Time: %lld\n", residency);
570
571 return 0;
572}
573DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
574
575static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
576 struct seq_file *s)
577{
578 u32 val;
579 int rc;
580
581 switch (pdev->cpu_id) {
582 case AMD_CPU_ID_CZN:
583 /* we haven't yet read SMU version */
584 if (!pdev->major) {
585 rc = amd_pmc_get_smu_version(pdev);
586 if (rc)
587 return rc;
588 }
589 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
590 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
591 else
592 return -EINVAL;
593 break;
594 case AMD_CPU_ID_YC:
595 case AMD_CPU_ID_CB:
596 case AMD_CPU_ID_PS:
597 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
598 break;
599 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
600 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH);
601 break;
602 default:
603 return -EINVAL;
604 }
605
606 if (dev)
607 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
608
609 if (s)
610 seq_printf(s, "SMU idlemask : 0x%x\n", val);
611
612 return 0;
613}
614
615static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
616{
617 return amd_pmc_idlemask_read(s->private, NULL, s);
618}
619DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
620
621static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
622{
623 debugfs_remove_recursive(dev->dbgfs_dir);
624}
625
626static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev)
627{
628 switch (dev->cpu_id) {
629 case AMD_CPU_ID_YC:
630 case AMD_CPU_ID_CB:
631 case AMD_CPU_ID_PS:
632 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
633 return true;
634 default:
635 return false;
636 }
637}
638
639static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
640{
641 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
642 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
643 &smu_fw_info_fops);
644 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
645 &s0ix_stats_fops);
646 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
647 &amd_pmc_idlemask_fops);
648 /* Enable STB only when the module_param is set */
649 if (enable_stb) {
650 if (amd_pmc_is_stb_supported(dev))
651 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
652 &amd_pmc_stb_debugfs_fops_v2);
653 else
654 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
655 &amd_pmc_stb_debugfs_fops);
656 }
657}
658
659static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
660{
661 u32 value, message, argument, response;
662
663 if (dev->msg_port) {
664 message = AMD_S2D_REGISTER_MESSAGE;
665 argument = AMD_S2D_REGISTER_ARGUMENT;
666 response = AMD_S2D_REGISTER_RESPONSE;
667 } else {
668 message = dev->smu_msg;
669 argument = AMD_PMC_REGISTER_ARGUMENT;
670 response = AMD_PMC_REGISTER_RESPONSE;
671 }
672
673 value = amd_pmc_reg_read(dev, response);
674 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
675
676 value = amd_pmc_reg_read(dev, argument);
677 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
678
679 value = amd_pmc_reg_read(dev, message);
680 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
681}
682
683static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
684{
685 int rc;
686 u32 val, message, argument, response;
687
688 mutex_lock(&dev->lock);
689
690 if (dev->msg_port) {
691 message = AMD_S2D_REGISTER_MESSAGE;
692 argument = AMD_S2D_REGISTER_ARGUMENT;
693 response = AMD_S2D_REGISTER_RESPONSE;
694 } else {
695 message = dev->smu_msg;
696 argument = AMD_PMC_REGISTER_ARGUMENT;
697 response = AMD_PMC_REGISTER_RESPONSE;
698 }
699
700 /* Wait until we get a valid response */
701 rc = readx_poll_timeout(ioread32, dev->regbase + response,
702 val, val != 0, PMC_MSG_DELAY_MIN_US,
703 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
704 if (rc) {
705 dev_err(dev->dev, "failed to talk to SMU\n");
706 goto out_unlock;
707 }
708
709 /* Write zero to response register */
710 amd_pmc_reg_write(dev, response, 0);
711
712 /* Write argument into response register */
713 amd_pmc_reg_write(dev, argument, arg);
714
715 /* Write message ID to message ID register */
716 amd_pmc_reg_write(dev, message, msg);
717
718 /* Wait until we get a valid response */
719 rc = readx_poll_timeout(ioread32, dev->regbase + response,
720 val, val != 0, PMC_MSG_DELAY_MIN_US,
721 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
722 if (rc) {
723 dev_err(dev->dev, "SMU response timed out\n");
724 goto out_unlock;
725 }
726
727 switch (val) {
728 case AMD_PMC_RESULT_OK:
729 if (ret) {
730 /* PMFW may take longer time to return back the data */
731 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
732 *data = amd_pmc_reg_read(dev, argument);
733 }
734 break;
735 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
736 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
737 rc = -EBUSY;
738 goto out_unlock;
739 case AMD_PMC_RESULT_CMD_UNKNOWN:
740 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
741 rc = -EINVAL;
742 goto out_unlock;
743 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
744 case AMD_PMC_RESULT_FAILED:
745 default:
746 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
747 rc = -EIO;
748 goto out_unlock;
749 }
750
751out_unlock:
752 mutex_unlock(&dev->lock);
753 amd_pmc_dump_registers(dev);
754 return rc;
755}
756
757static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
758{
759 switch (dev->cpu_id) {
760 case AMD_CPU_ID_PCO:
761 return MSG_OS_HINT_PCO;
762 case AMD_CPU_ID_RN:
763 case AMD_CPU_ID_YC:
764 case AMD_CPU_ID_CB:
765 case AMD_CPU_ID_PS:
766 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
767 return MSG_OS_HINT_RN;
768 }
769 return -EINVAL;
770}
771
772static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev)
773{
774 struct device *d;
775 int rc;
776
777 /* cezanne platform firmware has a fix in 64.66.0 */
778 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
779 if (!pdev->major) {
780 rc = amd_pmc_get_smu_version(pdev);
781 if (rc)
782 return rc;
783 }
784
785 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
786 return 0;
787 }
788
789 d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
790 if (!d)
791 return 0;
792 if (device_may_wakeup(d)) {
793 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
794 disable_irq_wake(1);
795 device_set_wakeup_enable(d, false);
796 }
797 put_device(d);
798
799 return 0;
800}
801
802static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
803{
804 struct rtc_device *rtc_device;
805 time64_t then, now, duration;
806 struct rtc_wkalrm alarm;
807 struct rtc_time tm;
808 int rc;
809
810 /* we haven't yet read SMU version */
811 if (!pdev->major) {
812 rc = amd_pmc_get_smu_version(pdev);
813 if (rc)
814 return rc;
815 }
816
817 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
818 return 0;
819
820 rtc_device = rtc_class_open("rtc0");
821 if (!rtc_device)
822 return 0;
823 rc = rtc_read_alarm(rtc_device, &alarm);
824 if (rc)
825 return rc;
826 if (!alarm.enabled) {
827 dev_dbg(pdev->dev, "alarm not enabled\n");
828 return 0;
829 }
830 rc = rtc_read_time(rtc_device, &tm);
831 if (rc)
832 return rc;
833 then = rtc_tm_to_time64(&alarm.time);
834 now = rtc_tm_to_time64(&tm);
835 duration = then-now;
836
837 /* in the past */
838 if (then < now)
839 return 0;
840
841 /* will be stored in upper 16 bits of s0i3 hint argument,
842 * so timer wakeup from s0i3 is limited to ~18 hours or less
843 */
844 if (duration <= 4 || duration > U16_MAX)
845 return -EINVAL;
846
847 *arg |= (duration << 16);
848 rc = rtc_alarm_irq_enable(rtc_device, 0);
849 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
850
851 return rc;
852}
853
854static void amd_pmc_s2idle_prepare(void)
855{
856 struct amd_pmc_dev *pdev = &pmc;
857 int rc;
858 u8 msg;
859 u32 arg = 1;
860
861 /* Reset and Start SMU logging - to monitor the s0i3 stats */
862 amd_pmc_setup_smu_logging(pdev);
863
864 /* Activate CZN specific platform bug workarounds */
865 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
866 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
867 if (rc) {
868 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
869 return;
870 }
871 }
872
873 msg = amd_pmc_get_os_hint(pdev);
874 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false);
875 if (rc) {
876 dev_err(pdev->dev, "suspend failed: %d\n", rc);
877 return;
878 }
879
880 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
881 if (rc)
882 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
883}
884
885static void amd_pmc_s2idle_check(void)
886{
887 struct amd_pmc_dev *pdev = &pmc;
888 struct smu_metrics table;
889 int rc;
890
891 /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
892 if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
893 table.s0i3_last_entry_status)
894 usleep_range(10000, 20000);
895
896 /* Dump the IdleMask before we add to the STB */
897 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
898
899 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
900 if (rc)
901 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
902}
903
904static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
905{
906 if (pdev->cpu_id == AMD_CPU_ID_PCO)
907 return -ENODEV;
908
909 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);
910}
911
912static void amd_pmc_s2idle_restore(void)
913{
914 struct amd_pmc_dev *pdev = &pmc;
915 int rc;
916 u8 msg;
917
918 msg = amd_pmc_get_os_hint(pdev);
919 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);
920 if (rc)
921 dev_err(pdev->dev, "resume failed: %d\n", rc);
922
923 /* Let SMU know that we are looking for stats */
924 amd_pmc_dump_data(pdev);
925
926 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
927 if (rc)
928 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
929
930 /* Notify on failed entry */
931 amd_pmc_validate_deepest(pdev);
932
933 amd_pmc_process_restore_quirks(pdev);
934}
935
936static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
937 .prepare = amd_pmc_s2idle_prepare,
938 .check = amd_pmc_s2idle_check,
939 .restore = amd_pmc_s2idle_restore,
940};
941
942static int amd_pmc_suspend_handler(struct device *dev)
943{
944 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
945
946 if (pdev->disable_8042_wakeup && !disable_workarounds) {
947 int rc = amd_pmc_wa_irq1(pdev);
948
949 if (rc) {
950 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
951 return rc;
952 }
953 }
954
955 return 0;
956}
957
958static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL);
959
960static const struct pci_device_id pmc_pci_ids[] = {
961 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
962 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
963 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
964 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
965 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
966 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
967 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
968 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
969 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
970 { }
971};
972
973static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
974{
975 u32 phys_addr_low, phys_addr_hi;
976 u64 stb_phys_addr;
977 u32 size = 0;
978 int ret;
979
980 /* Spill to DRAM feature uses separate SMU message port */
981 dev->msg_port = 1;
982
983 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true);
984 if (size != S2D_TELEMETRY_BYTES_MAX)
985 return -EIO;
986
987 /* Get DRAM size */
988 ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true);
989 if (ret || !dev->dram_size)
990 dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
991
992 /* Get STB DRAM address */
993 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true);
994 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true);
995
996 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
997
998 /* Clear msg_port for other SMU operation */
999 dev->msg_port = 0;
1000
1001 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
1002 if (!dev->stb_virt_addr)
1003 return -ENOMEM;
1004
1005 return 0;
1006}
1007
1008static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
1009{
1010 int err;
1011
1012 err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data);
1013 if (err) {
1014 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0);
1015 return pcibios_err_to_errno(err);
1016 }
1017
1018 return 0;
1019}
1020
1021static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
1022{
1023 int i, err;
1024
1025 for (i = 0; i < FIFO_SIZE; i++) {
1026 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++);
1027 if (err) {
1028 dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0);
1029 return pcibios_err_to_errno(err);
1030 }
1031 }
1032
1033 return 0;
1034}
1035
1036static int amd_pmc_probe(struct platform_device *pdev)
1037{
1038 struct amd_pmc_dev *dev = &pmc;
1039 struct pci_dev *rdev;
1040 u32 base_addr_lo, base_addr_hi;
1041 u64 base_addr;
1042 int err;
1043 u32 val;
1044
1045 dev->dev = &pdev->dev;
1046
1047 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
1048 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
1049 err = -ENODEV;
1050 goto err_pci_dev_put;
1051 }
1052
1053 dev->cpu_id = rdev->device;
1054
1055 if (dev->cpu_id == AMD_CPU_ID_SP) {
1056 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
1057 err = -ENODEV;
1058 goto err_pci_dev_put;
1059 }
1060
1061 dev->rdev = rdev;
1062 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
1063 if (err) {
1064 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
1065 err = pcibios_err_to_errno(err);
1066 goto err_pci_dev_put;
1067 }
1068
1069 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
1070
1071 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
1072 if (err) {
1073 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
1074 err = pcibios_err_to_errno(err);
1075 goto err_pci_dev_put;
1076 }
1077
1078 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
1079 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
1080
1081 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
1082 AMD_PMC_MAPPING_SIZE);
1083 if (!dev->regbase) {
1084 err = -ENOMEM;
1085 goto err_pci_dev_put;
1086 }
1087
1088 mutex_init(&dev->lock);
1089
1090 /* Get num of IP blocks within the SoC */
1091 amd_pmc_get_ip_info(dev);
1092
1093 if (enable_stb && amd_pmc_is_stb_supported(dev)) {
1094 err = amd_pmc_s2d_init(dev);
1095 if (err)
1096 goto err_pci_dev_put;
1097 }
1098
1099 platform_set_drvdata(pdev, dev);
1100 if (IS_ENABLED(CONFIG_SUSPEND)) {
1101 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1102 if (err)
1103 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1104 if (!disable_workarounds)
1105 amd_pmc_quirks_init(dev);
1106 }
1107
1108 amd_pmc_dbgfs_register(dev);
1109 pm_report_max_hw_sleep(U64_MAX);
1110 return 0;
1111
1112err_pci_dev_put:
1113 pci_dev_put(rdev);
1114 return err;
1115}
1116
1117static void amd_pmc_remove(struct platform_device *pdev)
1118{
1119 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1120
1121 if (IS_ENABLED(CONFIG_SUSPEND))
1122 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1123 amd_pmc_dbgfs_unregister(dev);
1124 pci_dev_put(dev->rdev);
1125 mutex_destroy(&dev->lock);
1126}
1127
1128static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1129 {"AMDI0005", 0},
1130 {"AMDI0006", 0},
1131 {"AMDI0007", 0},
1132 {"AMDI0008", 0},
1133 {"AMDI0009", 0},
1134 {"AMDI000A", 0},
1135 {"AMD0004", 0},
1136 {"AMD0005", 0},
1137 { }
1138};
1139MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1140
1141static struct platform_driver amd_pmc_driver = {
1142 .driver = {
1143 .name = "amd_pmc",
1144 .acpi_match_table = amd_pmc_acpi_ids,
1145 .dev_groups = pmc_groups,
1146 .pm = pm_sleep_ptr(&amd_pmc_pm),
1147 },
1148 .probe = amd_pmc_probe,
1149 .remove_new = amd_pmc_remove,
1150};
1151module_platform_driver(amd_pmc_driver);
1152
1153MODULE_LICENSE("GPL v2");
1154MODULE_DESCRIPTION("AMD PMC Driver");