1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2023 Intel Corporation
  4 */
  5
  6#include "xe_reg_whitelist.h"
  7
  8#include "regs/xe_engine_regs.h"
  9#include "regs/xe_gt_regs.h"
 10#include "regs/xe_regs.h"
 11#include "xe_gt_types.h"
 12#include "xe_platform_types.h"
 13#include "xe_rtp.h"
 14#include "xe_step.h"
 15
 16#undef XE_REG_MCR
 17#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
 18
 19static bool match_not_render(const struct xe_gt *gt,
 20			     const struct xe_hw_engine *hwe)
 21{
 22	return hwe->class != XE_ENGINE_CLASS_RENDER;
 23}
 24
 25static const struct xe_rtp_entry_sr register_whitelist[] = {
 26	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
 27	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 28	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
 29				   RING_FORCE_TO_NONPRIV_ACCESS_RD |
 30				   RING_FORCE_TO_NONPRIV_RANGE_4))
 31	},
 32	{ XE_RTP_NAME("1508744258, 14012131227, 1808121037"),
 33	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 34	  XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))
 35	},
 36	{ XE_RTP_NAME("1806527549"),
 37	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 38	  XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))
 39	},
 40	{ XE_RTP_NAME("allow_read_ctx_timestamp"),
 41	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)),
 42	  XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
 43				RING_FORCE_TO_NONPRIV_ACCESS_RD,
 44				XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 45	},
 46	{ XE_RTP_NAME("16014440446"),
 47	  XE_RTP_RULES(PLATFORM(PVC)),
 48	  XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
 49				   RING_FORCE_TO_NONPRIV_DENY |
 50				   RING_FORCE_TO_NONPRIV_RANGE_64),
 51			 WHITELIST(XE_REG(0x4500),
 52				   RING_FORCE_TO_NONPRIV_DENY |
 53				   RING_FORCE_TO_NONPRIV_RANGE_64))
 54	},
 55	{ XE_RTP_NAME("16017236439"),
 56	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY)),
 57	  XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0),
 58				   RING_FORCE_TO_NONPRIV_DENY,
 59				   XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 60	},
 61	{ XE_RTP_NAME("16020183090"),
 62	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
 63		       ENGINE_CLASS(RENDER)),
 64	  XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
 65	},
 66
 67	{}
 68};
 69
 70/**
 71 * xe_reg_whitelist_process_engine - process table of registers to whitelist
 72 * @hwe: engine instance to process whitelist for
 73 *
 74 * Process wwhitelist table for this platform, saving in @hwe all the
 75 * registers that need to be whitelisted by the hardware so they can be accessed
 76 * by userspace.
 77 */
 78void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 79{
 80	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
 81
 82	xe_rtp_process_to_sr(&ctx, register_whitelist, &hwe->reg_whitelist);
 83}
 84
 85/**
 86 * xe_reg_whitelist_print_entry - print one whitelist entry
 87 * @p: DRM printer
 88 * @indent: indent level
 89 * @reg: register allowed/denied
 90 * @entry: save-restore entry
 91 *
 92 * Print details about the entry added to allow/deny access
 93 */
 94void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
 95				  u32 reg, struct xe_reg_sr_entry *entry)
 96{
 97	u32 val = entry->set_bits;
 98	const char *access_str = "(invalid)";
 99	unsigned int range_bit = 2;
100	u32 range_start, range_end;
101	bool deny;
102
103	deny = val & RING_FORCE_TO_NONPRIV_DENY;
104
105	switch (val & RING_FORCE_TO_NONPRIV_RANGE_MASK) {
106	case RING_FORCE_TO_NONPRIV_RANGE_4:
107		range_bit = 4;
108		break;
109	case RING_FORCE_TO_NONPRIV_RANGE_16:
110		range_bit = 6;
111		break;
112	case RING_FORCE_TO_NONPRIV_RANGE_64:
113		range_bit = 8;
114		break;
115	}
116
117	range_start = reg & REG_GENMASK(25, range_bit);
118	range_end = range_start | REG_GENMASK(range_bit, 0);
119
120	switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) {
121	case RING_FORCE_TO_NONPRIV_ACCESS_RW:
122		access_str = "rw";
123		break;
124	case RING_FORCE_TO_NONPRIV_ACCESS_RD:
125		access_str = "read";
126		break;
127	case RING_FORCE_TO_NONPRIV_ACCESS_WR:
128		access_str = "write";
129		break;
130	}
131
132	drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n",
133			  range_start, range_end,
134			  deny ? "deny" : "allow",
135			  access_str);
136}
137
138/**
139 * xe_reg_whitelist_dump - print all whitelist entries
140 * @sr: Save/restore entries
141 * @p: DRM printer
142 */
143void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p)
144{
145	struct xe_reg_sr_entry *entry;
146	unsigned long reg;
147
148	if (!sr->name || xa_empty(&sr->xa))
149		return;
150
151	drm_printf(p, "%s\n", sr->name);
152	xa_for_each(&sr->xa, reg, entry)
153		xe_reg_whitelist_print_entry(p, 1, reg, entry);
154}