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1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2017-2018 Broadcom */
3
4#ifndef V3D_REGS_H
5#define V3D_REGS_H
6
7#include <linux/bitops.h>
8
9#define V3D_MASK(high, low) ((u32)GENMASK(high, low))
10/* Using the GNU statement expression extension */
11#define V3D_SET_FIELD(value, field) \
12 ({ \
13 u32 fieldval = (value) << field##_SHIFT; \
14 WARN_ON((fieldval & ~field##_MASK) != 0); \
15 fieldval & field##_MASK; \
16 })
17
18#define V3D_GET_FIELD(word, field) (((word) & field##_MASK) >> \
19 field##_SHIFT)
20
21/* Hub registers for shared hardware between V3D cores. */
22
23#define V3D_HUB_AXICFG 0x00000
24# define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0)
25# define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0
26#define V3D_HUB_UIFCFG 0x00004
27#define V3D_HUB_IDENT0 0x00008
28
29#define V3D_HUB_IDENT1 0x0000c
30# define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31# define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32# define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33# define V3D_HUB_IDENT1_WITH_L3C BIT(16)
34# define V3D_HUB_IDENT1_NHOSTS_MASK V3D_MASK(15, 12)
35# define V3D_HUB_IDENT1_NHOSTS_SHIFT 12
36# define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37# define V3D_HUB_IDENT1_NCORES_SHIFT 8
38# define V3D_HUB_IDENT1_REV_MASK V3D_MASK(7, 4)
39# define V3D_HUB_IDENT1_REV_SHIFT 4
40# define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0)
41# define V3D_HUB_IDENT1_TVER_SHIFT 0
42
43#define V3D_HUB_IDENT2 0x00010
44# define V3D_HUB_IDENT2_WITH_MMU BIT(8)
45# define V3D_HUB_IDENT2_L3C_NKB_MASK V3D_MASK(7, 0)
46# define V3D_HUB_IDENT2_L3C_NKB_SHIFT 0
47
48#define V3D_HUB_IDENT3 0x00014
49# define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
50# define V3D_HUB_IDENT3_IPREV_SHIFT 8
51# define V3D_HUB_IDENT3_IPIDX_MASK V3D_MASK(7, 0)
52# define V3D_HUB_IDENT3_IPIDX_SHIFT 0
53
54#define V3D_HUB_INT_STS 0x00050
55#define V3D_HUB_INT_SET 0x00054
56#define V3D_HUB_INT_CLR 0x00058
57#define V3D_HUB_INT_MSK_STS 0x0005c
58#define V3D_HUB_INT_MSK_SET 0x00060
59#define V3D_HUB_INT_MSK_CLR 0x00064
60# define V3D_V7_HUB_INT_GMPV BIT(6)
61# define V3D_HUB_INT_MMU_WRV BIT(5)
62# define V3D_HUB_INT_MMU_PTI BIT(4)
63# define V3D_HUB_INT_MMU_CAP BIT(3)
64# define V3D_HUB_INT_MSO BIT(2)
65# define V3D_HUB_INT_TFUC BIT(1)
66# define V3D_HUB_INT_TFUF BIT(0)
67
68/* GCA registers only exist in V3D < 41 */
69#define V3D_GCA_CACHE_CTRL 0x0000c
70# define V3D_GCA_CACHE_CTRL_FLUSH BIT(0)
71
72#define V3D_GCA_SAFE_SHUTDOWN 0x000b0
73# define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0)
74
75#define V3D_GCA_SAFE_SHUTDOWN_ACK 0x000b4
76# define V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED 3
77
78# define V3D_TOP_GR_BRIDGE_REVISION 0x00000
79# define V3D_TOP_GR_BRIDGE_MAJOR_MASK V3D_MASK(15, 8)
80# define V3D_TOP_GR_BRIDGE_MAJOR_SHIFT 8
81# define V3D_TOP_GR_BRIDGE_MINOR_MASK V3D_MASK(7, 0)
82# define V3D_TOP_GR_BRIDGE_MINOR_SHIFT 0
83
84/* 7268 reset reg */
85# define V3D_TOP_GR_BRIDGE_SW_INIT_0 0x00008
86# define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0)
87/* 7278 reset reg */
88# define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c
89# define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)
90
91#define V3D_TFU_CS(ver) ((ver >= 71) ? 0x00700 : 0x00400)
92
93/* Stops current job, empties input fifo. */
94# define V3D_TFU_CS_TFURST BIT(31)
95# define V3D_TFU_CS_CVTCT_MASK V3D_MASK(23, 16)
96# define V3D_TFU_CS_CVTCT_SHIFT 16
97# define V3D_TFU_CS_NFREE_MASK V3D_MASK(13, 8)
98# define V3D_TFU_CS_NFREE_SHIFT 8
99# define V3D_TFU_CS_BUSY BIT(0)
100
101#define V3D_TFU_SU(ver) ((ver >= 71) ? 0x00704 : 0x00404)
102/* Interrupt when FINTTHR input slots are free (0 = disabled) */
103# define V3D_TFU_SU_FINTTHR_MASK V3D_MASK(13, 8)
104# define V3D_TFU_SU_FINTTHR_SHIFT 8
105/* Skips resetting the CRC at the start of CRC generation. */
106# define V3D_TFU_SU_CRCCHAIN BIT(4)
107/* skips writes, computes CRC of the image. miplevels must be 0. */
108# define V3D_TFU_SU_CRC BIT(3)
109# define V3D_TFU_SU_THROTTLE_MASK V3D_MASK(1, 0)
110# define V3D_TFU_SU_THROTTLE_SHIFT 0
111
112#define V3D_TFU_ICFG(ver) ((ver >= 71) ? 0x00708 : 0x00408)
113/* Interrupt when the conversion is complete. */
114# define V3D_TFU_ICFG_IOC BIT(0)
115
116/* Input Image Address */
117#define V3D_TFU_IIA(ver) ((ver >= 71) ? 0x0070c : 0x0040c)
118/* Input Chroma Address */
119#define V3D_TFU_ICA(ver) ((ver >= 71) ? 0x00710 : 0x00410)
120/* Input Image Stride */
121#define V3D_TFU_IIS(ver) ((ver >= 71) ? 0x00714 : 0x00414)
122/* Input Image U-Plane Address */
123#define V3D_TFU_IUA(ver) ((ver >= 71) ? 0x00718 : 0x00418)
124/* Image output config (VD 7.x only) */
125#define V3D_V7_TFU_IOC 0x0071c
126/* Output Image Address */
127#define V3D_TFU_IOA(ver) ((ver >= 71) ? 0x00720 : 0x0041c)
128/* Image Output Size */
129#define V3D_TFU_IOS(ver) ((ver >= 71) ? 0x00724 : 0x00420)
130/* TFU YUV Coefficient 0 */
131#define V3D_TFU_COEF0(ver) ((ver >= 71) ? 0x00728 : 0x00424)
132/* Use these regs instead of the defaults (V3D 4.x only) */
133# define V3D_TFU_COEF0_USECOEF BIT(31)
134/* TFU YUV Coefficient 1 */
135#define V3D_TFU_COEF1(ver) ((ver >= 71) ? 0x0072c : 0x00428)
136/* TFU YUV Coefficient 2 */
137#define V3D_TFU_COEF2(ver) ((ver >= 71) ? 0x00730 : 0x0042c)
138/* TFU YUV Coefficient 3 */
139#define V3D_TFU_COEF3(ver) ((ver >= 71) ? 0x00734 : 0x00430)
140
141/* V3D 4.x only */
142#define V3D_TFU_CRC 0x00434
143
144/* Per-MMU registers. */
145
146#define V3D_MMUC_CONTROL 0x01000
147#define V3D_MMUC_CONTROL_CLEAR(ver) ((ver >= 71) ? BIT(11) : BIT(3))
148# define V3D_MMUC_CONTROL_FLUSHING BIT(2)
149# define V3D_MMUC_CONTROL_FLUSH BIT(1)
150# define V3D_MMUC_CONTROL_ENABLE BIT(0)
151
152#define V3D_MMU_CTL 0x01200
153# define V3D_MMU_CTL_CAP_EXCEEDED BIT(27)
154# define V3D_MMU_CTL_CAP_EXCEEDED_ABORT BIT(26)
155# define V3D_MMU_CTL_CAP_EXCEEDED_INT BIT(25)
156# define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION BIT(24)
157# define V3D_MMU_CTL_PT_INVALID BIT(20)
158# define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19)
159# define V3D_MMU_CTL_PT_INVALID_INT BIT(18)
160# define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17)
161# define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16)
162# define V3D_MMU_CTL_WRITE_VIOLATION BIT(12)
163# define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11)
164# define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10)
165# define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9)
166# define V3D_MMU_CTL_TLB_CLEARING BIT(7)
167# define V3D_MMU_CTL_TLB_STATS_CLEAR BIT(3)
168# define V3D_MMU_CTL_TLB_CLEAR BIT(2)
169# define V3D_MMU_CTL_TLB_STATS_ENABLE BIT(1)
170# define V3D_MMU_CTL_ENABLE BIT(0)
171
172#define V3D_MMU_PT_PA_BASE 0x01204
173#define V3D_MMU_HIT 0x01208
174#define V3D_MMU_MISSES 0x0120c
175#define V3D_MMU_STALLS 0x01210
176
177#define V3D_MMU_ADDR_CAP 0x01214
178# define V3D_MMU_ADDR_CAP_ENABLE BIT(31)
179# define V3D_MMU_ADDR_CAP_MPAGE_MASK V3D_MASK(11, 0)
180# define V3D_MMU_ADDR_CAP_MPAGE_SHIFT 0
181
182#define V3D_MMU_SHOOT_DOWN 0x01218
183# define V3D_MMU_SHOOT_DOWN_SHOOTING BIT(29)
184# define V3D_MMU_SHOOT_DOWN_SHOOT BIT(28)
185# define V3D_MMU_SHOOT_DOWN_PAGE_MASK V3D_MASK(27, 0)
186# define V3D_MMU_SHOOT_DOWN_PAGE_SHIFT 0
187
188#define V3D_MMU_BYPASS_START 0x0121c
189#define V3D_MMU_BYPASS_END 0x01220
190
191/* AXI ID of the access that faulted */
192#define V3D_MMU_VIO_ID 0x0122c
193
194/* Address for illegal PTEs to return */
195#define V3D_MMU_ILLEGAL_ADDR 0x01230
196# define V3D_MMU_ILLEGAL_ADDR_ENABLE BIT(31)
197
198/* Address that faulted */
199#define V3D_MMU_VIO_ADDR 0x01234
200
201#define V3D_MMU_DEBUG_INFO 0x01238
202# define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8)
203# define V3D_MMU_PA_WIDTH_SHIFT 8
204# define V3D_MMU_VA_WIDTH_MASK V3D_MASK(7, 4)
205# define V3D_MMU_VA_WIDTH_SHIFT 4
206# define V3D_MMU_VERSION_MASK V3D_MASK(3, 0)
207# define V3D_MMU_VERSION_SHIFT 0
208
209/* Per-V3D-core registers */
210
211#define V3D_CTL_IDENT0 0x00000
212# define V3D_IDENT0_VER_MASK V3D_MASK(31, 24)
213# define V3D_IDENT0_VER_SHIFT 24
214
215#define V3D_CTL_IDENT1 0x00004
216/* Multiples of 1kb */
217# define V3D_IDENT1_VPM_SIZE_MASK V3D_MASK(31, 28)
218# define V3D_IDENT1_VPM_SIZE_SHIFT 28
219# define V3D_IDENT1_NSEM_MASK V3D_MASK(23, 16)
220# define V3D_IDENT1_NSEM_SHIFT 16
221# define V3D_IDENT1_NTMU_MASK V3D_MASK(15, 12)
222# define V3D_IDENT1_NTMU_SHIFT 12
223# define V3D_IDENT1_QUPS_MASK V3D_MASK(11, 8)
224# define V3D_IDENT1_QUPS_SHIFT 8
225# define V3D_IDENT1_NSLC_MASK V3D_MASK(7, 4)
226# define V3D_IDENT1_NSLC_SHIFT 4
227# define V3D_IDENT1_REV_MASK V3D_MASK(3, 0)
228# define V3D_IDENT1_REV_SHIFT 0
229
230#define V3D_CTL_IDENT2 0x00008
231# define V3D_IDENT2_BCG_INT BIT(28)
232
233#define V3D_CTL_MISCCFG 0x00018
234# define V3D_CTL_MISCCFG_QRMAXCNT_MASK V3D_MASK(3, 1)
235# define V3D_CTL_MISCCFG_QRMAXCNT_SHIFT 1
236# define V3D_MISCCFG_OVRTMUOUT BIT(0)
237
238#define V3D_CTL_L2CACTL 0x00020
239# define V3D_L2CACTL_L2CCLR BIT(2)
240# define V3D_L2CACTL_L2CDIS BIT(1)
241# define V3D_L2CACTL_L2CENA BIT(0)
242
243#define V3D_CTL_SLCACTL 0x00024
244# define V3D_SLCACTL_TVCCS_MASK V3D_MASK(27, 24)
245# define V3D_SLCACTL_TVCCS_SHIFT 24
246# define V3D_SLCACTL_TDCCS_MASK V3D_MASK(19, 16)
247# define V3D_SLCACTL_TDCCS_SHIFT 16
248# define V3D_SLCACTL_UCC_MASK V3D_MASK(11, 8)
249# define V3D_SLCACTL_UCC_SHIFT 8
250# define V3D_SLCACTL_ICC_MASK V3D_MASK(3, 0)
251# define V3D_SLCACTL_ICC_SHIFT 0
252
253#define V3D_CTL_L2TCACTL 0x00030
254# define V3D_L2TCACTL_TMUWCF BIT(8)
255/* Invalidates cache lines. */
256# define V3D_L2TCACTL_FLM_FLUSH 0
257/* Removes cachelines without writing dirty lines back. */
258# define V3D_L2TCACTL_FLM_CLEAR 1
259/* Writes out dirty cachelines and marks them clean, but doesn't invalidate. */
260# define V3D_L2TCACTL_FLM_CLEAN 2
261# define V3D_L2TCACTL_FLM_MASK V3D_MASK(2, 1)
262# define V3D_L2TCACTL_FLM_SHIFT 1
263# define V3D_L2TCACTL_L2TFLS BIT(0)
264#define V3D_CTL_L2TFLSTA 0x00034
265#define V3D_CTL_L2TFLEND 0x00038
266
267#define V3D_CTL_INT_STS 0x00050
268#define V3D_CTL_INT_SET 0x00054
269#define V3D_CTL_INT_CLR 0x00058
270#define V3D_CTL_INT_MSK_STS 0x0005c
271#define V3D_CTL_INT_MSK_SET 0x00060
272#define V3D_CTL_INT_MSK_CLR 0x00064
273# define V3D_INT_QPU_MASK V3D_MASK(27, 16)
274# define V3D_INT_QPU_SHIFT 16
275#define V3D_INT_CSDDONE(ver) ((ver >= 71) ? BIT(6) : BIT(7))
276#define V3D_INT_PCTR(ver) ((ver >= 71) ? BIT(5) : BIT(6))
277# define V3D_INT_GMPV BIT(5)
278# define V3D_INT_TRFB BIT(4)
279# define V3D_INT_SPILLUSE BIT(3)
280# define V3D_INT_OUTOMEM BIT(2)
281# define V3D_INT_FLDONE BIT(1)
282# define V3D_INT_FRDONE BIT(0)
283
284#define V3D_CLE_CT0CS 0x00100
285#define V3D_CLE_CT1CS 0x00104
286#define V3D_CLE_CTNCS(n) (V3D_CLE_CT0CS + 4 * n)
287#define V3D_CLE_CT0EA 0x00108
288#define V3D_CLE_CT1EA 0x0010c
289#define V3D_CLE_CTNEA(n) (V3D_CLE_CT0EA + 4 * n)
290#define V3D_CLE_CT0CA 0x00110
291#define V3D_CLE_CT1CA 0x00114
292#define V3D_CLE_CTNCA(n) (V3D_CLE_CT0CA + 4 * n)
293#define V3D_CLE_CT0RA 0x00118
294#define V3D_CLE_CT1RA 0x0011c
295#define V3D_CLE_CTNRA(n) (V3D_CLE_CT0RA + 4 * n)
296#define V3D_CLE_CT0LC 0x00120
297#define V3D_CLE_CT1LC 0x00124
298#define V3D_CLE_CT0PC 0x00128
299#define V3D_CLE_CT1PC 0x0012c
300#define V3D_CLE_PCS 0x00130
301#define V3D_CLE_BFC 0x00134
302#define V3D_CLE_RFC 0x00138
303#define V3D_CLE_TFBC 0x0013c
304#define V3D_CLE_TFIT 0x00140
305#define V3D_CLE_CT1CFG 0x00144
306#define V3D_CLE_CT1TILECT 0x00148
307#define V3D_CLE_CT1TSKIP 0x0014c
308#define V3D_CLE_CT1PTCT 0x00150
309#define V3D_CLE_CT0SYNC 0x00154
310#define V3D_CLE_CT1SYNC 0x00158
311#define V3D_CLE_CT0QTS 0x0015c
312# define V3D_CLE_CT0QTS_ENABLE BIT(1)
313#define V3D_CLE_CT0QBA 0x00160
314#define V3D_CLE_CT1QBA 0x00164
315#define V3D_CLE_CTNQBA(n) (V3D_CLE_CT0QBA + 4 * n)
316#define V3D_CLE_CT0QEA 0x00168
317#define V3D_CLE_CT1QEA 0x0016c
318#define V3D_CLE_CTNQEA(n) (V3D_CLE_CT0QEA + 4 * n)
319#define V3D_CLE_CT0QMA 0x00170
320#define V3D_CLE_CT0QMS 0x00174
321#define V3D_CLE_CT1QCFG 0x00178
322/* If set without ETPROC, entirely skip tiles with no primitives. */
323# define V3D_CLE_QCFG_ETFILT BIT(7)
324/* If set with ETFILT, just write the clear color to tiles with no
325 * primitives.
326 */
327# define V3D_CLE_QCFG_ETPROC BIT(6)
328# define V3D_CLE_QCFG_ETSFLUSH BIT(1)
329# define V3D_CLE_QCFG_MCDIS BIT(0)
330
331#define V3D_PTB_BPCA 0x00300
332#define V3D_PTB_BPCS 0x00304
333#define V3D_PTB_BPOA 0x00308
334#define V3D_PTB_BPOS 0x0030c
335
336#define V3D_PTB_BXCF 0x00310
337# define V3D_PTB_BXCF_RWORDERDISA BIT(1)
338# define V3D_PTB_BXCF_CLIPDISA BIT(0)
339
340#define V3D_V3_PCTR_0_EN 0x00674
341#define V3D_V3_PCTR_0_EN_ENABLE BIT(31)
342#define V3D_V4_PCTR_0_EN 0x00650
343/* When a bit is set, resets the counter to 0. */
344#define V3D_V3_PCTR_0_CLR 0x00670
345#define V3D_V4_PCTR_0_CLR 0x00654
346#define V3D_PCTR_0_OVERFLOW 0x00658
347
348#define V3D_V3_PCTR_0_PCTRS0 0x00684
349#define V3D_V3_PCTR_0_PCTRS15 0x00660
350#define V3D_V3_PCTR_0_PCTRSX(x) (V3D_V3_PCTR_0_PCTRS0 + \
351 4 * (x))
352/* Each src reg muxes four counters each. */
353#define V3D_V4_PCTR_0_SRC_0_3 0x00660
354#define V3D_V4_PCTR_0_SRC_28_31 0x0067c
355#define V3D_V4_PCTR_0_SRC_X(x) (V3D_V4_PCTR_0_SRC_0_3 + \
356 4 * (x))
357# define V3D_PCTR_S0_MASK V3D_MASK(6, 0)
358# define V3D_V7_PCTR_S0_MASK V3D_MASK(7, 0)
359# define V3D_PCTR_S0_SHIFT 0
360# define V3D_PCTR_S1_MASK V3D_MASK(14, 8)
361# define V3D_V7_PCTR_S1_MASK V3D_MASK(15, 8)
362# define V3D_PCTR_S1_SHIFT 8
363# define V3D_PCTR_S2_MASK V3D_MASK(22, 16)
364# define V3D_V7_PCTR_S2_MASK V3D_MASK(23, 16)
365# define V3D_PCTR_S2_SHIFT 16
366# define V3D_PCTR_S3_MASK V3D_MASK(30, 24)
367# define V3D_V7_PCTR_S3_MASK V3D_MASK(31, 24)
368# define V3D_PCTR_S3_SHIFT 24
369#define V3D_PCTR_CYCLE_COUNT(ver) ((ver >= 71) ? 0 : 32)
370
371/* Output values of the counters. */
372#define V3D_PCTR_0_PCTR0 0x00680
373#define V3D_PCTR_0_PCTR31 0x006fc
374#define V3D_PCTR_0_PCTRX(x) (V3D_PCTR_0_PCTR0 + \
375 4 * (x))
376#define V3D_GMP_STATUS(ver) ((ver >= 71) ? 0x00600 : 0x00800)
377# define V3D_GMP_STATUS_GMPRST BIT(31)
378# define V3D_GMP_STATUS_WR_COUNT_MASK V3D_MASK(30, 24)
379# define V3D_GMP_STATUS_WR_COUNT_SHIFT 24
380# define V3D_GMP_STATUS_RD_COUNT_MASK V3D_MASK(22, 16)
381# define V3D_GMP_STATUS_RD_COUNT_SHIFT 16
382# define V3D_GMP_STATUS_WR_ACTIVE BIT(5)
383# define V3D_GMP_STATUS_RD_ACTIVE BIT(4)
384# define V3D_GMP_STATUS_CFG_BUSY BIT(3)
385# define V3D_GMP_STATUS_CNTOVF BIT(2)
386# define V3D_GMP_STATUS_INVPROT BIT(1)
387# define V3D_GMP_STATUS_VIO BIT(0)
388
389#define V3D_GMP_CFG(ver) ((ver >= 71) ? 0x00604 : 0x00804)
390# define V3D_GMP_CFG_LBURSTEN BIT(3)
391# define V3D_GMP_CFG_PGCRSEN BIT()
392# define V3D_GMP_CFG_STOP_REQ BIT(1)
393# define V3D_GMP_CFG_PROT_ENABLE BIT(0)
394
395#define V3D_GMP_VIO_ADDR(ver) ((ver >= 71) ? 0x00608 : 0x00808)
396#define V3D_GMP_VIO_TYPE 0x0080c
397#define V3D_GMP_TABLE_ADDR 0x00810
398#define V3D_GMP_CLEAR_LOAD 0x00814
399#define V3D_GMP_PRESERVE_LOAD 0x00818
400#define V3D_GMP_VALID_LINES 0x00820
401
402#define V3D_CSD_STATUS 0x00900
403# define V3D_CSD_STATUS_NUM_COMPLETED_MASK V3D_MASK(11, 4)
404# define V3D_CSD_STATUS_NUM_COMPLETED_SHIFT 4
405# define V3D_CSD_STATUS_NUM_ACTIVE_MASK V3D_MASK(3, 2)
406# define V3D_CSD_STATUS_NUM_ACTIVE_SHIFT 2
407# define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH BIT(1)
408# define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0)
409
410#define V3D_CSD_QUEUED_CFG0(ver) ((ver >= 71) ? 0x00930 : 0x00904)
411# define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_MASK V3D_MASK(31, 16)
412# define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_SHIFT 16
413# define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK V3D_MASK(15, 0)
414# define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT 0
415
416#define V3D_CSD_QUEUED_CFG1(ver) ((ver >= 71) ? 0x00934 : 0x00908)
417# define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_MASK V3D_MASK(31, 16)
418# define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_SHIFT 16
419# define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK V3D_MASK(15, 0)
420# define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT 0
421
422#define V3D_CSD_QUEUED_CFG2(ver) ((ver >= 71) ? 0x00938 : 0x0090c)
423# define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_MASK V3D_MASK(31, 16)
424# define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_SHIFT 16
425# define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK V3D_MASK(15, 0)
426# define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT 0
427
428#define V3D_CSD_QUEUED_CFG3(ver) ((ver >= 71) ? 0x0093c : 0x00910)
429# define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV BIT(26)
430# define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_MASK V3D_MASK(25, 20)
431# define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_SHIFT 20
432# define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_MASK V3D_MASK(19, 12)
433# define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_SHIFT 12
434# define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK V3D_MASK(11, 8)
435# define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT 8
436# define V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK V3D_MASK(7, 0)
437# define V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT 0
438
439/* Number of batches, minus 1 */
440#define V3D_CSD_QUEUED_CFG4(ver) ((ver >= 71) ? 0x00940 : 0x00914)
441
442/* Shader address, pnan, singleseg, threading, like a shader record. */
443#define V3D_CSD_QUEUED_CFG5(ver) ((ver >= 71) ? 0x00944 : 0x00918)
444
445/* Uniforms address (4 byte aligned) */
446#define V3D_CSD_QUEUED_CFG6(ver) ((ver >= 71) ? 0x00948 : 0x0091c)
447
448/* V3D 7.x+ only */
449#define V3D_V7_CSD_QUEUED_CFG7 0x0094c
450
451#define V3D_CSD_CURRENT_CFG0(ver) ((ver >= 71) ? 0x00958 : 0x00920)
452#define V3D_CSD_CURRENT_CFG1(ver) ((ver >= 71) ? 0x0095c : 0x00924)
453#define V3D_CSD_CURRENT_CFG2(ver) ((ver >= 71) ? 0x00960 : 0x00928)
454#define V3D_CSD_CURRENT_CFG3(ver) ((ver >= 71) ? 0x00964 : 0x0092c)
455#define V3D_CSD_CURRENT_CFG4(ver) ((ver >= 71) ? 0x00968 : 0x00930)
456#define V3D_CSD_CURRENT_CFG5(ver) ((ver >= 71) ? 0x0096c : 0x00934)
457#define V3D_CSD_CURRENT_CFG6(ver) ((ver >= 71) ? 0x00970 : 0x00938)
458/* V3D 7.x+ only */
459#define V3D_V7_CSD_CURRENT_CFG7 0x00974
460
461#define V3D_CSD_CURRENT_ID0(ver) ((ver >= 71) ? 0x00978 : 0x0093c)
462# define V3D_CSD_CURRENT_ID0_WG_X_MASK V3D_MASK(31, 16)
463# define V3D_CSD_CURRENT_ID0_WG_X_SHIFT 16
464# define V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK V3D_MASK(11, 8)
465# define V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT 8
466# define V3D_CSD_CURRENT_ID0_L_IDX_MASK V3D_MASK(7, 0)
467# define V3D_CSD_CURRENT_ID0_L_IDX_SHIFT 0
468
469#define V3D_CSD_CURRENT_ID1(ver) ((ver >= 71) ? 0x0097c : 0x00940)
470# define V3D_CSD_CURRENT_ID0_WG_Z_MASK V3D_MASK(31, 16)
471# define V3D_CSD_CURRENT_ID0_WG_Z_SHIFT 16
472# define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0)
473# define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0
474
475#define V3D_ERR_FDBGO 0x00f04
476#define V3D_ERR_FDBGB 0x00f08
477#define V3D_ERR_FDBGR 0x00f0c
478
479#define V3D_ERR_FDBGS 0x00f10
480# define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17)
481# define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16)
482# define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14)
483# define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13)
484# define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12)
485# define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11)
486# define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7)
487# define V3D_ERR_FDBGS_EZTEST_PASS BIT(6)
488# define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5)
489# define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4)
490# define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3)
491# define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2)
492# define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1)
493# define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0)
494
495#define V3D_ERR_STAT 0x00f20
496# define V3D_ERR_L2CARE BIT(15)
497# define V3D_ERR_VCMBE BIT(14)
498# define V3D_ERR_VCMRE BIT(13)
499# define V3D_ERR_VCDI BIT(12)
500# define V3D_ERR_VCDE BIT(11)
501# define V3D_ERR_VDWE BIT(10)
502# define V3D_ERR_VPMEAS BIT(9)
503# define V3D_ERR_VPMEFNA BIT(8)
504# define V3D_ERR_VPMEWNA BIT(7)
505# define V3D_ERR_VPMERNA BIT(6)
506# define V3D_ERR_VPMERR BIT(5)
507# define V3D_ERR_VPMEWR BIT(4)
508# define V3D_ERR_VPAERRGL BIT(3)
509# define V3D_ERR_VPAEBRGL BIT(2)
510# define V3D_ERR_VPAERGS BIT(1)
511# define V3D_ERR_VPAEABB BIT(0)
512
513#endif /* V3D_REGS_H */