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1/*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <drm/drm.h>
16#include <drm/drmP.h>
17#include <drm/drm_atomic.h>
18#include <drm/drm_crtc.h>
19#include <drm/drm_crtc_helper.h>
20#include <drm/drm_plane_helper.h>
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/clk.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/component.h>
30
31#include <linux/reset.h>
32#include <linux/delay.h>
33
34#include "rockchip_drm_drv.h"
35#include "rockchip_drm_gem.h"
36#include "rockchip_drm_fb.h"
37#include "rockchip_drm_vop.h"
38
39#define __REG_SET_RELAXED(x, off, mask, shift, v) \
40 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
41#define __REG_SET_NORMAL(x, off, mask, shift, v) \
42 vop_mask_write(x, off, (mask) << shift, (v) << shift)
43
44#define REG_SET(x, base, reg, v, mode) \
45 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
46#define REG_SET_MASK(x, base, reg, mask, v, mode) \
47 __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v)
48
49#define VOP_WIN_SET(x, win, name, v) \
50 REG_SET(x, win->base, win->phy->name, v, RELAXED)
51#define VOP_SCL_SET(x, win, name, v) \
52 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
53#define VOP_SCL_SET_EXT(x, win, name, v) \
54 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
55#define VOP_CTRL_SET(x, name, v) \
56 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
57
58#define VOP_INTR_GET(vop, name) \
59 vop_read_reg(vop, 0, &vop->data->ctrl->name)
60
61#define VOP_INTR_SET(vop, name, mask, v) \
62 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
63#define VOP_INTR_SET_TYPE(vop, name, type, v) \
64 do { \
65 int i, reg = 0, mask = 0; \
66 for (i = 0; i < vop->data->intr->nintrs; i++) { \
67 if (vop->data->intr->intrs[i] & type) { \
68 reg |= (v) << i; \
69 mask |= 1 << i; \
70 } \
71 } \
72 VOP_INTR_SET(vop, name, mask, reg); \
73 } while (0)
74#define VOP_INTR_GET_TYPE(vop, name, type) \
75 vop_get_intr_type(vop, &vop->data->intr->name, type)
76
77#define VOP_WIN_GET(x, win, name) \
78 vop_read_reg(x, win->base, &win->phy->name)
79
80#define VOP_WIN_GET_YRGBADDR(vop, win) \
81 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
82
83#define to_vop(x) container_of(x, struct vop, crtc)
84#define to_vop_win(x) container_of(x, struct vop_win, base)
85#define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
86
87struct vop_plane_state {
88 struct drm_plane_state base;
89 int format;
90 struct drm_rect src;
91 struct drm_rect dest;
92 dma_addr_t yrgb_mst;
93 bool enable;
94};
95
96struct vop_win {
97 struct drm_plane base;
98 const struct vop_win_data *data;
99 struct vop *vop;
100
101 struct vop_plane_state state;
102};
103
104struct vop {
105 struct drm_crtc crtc;
106 struct device *dev;
107 struct drm_device *drm_dev;
108 bool is_enabled;
109
110 /* mutex vsync_ work */
111 struct mutex vsync_mutex;
112 bool vsync_work_pending;
113 struct completion dsp_hold_completion;
114 struct completion wait_update_complete;
115 struct drm_pending_vblank_event *event;
116
117 const struct vop_data *data;
118
119 uint32_t *regsbak;
120 void __iomem *regs;
121
122 /* physical map length of vop register */
123 uint32_t len;
124
125 /* one time only one process allowed to config the register */
126 spinlock_t reg_lock;
127 /* lock vop irq reg */
128 spinlock_t irq_lock;
129
130 unsigned int irq;
131
132 /* vop AHP clk */
133 struct clk *hclk;
134 /* vop dclk */
135 struct clk *dclk;
136 /* vop share memory frequency */
137 struct clk *aclk;
138
139 /* vop dclk reset */
140 struct reset_control *dclk_rst;
141
142 struct vop_win win[];
143};
144
145static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
146{
147 writel(v, vop->regs + offset);
148 vop->regsbak[offset >> 2] = v;
149}
150
151static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
152{
153 return readl(vop->regs + offset);
154}
155
156static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
157 const struct vop_reg *reg)
158{
159 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
160}
161
162static inline void vop_mask_write(struct vop *vop, uint32_t offset,
163 uint32_t mask, uint32_t v)
164{
165 if (mask) {
166 uint32_t cached_val = vop->regsbak[offset >> 2];
167
168 cached_val = (cached_val & ~mask) | v;
169 writel(cached_val, vop->regs + offset);
170 vop->regsbak[offset >> 2] = cached_val;
171 }
172}
173
174static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
175 uint32_t mask, uint32_t v)
176{
177 if (mask) {
178 uint32_t cached_val = vop->regsbak[offset >> 2];
179
180 cached_val = (cached_val & ~mask) | v;
181 writel_relaxed(cached_val, vop->regs + offset);
182 vop->regsbak[offset >> 2] = cached_val;
183 }
184}
185
186static inline uint32_t vop_get_intr_type(struct vop *vop,
187 const struct vop_reg *reg, int type)
188{
189 uint32_t i, ret = 0;
190 uint32_t regs = vop_read_reg(vop, 0, reg);
191
192 for (i = 0; i < vop->data->intr->nintrs; i++) {
193 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
194 ret |= vop->data->intr->intrs[i];
195 }
196
197 return ret;
198}
199
200static inline void vop_cfg_done(struct vop *vop)
201{
202 VOP_CTRL_SET(vop, cfg_done, 1);
203}
204
205static bool has_rb_swapped(uint32_t format)
206{
207 switch (format) {
208 case DRM_FORMAT_XBGR8888:
209 case DRM_FORMAT_ABGR8888:
210 case DRM_FORMAT_BGR888:
211 case DRM_FORMAT_BGR565:
212 return true;
213 default:
214 return false;
215 }
216}
217
218static enum vop_data_format vop_convert_format(uint32_t format)
219{
220 switch (format) {
221 case DRM_FORMAT_XRGB8888:
222 case DRM_FORMAT_ARGB8888:
223 case DRM_FORMAT_XBGR8888:
224 case DRM_FORMAT_ABGR8888:
225 return VOP_FMT_ARGB8888;
226 case DRM_FORMAT_RGB888:
227 case DRM_FORMAT_BGR888:
228 return VOP_FMT_RGB888;
229 case DRM_FORMAT_RGB565:
230 case DRM_FORMAT_BGR565:
231 return VOP_FMT_RGB565;
232 case DRM_FORMAT_NV12:
233 return VOP_FMT_YUV420SP;
234 case DRM_FORMAT_NV16:
235 return VOP_FMT_YUV422SP;
236 case DRM_FORMAT_NV24:
237 return VOP_FMT_YUV444SP;
238 default:
239 DRM_ERROR("unsupport format[%08x]\n", format);
240 return -EINVAL;
241 }
242}
243
244static bool is_yuv_support(uint32_t format)
245{
246 switch (format) {
247 case DRM_FORMAT_NV12:
248 case DRM_FORMAT_NV16:
249 case DRM_FORMAT_NV24:
250 return true;
251 default:
252 return false;
253 }
254}
255
256static bool is_alpha_support(uint32_t format)
257{
258 switch (format) {
259 case DRM_FORMAT_ARGB8888:
260 case DRM_FORMAT_ABGR8888:
261 return true;
262 default:
263 return false;
264 }
265}
266
267static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
268 uint32_t dst, bool is_horizontal,
269 int vsu_mode, int *vskiplines)
270{
271 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
272
273 if (is_horizontal) {
274 if (mode == SCALE_UP)
275 val = GET_SCL_FT_BIC(src, dst);
276 else if (mode == SCALE_DOWN)
277 val = GET_SCL_FT_BILI_DN(src, dst);
278 } else {
279 if (mode == SCALE_UP) {
280 if (vsu_mode == SCALE_UP_BIL)
281 val = GET_SCL_FT_BILI_UP(src, dst);
282 else
283 val = GET_SCL_FT_BIC(src, dst);
284 } else if (mode == SCALE_DOWN) {
285 if (vskiplines) {
286 *vskiplines = scl_get_vskiplines(src, dst);
287 val = scl_get_bili_dn_vskip(src, dst,
288 *vskiplines);
289 } else {
290 val = GET_SCL_FT_BILI_DN(src, dst);
291 }
292 }
293 }
294
295 return val;
296}
297
298static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
299 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
300 uint32_t dst_h, uint32_t pixel_format)
301{
302 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
303 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
304 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
305 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
306 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
307 bool is_yuv = is_yuv_support(pixel_format);
308 uint16_t cbcr_src_w = src_w / hsub;
309 uint16_t cbcr_src_h = src_h / vsub;
310 uint16_t vsu_mode;
311 uint16_t lb_mode;
312 uint32_t val;
313 int vskiplines;
314
315 if (dst_w > 3840) {
316 DRM_ERROR("Maximum destination width (3840) exceeded\n");
317 return;
318 }
319
320 if (!win->phy->scl->ext) {
321 VOP_SCL_SET(vop, win, scale_yrgb_x,
322 scl_cal_scale2(src_w, dst_w));
323 VOP_SCL_SET(vop, win, scale_yrgb_y,
324 scl_cal_scale2(src_h, dst_h));
325 if (is_yuv) {
326 VOP_SCL_SET(vop, win, scale_cbcr_x,
327 scl_cal_scale2(src_w, dst_w));
328 VOP_SCL_SET(vop, win, scale_cbcr_y,
329 scl_cal_scale2(src_h, dst_h));
330 }
331 return;
332 }
333
334 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
335 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
336
337 if (is_yuv) {
338 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
339 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
340 if (cbcr_hor_scl_mode == SCALE_DOWN)
341 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
342 else
343 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
344 } else {
345 if (yrgb_hor_scl_mode == SCALE_DOWN)
346 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
347 else
348 lb_mode = scl_vop_cal_lb_mode(src_w, false);
349 }
350
351 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
352 if (lb_mode == LB_RGB_3840X2) {
353 if (yrgb_ver_scl_mode != SCALE_NONE) {
354 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
355 return;
356 }
357 if (cbcr_ver_scl_mode != SCALE_NONE) {
358 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
359 return;
360 }
361 vsu_mode = SCALE_UP_BIL;
362 } else if (lb_mode == LB_RGB_2560X4) {
363 vsu_mode = SCALE_UP_BIL;
364 } else {
365 vsu_mode = SCALE_UP_BIC;
366 }
367
368 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
369 true, 0, NULL);
370 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
371 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
372 false, vsu_mode, &vskiplines);
373 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
374
375 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
376 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
377
378 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
379 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
380 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
381 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
382 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
383 if (is_yuv) {
384 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
385 dst_w, true, 0, NULL);
386 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
387 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
388 dst_h, false, vsu_mode, &vskiplines);
389 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
390
391 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
392 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
393 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
394 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
395 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
396 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
397 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
398 }
399}
400
401static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
402{
403 unsigned long flags;
404
405 if (WARN_ON(!vop->is_enabled))
406 return;
407
408 spin_lock_irqsave(&vop->irq_lock, flags);
409
410 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
411
412 spin_unlock_irqrestore(&vop->irq_lock, flags);
413}
414
415static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
416{
417 unsigned long flags;
418
419 if (WARN_ON(!vop->is_enabled))
420 return;
421
422 spin_lock_irqsave(&vop->irq_lock, flags);
423
424 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
425
426 spin_unlock_irqrestore(&vop->irq_lock, flags);
427}
428
429static void vop_enable(struct drm_crtc *crtc)
430{
431 struct vop *vop = to_vop(crtc);
432 int ret;
433
434 if (vop->is_enabled)
435 return;
436
437 ret = pm_runtime_get_sync(vop->dev);
438 if (ret < 0) {
439 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
440 return;
441 }
442
443 ret = clk_enable(vop->hclk);
444 if (ret < 0) {
445 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
446 return;
447 }
448
449 ret = clk_enable(vop->dclk);
450 if (ret < 0) {
451 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
452 goto err_disable_hclk;
453 }
454
455 ret = clk_enable(vop->aclk);
456 if (ret < 0) {
457 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
458 goto err_disable_dclk;
459 }
460
461 /*
462 * Slave iommu shares power, irq and clock with vop. It was associated
463 * automatically with this master device via common driver code.
464 * Now that we have enabled the clock we attach it to the shared drm
465 * mapping.
466 */
467 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
468 if (ret) {
469 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
470 goto err_disable_aclk;
471 }
472
473 memcpy(vop->regs, vop->regsbak, vop->len);
474 /*
475 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
476 */
477 vop->is_enabled = true;
478
479 spin_lock(&vop->reg_lock);
480
481 VOP_CTRL_SET(vop, standby, 0);
482
483 spin_unlock(&vop->reg_lock);
484
485 enable_irq(vop->irq);
486
487 drm_crtc_vblank_on(crtc);
488
489 return;
490
491err_disable_aclk:
492 clk_disable(vop->aclk);
493err_disable_dclk:
494 clk_disable(vop->dclk);
495err_disable_hclk:
496 clk_disable(vop->hclk);
497}
498
499static void vop_crtc_disable(struct drm_crtc *crtc)
500{
501 struct vop *vop = to_vop(crtc);
502 int i;
503
504 if (!vop->is_enabled)
505 return;
506
507 /*
508 * We need to make sure that all windows are disabled before we
509 * disable that crtc. Otherwise we might try to scan from a destroyed
510 * buffer later.
511 */
512 for (i = 0; i < vop->data->win_size; i++) {
513 struct vop_win *vop_win = &vop->win[i];
514 const struct vop_win_data *win = vop_win->data;
515
516 spin_lock(&vop->reg_lock);
517 VOP_WIN_SET(vop, win, enable, 0);
518 spin_unlock(&vop->reg_lock);
519 }
520
521 drm_crtc_vblank_off(crtc);
522
523 /*
524 * Vop standby will take effect at end of current frame,
525 * if dsp hold valid irq happen, it means standby complete.
526 *
527 * we must wait standby complete when we want to disable aclk,
528 * if not, memory bus maybe dead.
529 */
530 reinit_completion(&vop->dsp_hold_completion);
531 vop_dsp_hold_valid_irq_enable(vop);
532
533 spin_lock(&vop->reg_lock);
534
535 VOP_CTRL_SET(vop, standby, 1);
536
537 spin_unlock(&vop->reg_lock);
538
539 wait_for_completion(&vop->dsp_hold_completion);
540
541 vop_dsp_hold_valid_irq_disable(vop);
542
543 disable_irq(vop->irq);
544
545 vop->is_enabled = false;
546
547 /*
548 * vop standby complete, so iommu detach is safe.
549 */
550 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
551
552 clk_disable(vop->dclk);
553 clk_disable(vop->aclk);
554 clk_disable(vop->hclk);
555 pm_runtime_put(vop->dev);
556}
557
558static void vop_plane_destroy(struct drm_plane *plane)
559{
560 drm_plane_cleanup(plane);
561}
562
563static int vop_plane_atomic_check(struct drm_plane *plane,
564 struct drm_plane_state *state)
565{
566 struct drm_crtc *crtc = state->crtc;
567 struct drm_crtc_state *crtc_state;
568 struct drm_framebuffer *fb = state->fb;
569 struct vop_win *vop_win = to_vop_win(plane);
570 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
571 const struct vop_win_data *win = vop_win->data;
572 bool visible;
573 int ret;
574 struct drm_rect *dest = &vop_plane_state->dest;
575 struct drm_rect *src = &vop_plane_state->src;
576 struct drm_rect clip;
577 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
578 DRM_PLANE_HELPER_NO_SCALING;
579 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
580 DRM_PLANE_HELPER_NO_SCALING;
581
582 if (!crtc || !fb)
583 goto out_disable;
584
585 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
586 if (WARN_ON(!crtc_state))
587 return -EINVAL;
588
589 src->x1 = state->src_x;
590 src->y1 = state->src_y;
591 src->x2 = state->src_x + state->src_w;
592 src->y2 = state->src_y + state->src_h;
593 dest->x1 = state->crtc_x;
594 dest->y1 = state->crtc_y;
595 dest->x2 = state->crtc_x + state->crtc_w;
596 dest->y2 = state->crtc_y + state->crtc_h;
597
598 clip.x1 = 0;
599 clip.y1 = 0;
600 clip.x2 = crtc_state->adjusted_mode.hdisplay;
601 clip.y2 = crtc_state->adjusted_mode.vdisplay;
602
603 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
604 src, dest, &clip,
605 min_scale,
606 max_scale,
607 true, true, &visible);
608 if (ret)
609 return ret;
610
611 if (!visible)
612 goto out_disable;
613
614 vop_plane_state->format = vop_convert_format(fb->pixel_format);
615 if (vop_plane_state->format < 0)
616 return vop_plane_state->format;
617
618 /*
619 * Src.x1 can be odd when do clip, but yuv plane start point
620 * need align with 2 pixel.
621 */
622 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
623 return -EINVAL;
624
625 vop_plane_state->enable = true;
626
627 return 0;
628
629out_disable:
630 vop_plane_state->enable = false;
631 return 0;
632}
633
634static void vop_plane_atomic_disable(struct drm_plane *plane,
635 struct drm_plane_state *old_state)
636{
637 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
638 struct vop_win *vop_win = to_vop_win(plane);
639 const struct vop_win_data *win = vop_win->data;
640 struct vop *vop = to_vop(old_state->crtc);
641
642 if (!old_state->crtc)
643 return;
644
645 spin_lock(&vop->reg_lock);
646
647 VOP_WIN_SET(vop, win, enable, 0);
648
649 spin_unlock(&vop->reg_lock);
650
651 vop_plane_state->enable = false;
652}
653
654static void vop_plane_atomic_update(struct drm_plane *plane,
655 struct drm_plane_state *old_state)
656{
657 struct drm_plane_state *state = plane->state;
658 struct drm_crtc *crtc = state->crtc;
659 struct vop_win *vop_win = to_vop_win(plane);
660 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
661 const struct vop_win_data *win = vop_win->data;
662 struct vop *vop = to_vop(state->crtc);
663 struct drm_framebuffer *fb = state->fb;
664 unsigned int actual_w, actual_h;
665 unsigned int dsp_stx, dsp_sty;
666 uint32_t act_info, dsp_info, dsp_st;
667 struct drm_rect *src = &vop_plane_state->src;
668 struct drm_rect *dest = &vop_plane_state->dest;
669 struct drm_gem_object *obj, *uv_obj;
670 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
671 unsigned long offset;
672 dma_addr_t dma_addr;
673 uint32_t val;
674 bool rb_swap;
675
676 /*
677 * can't update plane when vop is disabled.
678 */
679 if (!crtc)
680 return;
681
682 if (WARN_ON(!vop->is_enabled))
683 return;
684
685 if (!vop_plane_state->enable) {
686 vop_plane_atomic_disable(plane, old_state);
687 return;
688 }
689
690 obj = rockchip_fb_get_gem_obj(fb, 0);
691 rk_obj = to_rockchip_obj(obj);
692
693 actual_w = drm_rect_width(src) >> 16;
694 actual_h = drm_rect_height(src) >> 16;
695 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
696
697 dsp_info = (drm_rect_height(dest) - 1) << 16;
698 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
699
700 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
701 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
702 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
703
704 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
705 offset += (src->y1 >> 16) * fb->pitches[0];
706 vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
707
708 spin_lock(&vop->reg_lock);
709
710 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
711 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
712 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
713 if (is_yuv_support(fb->pixel_format)) {
714 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
715 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
716 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
717
718 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
719 rk_uv_obj = to_rockchip_obj(uv_obj);
720
721 offset = (src->x1 >> 16) * bpp / hsub;
722 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
723
724 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
725 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
726 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
727 }
728
729 if (win->phy->scl)
730 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
731 drm_rect_width(dest), drm_rect_height(dest),
732 fb->pixel_format);
733
734 VOP_WIN_SET(vop, win, act_info, act_info);
735 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
736 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
737
738 rb_swap = has_rb_swapped(fb->pixel_format);
739 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
740
741 if (is_alpha_support(fb->pixel_format)) {
742 VOP_WIN_SET(vop, win, dst_alpha_ctl,
743 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
744 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
745 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
746 SRC_BLEND_M0(ALPHA_PER_PIX) |
747 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
748 SRC_FACTOR_M0(ALPHA_ONE);
749 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
750 } else {
751 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
752 }
753
754 VOP_WIN_SET(vop, win, enable, 1);
755 spin_unlock(&vop->reg_lock);
756}
757
758static const struct drm_plane_helper_funcs plane_helper_funcs = {
759 .atomic_check = vop_plane_atomic_check,
760 .atomic_update = vop_plane_atomic_update,
761 .atomic_disable = vop_plane_atomic_disable,
762};
763
764void vop_atomic_plane_reset(struct drm_plane *plane)
765{
766 struct vop_plane_state *vop_plane_state =
767 to_vop_plane_state(plane->state);
768
769 if (plane->state && plane->state->fb)
770 drm_framebuffer_unreference(plane->state->fb);
771
772 kfree(vop_plane_state);
773 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
774 if (!vop_plane_state)
775 return;
776
777 plane->state = &vop_plane_state->base;
778 plane->state->plane = plane;
779}
780
781struct drm_plane_state *
782vop_atomic_plane_duplicate_state(struct drm_plane *plane)
783{
784 struct vop_plane_state *old_vop_plane_state;
785 struct vop_plane_state *vop_plane_state;
786
787 if (WARN_ON(!plane->state))
788 return NULL;
789
790 old_vop_plane_state = to_vop_plane_state(plane->state);
791 vop_plane_state = kmemdup(old_vop_plane_state,
792 sizeof(*vop_plane_state), GFP_KERNEL);
793 if (!vop_plane_state)
794 return NULL;
795
796 __drm_atomic_helper_plane_duplicate_state(plane,
797 &vop_plane_state->base);
798
799 return &vop_plane_state->base;
800}
801
802static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
803 struct drm_plane_state *state)
804{
805 struct vop_plane_state *vop_state = to_vop_plane_state(state);
806
807 __drm_atomic_helper_plane_destroy_state(plane, state);
808
809 kfree(vop_state);
810}
811
812static const struct drm_plane_funcs vop_plane_funcs = {
813 .update_plane = drm_atomic_helper_update_plane,
814 .disable_plane = drm_atomic_helper_disable_plane,
815 .destroy = vop_plane_destroy,
816 .reset = vop_atomic_plane_reset,
817 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
818 .atomic_destroy_state = vop_atomic_plane_destroy_state,
819};
820
821int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
822 int connector_type,
823 int out_mode)
824{
825 struct vop *vop = to_vop(crtc);
826
827 if (WARN_ON(!vop->is_enabled))
828 return -EINVAL;
829
830 switch (connector_type) {
831 case DRM_MODE_CONNECTOR_LVDS:
832 VOP_CTRL_SET(vop, rgb_en, 1);
833 break;
834 case DRM_MODE_CONNECTOR_eDP:
835 VOP_CTRL_SET(vop, edp_en, 1);
836 break;
837 case DRM_MODE_CONNECTOR_HDMIA:
838 VOP_CTRL_SET(vop, hdmi_en, 1);
839 break;
840 case DRM_MODE_CONNECTOR_DSI:
841 VOP_CTRL_SET(vop, mipi_en, 1);
842 break;
843 default:
844 DRM_ERROR("unsupport connector_type[%d]\n", connector_type);
845 return -EINVAL;
846 };
847 VOP_CTRL_SET(vop, out_mode, out_mode);
848
849 return 0;
850}
851EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
852
853static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
854{
855 struct vop *vop = to_vop(crtc);
856 unsigned long flags;
857
858 if (WARN_ON(!vop->is_enabled))
859 return -EPERM;
860
861 spin_lock_irqsave(&vop->irq_lock, flags);
862
863 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
864
865 spin_unlock_irqrestore(&vop->irq_lock, flags);
866
867 return 0;
868}
869
870static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
871{
872 struct vop *vop = to_vop(crtc);
873 unsigned long flags;
874
875 if (WARN_ON(!vop->is_enabled))
876 return;
877
878 spin_lock_irqsave(&vop->irq_lock, flags);
879
880 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
881
882 spin_unlock_irqrestore(&vop->irq_lock, flags);
883}
884
885static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
886{
887 struct vop *vop = to_vop(crtc);
888
889 reinit_completion(&vop->wait_update_complete);
890 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
891}
892
893static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
894 struct drm_file *file_priv)
895{
896 struct drm_device *drm = crtc->dev;
897 struct vop *vop = to_vop(crtc);
898 struct drm_pending_vblank_event *e;
899 unsigned long flags;
900
901 spin_lock_irqsave(&drm->event_lock, flags);
902 e = vop->event;
903 if (e && e->base.file_priv == file_priv) {
904 vop->event = NULL;
905
906 e->base.destroy(&e->base);
907 file_priv->event_space += sizeof(e->event);
908 }
909 spin_unlock_irqrestore(&drm->event_lock, flags);
910}
911
912static const struct rockchip_crtc_funcs private_crtc_funcs = {
913 .enable_vblank = vop_crtc_enable_vblank,
914 .disable_vblank = vop_crtc_disable_vblank,
915 .wait_for_update = vop_crtc_wait_for_update,
916 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
917};
918
919static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
920 const struct drm_display_mode *mode,
921 struct drm_display_mode *adjusted_mode)
922{
923 struct vop *vop = to_vop(crtc);
924
925 adjusted_mode->clock =
926 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
927
928 return true;
929}
930
931static void vop_crtc_enable(struct drm_crtc *crtc)
932{
933 struct vop *vop = to_vop(crtc);
934 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
935 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
936 u16 hdisplay = adjusted_mode->hdisplay;
937 u16 htotal = adjusted_mode->htotal;
938 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
939 u16 hact_end = hact_st + hdisplay;
940 u16 vdisplay = adjusted_mode->vdisplay;
941 u16 vtotal = adjusted_mode->vtotal;
942 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
943 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
944 u16 vact_end = vact_st + vdisplay;
945 uint32_t val;
946
947 vop_enable(crtc);
948 /*
949 * If dclk rate is zero, mean that scanout is stop,
950 * we don't need wait any more.
951 */
952 if (clk_get_rate(vop->dclk)) {
953 /*
954 * Rk3288 vop timing register is immediately, when configure
955 * display timing on display time, may cause tearing.
956 *
957 * Vop standby will take effect at end of current frame,
958 * if dsp hold valid irq happen, it means standby complete.
959 *
960 * mode set:
961 * standby and wait complete --> |----
962 * | display time
963 * |----
964 * |---> dsp hold irq
965 * configure display timing --> |
966 * standby exit |
967 * | new frame start.
968 */
969
970 reinit_completion(&vop->dsp_hold_completion);
971 vop_dsp_hold_valid_irq_enable(vop);
972
973 spin_lock(&vop->reg_lock);
974
975 VOP_CTRL_SET(vop, standby, 1);
976
977 spin_unlock(&vop->reg_lock);
978
979 wait_for_completion(&vop->dsp_hold_completion);
980
981 vop_dsp_hold_valid_irq_disable(vop);
982 }
983
984 val = 0x8;
985 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
986 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
987 VOP_CTRL_SET(vop, pin_pol, val);
988
989 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
990 val = hact_st << 16;
991 val |= hact_end;
992 VOP_CTRL_SET(vop, hact_st_end, val);
993 VOP_CTRL_SET(vop, hpost_st_end, val);
994
995 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
996 val = vact_st << 16;
997 val |= vact_end;
998 VOP_CTRL_SET(vop, vact_st_end, val);
999 VOP_CTRL_SET(vop, vpost_st_end, val);
1000
1001 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1002
1003 VOP_CTRL_SET(vop, standby, 0);
1004}
1005
1006static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1007 struct drm_crtc_state *old_crtc_state)
1008{
1009 struct vop *vop = to_vop(crtc);
1010
1011 if (WARN_ON(!vop->is_enabled))
1012 return;
1013
1014 spin_lock(&vop->reg_lock);
1015
1016 vop_cfg_done(vop);
1017
1018 spin_unlock(&vop->reg_lock);
1019}
1020
1021static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1022 struct drm_crtc_state *old_crtc_state)
1023{
1024 struct vop *vop = to_vop(crtc);
1025
1026 if (crtc->state->event) {
1027 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1028
1029 vop->event = crtc->state->event;
1030 crtc->state->event = NULL;
1031 }
1032}
1033
1034static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1035 .enable = vop_crtc_enable,
1036 .disable = vop_crtc_disable,
1037 .mode_fixup = vop_crtc_mode_fixup,
1038 .atomic_flush = vop_crtc_atomic_flush,
1039 .atomic_begin = vop_crtc_atomic_begin,
1040};
1041
1042static void vop_crtc_destroy(struct drm_crtc *crtc)
1043{
1044 drm_crtc_cleanup(crtc);
1045}
1046
1047static const struct drm_crtc_funcs vop_crtc_funcs = {
1048 .set_config = drm_atomic_helper_set_config,
1049 .page_flip = drm_atomic_helper_page_flip,
1050 .destroy = vop_crtc_destroy,
1051 .reset = drm_atomic_helper_crtc_reset,
1052 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1053 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1054};
1055
1056static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1057{
1058 struct drm_plane *plane = &vop_win->base;
1059 struct vop_plane_state *state = to_vop_plane_state(plane->state);
1060 dma_addr_t yrgb_mst;
1061
1062 if (!state->enable)
1063 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
1064
1065 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1066
1067 return yrgb_mst == state->yrgb_mst;
1068}
1069
1070static void vop_handle_vblank(struct vop *vop)
1071{
1072 struct drm_device *drm = vop->drm_dev;
1073 struct drm_crtc *crtc = &vop->crtc;
1074 unsigned long flags;
1075 int i;
1076
1077 for (i = 0; i < vop->data->win_size; i++) {
1078 if (!vop_win_pending_is_complete(&vop->win[i]))
1079 return;
1080 }
1081
1082 if (vop->event) {
1083 spin_lock_irqsave(&drm->event_lock, flags);
1084
1085 drm_crtc_send_vblank_event(crtc, vop->event);
1086 drm_crtc_vblank_put(crtc);
1087 vop->event = NULL;
1088
1089 spin_unlock_irqrestore(&drm->event_lock, flags);
1090 }
1091 if (!completion_done(&vop->wait_update_complete))
1092 complete(&vop->wait_update_complete);
1093}
1094
1095static irqreturn_t vop_isr(int irq, void *data)
1096{
1097 struct vop *vop = data;
1098 struct drm_crtc *crtc = &vop->crtc;
1099 uint32_t active_irqs;
1100 unsigned long flags;
1101 int ret = IRQ_NONE;
1102
1103 /*
1104 * interrupt register has interrupt status, enable and clear bits, we
1105 * must hold irq_lock to avoid a race with enable/disable_vblank().
1106 */
1107 spin_lock_irqsave(&vop->irq_lock, flags);
1108
1109 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1110 /* Clear all active interrupt sources */
1111 if (active_irqs)
1112 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1113
1114 spin_unlock_irqrestore(&vop->irq_lock, flags);
1115
1116 /* This is expected for vop iommu irqs, since the irq is shared */
1117 if (!active_irqs)
1118 return IRQ_NONE;
1119
1120 if (active_irqs & DSP_HOLD_VALID_INTR) {
1121 complete(&vop->dsp_hold_completion);
1122 active_irqs &= ~DSP_HOLD_VALID_INTR;
1123 ret = IRQ_HANDLED;
1124 }
1125
1126 if (active_irqs & FS_INTR) {
1127 drm_crtc_handle_vblank(crtc);
1128 vop_handle_vblank(vop);
1129 active_irqs &= ~FS_INTR;
1130 ret = IRQ_HANDLED;
1131 }
1132
1133 /* Unhandled irqs are spurious. */
1134 if (active_irqs)
1135 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1136
1137 return ret;
1138}
1139
1140static int vop_create_crtc(struct vop *vop)
1141{
1142 const struct vop_data *vop_data = vop->data;
1143 struct device *dev = vop->dev;
1144 struct drm_device *drm_dev = vop->drm_dev;
1145 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1146 struct drm_crtc *crtc = &vop->crtc;
1147 struct device_node *port;
1148 int ret;
1149 int i;
1150
1151 /*
1152 * Create drm_plane for primary and cursor planes first, since we need
1153 * to pass them to drm_crtc_init_with_planes, which sets the
1154 * "possible_crtcs" to the newly initialized crtc.
1155 */
1156 for (i = 0; i < vop_data->win_size; i++) {
1157 struct vop_win *vop_win = &vop->win[i];
1158 const struct vop_win_data *win_data = vop_win->data;
1159
1160 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1161 win_data->type != DRM_PLANE_TYPE_CURSOR)
1162 continue;
1163
1164 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1165 0, &vop_plane_funcs,
1166 win_data->phy->data_formats,
1167 win_data->phy->nformats,
1168 win_data->type, NULL);
1169 if (ret) {
1170 DRM_ERROR("failed to initialize plane\n");
1171 goto err_cleanup_planes;
1172 }
1173
1174 plane = &vop_win->base;
1175 drm_plane_helper_add(plane, &plane_helper_funcs);
1176 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1177 primary = plane;
1178 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1179 cursor = plane;
1180 }
1181
1182 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1183 &vop_crtc_funcs, NULL);
1184 if (ret)
1185 goto err_cleanup_planes;
1186
1187 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1188
1189 /*
1190 * Create drm_planes for overlay windows with possible_crtcs restricted
1191 * to the newly created crtc.
1192 */
1193 for (i = 0; i < vop_data->win_size; i++) {
1194 struct vop_win *vop_win = &vop->win[i];
1195 const struct vop_win_data *win_data = vop_win->data;
1196 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1197
1198 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1199 continue;
1200
1201 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1202 possible_crtcs,
1203 &vop_plane_funcs,
1204 win_data->phy->data_formats,
1205 win_data->phy->nformats,
1206 win_data->type, NULL);
1207 if (ret) {
1208 DRM_ERROR("failed to initialize overlay plane\n");
1209 goto err_cleanup_crtc;
1210 }
1211 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1212 }
1213
1214 port = of_get_child_by_name(dev->of_node, "port");
1215 if (!port) {
1216 DRM_ERROR("no port node found in %s\n",
1217 dev->of_node->full_name);
1218 ret = -ENOENT;
1219 goto err_cleanup_crtc;
1220 }
1221
1222 init_completion(&vop->dsp_hold_completion);
1223 init_completion(&vop->wait_update_complete);
1224 crtc->port = port;
1225 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1226
1227 return 0;
1228
1229err_cleanup_crtc:
1230 drm_crtc_cleanup(crtc);
1231err_cleanup_planes:
1232 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1233 head)
1234 drm_plane_cleanup(plane);
1235 return ret;
1236}
1237
1238static void vop_destroy_crtc(struct vop *vop)
1239{
1240 struct drm_crtc *crtc = &vop->crtc;
1241 struct drm_device *drm_dev = vop->drm_dev;
1242 struct drm_plane *plane, *tmp;
1243
1244 rockchip_unregister_crtc_funcs(crtc);
1245 of_node_put(crtc->port);
1246
1247 /*
1248 * We need to cleanup the planes now. Why?
1249 *
1250 * The planes are "&vop->win[i].base". That means the memory is
1251 * all part of the big "struct vop" chunk of memory. That memory
1252 * was devm allocated and associated with this component. We need to
1253 * free it ourselves before vop_unbind() finishes.
1254 */
1255 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1256 head)
1257 vop_plane_destroy(plane);
1258
1259 /*
1260 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1261 * references the CRTC.
1262 */
1263 drm_crtc_cleanup(crtc);
1264}
1265
1266static int vop_initial(struct vop *vop)
1267{
1268 const struct vop_data *vop_data = vop->data;
1269 const struct vop_reg_data *init_table = vop_data->init_table;
1270 struct reset_control *ahb_rst;
1271 int i, ret;
1272
1273 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1274 if (IS_ERR(vop->hclk)) {
1275 dev_err(vop->dev, "failed to get hclk source\n");
1276 return PTR_ERR(vop->hclk);
1277 }
1278 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1279 if (IS_ERR(vop->aclk)) {
1280 dev_err(vop->dev, "failed to get aclk source\n");
1281 return PTR_ERR(vop->aclk);
1282 }
1283 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1284 if (IS_ERR(vop->dclk)) {
1285 dev_err(vop->dev, "failed to get dclk source\n");
1286 return PTR_ERR(vop->dclk);
1287 }
1288
1289 ret = clk_prepare(vop->dclk);
1290 if (ret < 0) {
1291 dev_err(vop->dev, "failed to prepare dclk\n");
1292 return ret;
1293 }
1294
1295 /* Enable both the hclk and aclk to setup the vop */
1296 ret = clk_prepare_enable(vop->hclk);
1297 if (ret < 0) {
1298 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1299 goto err_unprepare_dclk;
1300 }
1301
1302 ret = clk_prepare_enable(vop->aclk);
1303 if (ret < 0) {
1304 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1305 goto err_disable_hclk;
1306 }
1307
1308 /*
1309 * do hclk_reset, reset all vop registers.
1310 */
1311 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1312 if (IS_ERR(ahb_rst)) {
1313 dev_err(vop->dev, "failed to get ahb reset\n");
1314 ret = PTR_ERR(ahb_rst);
1315 goto err_disable_aclk;
1316 }
1317 reset_control_assert(ahb_rst);
1318 usleep_range(10, 20);
1319 reset_control_deassert(ahb_rst);
1320
1321 memcpy(vop->regsbak, vop->regs, vop->len);
1322
1323 for (i = 0; i < vop_data->table_size; i++)
1324 vop_writel(vop, init_table[i].offset, init_table[i].value);
1325
1326 for (i = 0; i < vop_data->win_size; i++) {
1327 const struct vop_win_data *win = &vop_data->win[i];
1328
1329 VOP_WIN_SET(vop, win, enable, 0);
1330 }
1331
1332 vop_cfg_done(vop);
1333
1334 /*
1335 * do dclk_reset, let all config take affect.
1336 */
1337 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1338 if (IS_ERR(vop->dclk_rst)) {
1339 dev_err(vop->dev, "failed to get dclk reset\n");
1340 ret = PTR_ERR(vop->dclk_rst);
1341 goto err_disable_aclk;
1342 }
1343 reset_control_assert(vop->dclk_rst);
1344 usleep_range(10, 20);
1345 reset_control_deassert(vop->dclk_rst);
1346
1347 clk_disable(vop->hclk);
1348 clk_disable(vop->aclk);
1349
1350 vop->is_enabled = false;
1351
1352 return 0;
1353
1354err_disable_aclk:
1355 clk_disable_unprepare(vop->aclk);
1356err_disable_hclk:
1357 clk_disable_unprepare(vop->hclk);
1358err_unprepare_dclk:
1359 clk_unprepare(vop->dclk);
1360 return ret;
1361}
1362
1363/*
1364 * Initialize the vop->win array elements.
1365 */
1366static void vop_win_init(struct vop *vop)
1367{
1368 const struct vop_data *vop_data = vop->data;
1369 unsigned int i;
1370
1371 for (i = 0; i < vop_data->win_size; i++) {
1372 struct vop_win *vop_win = &vop->win[i];
1373 const struct vop_win_data *win_data = &vop_data->win[i];
1374
1375 vop_win->data = win_data;
1376 vop_win->vop = vop;
1377 }
1378}
1379
1380static int vop_bind(struct device *dev, struct device *master, void *data)
1381{
1382 struct platform_device *pdev = to_platform_device(dev);
1383 const struct vop_data *vop_data;
1384 struct drm_device *drm_dev = data;
1385 struct vop *vop;
1386 struct resource *res;
1387 size_t alloc_size;
1388 int ret, irq;
1389
1390 vop_data = of_device_get_match_data(dev);
1391 if (!vop_data)
1392 return -ENODEV;
1393
1394 /* Allocate vop struct and its vop_win array */
1395 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1396 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1397 if (!vop)
1398 return -ENOMEM;
1399
1400 vop->dev = dev;
1401 vop->data = vop_data;
1402 vop->drm_dev = drm_dev;
1403 dev_set_drvdata(dev, vop);
1404
1405 vop_win_init(vop);
1406
1407 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1408 vop->len = resource_size(res);
1409 vop->regs = devm_ioremap_resource(dev, res);
1410 if (IS_ERR(vop->regs))
1411 return PTR_ERR(vop->regs);
1412
1413 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1414 if (!vop->regsbak)
1415 return -ENOMEM;
1416
1417 ret = vop_initial(vop);
1418 if (ret < 0) {
1419 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1420 return ret;
1421 }
1422
1423 irq = platform_get_irq(pdev, 0);
1424 if (irq < 0) {
1425 dev_err(dev, "cannot find irq for vop\n");
1426 return irq;
1427 }
1428 vop->irq = (unsigned int)irq;
1429
1430 spin_lock_init(&vop->reg_lock);
1431 spin_lock_init(&vop->irq_lock);
1432
1433 mutex_init(&vop->vsync_mutex);
1434
1435 ret = devm_request_irq(dev, vop->irq, vop_isr,
1436 IRQF_SHARED, dev_name(dev), vop);
1437 if (ret)
1438 return ret;
1439
1440 /* IRQ is initially disabled; it gets enabled in power_on */
1441 disable_irq(vop->irq);
1442
1443 ret = vop_create_crtc(vop);
1444 if (ret)
1445 return ret;
1446
1447 pm_runtime_enable(&pdev->dev);
1448 return 0;
1449}
1450
1451static void vop_unbind(struct device *dev, struct device *master, void *data)
1452{
1453 struct vop *vop = dev_get_drvdata(dev);
1454
1455 pm_runtime_disable(dev);
1456 vop_destroy_crtc(vop);
1457}
1458
1459const struct component_ops vop_component_ops = {
1460 .bind = vop_bind,
1461 .unbind = vop_unbind,
1462};
1463EXPORT_SYMBOL_GPL(vop_component_ops);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/component.h>
9#include <linux/delay.h>
10#include <linux/iopoll.h>
11#include <linux/kernel.h>
12#include <linux/log2.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/overflow.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/reset.h>
19
20#include <drm/drm.h>
21#include <drm/drm_atomic.h>
22#include <drm/drm_atomic_uapi.h>
23#include <drm/drm_blend.h>
24#include <drm/drm_crtc.h>
25#include <drm/drm_flip_work.h>
26#include <drm/drm_fourcc.h>
27#include <drm/drm_framebuffer.h>
28#include <drm/drm_gem_atomic_helper.h>
29#include <drm/drm_gem_framebuffer_helper.h>
30#include <drm/drm_probe_helper.h>
31#include <drm/drm_self_refresh_helper.h>
32#include <drm/drm_vblank.h>
33
34#ifdef CONFIG_DRM_ANALOGIX_DP
35#include <drm/bridge/analogix_dp.h>
36#endif
37
38#include "rockchip_drm_drv.h"
39#include "rockchip_drm_gem.h"
40#include "rockchip_drm_fb.h"
41#include "rockchip_drm_vop.h"
42#include "rockchip_rgb.h"
43
44#define VOP_WIN_SET(vop, win, name, v) \
45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
46#define VOP_SCL_SET(vop, win, name, v) \
47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
48#define VOP_SCL_SET_EXT(vop, win, name, v) \
49 vop_reg_set(vop, &win->phy->scl->ext->name, \
50 win->base, ~0, v, #name)
51
52#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
53 do { \
54 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
56 } while (0)
57
58#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
59 do { \
60 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
62 } while (0)
63
64#define VOP_INTR_SET_MASK(vop, name, mask, v) \
65 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
66
67#define VOP_REG_SET(vop, group, name, v) \
68 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
69
70#define VOP_HAS_REG(vop, group, name) \
71 (!!(vop->data->group->name.mask))
72
73#define VOP_INTR_SET_TYPE(vop, name, type, v) \
74 do { \
75 int i, reg = 0, mask = 0; \
76 for (i = 0; i < vop->data->intr->nintrs; i++) { \
77 if (vop->data->intr->intrs[i] & type) { \
78 reg |= (v) << i; \
79 mask |= 1 << i; \
80 } \
81 } \
82 VOP_INTR_SET_MASK(vop, name, mask, reg); \
83 } while (0)
84#define VOP_INTR_GET_TYPE(vop, name, type) \
85 vop_get_intr_type(vop, &vop->data->intr->name, type)
86
87#define VOP_WIN_GET(vop, win, name) \
88 vop_read_reg(vop, win->base, &win->phy->name)
89
90#define VOP_WIN_HAS_REG(win, name) \
91 (!!(win->phy->name.mask))
92
93#define VOP_WIN_GET_YRGBADDR(vop, win) \
94 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
95
96#define VOP_WIN_TO_INDEX(vop_win) \
97 ((vop_win) - (vop_win)->vop->win)
98
99#define VOP_AFBC_SET(vop, name, v) \
100 do { \
101 if ((vop)->data->afbc) \
102 vop_reg_set((vop), &(vop)->data->afbc->name, \
103 0, ~0, v, #name); \
104 } while (0)
105
106#define to_vop(x) container_of(x, struct vop, crtc)
107#define to_vop_win(x) container_of(x, struct vop_win, base)
108
109#define AFBC_FMT_RGB565 0x0
110#define AFBC_FMT_U8U8U8U8 0x5
111#define AFBC_FMT_U8U8U8 0x4
112
113#define AFBC_TILE_16x16 BIT(4)
114
115/*
116 * The coefficients of the following matrix are all fixed points.
117 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
118 * They are all represented in two's complement.
119 */
120static const uint32_t bt601_yuv2rgb[] = {
121 0x4A8, 0x0, 0x662,
122 0x4A8, 0x1E6F, 0x1CBF,
123 0x4A8, 0x812, 0x0,
124 0x321168, 0x0877CF, 0x2EB127
125};
126
127enum vop_pending {
128 VOP_PENDING_FB_UNREF,
129};
130
131struct vop_win {
132 struct drm_plane base;
133 const struct vop_win_data *data;
134 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
135 struct vop *vop;
136};
137
138struct rockchip_rgb;
139struct vop {
140 struct drm_crtc crtc;
141 struct device *dev;
142 struct drm_device *drm_dev;
143 bool is_enabled;
144
145 struct completion dsp_hold_completion;
146 unsigned int win_enabled;
147
148 /* protected by dev->event_lock */
149 struct drm_pending_vblank_event *event;
150
151 struct drm_flip_work fb_unref_work;
152 unsigned long pending;
153
154 struct completion line_flag_completion;
155
156 const struct vop_data *data;
157
158 uint32_t *regsbak;
159 void __iomem *regs;
160 void __iomem *lut_regs;
161
162 /* physical map length of vop register */
163 uint32_t len;
164
165 /* one time only one process allowed to config the register */
166 spinlock_t reg_lock;
167 /* lock vop irq reg */
168 spinlock_t irq_lock;
169 /* protects crtc enable/disable */
170 struct mutex vop_lock;
171
172 unsigned int irq;
173
174 /* vop AHP clk */
175 struct clk *hclk;
176 /* vop dclk */
177 struct clk *dclk;
178 /* vop share memory frequency */
179 struct clk *aclk;
180
181 /* vop dclk reset */
182 struct reset_control *dclk_rst;
183
184 /* optional internal rgb encoder */
185 struct rockchip_rgb *rgb;
186
187 struct vop_win win[];
188};
189
190static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
191{
192 return readl(vop->regs + offset);
193}
194
195static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
196 const struct vop_reg *reg)
197{
198 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
199}
200
201static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
202 uint32_t _offset, uint32_t _mask, uint32_t v,
203 const char *reg_name)
204{
205 int offset, mask, shift;
206
207 if (!reg || !reg->mask) {
208 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
209 return;
210 }
211
212 offset = reg->offset + _offset;
213 mask = reg->mask & _mask;
214 shift = reg->shift;
215
216 if (reg->write_mask) {
217 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
218 } else {
219 uint32_t cached_val = vop->regsbak[offset >> 2];
220
221 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
222 vop->regsbak[offset >> 2] = v;
223 }
224
225 if (reg->relaxed)
226 writel_relaxed(v, vop->regs + offset);
227 else
228 writel(v, vop->regs + offset);
229}
230
231static inline uint32_t vop_get_intr_type(struct vop *vop,
232 const struct vop_reg *reg, int type)
233{
234 uint32_t i, ret = 0;
235 uint32_t regs = vop_read_reg(vop, 0, reg);
236
237 for (i = 0; i < vop->data->intr->nintrs; i++) {
238 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
239 ret |= vop->data->intr->intrs[i];
240 }
241
242 return ret;
243}
244
245static inline void vop_cfg_done(struct vop *vop)
246{
247 VOP_REG_SET(vop, common, cfg_done, 1);
248}
249
250static bool has_rb_swapped(uint32_t version, uint32_t format)
251{
252 switch (format) {
253 case DRM_FORMAT_XBGR8888:
254 case DRM_FORMAT_ABGR8888:
255 case DRM_FORMAT_BGR565:
256 return true;
257 /*
258 * full framework (IP version 3.x) only need rb swapped for RGB888 and
259 * little framework (IP version 2.x) only need rb swapped for BGR888,
260 * check for 3.x to also only rb swap BGR888 for unknown vop version
261 */
262 case DRM_FORMAT_RGB888:
263 return VOP_MAJOR(version) == 3;
264 case DRM_FORMAT_BGR888:
265 return VOP_MAJOR(version) != 3;
266 default:
267 return false;
268 }
269}
270
271static bool has_uv_swapped(uint32_t format)
272{
273 switch (format) {
274 case DRM_FORMAT_NV21:
275 case DRM_FORMAT_NV61:
276 case DRM_FORMAT_NV42:
277 return true;
278 default:
279 return false;
280 }
281}
282
283static bool is_fmt_10(uint32_t format)
284{
285 switch (format) {
286 case DRM_FORMAT_NV15:
287 case DRM_FORMAT_NV20:
288 case DRM_FORMAT_NV30:
289 return true;
290 default:
291 return false;
292 }
293}
294
295static enum vop_data_format vop_convert_format(uint32_t format)
296{
297 switch (format) {
298 case DRM_FORMAT_XRGB8888:
299 case DRM_FORMAT_ARGB8888:
300 case DRM_FORMAT_XBGR8888:
301 case DRM_FORMAT_ABGR8888:
302 return VOP_FMT_ARGB8888;
303 case DRM_FORMAT_RGB888:
304 case DRM_FORMAT_BGR888:
305 return VOP_FMT_RGB888;
306 case DRM_FORMAT_RGB565:
307 case DRM_FORMAT_BGR565:
308 return VOP_FMT_RGB565;
309 case DRM_FORMAT_NV12:
310 case DRM_FORMAT_NV15:
311 case DRM_FORMAT_NV21:
312 return VOP_FMT_YUV420SP;
313 case DRM_FORMAT_NV16:
314 case DRM_FORMAT_NV20:
315 case DRM_FORMAT_NV61:
316 return VOP_FMT_YUV422SP;
317 case DRM_FORMAT_NV24:
318 case DRM_FORMAT_NV30:
319 case DRM_FORMAT_NV42:
320 return VOP_FMT_YUV444SP;
321 default:
322 DRM_ERROR("unsupported format[%08x]\n", format);
323 return -EINVAL;
324 }
325}
326
327static int vop_convert_afbc_format(uint32_t format)
328{
329 switch (format) {
330 case DRM_FORMAT_XRGB8888:
331 case DRM_FORMAT_ARGB8888:
332 case DRM_FORMAT_XBGR8888:
333 case DRM_FORMAT_ABGR8888:
334 return AFBC_FMT_U8U8U8U8;
335 case DRM_FORMAT_RGB888:
336 case DRM_FORMAT_BGR888:
337 return AFBC_FMT_U8U8U8;
338 case DRM_FORMAT_RGB565:
339 case DRM_FORMAT_BGR565:
340 return AFBC_FMT_RGB565;
341 default:
342 DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n", format);
343 return -EINVAL;
344 }
345}
346
347static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
348 uint32_t dst, bool is_horizontal,
349 int vsu_mode, int *vskiplines)
350{
351 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
352
353 if (vskiplines)
354 *vskiplines = 0;
355
356 if (is_horizontal) {
357 if (mode == SCALE_UP)
358 val = GET_SCL_FT_BIC(src, dst);
359 else if (mode == SCALE_DOWN)
360 val = GET_SCL_FT_BILI_DN(src, dst);
361 } else {
362 if (mode == SCALE_UP) {
363 if (vsu_mode == SCALE_UP_BIL)
364 val = GET_SCL_FT_BILI_UP(src, dst);
365 else
366 val = GET_SCL_FT_BIC(src, dst);
367 } else if (mode == SCALE_DOWN) {
368 if (vskiplines) {
369 *vskiplines = scl_get_vskiplines(src, dst);
370 val = scl_get_bili_dn_vskip(src, dst,
371 *vskiplines);
372 } else {
373 val = GET_SCL_FT_BILI_DN(src, dst);
374 }
375 }
376 }
377
378 return val;
379}
380
381static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
382 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
383 uint32_t dst_h, const struct drm_format_info *info)
384{
385 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
386 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
387 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
388 bool is_yuv = false;
389 uint16_t cbcr_src_w = src_w / info->hsub;
390 uint16_t cbcr_src_h = src_h / info->vsub;
391 uint16_t vsu_mode;
392 uint16_t lb_mode;
393 uint32_t val;
394 int vskiplines;
395
396 if (info->is_yuv)
397 is_yuv = true;
398
399 if (dst_w > 3840) {
400 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
401 return;
402 }
403
404 if (!win->phy->scl->ext) {
405 VOP_SCL_SET(vop, win, scale_yrgb_x,
406 scl_cal_scale2(src_w, dst_w));
407 VOP_SCL_SET(vop, win, scale_yrgb_y,
408 scl_cal_scale2(src_h, dst_h));
409 if (is_yuv) {
410 VOP_SCL_SET(vop, win, scale_cbcr_x,
411 scl_cal_scale2(cbcr_src_w, dst_w));
412 VOP_SCL_SET(vop, win, scale_cbcr_y,
413 scl_cal_scale2(cbcr_src_h, dst_h));
414 }
415 return;
416 }
417
418 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
419 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
420
421 if (is_yuv) {
422 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
423 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
424 if (cbcr_hor_scl_mode == SCALE_DOWN)
425 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
426 else
427 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
428 } else {
429 if (yrgb_hor_scl_mode == SCALE_DOWN)
430 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
431 else
432 lb_mode = scl_vop_cal_lb_mode(src_w, false);
433 }
434
435 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
436 if (lb_mode == LB_RGB_3840X2) {
437 if (yrgb_ver_scl_mode != SCALE_NONE) {
438 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
439 return;
440 }
441 if (cbcr_ver_scl_mode != SCALE_NONE) {
442 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
443 return;
444 }
445 vsu_mode = SCALE_UP_BIL;
446 } else if (lb_mode == LB_RGB_2560X4) {
447 vsu_mode = SCALE_UP_BIL;
448 } else {
449 vsu_mode = SCALE_UP_BIC;
450 }
451
452 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
453 true, 0, NULL);
454 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
455 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
456 false, vsu_mode, &vskiplines);
457 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
458
459 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
460 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
461
462 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
463 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
464 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
465 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
466 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
467 if (is_yuv) {
468 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
469 dst_w, true, 0, NULL);
470 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
471 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
472 dst_h, false, vsu_mode, &vskiplines);
473 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
474
475 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
476 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
477 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
478 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
479 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
480 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
481 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
482 }
483}
484
485static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
486{
487 unsigned long flags;
488
489 if (WARN_ON(!vop->is_enabled))
490 return;
491
492 spin_lock_irqsave(&vop->irq_lock, flags);
493
494 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
495 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
496
497 spin_unlock_irqrestore(&vop->irq_lock, flags);
498}
499
500static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
501{
502 unsigned long flags;
503
504 if (WARN_ON(!vop->is_enabled))
505 return;
506
507 spin_lock_irqsave(&vop->irq_lock, flags);
508
509 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
510
511 spin_unlock_irqrestore(&vop->irq_lock, flags);
512}
513
514/*
515 * (1) each frame starts at the start of the Vsync pulse which is signaled by
516 * the "FRAME_SYNC" interrupt.
517 * (2) the active data region of each frame ends at dsp_vact_end
518 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
519 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
520 *
521 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
522 * Interrupts
523 * LINE_FLAG -------------------------------+
524 * FRAME_SYNC ----+ |
525 * | |
526 * v v
527 * | Vsync | Vbp | Vactive | Vfp |
528 * ^ ^ ^ ^
529 * | | | |
530 * | | | |
531 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
532 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
533 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
534 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
535 */
536static bool vop_line_flag_irq_is_enabled(struct vop *vop)
537{
538 uint32_t line_flag_irq;
539 unsigned long flags;
540
541 spin_lock_irqsave(&vop->irq_lock, flags);
542
543 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
544
545 spin_unlock_irqrestore(&vop->irq_lock, flags);
546
547 return !!line_flag_irq;
548}
549
550static void vop_line_flag_irq_enable(struct vop *vop)
551{
552 unsigned long flags;
553
554 if (WARN_ON(!vop->is_enabled))
555 return;
556
557 spin_lock_irqsave(&vop->irq_lock, flags);
558
559 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
560 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
561
562 spin_unlock_irqrestore(&vop->irq_lock, flags);
563}
564
565static void vop_line_flag_irq_disable(struct vop *vop)
566{
567 unsigned long flags;
568
569 if (WARN_ON(!vop->is_enabled))
570 return;
571
572 spin_lock_irqsave(&vop->irq_lock, flags);
573
574 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
575
576 spin_unlock_irqrestore(&vop->irq_lock, flags);
577}
578
579static int vop_core_clks_enable(struct vop *vop)
580{
581 int ret;
582
583 ret = clk_enable(vop->hclk);
584 if (ret < 0)
585 return ret;
586
587 ret = clk_enable(vop->aclk);
588 if (ret < 0)
589 goto err_disable_hclk;
590
591 return 0;
592
593err_disable_hclk:
594 clk_disable(vop->hclk);
595 return ret;
596}
597
598static void vop_core_clks_disable(struct vop *vop)
599{
600 clk_disable(vop->aclk);
601 clk_disable(vop->hclk);
602}
603
604static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
605{
606 const struct vop_win_data *win = vop_win->data;
607
608 if (win->phy->scl && win->phy->scl->ext) {
609 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
610 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
611 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
612 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
613 }
614
615 VOP_WIN_SET(vop, win, enable, 0);
616 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
617}
618
619static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
620{
621 struct vop *vop = to_vop(crtc);
622 int ret, i;
623
624 ret = pm_runtime_resume_and_get(vop->dev);
625 if (ret < 0) {
626 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
627 return ret;
628 }
629
630 ret = vop_core_clks_enable(vop);
631 if (WARN_ON(ret < 0))
632 goto err_put_pm_runtime;
633
634 ret = clk_enable(vop->dclk);
635 if (WARN_ON(ret < 0))
636 goto err_disable_core;
637
638 /*
639 * Slave iommu shares power, irq and clock with vop. It was associated
640 * automatically with this master device via common driver code.
641 * Now that we have enabled the clock we attach it to the shared drm
642 * mapping.
643 */
644 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
645 if (ret) {
646 DRM_DEV_ERROR(vop->dev,
647 "failed to attach dma mapping, %d\n", ret);
648 goto err_disable_dclk;
649 }
650
651 spin_lock(&vop->reg_lock);
652 for (i = 0; i < vop->len; i += 4)
653 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
654
655 /*
656 * We need to make sure that all windows are disabled before we
657 * enable the crtc. Otherwise we might try to scan from a destroyed
658 * buffer later.
659 *
660 * In the case of enable-after-PSR, we don't need to worry about this
661 * case since the buffer is guaranteed to be valid and disabling the
662 * window will result in screen glitches on PSR exit.
663 */
664 if (!old_state || !old_state->self_refresh_active) {
665 for (i = 0; i < vop->data->win_size; i++) {
666 struct vop_win *vop_win = &vop->win[i];
667
668 vop_win_disable(vop, vop_win);
669 }
670 }
671
672 if (vop->data->afbc) {
673 struct rockchip_crtc_state *s;
674 /*
675 * Disable AFBC and forget there was a vop window with AFBC
676 */
677 VOP_AFBC_SET(vop, enable, 0);
678 s = to_rockchip_crtc_state(crtc->state);
679 s->enable_afbc = false;
680 }
681
682 vop_cfg_done(vop);
683
684 spin_unlock(&vop->reg_lock);
685
686 /*
687 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
688 */
689 vop->is_enabled = true;
690
691 spin_lock(&vop->reg_lock);
692
693 VOP_REG_SET(vop, common, standby, 1);
694
695 spin_unlock(&vop->reg_lock);
696
697 drm_crtc_vblank_on(crtc);
698
699 return 0;
700
701err_disable_dclk:
702 clk_disable(vop->dclk);
703err_disable_core:
704 vop_core_clks_disable(vop);
705err_put_pm_runtime:
706 pm_runtime_put_sync(vop->dev);
707 return ret;
708}
709
710static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
711{
712 struct vop *vop = to_vop(crtc);
713 int i;
714
715 spin_lock(&vop->reg_lock);
716
717 for (i = 0; i < vop->data->win_size; i++) {
718 struct vop_win *vop_win = &vop->win[i];
719 const struct vop_win_data *win = vop_win->data;
720
721 VOP_WIN_SET(vop, win, enable,
722 enabled && (vop->win_enabled & BIT(i)));
723 }
724 vop_cfg_done(vop);
725
726 spin_unlock(&vop->reg_lock);
727}
728
729static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
730 struct drm_atomic_state *state)
731{
732 struct vop *vop = to_vop(crtc);
733
734 WARN_ON(vop->event);
735
736 if (crtc->state->self_refresh_active)
737 rockchip_drm_set_win_enabled(crtc, false);
738
739 if (crtc->state->self_refresh_active)
740 goto out;
741
742 mutex_lock(&vop->vop_lock);
743
744 drm_crtc_vblank_off(crtc);
745
746 /*
747 * Vop standby will take effect at end of current frame,
748 * if dsp hold valid irq happen, it means standby complete.
749 *
750 * we must wait standby complete when we want to disable aclk,
751 * if not, memory bus maybe dead.
752 */
753 reinit_completion(&vop->dsp_hold_completion);
754 vop_dsp_hold_valid_irq_enable(vop);
755
756 spin_lock(&vop->reg_lock);
757
758 VOP_REG_SET(vop, common, standby, 1);
759
760 spin_unlock(&vop->reg_lock);
761
762 if (!wait_for_completion_timeout(&vop->dsp_hold_completion,
763 msecs_to_jiffies(200)))
764 WARN(1, "%s: timed out waiting for DSP hold", crtc->name);
765
766 vop_dsp_hold_valid_irq_disable(vop);
767
768 vop->is_enabled = false;
769
770 /*
771 * vop standby complete, so iommu detach is safe.
772 */
773 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
774
775 clk_disable(vop->dclk);
776 vop_core_clks_disable(vop);
777 pm_runtime_put(vop->dev);
778
779 mutex_unlock(&vop->vop_lock);
780
781out:
782 if (crtc->state->event && !crtc->state->active) {
783 spin_lock_irq(&crtc->dev->event_lock);
784 drm_crtc_send_vblank_event(crtc, crtc->state->event);
785 spin_unlock_irq(&crtc->dev->event_lock);
786
787 crtc->state->event = NULL;
788 }
789}
790
791static inline bool rockchip_afbc(u64 modifier)
792{
793 return modifier == ROCKCHIP_AFBC_MOD;
794}
795
796static bool rockchip_mod_supported(struct drm_plane *plane,
797 u32 format, u64 modifier)
798{
799 if (modifier == DRM_FORMAT_MOD_LINEAR)
800 return true;
801
802 if (!rockchip_afbc(modifier)) {
803 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
804
805 return false;
806 }
807
808 return vop_convert_afbc_format(format) >= 0;
809}
810
811static int vop_plane_atomic_check(struct drm_plane *plane,
812 struct drm_atomic_state *state)
813{
814 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
815 plane);
816 struct drm_crtc *crtc = new_plane_state->crtc;
817 struct drm_crtc_state *crtc_state;
818 struct drm_framebuffer *fb = new_plane_state->fb;
819 struct vop_win *vop_win = to_vop_win(plane);
820 const struct vop_win_data *win = vop_win->data;
821 int ret;
822 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
823 DRM_PLANE_NO_SCALING;
824 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
825 DRM_PLANE_NO_SCALING;
826
827 if (!crtc || WARN_ON(!fb))
828 return 0;
829
830 crtc_state = drm_atomic_get_existing_crtc_state(state,
831 crtc);
832 if (WARN_ON(!crtc_state))
833 return -EINVAL;
834
835 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
836 min_scale, max_scale,
837 true, true);
838 if (ret)
839 return ret;
840
841 if (!new_plane_state->visible)
842 return 0;
843
844 ret = vop_convert_format(fb->format->format);
845 if (ret < 0)
846 return ret;
847
848 /*
849 * Src.x1 can be odd when do clip, but yuv plane start point
850 * need align with 2 pixel.
851 */
852 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) {
853 DRM_DEBUG_KMS("Invalid Source: Yuv format not support odd xpos\n");
854 return -EINVAL;
855 }
856
857 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) {
858 DRM_DEBUG_KMS("Invalid Source: Yuv format does not support this rotation\n");
859 return -EINVAL;
860 }
861
862 if (rockchip_afbc(fb->modifier)) {
863 struct vop *vop = to_vop(crtc);
864
865 if (!vop->data->afbc) {
866 DRM_DEBUG_KMS("vop does not support AFBC\n");
867 return -EINVAL;
868 }
869
870 ret = vop_convert_afbc_format(fb->format->format);
871 if (ret < 0)
872 return ret;
873
874 if (new_plane_state->src.x1 || new_plane_state->src.y1) {
875 DRM_DEBUG_KMS("AFBC does not support offset display, " \
876 "xpos=%d, ypos=%d, offset=%d\n",
877 new_plane_state->src.x1, new_plane_state->src.y1,
878 fb->offsets[0]);
879 return -EINVAL;
880 }
881
882 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) {
883 DRM_DEBUG_KMS("No rotation support in AFBC, rotation=%d\n",
884 new_plane_state->rotation);
885 return -EINVAL;
886 }
887 }
888
889 return 0;
890}
891
892static void vop_plane_atomic_disable(struct drm_plane *plane,
893 struct drm_atomic_state *state)
894{
895 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
896 plane);
897 struct vop_win *vop_win = to_vop_win(plane);
898 struct vop *vop = to_vop(old_state->crtc);
899
900 if (!old_state->crtc)
901 return;
902
903 spin_lock(&vop->reg_lock);
904
905 vop_win_disable(vop, vop_win);
906
907 spin_unlock(&vop->reg_lock);
908}
909
910static void vop_plane_atomic_update(struct drm_plane *plane,
911 struct drm_atomic_state *state)
912{
913 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
914 plane);
915 struct drm_crtc *crtc = new_state->crtc;
916 struct vop_win *vop_win = to_vop_win(plane);
917 const struct vop_win_data *win = vop_win->data;
918 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
919 struct vop *vop = to_vop(new_state->crtc);
920 struct drm_framebuffer *fb = new_state->fb;
921 unsigned int actual_w, actual_h;
922 unsigned int dsp_stx, dsp_sty;
923 uint32_t act_info, dsp_info, dsp_st;
924 struct drm_rect *src = &new_state->src;
925 struct drm_rect *dest = &new_state->dst;
926 struct drm_gem_object *obj, *uv_obj;
927 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
928 unsigned long offset;
929 dma_addr_t dma_addr;
930 uint32_t val;
931 bool rb_swap, uv_swap;
932 int win_index = VOP_WIN_TO_INDEX(vop_win);
933 int format;
934 int is_yuv = fb->format->is_yuv;
935 int i;
936
937 /*
938 * can't update plane when vop is disabled.
939 */
940 if (WARN_ON(!crtc))
941 return;
942
943 if (WARN_ON(!vop->is_enabled))
944 return;
945
946 if (!new_state->visible) {
947 vop_plane_atomic_disable(plane, state);
948 return;
949 }
950
951 obj = fb->obj[0];
952 rk_obj = to_rockchip_obj(obj);
953
954 actual_w = drm_rect_width(src) >> 16;
955 actual_h = drm_rect_height(src) >> 16;
956 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
957
958 dsp_info = (drm_rect_height(dest) - 1) << 16;
959 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
960
961 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
962 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
963 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
964
965 if (fb->format->char_per_block[0])
966 offset = drm_format_info_min_pitch(fb->format, 0,
967 src->x1 >> 16);
968 else
969 offset = (src->x1 >> 16) * fb->format->cpp[0];
970
971 offset += (src->y1 >> 16) * fb->pitches[0];
972 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
973
974 /*
975 * For y-mirroring we need to move address
976 * to the beginning of the last line.
977 */
978 if (new_state->rotation & DRM_MODE_REFLECT_Y)
979 dma_addr += (actual_h - 1) * fb->pitches[0];
980
981 format = vop_convert_format(fb->format->format);
982
983 spin_lock(&vop->reg_lock);
984
985 if (rockchip_afbc(fb->modifier)) {
986 int afbc_format = vop_convert_afbc_format(fb->format->format);
987
988 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
989 VOP_AFBC_SET(vop, hreg_block_split, 0);
990 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
991 VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
992 VOP_AFBC_SET(vop, pic_size, act_info);
993 }
994
995 VOP_WIN_SET(vop, win, format, format);
996 VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
997 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
998 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
999 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
1000 VOP_WIN_SET(vop, win, y_mir_en,
1001 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
1002 VOP_WIN_SET(vop, win, x_mir_en,
1003 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
1004
1005 if (is_yuv) {
1006 uv_obj = fb->obj[1];
1007 rk_uv_obj = to_rockchip_obj(uv_obj);
1008
1009 if (fb->format->char_per_block[1])
1010 offset = drm_format_info_min_pitch(fb->format, 1,
1011 src->x1 >> 16);
1012 else
1013 offset = (src->x1 >> 16) * fb->format->cpp[1];
1014 offset /= fb->format->hsub;
1015 offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub;
1016
1017 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
1018 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
1019 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
1020
1021 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
1022 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
1023 win_yuv2yuv,
1024 y2r_coefficients[i],
1025 bt601_yuv2rgb[i]);
1026 }
1027
1028 uv_swap = has_uv_swapped(fb->format->format);
1029 VOP_WIN_SET(vop, win, uv_swap, uv_swap);
1030 }
1031
1032 if (win->phy->scl)
1033 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1034 drm_rect_width(dest), drm_rect_height(dest),
1035 fb->format);
1036
1037 VOP_WIN_SET(vop, win, act_info, act_info);
1038 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1039 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1040
1041 rb_swap = has_rb_swapped(vop->data->version, fb->format->format);
1042 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1043
1044 /*
1045 * Blending win0 with the background color doesn't seem to work
1046 * correctly. We only get the background color, no matter the contents
1047 * of the win0 framebuffer. However, blending pre-multiplied color
1048 * with the default opaque black default background color is a no-op,
1049 * so we can just disable blending to get the correct result.
1050 */
1051 if (fb->format->has_alpha && win_index > 0) {
1052 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1053 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1054 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1055 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1056 SRC_BLEND_M0(ALPHA_PER_PIX) |
1057 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1058 SRC_FACTOR_M0(ALPHA_ONE);
1059 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1060
1061 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
1062 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
1063 VOP_WIN_SET(vop, win, alpha_en, 1);
1064 } else {
1065 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1066 VOP_WIN_SET(vop, win, alpha_en, 0);
1067 }
1068
1069 VOP_WIN_SET(vop, win, enable, 1);
1070 vop->win_enabled |= BIT(win_index);
1071 spin_unlock(&vop->reg_lock);
1072}
1073
1074static int vop_plane_atomic_async_check(struct drm_plane *plane,
1075 struct drm_atomic_state *state)
1076{
1077 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1078 plane);
1079 struct vop_win *vop_win = to_vop_win(plane);
1080 const struct vop_win_data *win = vop_win->data;
1081 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1082 DRM_PLANE_NO_SCALING;
1083 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1084 DRM_PLANE_NO_SCALING;
1085 struct drm_crtc_state *crtc_state;
1086
1087 if (plane != new_plane_state->crtc->cursor)
1088 return -EINVAL;
1089
1090 if (!plane->state)
1091 return -EINVAL;
1092
1093 if (!plane->state->fb)
1094 return -EINVAL;
1095
1096 if (state)
1097 crtc_state = drm_atomic_get_existing_crtc_state(state,
1098 new_plane_state->crtc);
1099 else /* Special case for asynchronous cursor updates. */
1100 crtc_state = plane->crtc->state;
1101
1102 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
1103 min_scale, max_scale,
1104 true, true);
1105}
1106
1107static void vop_plane_atomic_async_update(struct drm_plane *plane,
1108 struct drm_atomic_state *state)
1109{
1110 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1111 plane);
1112 struct vop *vop = to_vop(plane->state->crtc);
1113 struct drm_framebuffer *old_fb = plane->state->fb;
1114
1115 plane->state->crtc_x = new_state->crtc_x;
1116 plane->state->crtc_y = new_state->crtc_y;
1117 plane->state->crtc_h = new_state->crtc_h;
1118 plane->state->crtc_w = new_state->crtc_w;
1119 plane->state->src_x = new_state->src_x;
1120 plane->state->src_y = new_state->src_y;
1121 plane->state->src_h = new_state->src_h;
1122 plane->state->src_w = new_state->src_w;
1123 swap(plane->state->fb, new_state->fb);
1124
1125 if (vop->is_enabled) {
1126 vop_plane_atomic_update(plane, state);
1127 spin_lock(&vop->reg_lock);
1128 vop_cfg_done(vop);
1129 spin_unlock(&vop->reg_lock);
1130
1131 /*
1132 * A scanout can still be occurring, so we can't drop the
1133 * reference to the old framebuffer. To solve this we get a
1134 * reference to old_fb and set a worker to release it later.
1135 * FIXME: if we perform 500 async_update calls before the
1136 * vblank, then we can have 500 different framebuffers waiting
1137 * to be released.
1138 */
1139 if (old_fb && plane->state->fb != old_fb) {
1140 drm_framebuffer_get(old_fb);
1141 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
1142 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
1143 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1144 }
1145 }
1146}
1147
1148static const struct drm_plane_helper_funcs plane_helper_funcs = {
1149 .atomic_check = vop_plane_atomic_check,
1150 .atomic_update = vop_plane_atomic_update,
1151 .atomic_disable = vop_plane_atomic_disable,
1152 .atomic_async_check = vop_plane_atomic_async_check,
1153 .atomic_async_update = vop_plane_atomic_async_update,
1154};
1155
1156static const struct drm_plane_funcs vop_plane_funcs = {
1157 .update_plane = drm_atomic_helper_update_plane,
1158 .disable_plane = drm_atomic_helper_disable_plane,
1159 .destroy = drm_plane_cleanup,
1160 .reset = drm_atomic_helper_plane_reset,
1161 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1162 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1163 .format_mod_supported = rockchip_mod_supported,
1164};
1165
1166static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1167{
1168 struct vop *vop = to_vop(crtc);
1169 unsigned long flags;
1170
1171 if (WARN_ON(!vop->is_enabled))
1172 return -EPERM;
1173
1174 spin_lock_irqsave(&vop->irq_lock, flags);
1175
1176 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1177 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1178
1179 spin_unlock_irqrestore(&vop->irq_lock, flags);
1180
1181 return 0;
1182}
1183
1184static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1185{
1186 struct vop *vop = to_vop(crtc);
1187 unsigned long flags;
1188
1189 if (WARN_ON(!vop->is_enabled))
1190 return;
1191
1192 spin_lock_irqsave(&vop->irq_lock, flags);
1193
1194 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1195
1196 spin_unlock_irqrestore(&vop->irq_lock, flags);
1197}
1198
1199static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
1200 const struct drm_display_mode *mode)
1201{
1202 struct vop *vop = to_vop(crtc);
1203
1204 if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width)
1205 return MODE_BAD_HVALUE;
1206
1207 return MODE_OK;
1208}
1209
1210static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1211 const struct drm_display_mode *mode,
1212 struct drm_display_mode *adjusted_mode)
1213{
1214 struct vop *vop = to_vop(crtc);
1215 unsigned long rate;
1216
1217 /*
1218 * Clock craziness.
1219 *
1220 * Key points:
1221 *
1222 * - DRM works in kHz.
1223 * - Clock framework works in Hz.
1224 * - Rockchip's clock driver picks the clock rate that is the
1225 * same _OR LOWER_ than the one requested.
1226 *
1227 * Action plan:
1228 *
1229 * 1. Try to set the exact rate first, and confirm the clock framework
1230 * can provide it.
1231 *
1232 * 2. If the clock framework cannot provide the exact rate, we should
1233 * add 999 Hz to the requested rate. That way if the clock we need
1234 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then
1235 * the clock framework will actually give us the right clock.
1236 *
1237 * 3. Get the clock framework to round the rate for us to tell us
1238 * what it will actually make.
1239 *
1240 * 4. Store the rounded up rate so that we don't need to worry about
1241 * this in the actual clk_set_rate().
1242 */
1243 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000);
1244 if (rate / 1000 != adjusted_mode->clock)
1245 rate = clk_round_rate(vop->dclk,
1246 adjusted_mode->clock * 1000 + 999);
1247 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000);
1248
1249 return true;
1250}
1251
1252static bool vop_dsp_lut_is_enabled(struct vop *vop)
1253{
1254 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1255}
1256
1257static u32 vop_lut_buffer_index(struct vop *vop)
1258{
1259 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);
1260}
1261
1262static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
1263{
1264 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
1265 unsigned int i, bpc = ilog2(vop->data->lut_size);
1266
1267 for (i = 0; i < crtc->gamma_size; i++) {
1268 u32 word;
1269
1270 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) |
1271 (drm_color_lut_extract(lut[i].green, bpc) << bpc) |
1272 drm_color_lut_extract(lut[i].blue, bpc);
1273 writel(word, vop->lut_regs + i * 4);
1274 }
1275}
1276
1277static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
1278 struct drm_crtc_state *old_state)
1279{
1280 struct drm_crtc_state *state = crtc->state;
1281 unsigned int idle;
1282 u32 lut_idx, old_idx;
1283 int ret;
1284
1285 if (!vop->lut_regs)
1286 return;
1287
1288 if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) {
1289 /*
1290 * To disable gamma (gamma_lut is null) or to write
1291 * an update to the LUT, clear dsp_lut_en.
1292 */
1293 spin_lock(&vop->reg_lock);
1294 VOP_REG_SET(vop, common, dsp_lut_en, 0);
1295 vop_cfg_done(vop);
1296 spin_unlock(&vop->reg_lock);
1297
1298 /*
1299 * In order to write the LUT to the internal memory,
1300 * we need to first make sure the dsp_lut_en bit is cleared.
1301 */
1302 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
1303 idle, !idle, 5, 30 * 1000);
1304 if (ret) {
1305 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
1306 return;
1307 }
1308
1309 if (!state->gamma_lut)
1310 return;
1311 } else {
1312 /*
1313 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en,
1314 * by setting update_gamma_lut then waiting for lut_buffer_index change
1315 */
1316 old_idx = vop_lut_buffer_index(vop);
1317 }
1318
1319 spin_lock(&vop->reg_lock);
1320 vop_crtc_write_gamma_lut(vop, crtc);
1321 VOP_REG_SET(vop, common, dsp_lut_en, 1);
1322 VOP_REG_SET(vop, common, update_gamma_lut, 1);
1323 vop_cfg_done(vop);
1324 spin_unlock(&vop->reg_lock);
1325
1326 if (VOP_HAS_REG(vop, common, update_gamma_lut)) {
1327 ret = readx_poll_timeout(vop_lut_buffer_index, vop,
1328 lut_idx, lut_idx != old_idx, 5, 30 * 1000);
1329 if (ret) {
1330 DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n");
1331 return;
1332 }
1333
1334 /*
1335 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit
1336 * in our backup of the regs.
1337 */
1338 spin_lock(&vop->reg_lock);
1339 VOP_REG_SET(vop, common, update_gamma_lut, 0);
1340 spin_unlock(&vop->reg_lock);
1341 }
1342}
1343
1344static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1345 struct drm_atomic_state *state)
1346{
1347 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1348 crtc);
1349 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1350 crtc);
1351 struct vop *vop = to_vop(crtc);
1352
1353 /*
1354 * Only update GAMMA if the 'active' flag is not changed,
1355 * otherwise it's updated by .atomic_enable.
1356 */
1357 if (crtc_state->color_mgmt_changed &&
1358 !crtc_state->active_changed)
1359 vop_crtc_gamma_set(vop, crtc, old_crtc_state);
1360}
1361
1362static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1363 struct drm_atomic_state *state)
1364{
1365 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
1366 crtc);
1367 struct vop *vop = to_vop(crtc);
1368 const struct vop_data *vop_data = vop->data;
1369 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1370 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1371 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1372 u16 hdisplay = adjusted_mode->hdisplay;
1373 u16 htotal = adjusted_mode->htotal;
1374 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1375 u16 hact_end = hact_st + hdisplay;
1376 u16 vdisplay = adjusted_mode->vdisplay;
1377 u16 vtotal = adjusted_mode->vtotal;
1378 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1379 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1380 u16 vact_end = vact_st + vdisplay;
1381 uint32_t pin_pol, val;
1382 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1383 int ret;
1384
1385 if (old_state && old_state->self_refresh_active) {
1386 drm_crtc_vblank_on(crtc);
1387 rockchip_drm_set_win_enabled(crtc, true);
1388 return;
1389 }
1390
1391 mutex_lock(&vop->vop_lock);
1392
1393 WARN_ON(vop->event);
1394
1395 ret = vop_enable(crtc, old_state);
1396 if (ret) {
1397 mutex_unlock(&vop->vop_lock);
1398 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1399 return;
1400 }
1401 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1402 BIT(HSYNC_POSITIVE) : 0;
1403 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1404 BIT(VSYNC_POSITIVE) : 0;
1405 VOP_REG_SET(vop, output, pin_pol, pin_pol);
1406 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1407
1408 switch (s->output_type) {
1409 case DRM_MODE_CONNECTOR_LVDS:
1410 VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
1411 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1412 VOP_REG_SET(vop, output, rgb_en, 1);
1413 break;
1414 case DRM_MODE_CONNECTOR_eDP:
1415 VOP_REG_SET(vop, output, edp_dclk_pol, 1);
1416 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1417 VOP_REG_SET(vop, output, edp_en, 1);
1418 break;
1419 case DRM_MODE_CONNECTOR_HDMIA:
1420 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
1421 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1422 VOP_REG_SET(vop, output, hdmi_en, 1);
1423 break;
1424 case DRM_MODE_CONNECTOR_DSI:
1425 VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
1426 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1427 VOP_REG_SET(vop, output, mipi_en, 1);
1428 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1429 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1430 break;
1431 case DRM_MODE_CONNECTOR_DisplayPort:
1432 VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1433 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1434 VOP_REG_SET(vop, output, dp_en, 1);
1435 break;
1436 default:
1437 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1438 s->output_type);
1439 }
1440
1441 /*
1442 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1443 */
1444 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1445 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1446 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1447
1448 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1449 VOP_REG_SET(vop, common, pre_dither_down, 1);
1450 else
1451 VOP_REG_SET(vop, common, pre_dither_down, 0);
1452
1453 if (dither_bpc == 6) {
1454 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1455 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1456 VOP_REG_SET(vop, common, dither_down_en, 1);
1457 } else {
1458 VOP_REG_SET(vop, common, dither_down_en, 0);
1459 }
1460
1461 VOP_REG_SET(vop, common, out_mode, s->output_mode);
1462
1463 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1464 val = hact_st << 16;
1465 val |= hact_end;
1466 VOP_REG_SET(vop, modeset, hact_st_end, val);
1467 VOP_REG_SET(vop, modeset, hpost_st_end, val);
1468
1469 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1470 val = vact_st << 16;
1471 val |= vact_end;
1472 VOP_REG_SET(vop, modeset, vact_st_end, val);
1473 VOP_REG_SET(vop, modeset, vpost_st_end, val);
1474
1475 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1476
1477 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1478
1479 VOP_REG_SET(vop, common, standby, 0);
1480 mutex_unlock(&vop->vop_lock);
1481
1482 /*
1483 * If we have a GAMMA LUT in the state, then let's make sure
1484 * it's updated. We might be coming out of suspend,
1485 * which means the LUT internal memory needs to be re-written.
1486 */
1487 if (crtc->state->gamma_lut)
1488 vop_crtc_gamma_set(vop, crtc, old_state);
1489}
1490
1491static bool vop_fs_irq_is_pending(struct vop *vop)
1492{
1493 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1494}
1495
1496static void vop_wait_for_irq_handler(struct vop *vop)
1497{
1498 bool pending;
1499 int ret;
1500
1501 /*
1502 * Spin until frame start interrupt status bit goes low, which means
1503 * that interrupt handler was invoked and cleared it. The timeout of
1504 * 10 msecs is really too long, but it is just a safety measure if
1505 * something goes really wrong. The wait will only happen in the very
1506 * unlikely case of a vblank happening exactly at the same time and
1507 * shouldn't exceed microseconds range.
1508 */
1509 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1510 !pending, 0, 10 * 1000);
1511 if (ret)
1512 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1513
1514 synchronize_irq(vop->irq);
1515}
1516
1517static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1518 struct drm_atomic_state *state)
1519{
1520 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1521 crtc);
1522 struct vop *vop = to_vop(crtc);
1523 struct drm_plane *plane;
1524 struct drm_plane_state *plane_state;
1525 struct rockchip_crtc_state *s;
1526 int afbc_planes = 0;
1527
1528 if (vop->lut_regs && crtc_state->color_mgmt_changed &&
1529 crtc_state->gamma_lut) {
1530 unsigned int len;
1531
1532 len = drm_color_lut_size(crtc_state->gamma_lut);
1533 if (len != crtc->gamma_size) {
1534 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1535 len, crtc->gamma_size);
1536 return -EINVAL;
1537 }
1538 }
1539
1540 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1541 plane_state =
1542 drm_atomic_get_plane_state(crtc_state->state, plane);
1543 if (IS_ERR(plane_state)) {
1544 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n",
1545 plane->name);
1546 return PTR_ERR(plane_state);
1547 }
1548
1549 if (drm_is_afbc(plane_state->fb->modifier))
1550 ++afbc_planes;
1551 }
1552
1553 if (afbc_planes > 1) {
1554 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes);
1555 return -EINVAL;
1556 }
1557
1558 s = to_rockchip_crtc_state(crtc_state);
1559 s->enable_afbc = afbc_planes > 0;
1560
1561 return 0;
1562}
1563
1564static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1565 struct drm_atomic_state *state)
1566{
1567 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1568 crtc);
1569 struct drm_atomic_state *old_state = old_crtc_state->state;
1570 struct drm_plane_state *old_plane_state, *new_plane_state;
1571 struct vop *vop = to_vop(crtc);
1572 struct drm_plane *plane;
1573 struct rockchip_crtc_state *s;
1574 int i;
1575
1576 if (WARN_ON(!vop->is_enabled))
1577 return;
1578
1579 spin_lock(&vop->reg_lock);
1580
1581 /* Enable AFBC if there is some AFBC window, disable otherwise. */
1582 s = to_rockchip_crtc_state(crtc->state);
1583 VOP_AFBC_SET(vop, enable, s->enable_afbc);
1584 vop_cfg_done(vop);
1585
1586 spin_unlock(&vop->reg_lock);
1587
1588 /*
1589 * There is a (rather unlikely) possiblity that a vblank interrupt
1590 * fired before we set the cfg_done bit. To avoid spuriously
1591 * signalling flip completion we need to wait for it to finish.
1592 */
1593 vop_wait_for_irq_handler(vop);
1594
1595 spin_lock_irq(&crtc->dev->event_lock);
1596 if (crtc->state->event) {
1597 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1598 WARN_ON(vop->event);
1599
1600 vop->event = crtc->state->event;
1601 crtc->state->event = NULL;
1602 }
1603 spin_unlock_irq(&crtc->dev->event_lock);
1604
1605 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1606 new_plane_state, i) {
1607 if (!old_plane_state->fb)
1608 continue;
1609
1610 if (old_plane_state->fb == new_plane_state->fb)
1611 continue;
1612
1613 drm_framebuffer_get(old_plane_state->fb);
1614 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1615 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1616 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1617 }
1618}
1619
1620static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1621 .mode_valid = vop_crtc_mode_valid,
1622 .mode_fixup = vop_crtc_mode_fixup,
1623 .atomic_check = vop_crtc_atomic_check,
1624 .atomic_begin = vop_crtc_atomic_begin,
1625 .atomic_flush = vop_crtc_atomic_flush,
1626 .atomic_enable = vop_crtc_atomic_enable,
1627 .atomic_disable = vop_crtc_atomic_disable,
1628};
1629
1630static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1631{
1632 struct rockchip_crtc_state *rockchip_state;
1633
1634 if (WARN_ON(!crtc->state))
1635 return NULL;
1636
1637 rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state),
1638 sizeof(*rockchip_state), GFP_KERNEL);
1639 if (!rockchip_state)
1640 return NULL;
1641
1642 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1643 return &rockchip_state->base;
1644}
1645
1646static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1647 struct drm_crtc_state *state)
1648{
1649 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1650
1651 __drm_atomic_helper_crtc_destroy_state(&s->base);
1652 kfree(s);
1653}
1654
1655static void vop_crtc_reset(struct drm_crtc *crtc)
1656{
1657 struct rockchip_crtc_state *crtc_state =
1658 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1659
1660 if (crtc->state)
1661 vop_crtc_destroy_state(crtc, crtc->state);
1662
1663 if (crtc_state)
1664 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1665 else
1666 __drm_atomic_helper_crtc_reset(crtc, NULL);
1667}
1668
1669#ifdef CONFIG_DRM_ANALOGIX_DP
1670static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1671{
1672 struct drm_connector *connector;
1673 struct drm_connector_list_iter conn_iter;
1674
1675 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1676 drm_for_each_connector_iter(connector, &conn_iter) {
1677 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1678 drm_connector_list_iter_end(&conn_iter);
1679 return connector;
1680 }
1681 }
1682 drm_connector_list_iter_end(&conn_iter);
1683
1684 return NULL;
1685}
1686
1687static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1688 const char *source_name)
1689{
1690 struct vop *vop = to_vop(crtc);
1691 struct drm_connector *connector;
1692 int ret;
1693
1694 connector = vop_get_edp_connector(vop);
1695 if (!connector)
1696 return -EINVAL;
1697
1698 if (source_name && strcmp(source_name, "auto") == 0)
1699 ret = analogix_dp_start_crc(connector);
1700 else if (!source_name)
1701 ret = analogix_dp_stop_crc(connector);
1702 else
1703 ret = -EINVAL;
1704
1705 return ret;
1706}
1707
1708static int
1709vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1710 size_t *values_cnt)
1711{
1712 if (source_name && strcmp(source_name, "auto") != 0)
1713 return -EINVAL;
1714
1715 *values_cnt = 3;
1716 return 0;
1717}
1718
1719#else
1720static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1721 const char *source_name)
1722{
1723 return -ENODEV;
1724}
1725
1726static int
1727vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1728 size_t *values_cnt)
1729{
1730 return -ENODEV;
1731}
1732#endif
1733
1734static const struct drm_crtc_funcs vop_crtc_funcs = {
1735 .set_config = drm_atomic_helper_set_config,
1736 .page_flip = drm_atomic_helper_page_flip,
1737 .destroy = drm_crtc_cleanup,
1738 .reset = vop_crtc_reset,
1739 .atomic_duplicate_state = vop_crtc_duplicate_state,
1740 .atomic_destroy_state = vop_crtc_destroy_state,
1741 .enable_vblank = vop_crtc_enable_vblank,
1742 .disable_vblank = vop_crtc_disable_vblank,
1743 .set_crc_source = vop_crtc_set_crc_source,
1744 .verify_crc_source = vop_crtc_verify_crc_source,
1745};
1746
1747static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1748{
1749 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1750 struct drm_framebuffer *fb = val;
1751
1752 drm_crtc_vblank_put(&vop->crtc);
1753 drm_framebuffer_put(fb);
1754}
1755
1756static void vop_handle_vblank(struct vop *vop)
1757{
1758 struct drm_device *drm = vop->drm_dev;
1759 struct drm_crtc *crtc = &vop->crtc;
1760
1761 spin_lock(&drm->event_lock);
1762 if (vop->event) {
1763 drm_crtc_send_vblank_event(crtc, vop->event);
1764 drm_crtc_vblank_put(crtc);
1765 vop->event = NULL;
1766 }
1767 spin_unlock(&drm->event_lock);
1768
1769 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1770 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1771}
1772
1773static irqreturn_t vop_isr(int irq, void *data)
1774{
1775 struct vop *vop = data;
1776 struct drm_crtc *crtc = &vop->crtc;
1777 uint32_t active_irqs;
1778 int ret = IRQ_NONE;
1779
1780 /*
1781 * The irq is shared with the iommu. If the runtime-pm state of the
1782 * vop-device is disabled the irq has to be targeted at the iommu.
1783 */
1784 if (!pm_runtime_get_if_in_use(vop->dev))
1785 return IRQ_NONE;
1786
1787 if (vop_core_clks_enable(vop)) {
1788 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1789 goto out;
1790 }
1791
1792 /*
1793 * interrupt register has interrupt status, enable and clear bits, we
1794 * must hold irq_lock to avoid a race with enable/disable_vblank().
1795 */
1796 spin_lock(&vop->irq_lock);
1797
1798 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1799 /* Clear all active interrupt sources */
1800 if (active_irqs)
1801 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1802
1803 spin_unlock(&vop->irq_lock);
1804
1805 /* This is expected for vop iommu irqs, since the irq is shared */
1806 if (!active_irqs)
1807 goto out_disable;
1808
1809 if (active_irqs & DSP_HOLD_VALID_INTR) {
1810 complete(&vop->dsp_hold_completion);
1811 active_irqs &= ~DSP_HOLD_VALID_INTR;
1812 ret = IRQ_HANDLED;
1813 }
1814
1815 if (active_irqs & LINE_FLAG_INTR) {
1816 complete(&vop->line_flag_completion);
1817 active_irqs &= ~LINE_FLAG_INTR;
1818 ret = IRQ_HANDLED;
1819 }
1820
1821 if (active_irqs & FS_INTR) {
1822 drm_crtc_handle_vblank(crtc);
1823 vop_handle_vblank(vop);
1824 active_irqs &= ~FS_INTR;
1825 ret = IRQ_HANDLED;
1826 }
1827
1828 /* Unhandled irqs are spurious. */
1829 if (active_irqs)
1830 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1831 active_irqs);
1832
1833out_disable:
1834 vop_core_clks_disable(vop);
1835out:
1836 pm_runtime_put(vop->dev);
1837 return ret;
1838}
1839
1840static void vop_plane_add_properties(struct drm_plane *plane,
1841 const struct vop_win_data *win_data)
1842{
1843 unsigned int flags = 0;
1844
1845 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1846 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1847 if (flags)
1848 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1849 DRM_MODE_ROTATE_0 | flags);
1850}
1851
1852static int vop_create_crtc(struct vop *vop)
1853{
1854 const struct vop_data *vop_data = vop->data;
1855 struct device *dev = vop->dev;
1856 struct drm_device *drm_dev = vop->drm_dev;
1857 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1858 struct drm_crtc *crtc = &vop->crtc;
1859 struct device_node *port;
1860 int ret;
1861 int i;
1862
1863 /*
1864 * Create drm_plane for primary and cursor planes first, since we need
1865 * to pass them to drm_crtc_init_with_planes, which sets the
1866 * "possible_crtcs" to the newly initialized crtc.
1867 */
1868 for (i = 0; i < vop_data->win_size; i++) {
1869 struct vop_win *vop_win = &vop->win[i];
1870 const struct vop_win_data *win_data = vop_win->data;
1871
1872 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1873 win_data->type != DRM_PLANE_TYPE_CURSOR)
1874 continue;
1875
1876 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1877 0, &vop_plane_funcs,
1878 win_data->phy->data_formats,
1879 win_data->phy->nformats,
1880 win_data->phy->format_modifiers,
1881 win_data->type, NULL);
1882 if (ret) {
1883 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1884 ret);
1885 goto err_cleanup_planes;
1886 }
1887
1888 plane = &vop_win->base;
1889 drm_plane_helper_add(plane, &plane_helper_funcs);
1890 vop_plane_add_properties(plane, win_data);
1891 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1892 primary = plane;
1893 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1894 cursor = plane;
1895 }
1896
1897 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1898 &vop_crtc_funcs, NULL);
1899 if (ret)
1900 goto err_cleanup_planes;
1901
1902 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1903 if (vop->lut_regs) {
1904 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size);
1905 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
1906 }
1907
1908 /*
1909 * Create drm_planes for overlay windows with possible_crtcs restricted
1910 * to the newly created crtc.
1911 */
1912 for (i = 0; i < vop_data->win_size; i++) {
1913 struct vop_win *vop_win = &vop->win[i];
1914 const struct vop_win_data *win_data = vop_win->data;
1915 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1916
1917 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1918 continue;
1919
1920 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1921 possible_crtcs,
1922 &vop_plane_funcs,
1923 win_data->phy->data_formats,
1924 win_data->phy->nformats,
1925 win_data->phy->format_modifiers,
1926 win_data->type, NULL);
1927 if (ret) {
1928 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1929 ret);
1930 goto err_cleanup_crtc;
1931 }
1932 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1933 vop_plane_add_properties(&vop_win->base, win_data);
1934 }
1935
1936 port = of_get_child_by_name(dev->of_node, "port");
1937 if (!port) {
1938 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1939 dev->of_node);
1940 ret = -ENOENT;
1941 goto err_cleanup_crtc;
1942 }
1943
1944 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1945 vop_fb_unref_worker);
1946
1947 init_completion(&vop->dsp_hold_completion);
1948 init_completion(&vop->line_flag_completion);
1949 crtc->port = port;
1950
1951 ret = drm_self_refresh_helper_init(crtc);
1952 if (ret)
1953 DRM_DEV_DEBUG_KMS(vop->dev,
1954 "Failed to init %s with SR helpers %d, ignoring\n",
1955 crtc->name, ret);
1956
1957 return 0;
1958
1959err_cleanup_crtc:
1960 drm_crtc_cleanup(crtc);
1961err_cleanup_planes:
1962 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1963 head)
1964 drm_plane_cleanup(plane);
1965 return ret;
1966}
1967
1968static void vop_destroy_crtc(struct vop *vop)
1969{
1970 struct drm_crtc *crtc = &vop->crtc;
1971 struct drm_device *drm_dev = vop->drm_dev;
1972 struct drm_plane *plane, *tmp;
1973
1974 drm_self_refresh_helper_cleanup(crtc);
1975
1976 of_node_put(crtc->port);
1977
1978 /*
1979 * We need to cleanup the planes now. Why?
1980 *
1981 * The planes are "&vop->win[i].base". That means the memory is
1982 * all part of the big "struct vop" chunk of memory. That memory
1983 * was devm allocated and associated with this component. We need to
1984 * free it ourselves before vop_unbind() finishes.
1985 */
1986 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1987 head)
1988 drm_plane_cleanup(plane);
1989
1990 /*
1991 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1992 * references the CRTC.
1993 */
1994 drm_crtc_cleanup(crtc);
1995 drm_flip_work_cleanup(&vop->fb_unref_work);
1996}
1997
1998static int vop_initial(struct vop *vop)
1999{
2000 struct reset_control *ahb_rst;
2001 int i, ret;
2002
2003 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2004 if (IS_ERR(vop->hclk)) {
2005 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
2006 return PTR_ERR(vop->hclk);
2007 }
2008 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2009 if (IS_ERR(vop->aclk)) {
2010 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
2011 return PTR_ERR(vop->aclk);
2012 }
2013 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2014 if (IS_ERR(vop->dclk)) {
2015 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
2016 return PTR_ERR(vop->dclk);
2017 }
2018
2019 ret = pm_runtime_resume_and_get(vop->dev);
2020 if (ret < 0) {
2021 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
2022 return ret;
2023 }
2024
2025 ret = clk_prepare(vop->dclk);
2026 if (ret < 0) {
2027 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
2028 goto err_put_pm_runtime;
2029 }
2030
2031 /* Enable both the hclk and aclk to setup the vop */
2032 ret = clk_prepare_enable(vop->hclk);
2033 if (ret < 0) {
2034 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
2035 goto err_unprepare_dclk;
2036 }
2037
2038 ret = clk_prepare_enable(vop->aclk);
2039 if (ret < 0) {
2040 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
2041 goto err_disable_hclk;
2042 }
2043
2044 /*
2045 * do hclk_reset, reset all vop registers.
2046 */
2047 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
2048 if (IS_ERR(ahb_rst)) {
2049 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
2050 ret = PTR_ERR(ahb_rst);
2051 goto err_disable_aclk;
2052 }
2053 reset_control_assert(ahb_rst);
2054 usleep_range(10, 20);
2055 reset_control_deassert(ahb_rst);
2056
2057 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
2058 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
2059
2060 for (i = 0; i < vop->len; i += sizeof(u32))
2061 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
2062
2063 VOP_REG_SET(vop, misc, global_regdone_en, 1);
2064 VOP_REG_SET(vop, common, dsp_blank, 0);
2065
2066 for (i = 0; i < vop->data->win_size; i++) {
2067 struct vop_win *vop_win = &vop->win[i];
2068 const struct vop_win_data *win = vop_win->data;
2069 int channel = i * 2 + 1;
2070
2071 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
2072 vop_win_disable(vop, vop_win);
2073 VOP_WIN_SET(vop, win, gate, 1);
2074 }
2075
2076 vop_cfg_done(vop);
2077
2078 /*
2079 * do dclk_reset, let all config take affect.
2080 */
2081 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
2082 if (IS_ERR(vop->dclk_rst)) {
2083 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
2084 ret = PTR_ERR(vop->dclk_rst);
2085 goto err_disable_aclk;
2086 }
2087 reset_control_assert(vop->dclk_rst);
2088 usleep_range(10, 20);
2089 reset_control_deassert(vop->dclk_rst);
2090
2091 clk_disable(vop->hclk);
2092 clk_disable(vop->aclk);
2093
2094 vop->is_enabled = false;
2095
2096 pm_runtime_put_sync(vop->dev);
2097
2098 return 0;
2099
2100err_disable_aclk:
2101 clk_disable_unprepare(vop->aclk);
2102err_disable_hclk:
2103 clk_disable_unprepare(vop->hclk);
2104err_unprepare_dclk:
2105 clk_unprepare(vop->dclk);
2106err_put_pm_runtime:
2107 pm_runtime_put_sync(vop->dev);
2108 return ret;
2109}
2110
2111/*
2112 * Initialize the vop->win array elements.
2113 */
2114static void vop_win_init(struct vop *vop)
2115{
2116 const struct vop_data *vop_data = vop->data;
2117 unsigned int i;
2118
2119 for (i = 0; i < vop_data->win_size; i++) {
2120 struct vop_win *vop_win = &vop->win[i];
2121 const struct vop_win_data *win_data = &vop_data->win[i];
2122
2123 vop_win->data = win_data;
2124 vop_win->vop = vop;
2125
2126 if (vop_data->win_yuv2yuv)
2127 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2128 }
2129}
2130
2131/**
2132 * rockchip_drm_wait_vact_end
2133 * @crtc: CRTC to enable line flag
2134 * @mstimeout: millisecond for timeout
2135 *
2136 * Wait for vact_end line flag irq or timeout.
2137 *
2138 * Returns:
2139 * Zero on success, negative errno on failure.
2140 */
2141int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
2142{
2143 struct vop *vop = to_vop(crtc);
2144 unsigned long jiffies_left;
2145 int ret = 0;
2146
2147 if (!crtc || !vop->is_enabled)
2148 return -ENODEV;
2149
2150 mutex_lock(&vop->vop_lock);
2151 if (mstimeout <= 0) {
2152 ret = -EINVAL;
2153 goto out;
2154 }
2155
2156 if (vop_line_flag_irq_is_enabled(vop)) {
2157 ret = -EBUSY;
2158 goto out;
2159 }
2160
2161 reinit_completion(&vop->line_flag_completion);
2162 vop_line_flag_irq_enable(vop);
2163
2164 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2165 msecs_to_jiffies(mstimeout));
2166 vop_line_flag_irq_disable(vop);
2167
2168 if (jiffies_left == 0) {
2169 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
2170 ret = -ETIMEDOUT;
2171 goto out;
2172 }
2173
2174out:
2175 mutex_unlock(&vop->vop_lock);
2176 return ret;
2177}
2178EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
2179
2180static int vop_bind(struct device *dev, struct device *master, void *data)
2181{
2182 struct platform_device *pdev = to_platform_device(dev);
2183 const struct vop_data *vop_data;
2184 struct drm_device *drm_dev = data;
2185 struct vop *vop;
2186 struct resource *res;
2187 int ret, irq;
2188
2189 vop_data = of_device_get_match_data(dev);
2190 if (!vop_data)
2191 return -ENODEV;
2192
2193 /* Allocate vop struct and its vop_win array */
2194 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
2195 GFP_KERNEL);
2196 if (!vop)
2197 return -ENOMEM;
2198
2199 vop->dev = dev;
2200 vop->data = vop_data;
2201 vop->drm_dev = drm_dev;
2202 dev_set_drvdata(dev, vop);
2203
2204 vop_win_init(vop);
2205
2206 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2207 vop->regs = devm_ioremap_resource(dev, res);
2208 if (IS_ERR(vop->regs))
2209 return PTR_ERR(vop->regs);
2210 vop->len = resource_size(res);
2211
2212 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2213 if (res) {
2214 if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) {
2215 DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size);
2216 return -EINVAL;
2217 }
2218 vop->lut_regs = devm_ioremap_resource(dev, res);
2219 if (IS_ERR(vop->lut_regs))
2220 return PTR_ERR(vop->lut_regs);
2221 }
2222
2223 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2224 if (!vop->regsbak)
2225 return -ENOMEM;
2226
2227 irq = platform_get_irq(pdev, 0);
2228 if (irq < 0) {
2229 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
2230 return irq;
2231 }
2232 vop->irq = (unsigned int)irq;
2233
2234 spin_lock_init(&vop->reg_lock);
2235 spin_lock_init(&vop->irq_lock);
2236 mutex_init(&vop->vop_lock);
2237
2238 ret = vop_create_crtc(vop);
2239 if (ret)
2240 return ret;
2241
2242 pm_runtime_enable(&pdev->dev);
2243
2244 ret = vop_initial(vop);
2245 if (ret < 0) {
2246 DRM_DEV_ERROR(&pdev->dev,
2247 "cannot initial vop dev - err %d\n", ret);
2248 goto err_disable_pm_runtime;
2249 }
2250
2251 ret = devm_request_irq(dev, vop->irq, vop_isr,
2252 IRQF_SHARED, dev_name(dev), vop);
2253 if (ret)
2254 goto err_disable_pm_runtime;
2255
2256 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
2257 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0);
2258 if (IS_ERR(vop->rgb)) {
2259 ret = PTR_ERR(vop->rgb);
2260 goto err_disable_pm_runtime;
2261 }
2262 }
2263
2264 rockchip_drm_dma_init_device(drm_dev, dev);
2265
2266 return 0;
2267
2268err_disable_pm_runtime:
2269 pm_runtime_disable(&pdev->dev);
2270 vop_destroy_crtc(vop);
2271 return ret;
2272}
2273
2274static void vop_unbind(struct device *dev, struct device *master, void *data)
2275{
2276 struct vop *vop = dev_get_drvdata(dev);
2277
2278 if (vop->rgb)
2279 rockchip_rgb_fini(vop->rgb);
2280
2281 pm_runtime_disable(dev);
2282 vop_destroy_crtc(vop);
2283
2284 clk_unprepare(vop->aclk);
2285 clk_unprepare(vop->hclk);
2286 clk_unprepare(vop->dclk);
2287}
2288
2289const struct component_ops vop_component_ops = {
2290 .bind = vop_bind,
2291 .unbind = vop_unbind,
2292};
2293EXPORT_SYMBOL_GPL(vop_component_ops);