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1/*
2 * linux/drivers/video/omap2/dss/dpi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DPI"
24
25#include <linux/kernel.h>
26#include <linux/delay.h>
27#include <linux/export.h>
28#include <linux/err.h>
29#include <linux/errno.h>
30#include <linux/platform_device.h>
31#include <linux/regulator/consumer.h>
32#include <linux/string.h>
33#include <linux/of.h>
34#include <linux/clk.h>
35#include <linux/component.h>
36
37#include <video/omapdss.h>
38
39#include "dss.h"
40#include "dss_features.h"
41
42#define HSDIV_DISPC 0
43
44struct dpi_data {
45 struct platform_device *pdev;
46
47 struct regulator *vdds_dsi_reg;
48 struct dss_pll *pll;
49
50 struct mutex lock;
51
52 struct omap_video_timings timings;
53 struct dss_lcd_mgr_config mgr_config;
54 int data_lines;
55
56 struct omap_dss_device output;
57
58 bool port_initialized;
59};
60
61static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev)
62{
63 return container_of(dssdev, struct dpi_data, output);
64}
65
66/* only used in non-DT mode */
67static struct dpi_data *dpi_get_data_from_pdev(struct platform_device *pdev)
68{
69 return dev_get_drvdata(&pdev->dev);
70}
71
72static struct dss_pll *dpi_get_pll(enum omap_channel channel)
73{
74 /*
75 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
76 * would also be used for DISPC fclk. Meaning, when the DPI output is
77 * disabled, DISPC clock will be disabled, and TV out will stop.
78 */
79 switch (omapdss_get_version()) {
80 case OMAPDSS_VER_OMAP24xx:
81 case OMAPDSS_VER_OMAP34xx_ES1:
82 case OMAPDSS_VER_OMAP34xx_ES3:
83 case OMAPDSS_VER_OMAP3630:
84 case OMAPDSS_VER_AM35xx:
85 case OMAPDSS_VER_AM43xx:
86 return NULL;
87
88 case OMAPDSS_VER_OMAP4430_ES1:
89 case OMAPDSS_VER_OMAP4430_ES2:
90 case OMAPDSS_VER_OMAP4:
91 switch (channel) {
92 case OMAP_DSS_CHANNEL_LCD:
93 return dss_pll_find("dsi0");
94 case OMAP_DSS_CHANNEL_LCD2:
95 return dss_pll_find("dsi1");
96 default:
97 return NULL;
98 }
99
100 case OMAPDSS_VER_OMAP5:
101 switch (channel) {
102 case OMAP_DSS_CHANNEL_LCD:
103 return dss_pll_find("dsi0");
104 case OMAP_DSS_CHANNEL_LCD3:
105 return dss_pll_find("dsi1");
106 default:
107 return NULL;
108 }
109
110 case OMAPDSS_VER_DRA7xx:
111 switch (channel) {
112 case OMAP_DSS_CHANNEL_LCD:
113 case OMAP_DSS_CHANNEL_LCD2:
114 return dss_pll_find("video0");
115 case OMAP_DSS_CHANNEL_LCD3:
116 return dss_pll_find("video1");
117 default:
118 return NULL;
119 }
120
121 default:
122 return NULL;
123 }
124}
125
126static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
127{
128 switch (channel) {
129 case OMAP_DSS_CHANNEL_LCD:
130 return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
131 case OMAP_DSS_CHANNEL_LCD2:
132 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
133 case OMAP_DSS_CHANNEL_LCD3:
134 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
135 default:
136 /* this shouldn't happen */
137 WARN_ON(1);
138 return OMAP_DSS_CLK_SRC_FCK;
139 }
140}
141
142struct dpi_clk_calc_ctx {
143 struct dss_pll *pll;
144
145 /* inputs */
146
147 unsigned long pck_min, pck_max;
148
149 /* outputs */
150
151 struct dss_pll_clock_info dsi_cinfo;
152 unsigned long fck;
153 struct dispc_clock_info dispc_cinfo;
154};
155
156static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
157 unsigned long pck, void *data)
158{
159 struct dpi_clk_calc_ctx *ctx = data;
160
161 /*
162 * Odd dividers give us uneven duty cycle, causing problem when level
163 * shifted. So skip all odd dividers when the pixel clock is on the
164 * higher side.
165 */
166 if (ctx->pck_min >= 100000000) {
167 if (lckd > 1 && lckd % 2 != 0)
168 return false;
169
170 if (pckd > 1 && pckd % 2 != 0)
171 return false;
172 }
173
174 ctx->dispc_cinfo.lck_div = lckd;
175 ctx->dispc_cinfo.pck_div = pckd;
176 ctx->dispc_cinfo.lck = lck;
177 ctx->dispc_cinfo.pck = pck;
178
179 return true;
180}
181
182
183static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
184 void *data)
185{
186 struct dpi_clk_calc_ctx *ctx = data;
187
188 /*
189 * Odd dividers give us uneven duty cycle, causing problem when level
190 * shifted. So skip all odd dividers when the pixel clock is on the
191 * higher side.
192 */
193 if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000)
194 return false;
195
196 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
197 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
198
199 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
200 dpi_calc_dispc_cb, ctx);
201}
202
203
204static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
205 unsigned long clkdco,
206 void *data)
207{
208 struct dpi_clk_calc_ctx *ctx = data;
209
210 ctx->dsi_cinfo.n = n;
211 ctx->dsi_cinfo.m = m;
212 ctx->dsi_cinfo.fint = fint;
213 ctx->dsi_cinfo.clkdco = clkdco;
214
215 return dss_pll_hsdiv_calc(ctx->pll, clkdco,
216 ctx->pck_min, dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
217 dpi_calc_hsdiv_cb, ctx);
218}
219
220static bool dpi_calc_dss_cb(unsigned long fck, void *data)
221{
222 struct dpi_clk_calc_ctx *ctx = data;
223
224 ctx->fck = fck;
225
226 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
227 dpi_calc_dispc_cb, ctx);
228}
229
230static bool dpi_dsi_clk_calc(struct dpi_data *dpi, unsigned long pck,
231 struct dpi_clk_calc_ctx *ctx)
232{
233 unsigned long clkin;
234 unsigned long pll_min, pll_max;
235
236 memset(ctx, 0, sizeof(*ctx));
237 ctx->pll = dpi->pll;
238 ctx->pck_min = pck - 1000;
239 ctx->pck_max = pck + 1000;
240
241 pll_min = 0;
242 pll_max = 0;
243
244 clkin = clk_get_rate(ctx->pll->clkin);
245
246 return dss_pll_calc(ctx->pll, clkin,
247 pll_min, pll_max,
248 dpi_calc_pll_cb, ctx);
249}
250
251static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
252{
253 int i;
254
255 /*
256 * DSS fck gives us very few possibilities, so finding a good pixel
257 * clock may not be possible. We try multiple times to find the clock,
258 * each time widening the pixel clock range we look for, up to
259 * +/- ~15MHz.
260 */
261
262 for (i = 0; i < 25; ++i) {
263 bool ok;
264
265 memset(ctx, 0, sizeof(*ctx));
266 if (pck > 1000 * i * i * i)
267 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
268 else
269 ctx->pck_min = 0;
270 ctx->pck_max = pck + 1000 * i * i * i;
271
272 ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx);
273 if (ok)
274 return ok;
275 }
276
277 return false;
278}
279
280
281
282static int dpi_set_dsi_clk(struct dpi_data *dpi, enum omap_channel channel,
283 unsigned long pck_req, unsigned long *fck, int *lck_div,
284 int *pck_div)
285{
286 struct dpi_clk_calc_ctx ctx;
287 int r;
288 bool ok;
289
290 ok = dpi_dsi_clk_calc(dpi, pck_req, &ctx);
291 if (!ok)
292 return -EINVAL;
293
294 r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo);
295 if (r)
296 return r;
297
298 dss_select_lcd_clk_source(channel,
299 dpi_get_alt_clk_src(channel));
300
301 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
302
303 *fck = ctx.dsi_cinfo.clkout[HSDIV_DISPC];
304 *lck_div = ctx.dispc_cinfo.lck_div;
305 *pck_div = ctx.dispc_cinfo.pck_div;
306
307 return 0;
308}
309
310static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req,
311 unsigned long *fck, int *lck_div, int *pck_div)
312{
313 struct dpi_clk_calc_ctx ctx;
314 int r;
315 bool ok;
316
317 ok = dpi_dss_clk_calc(pck_req, &ctx);
318 if (!ok)
319 return -EINVAL;
320
321 r = dss_set_fck_rate(ctx.fck);
322 if (r)
323 return r;
324
325 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
326
327 *fck = ctx.fck;
328 *lck_div = ctx.dispc_cinfo.lck_div;
329 *pck_div = ctx.dispc_cinfo.pck_div;
330
331 return 0;
332}
333
334static int dpi_set_mode(struct dpi_data *dpi)
335{
336 struct omap_dss_device *out = &dpi->output;
337 enum omap_channel channel = out->dispc_channel;
338 struct omap_video_timings *t = &dpi->timings;
339 int lck_div = 0, pck_div = 0;
340 unsigned long fck = 0;
341 unsigned long pck;
342 int r = 0;
343
344 if (dpi->pll)
345 r = dpi_set_dsi_clk(dpi, channel, t->pixelclock, &fck,
346 &lck_div, &pck_div);
347 else
348 r = dpi_set_dispc_clk(dpi, t->pixelclock, &fck,
349 &lck_div, &pck_div);
350 if (r)
351 return r;
352
353 pck = fck / lck_div / pck_div;
354
355 if (pck != t->pixelclock) {
356 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
357 t->pixelclock, pck);
358
359 t->pixelclock = pck;
360 }
361
362 dss_mgr_set_timings(channel, t);
363
364 return 0;
365}
366
367static void dpi_config_lcd_manager(struct dpi_data *dpi)
368{
369 struct omap_dss_device *out = &dpi->output;
370 enum omap_channel channel = out->dispc_channel;
371
372 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
373
374 dpi->mgr_config.stallmode = false;
375 dpi->mgr_config.fifohandcheck = false;
376
377 dpi->mgr_config.video_port_width = dpi->data_lines;
378
379 dpi->mgr_config.lcden_sig_polarity = 0;
380
381 dss_mgr_set_lcd_config(channel, &dpi->mgr_config);
382}
383
384static int dpi_display_enable(struct omap_dss_device *dssdev)
385{
386 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
387 struct omap_dss_device *out = &dpi->output;
388 enum omap_channel channel = out->dispc_channel;
389 int r;
390
391 mutex_lock(&dpi->lock);
392
393 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi->vdds_dsi_reg) {
394 DSSERR("no VDSS_DSI regulator\n");
395 r = -ENODEV;
396 goto err_no_reg;
397 }
398
399 if (!out->dispc_channel_connected) {
400 DSSERR("failed to enable display: no output/manager\n");
401 r = -ENODEV;
402 goto err_no_out_mgr;
403 }
404
405 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) {
406 r = regulator_enable(dpi->vdds_dsi_reg);
407 if (r)
408 goto err_reg_enable;
409 }
410
411 r = dispc_runtime_get();
412 if (r)
413 goto err_get_dispc;
414
415 r = dss_dpi_select_source(out->port_num, channel);
416 if (r)
417 goto err_src_sel;
418
419 if (dpi->pll) {
420 r = dss_pll_enable(dpi->pll);
421 if (r)
422 goto err_dsi_pll_init;
423 }
424
425 r = dpi_set_mode(dpi);
426 if (r)
427 goto err_set_mode;
428
429 dpi_config_lcd_manager(dpi);
430
431 mdelay(2);
432
433 r = dss_mgr_enable(channel);
434 if (r)
435 goto err_mgr_enable;
436
437 mutex_unlock(&dpi->lock);
438
439 return 0;
440
441err_mgr_enable:
442err_set_mode:
443 if (dpi->pll)
444 dss_pll_disable(dpi->pll);
445err_dsi_pll_init:
446err_src_sel:
447 dispc_runtime_put();
448err_get_dispc:
449 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
450 regulator_disable(dpi->vdds_dsi_reg);
451err_reg_enable:
452err_no_out_mgr:
453err_no_reg:
454 mutex_unlock(&dpi->lock);
455 return r;
456}
457
458static void dpi_display_disable(struct omap_dss_device *dssdev)
459{
460 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
461 enum omap_channel channel = dpi->output.dispc_channel;
462
463 mutex_lock(&dpi->lock);
464
465 dss_mgr_disable(channel);
466
467 if (dpi->pll) {
468 dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK);
469 dss_pll_disable(dpi->pll);
470 }
471
472 dispc_runtime_put();
473
474 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
475 regulator_disable(dpi->vdds_dsi_reg);
476
477 mutex_unlock(&dpi->lock);
478}
479
480static void dpi_set_timings(struct omap_dss_device *dssdev,
481 struct omap_video_timings *timings)
482{
483 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
484
485 DSSDBG("dpi_set_timings\n");
486
487 mutex_lock(&dpi->lock);
488
489 dpi->timings = *timings;
490
491 mutex_unlock(&dpi->lock);
492}
493
494static void dpi_get_timings(struct omap_dss_device *dssdev,
495 struct omap_video_timings *timings)
496{
497 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
498
499 mutex_lock(&dpi->lock);
500
501 *timings = dpi->timings;
502
503 mutex_unlock(&dpi->lock);
504}
505
506static int dpi_check_timings(struct omap_dss_device *dssdev,
507 struct omap_video_timings *timings)
508{
509 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
510 enum omap_channel channel = dpi->output.dispc_channel;
511 int lck_div, pck_div;
512 unsigned long fck;
513 unsigned long pck;
514 struct dpi_clk_calc_ctx ctx;
515 bool ok;
516
517 if (timings->x_res % 8 != 0)
518 return -EINVAL;
519
520 if (!dispc_mgr_timings_ok(channel, timings))
521 return -EINVAL;
522
523 if (timings->pixelclock == 0)
524 return -EINVAL;
525
526 if (dpi->pll) {
527 ok = dpi_dsi_clk_calc(dpi, timings->pixelclock, &ctx);
528 if (!ok)
529 return -EINVAL;
530
531 fck = ctx.dsi_cinfo.clkout[HSDIV_DISPC];
532 } else {
533 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx);
534 if (!ok)
535 return -EINVAL;
536
537 fck = ctx.fck;
538 }
539
540 lck_div = ctx.dispc_cinfo.lck_div;
541 pck_div = ctx.dispc_cinfo.pck_div;
542
543 pck = fck / lck_div / pck_div;
544
545 timings->pixelclock = pck;
546
547 return 0;
548}
549
550static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
551{
552 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
553
554 mutex_lock(&dpi->lock);
555
556 dpi->data_lines = data_lines;
557
558 mutex_unlock(&dpi->lock);
559}
560
561static int dpi_verify_dsi_pll(struct dss_pll *pll)
562{
563 int r;
564
565 /* do initial setup with the PLL to see if it is operational */
566
567 r = dss_pll_enable(pll);
568 if (r)
569 return r;
570
571 dss_pll_disable(pll);
572
573 return 0;
574}
575
576static int dpi_init_regulator(struct dpi_data *dpi)
577{
578 struct regulator *vdds_dsi;
579
580 if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
581 return 0;
582
583 if (dpi->vdds_dsi_reg)
584 return 0;
585
586 vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi");
587 if (IS_ERR(vdds_dsi)) {
588 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
589 DSSERR("can't get VDDS_DSI regulator\n");
590 return PTR_ERR(vdds_dsi);
591 }
592
593 dpi->vdds_dsi_reg = vdds_dsi;
594
595 return 0;
596}
597
598static void dpi_init_pll(struct dpi_data *dpi)
599{
600 struct dss_pll *pll;
601
602 if (dpi->pll)
603 return;
604
605 pll = dpi_get_pll(dpi->output.dispc_channel);
606 if (!pll)
607 return;
608
609 /* On DRA7 we need to set a mux to use the PLL */
610 if (omapdss_get_version() == OMAPDSS_VER_DRA7xx)
611 dss_ctrl_pll_set_control_mux(pll->id, dpi->output.dispc_channel);
612
613 if (dpi_verify_dsi_pll(pll)) {
614 DSSWARN("DSI PLL not operational\n");
615 return;
616 }
617
618 dpi->pll = pll;
619}
620
621/*
622 * Return a hardcoded channel for the DPI output. This should work for
623 * current use cases, but this can be later expanded to either resolve
624 * the channel in some more dynamic manner, or get the channel as a user
625 * parameter.
626 */
627static enum omap_channel dpi_get_channel(int port_num)
628{
629 switch (omapdss_get_version()) {
630 case OMAPDSS_VER_OMAP24xx:
631 case OMAPDSS_VER_OMAP34xx_ES1:
632 case OMAPDSS_VER_OMAP34xx_ES3:
633 case OMAPDSS_VER_OMAP3630:
634 case OMAPDSS_VER_AM35xx:
635 case OMAPDSS_VER_AM43xx:
636 return OMAP_DSS_CHANNEL_LCD;
637
638 case OMAPDSS_VER_DRA7xx:
639 switch (port_num) {
640 case 2:
641 return OMAP_DSS_CHANNEL_LCD3;
642 case 1:
643 return OMAP_DSS_CHANNEL_LCD2;
644 case 0:
645 default:
646 return OMAP_DSS_CHANNEL_LCD;
647 }
648
649 case OMAPDSS_VER_OMAP4430_ES1:
650 case OMAPDSS_VER_OMAP4430_ES2:
651 case OMAPDSS_VER_OMAP4:
652 return OMAP_DSS_CHANNEL_LCD2;
653
654 case OMAPDSS_VER_OMAP5:
655 return OMAP_DSS_CHANNEL_LCD3;
656
657 default:
658 DSSWARN("unsupported DSS version\n");
659 return OMAP_DSS_CHANNEL_LCD;
660 }
661}
662
663static int dpi_connect(struct omap_dss_device *dssdev,
664 struct omap_dss_device *dst)
665{
666 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
667 enum omap_channel channel = dpi->output.dispc_channel;
668 int r;
669
670 r = dpi_init_regulator(dpi);
671 if (r)
672 return r;
673
674 dpi_init_pll(dpi);
675
676 r = dss_mgr_connect(channel, dssdev);
677 if (r)
678 return r;
679
680 r = omapdss_output_set_device(dssdev, dst);
681 if (r) {
682 DSSERR("failed to connect output to new device: %s\n",
683 dst->name);
684 dss_mgr_disconnect(channel, dssdev);
685 return r;
686 }
687
688 return 0;
689}
690
691static void dpi_disconnect(struct omap_dss_device *dssdev,
692 struct omap_dss_device *dst)
693{
694 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
695 enum omap_channel channel = dpi->output.dispc_channel;
696
697 WARN_ON(dst != dssdev->dst);
698
699 if (dst != dssdev->dst)
700 return;
701
702 omapdss_output_unset_device(dssdev);
703
704 dss_mgr_disconnect(channel, dssdev);
705}
706
707static const struct omapdss_dpi_ops dpi_ops = {
708 .connect = dpi_connect,
709 .disconnect = dpi_disconnect,
710
711 .enable = dpi_display_enable,
712 .disable = dpi_display_disable,
713
714 .check_timings = dpi_check_timings,
715 .set_timings = dpi_set_timings,
716 .get_timings = dpi_get_timings,
717
718 .set_data_lines = dpi_set_data_lines,
719};
720
721static void dpi_init_output(struct platform_device *pdev)
722{
723 struct dpi_data *dpi = dpi_get_data_from_pdev(pdev);
724 struct omap_dss_device *out = &dpi->output;
725
726 out->dev = &pdev->dev;
727 out->id = OMAP_DSS_OUTPUT_DPI;
728 out->output_type = OMAP_DISPLAY_TYPE_DPI;
729 out->name = "dpi.0";
730 out->dispc_channel = dpi_get_channel(0);
731 out->ops.dpi = &dpi_ops;
732 out->owner = THIS_MODULE;
733
734 omapdss_register_output(out);
735}
736
737static void dpi_uninit_output(struct platform_device *pdev)
738{
739 struct dpi_data *dpi = dpi_get_data_from_pdev(pdev);
740 struct omap_dss_device *out = &dpi->output;
741
742 omapdss_unregister_output(out);
743}
744
745static void dpi_init_output_port(struct platform_device *pdev,
746 struct device_node *port)
747{
748 struct dpi_data *dpi = port->data;
749 struct omap_dss_device *out = &dpi->output;
750 int r;
751 u32 port_num;
752
753 r = of_property_read_u32(port, "reg", &port_num);
754 if (r)
755 port_num = 0;
756
757 switch (port_num) {
758 case 2:
759 out->name = "dpi.2";
760 break;
761 case 1:
762 out->name = "dpi.1";
763 break;
764 case 0:
765 default:
766 out->name = "dpi.0";
767 break;
768 }
769
770 out->dev = &pdev->dev;
771 out->id = OMAP_DSS_OUTPUT_DPI;
772 out->output_type = OMAP_DISPLAY_TYPE_DPI;
773 out->dispc_channel = dpi_get_channel(port_num);
774 out->port_num = port_num;
775 out->ops.dpi = &dpi_ops;
776 out->owner = THIS_MODULE;
777
778 omapdss_register_output(out);
779}
780
781static void dpi_uninit_output_port(struct device_node *port)
782{
783 struct dpi_data *dpi = port->data;
784 struct omap_dss_device *out = &dpi->output;
785
786 omapdss_unregister_output(out);
787}
788
789static int dpi_bind(struct device *dev, struct device *master, void *data)
790{
791 struct platform_device *pdev = to_platform_device(dev);
792 struct dpi_data *dpi;
793
794 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
795 if (!dpi)
796 return -ENOMEM;
797
798 dpi->pdev = pdev;
799
800 dev_set_drvdata(&pdev->dev, dpi);
801
802 mutex_init(&dpi->lock);
803
804 dpi_init_output(pdev);
805
806 return 0;
807}
808
809static void dpi_unbind(struct device *dev, struct device *master, void *data)
810{
811 struct platform_device *pdev = to_platform_device(dev);
812
813 dpi_uninit_output(pdev);
814}
815
816static const struct component_ops dpi_component_ops = {
817 .bind = dpi_bind,
818 .unbind = dpi_unbind,
819};
820
821static int dpi_probe(struct platform_device *pdev)
822{
823 return component_add(&pdev->dev, &dpi_component_ops);
824}
825
826static int dpi_remove(struct platform_device *pdev)
827{
828 component_del(&pdev->dev, &dpi_component_ops);
829 return 0;
830}
831
832static struct platform_driver omap_dpi_driver = {
833 .probe = dpi_probe,
834 .remove = dpi_remove,
835 .driver = {
836 .name = "omapdss_dpi",
837 .suppress_bind_attrs = true,
838 },
839};
840
841int __init dpi_init_platform_driver(void)
842{
843 return platform_driver_register(&omap_dpi_driver);
844}
845
846void dpi_uninit_platform_driver(void)
847{
848 platform_driver_unregister(&omap_dpi_driver);
849}
850
851int dpi_init_port(struct platform_device *pdev, struct device_node *port)
852{
853 struct dpi_data *dpi;
854 struct device_node *ep;
855 u32 datalines;
856 int r;
857
858 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
859 if (!dpi)
860 return -ENOMEM;
861
862 ep = omapdss_of_get_next_endpoint(port, NULL);
863 if (!ep)
864 return 0;
865
866 r = of_property_read_u32(ep, "data-lines", &datalines);
867 if (r) {
868 DSSERR("failed to parse datalines\n");
869 goto err_datalines;
870 }
871
872 dpi->data_lines = datalines;
873
874 of_node_put(ep);
875
876 dpi->pdev = pdev;
877 port->data = dpi;
878
879 mutex_init(&dpi->lock);
880
881 dpi_init_output_port(pdev, port);
882
883 dpi->port_initialized = true;
884
885 return 0;
886
887err_datalines:
888 of_node_put(ep);
889
890 return r;
891}
892
893void dpi_uninit_port(struct device_node *port)
894{
895 struct dpi_data *dpi = port->data;
896
897 if (!dpi->port_initialized)
898 return;
899
900 dpi_uninit_output_port(port);
901}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 *
6 * Some code and ideas taken from drivers/video/omap/ driver
7 * by Imre Deak.
8 */
9
10#define DSS_SUBSYS_NAME "DPI"
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/errno.h>
16#include <linux/export.h>
17#include <linux/kernel.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/consumer.h>
21#include <linux/string.h>
22#include <linux/sys_soc.h>
23
24#include <drm/drm_bridge.h>
25
26#include "dss.h"
27#include "omapdss.h"
28
29struct dpi_data {
30 struct platform_device *pdev;
31 enum dss_model dss_model;
32 struct dss_device *dss;
33 unsigned int id;
34
35 struct regulator *vdds_dsi_reg;
36 enum dss_clk_source clk_src;
37 struct dss_pll *pll;
38
39 struct dss_lcd_mgr_config mgr_config;
40 unsigned long pixelclock;
41 int data_lines;
42
43 struct omap_dss_device output;
44 struct drm_bridge bridge;
45};
46
47#define drm_bridge_to_dpi(bridge) container_of(bridge, struct dpi_data, bridge)
48
49/* -----------------------------------------------------------------------------
50 * Clock Handling and PLL
51 */
52
53static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi,
54 enum omap_channel channel)
55{
56 /*
57 * Possible clock sources:
58 * LCD1: FCK/PLL1_1/HDMI_PLL
59 * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3)
60 * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1)
61 */
62
63 switch (channel) {
64 case OMAP_DSS_CHANNEL_LCD:
65 {
66 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1))
67 return DSS_CLK_SRC_PLL1_1;
68 break;
69 }
70 case OMAP_DSS_CHANNEL_LCD2:
71 {
72 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
73 return DSS_CLK_SRC_PLL1_3;
74 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3))
75 return DSS_CLK_SRC_PLL2_3;
76 break;
77 }
78 case OMAP_DSS_CHANNEL_LCD3:
79 {
80 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1))
81 return DSS_CLK_SRC_PLL2_1;
82 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
83 return DSS_CLK_SRC_PLL1_3;
84 break;
85 }
86 default:
87 break;
88 }
89
90 return DSS_CLK_SRC_FCK;
91}
92
93static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi)
94{
95 enum omap_channel channel = dpi->output.dispc_channel;
96
97 /*
98 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
99 * would also be used for DISPC fclk. Meaning, when the DPI output is
100 * disabled, DISPC clock will be disabled, and TV out will stop.
101 */
102 switch (dpi->dss_model) {
103 case DSS_MODEL_OMAP2:
104 case DSS_MODEL_OMAP3:
105 return DSS_CLK_SRC_FCK;
106
107 case DSS_MODEL_OMAP4:
108 switch (channel) {
109 case OMAP_DSS_CHANNEL_LCD:
110 return DSS_CLK_SRC_PLL1_1;
111 case OMAP_DSS_CHANNEL_LCD2:
112 return DSS_CLK_SRC_PLL2_1;
113 default:
114 return DSS_CLK_SRC_FCK;
115 }
116
117 case DSS_MODEL_OMAP5:
118 switch (channel) {
119 case OMAP_DSS_CHANNEL_LCD:
120 return DSS_CLK_SRC_PLL1_1;
121 case OMAP_DSS_CHANNEL_LCD3:
122 return DSS_CLK_SRC_PLL2_1;
123 case OMAP_DSS_CHANNEL_LCD2:
124 default:
125 return DSS_CLK_SRC_FCK;
126 }
127
128 case DSS_MODEL_DRA7:
129 return dpi_get_clk_src_dra7xx(dpi, channel);
130
131 default:
132 return DSS_CLK_SRC_FCK;
133 }
134}
135
136struct dpi_clk_calc_ctx {
137 struct dpi_data *dpi;
138 unsigned int clkout_idx;
139
140 /* inputs */
141
142 unsigned long pck_min, pck_max;
143
144 /* outputs */
145
146 struct dss_pll_clock_info pll_cinfo;
147 unsigned long fck;
148 struct dispc_clock_info dispc_cinfo;
149};
150
151static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
152 unsigned long pck, void *data)
153{
154 struct dpi_clk_calc_ctx *ctx = data;
155
156 /*
157 * Odd dividers give us uneven duty cycle, causing problem when level
158 * shifted. So skip all odd dividers when the pixel clock is on the
159 * higher side.
160 */
161 if (ctx->pck_min >= 100000000) {
162 if (lckd > 1 && lckd % 2 != 0)
163 return false;
164
165 if (pckd > 1 && pckd % 2 != 0)
166 return false;
167 }
168
169 ctx->dispc_cinfo.lck_div = lckd;
170 ctx->dispc_cinfo.pck_div = pckd;
171 ctx->dispc_cinfo.lck = lck;
172 ctx->dispc_cinfo.pck = pck;
173
174 return true;
175}
176
177
178static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
179 void *data)
180{
181 struct dpi_clk_calc_ctx *ctx = data;
182
183 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc;
184 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;
185
186 return dispc_div_calc(ctx->dpi->dss->dispc, dispc,
187 ctx->pck_min, ctx->pck_max,
188 dpi_calc_dispc_cb, ctx);
189}
190
191
192static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
193 unsigned long clkdco,
194 void *data)
195{
196 struct dpi_clk_calc_ctx *ctx = data;
197
198 ctx->pll_cinfo.n = n;
199 ctx->pll_cinfo.m = m;
200 ctx->pll_cinfo.fint = fint;
201 ctx->pll_cinfo.clkdco = clkdco;
202
203 return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco,
204 ctx->pck_min, dss_get_max_fck_rate(ctx->dpi->dss),
205 dpi_calc_hsdiv_cb, ctx);
206}
207
208static bool dpi_calc_dss_cb(unsigned long fck, void *data)
209{
210 struct dpi_clk_calc_ctx *ctx = data;
211
212 ctx->fck = fck;
213
214 return dispc_div_calc(ctx->dpi->dss->dispc, fck,
215 ctx->pck_min, ctx->pck_max,
216 dpi_calc_dispc_cb, ctx);
217}
218
219static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck,
220 struct dpi_clk_calc_ctx *ctx)
221{
222 unsigned long clkin;
223
224 memset(ctx, 0, sizeof(*ctx));
225 ctx->dpi = dpi;
226 ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src);
227
228 clkin = clk_get_rate(dpi->pll->clkin);
229
230 if (dpi->pll->hw->type == DSS_PLL_TYPE_A) {
231 unsigned long pll_min, pll_max;
232
233 ctx->pck_min = pck - 1000;
234 ctx->pck_max = pck + 1000;
235
236 pll_min = 0;
237 pll_max = 0;
238
239 return dss_pll_calc_a(ctx->dpi->pll, clkin,
240 pll_min, pll_max,
241 dpi_calc_pll_cb, ctx);
242 } else { /* DSS_PLL_TYPE_B */
243 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo);
244
245 ctx->dispc_cinfo.lck_div = 1;
246 ctx->dispc_cinfo.pck_div = 1;
247 ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0];
248 ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck;
249
250 return true;
251 }
252}
253
254static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck,
255 struct dpi_clk_calc_ctx *ctx)
256{
257 int i;
258
259 /*
260 * DSS fck gives us very few possibilities, so finding a good pixel
261 * clock may not be possible. We try multiple times to find the clock,
262 * each time widening the pixel clock range we look for, up to
263 * +/- ~15MHz.
264 */
265
266 for (i = 0; i < 25; ++i) {
267 bool ok;
268
269 memset(ctx, 0, sizeof(*ctx));
270 ctx->dpi = dpi;
271 if (pck > 1000 * i * i * i)
272 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
273 else
274 ctx->pck_min = 0;
275 ctx->pck_max = pck + 1000 * i * i * i;
276
277 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min,
278 dpi_calc_dss_cb, ctx);
279 if (ok)
280 return ok;
281 }
282
283 return false;
284}
285
286
287
288static int dpi_set_pll_clk(struct dpi_data *dpi, unsigned long pck_req)
289{
290 struct dpi_clk_calc_ctx ctx;
291 int r;
292 bool ok;
293
294 ok = dpi_pll_clk_calc(dpi, pck_req, &ctx);
295 if (!ok)
296 return -EINVAL;
297
298 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo);
299 if (r)
300 return r;
301
302 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
303 dpi->clk_src);
304
305 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
306
307 return 0;
308}
309
310static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req)
311{
312 struct dpi_clk_calc_ctx ctx;
313 int r;
314 bool ok;
315
316 ok = dpi_dss_clk_calc(dpi, pck_req, &ctx);
317 if (!ok)
318 return -EINVAL;
319
320 r = dss_set_fck_rate(dpi->dss, ctx.fck);
321 if (r)
322 return r;
323
324 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
325
326 return 0;
327}
328
329static int dpi_set_mode(struct dpi_data *dpi)
330{
331 int r;
332
333 if (dpi->pll)
334 r = dpi_set_pll_clk(dpi, dpi->pixelclock);
335 else
336 r = dpi_set_dispc_clk(dpi, dpi->pixelclock);
337
338 return r;
339}
340
341static void dpi_config_lcd_manager(struct dpi_data *dpi)
342{
343 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
344
345 dpi->mgr_config.stallmode = false;
346 dpi->mgr_config.fifohandcheck = false;
347
348 dpi->mgr_config.video_port_width = dpi->data_lines;
349
350 dpi->mgr_config.lcden_sig_polarity = 0;
351
352 dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config);
353}
354
355static int dpi_clock_update(struct dpi_data *dpi, unsigned long *clock)
356{
357 int lck_div, pck_div;
358 unsigned long fck;
359 struct dpi_clk_calc_ctx ctx;
360
361 if (dpi->pll) {
362 if (!dpi_pll_clk_calc(dpi, *clock, &ctx))
363 return -EINVAL;
364
365 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
366 } else {
367 if (!dpi_dss_clk_calc(dpi, *clock, &ctx))
368 return -EINVAL;
369
370 fck = ctx.fck;
371 }
372
373 lck_div = ctx.dispc_cinfo.lck_div;
374 pck_div = ctx.dispc_cinfo.pck_div;
375
376 *clock = fck / lck_div / pck_div;
377
378 return 0;
379}
380
381static int dpi_verify_pll(struct dss_pll *pll)
382{
383 int r;
384
385 /* do initial setup with the PLL to see if it is operational */
386
387 r = dss_pll_enable(pll);
388 if (r)
389 return r;
390
391 dss_pll_disable(pll);
392
393 return 0;
394}
395
396static void dpi_init_pll(struct dpi_data *dpi)
397{
398 struct dss_pll *pll;
399
400 if (dpi->pll)
401 return;
402
403 dpi->clk_src = dpi_get_clk_src(dpi);
404
405 pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src);
406 if (!pll)
407 return;
408
409 if (dpi_verify_pll(pll)) {
410 DSSWARN("PLL not operational\n");
411 return;
412 }
413
414 dpi->pll = pll;
415}
416
417/* -----------------------------------------------------------------------------
418 * DRM Bridge Operations
419 */
420
421static int dpi_bridge_attach(struct drm_bridge *bridge,
422 enum drm_bridge_attach_flags flags)
423{
424 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
425
426 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
427 return -EINVAL;
428
429 dpi_init_pll(dpi);
430
431 return drm_bridge_attach(bridge->encoder, dpi->output.next_bridge,
432 bridge, flags);
433}
434
435static enum drm_mode_status
436dpi_bridge_mode_valid(struct drm_bridge *bridge,
437 const struct drm_display_info *info,
438 const struct drm_display_mode *mode)
439{
440 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
441 unsigned long clock = mode->clock * 1000;
442 int ret;
443
444 if (mode->hdisplay % 8 != 0)
445 return MODE_BAD_WIDTH;
446
447 if (mode->clock == 0)
448 return MODE_NOCLOCK;
449
450 ret = dpi_clock_update(dpi, &clock);
451 if (ret < 0)
452 return MODE_CLOCK_RANGE;
453
454 return MODE_OK;
455}
456
457static bool dpi_bridge_mode_fixup(struct drm_bridge *bridge,
458 const struct drm_display_mode *mode,
459 struct drm_display_mode *adjusted_mode)
460{
461 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
462 unsigned long clock = mode->clock * 1000;
463 int ret;
464
465 ret = dpi_clock_update(dpi, &clock);
466 if (ret < 0)
467 return false;
468
469 adjusted_mode->clock = clock / 1000;
470
471 return true;
472}
473
474static void dpi_bridge_mode_set(struct drm_bridge *bridge,
475 const struct drm_display_mode *mode,
476 const struct drm_display_mode *adjusted_mode)
477{
478 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
479
480 dpi->pixelclock = adjusted_mode->clock * 1000;
481}
482
483static void dpi_bridge_enable(struct drm_bridge *bridge)
484{
485 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
486 int r;
487
488 if (dpi->vdds_dsi_reg) {
489 r = regulator_enable(dpi->vdds_dsi_reg);
490 if (r)
491 return;
492 }
493
494 r = dispc_runtime_get(dpi->dss->dispc);
495 if (r)
496 goto err_get_dispc;
497
498 r = dss_dpi_select_source(dpi->dss, dpi->id, dpi->output.dispc_channel);
499 if (r)
500 goto err_src_sel;
501
502 if (dpi->pll) {
503 r = dss_pll_enable(dpi->pll);
504 if (r)
505 goto err_pll_init;
506 }
507
508 r = dpi_set_mode(dpi);
509 if (r)
510 goto err_set_mode;
511
512 dpi_config_lcd_manager(dpi);
513
514 mdelay(2);
515
516 r = dss_mgr_enable(&dpi->output);
517 if (r)
518 goto err_mgr_enable;
519
520 return;
521
522err_mgr_enable:
523err_set_mode:
524 if (dpi->pll)
525 dss_pll_disable(dpi->pll);
526err_pll_init:
527err_src_sel:
528 dispc_runtime_put(dpi->dss->dispc);
529err_get_dispc:
530 if (dpi->vdds_dsi_reg)
531 regulator_disable(dpi->vdds_dsi_reg);
532}
533
534static void dpi_bridge_disable(struct drm_bridge *bridge)
535{
536 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
537
538 dss_mgr_disable(&dpi->output);
539
540 if (dpi->pll) {
541 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
542 DSS_CLK_SRC_FCK);
543 dss_pll_disable(dpi->pll);
544 }
545
546 dispc_runtime_put(dpi->dss->dispc);
547
548 if (dpi->vdds_dsi_reg)
549 regulator_disable(dpi->vdds_dsi_reg);
550}
551
552static const struct drm_bridge_funcs dpi_bridge_funcs = {
553 .attach = dpi_bridge_attach,
554 .mode_valid = dpi_bridge_mode_valid,
555 .mode_fixup = dpi_bridge_mode_fixup,
556 .mode_set = dpi_bridge_mode_set,
557 .enable = dpi_bridge_enable,
558 .disable = dpi_bridge_disable,
559};
560
561static void dpi_bridge_init(struct dpi_data *dpi)
562{
563 dpi->bridge.funcs = &dpi_bridge_funcs;
564 dpi->bridge.of_node = dpi->pdev->dev.of_node;
565 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
566
567 drm_bridge_add(&dpi->bridge);
568}
569
570static void dpi_bridge_cleanup(struct dpi_data *dpi)
571{
572 drm_bridge_remove(&dpi->bridge);
573}
574
575/* -----------------------------------------------------------------------------
576 * Initialisation and Cleanup
577 */
578
579/*
580 * Return a hardcoded channel for the DPI output. This should work for
581 * current use cases, but this can be later expanded to either resolve
582 * the channel in some more dynamic manner, or get the channel as a user
583 * parameter.
584 */
585static enum omap_channel dpi_get_channel(struct dpi_data *dpi)
586{
587 switch (dpi->dss_model) {
588 case DSS_MODEL_OMAP2:
589 case DSS_MODEL_OMAP3:
590 return OMAP_DSS_CHANNEL_LCD;
591
592 case DSS_MODEL_DRA7:
593 switch (dpi->id) {
594 case 2:
595 return OMAP_DSS_CHANNEL_LCD3;
596 case 1:
597 return OMAP_DSS_CHANNEL_LCD2;
598 case 0:
599 default:
600 return OMAP_DSS_CHANNEL_LCD;
601 }
602
603 case DSS_MODEL_OMAP4:
604 return OMAP_DSS_CHANNEL_LCD2;
605
606 case DSS_MODEL_OMAP5:
607 return OMAP_DSS_CHANNEL_LCD3;
608
609 default:
610 DSSWARN("unsupported DSS version\n");
611 return OMAP_DSS_CHANNEL_LCD;
612 }
613}
614
615static int dpi_init_output_port(struct dpi_data *dpi, struct device_node *port)
616{
617 struct omap_dss_device *out = &dpi->output;
618 u32 port_num = 0;
619 int r;
620
621 dpi_bridge_init(dpi);
622
623 of_property_read_u32(port, "reg", &port_num);
624 dpi->id = port_num <= 2 ? port_num : 0;
625
626 switch (port_num) {
627 case 2:
628 out->name = "dpi.2";
629 break;
630 case 1:
631 out->name = "dpi.1";
632 break;
633 case 0:
634 default:
635 out->name = "dpi.0";
636 break;
637 }
638
639 out->dev = &dpi->pdev->dev;
640 out->id = OMAP_DSS_OUTPUT_DPI;
641 out->type = OMAP_DISPLAY_TYPE_DPI;
642 out->dispc_channel = dpi_get_channel(dpi);
643 out->of_port = port_num;
644
645 r = omapdss_device_init_output(out, &dpi->bridge);
646 if (r < 0) {
647 dpi_bridge_cleanup(dpi);
648 return r;
649 }
650
651 omapdss_device_register(out);
652
653 return 0;
654}
655
656static void dpi_uninit_output_port(struct device_node *port)
657{
658 struct dpi_data *dpi = port->data;
659 struct omap_dss_device *out = &dpi->output;
660
661 omapdss_device_unregister(out);
662 omapdss_device_cleanup_output(out);
663
664 dpi_bridge_cleanup(dpi);
665}
666
667/* -----------------------------------------------------------------------------
668 * Initialisation and Cleanup
669 */
670
671static const struct soc_device_attribute dpi_soc_devices[] = {
672 { .machine = "OMAP3[456]*" },
673 { .machine = "[AD]M37*" },
674 { /* sentinel */ }
675};
676
677static int dpi_init_regulator(struct dpi_data *dpi)
678{
679 struct regulator *vdds_dsi;
680
681 /*
682 * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and
683 * DM37xx only.
684 */
685 if (!soc_device_match(dpi_soc_devices))
686 return 0;
687
688 vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi");
689 if (IS_ERR(vdds_dsi)) {
690 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
691 DSSERR("can't get VDDS_DSI regulator\n");
692 return PTR_ERR(vdds_dsi);
693 }
694
695 dpi->vdds_dsi_reg = vdds_dsi;
696
697 return 0;
698}
699
700int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
701 struct device_node *port, enum dss_model dss_model)
702{
703 struct dpi_data *dpi;
704 struct device_node *ep;
705 u32 datalines;
706 int r;
707
708 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
709 if (!dpi)
710 return -ENOMEM;
711
712 ep = of_get_next_child(port, NULL);
713 if (!ep)
714 return 0;
715
716 r = of_property_read_u32(ep, "data-lines", &datalines);
717 of_node_put(ep);
718 if (r) {
719 DSSERR("failed to parse datalines\n");
720 return r;
721 }
722
723 dpi->data_lines = datalines;
724
725 dpi->pdev = pdev;
726 dpi->dss_model = dss_model;
727 dpi->dss = dss;
728 port->data = dpi;
729
730 r = dpi_init_regulator(dpi);
731 if (r)
732 return r;
733
734 return dpi_init_output_port(dpi, port);
735}
736
737void dpi_uninit_port(struct device_node *port)
738{
739 struct dpi_data *dpi = port->data;
740
741 if (!dpi)
742 return;
743
744 dpi_uninit_output_port(port);
745}