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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <linux/dmi.h>
27#include <linux/slab.h>
28
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_crtc.h>
31#include <drm/drm_edid.h>
32#include <drm/drm_mipi_dsi.h>
33
34#include "i915_drv.h"
35#include "i915_reg.h"
36#include "intel_atomic.h"
37#include "intel_backlight.h"
38#include "intel_connector.h"
39#include "intel_crtc.h"
40#include "intel_de.h"
41#include "intel_display_types.h"
42#include "intel_dsi.h"
43#include "intel_dsi_vbt.h"
44#include "intel_fifo_underrun.h"
45#include "intel_panel.h"
46#include "skl_scaler.h"
47#include "vlv_dsi.h"
48#include "vlv_dsi_pll.h"
49#include "vlv_dsi_regs.h"
50#include "vlv_sideband.h"
51
52/* return pixels in terms of txbyteclkhs */
53static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
54 u16 burst_mode_ratio)
55{
56 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
57 8 * 100), lane_count);
58}
59
60/* return pixels equvalent to txbyteclkhs */
61static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
62 u16 burst_mode_ratio)
63{
64 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
65 (bpp * burst_mode_ratio));
66}
67
68enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
69{
70 /* It just so happens the VBT matches register contents. */
71 switch (fmt) {
72 case VID_MODE_FORMAT_RGB888:
73 return MIPI_DSI_FMT_RGB888;
74 case VID_MODE_FORMAT_RGB666:
75 return MIPI_DSI_FMT_RGB666;
76 case VID_MODE_FORMAT_RGB666_PACKED:
77 return MIPI_DSI_FMT_RGB666_PACKED;
78 case VID_MODE_FORMAT_RGB565:
79 return MIPI_DSI_FMT_RGB565;
80 default:
81 MISSING_CASE(fmt);
82 return MIPI_DSI_FMT_RGB666;
83 }
84}
85
86void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
87{
88 struct drm_encoder *encoder = &intel_dsi->base.base;
89 struct drm_device *dev = encoder->dev;
90 struct drm_i915_private *dev_priv = to_i915(dev);
91 u32 mask;
92
93 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
94 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
95
96 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
97 mask, 100))
98 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
99}
100
101static void write_data(struct drm_i915_private *dev_priv,
102 i915_reg_t reg,
103 const u8 *data, u32 len)
104{
105 u32 i, j;
106
107 for (i = 0; i < len; i += 4) {
108 u32 val = 0;
109
110 for (j = 0; j < min_t(u32, len - i, 4); j++)
111 val |= *data++ << 8 * j;
112
113 intel_de_write(dev_priv, reg, val);
114 }
115}
116
117static void read_data(struct drm_i915_private *dev_priv,
118 i915_reg_t reg,
119 u8 *data, u32 len)
120{
121 u32 i, j;
122
123 for (i = 0; i < len; i += 4) {
124 u32 val = intel_de_read(dev_priv, reg);
125
126 for (j = 0; j < min_t(u32, len - i, 4); j++)
127 *data++ = val >> 8 * j;
128 }
129}
130
131static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
132 const struct mipi_dsi_msg *msg)
133{
134 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
135 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
136 struct drm_i915_private *dev_priv = to_i915(dev);
137 enum port port = intel_dsi_host->port;
138 struct mipi_dsi_packet packet;
139 ssize_t ret;
140 const u8 *header;
141 i915_reg_t data_reg, ctrl_reg;
142 u32 data_mask, ctrl_mask;
143
144 ret = mipi_dsi_create_packet(&packet, msg);
145 if (ret < 0)
146 return ret;
147
148 header = packet.header;
149
150 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
151 data_reg = MIPI_LP_GEN_DATA(port);
152 data_mask = LP_DATA_FIFO_FULL;
153 ctrl_reg = MIPI_LP_GEN_CTRL(port);
154 ctrl_mask = LP_CTRL_FIFO_FULL;
155 } else {
156 data_reg = MIPI_HS_GEN_DATA(port);
157 data_mask = HS_DATA_FIFO_FULL;
158 ctrl_reg = MIPI_HS_GEN_CTRL(port);
159 ctrl_mask = HS_CTRL_FIFO_FULL;
160 }
161
162 /* note: this is never true for reads */
163 if (packet.payload_length) {
164 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
165 data_mask, 50))
166 drm_err(&dev_priv->drm,
167 "Timeout waiting for HS/LP DATA FIFO !full\n");
168
169 write_data(dev_priv, data_reg, packet.payload,
170 packet.payload_length);
171 }
172
173 if (msg->rx_len) {
174 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
175 GEN_READ_DATA_AVAIL);
176 }
177
178 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
179 ctrl_mask, 50)) {
180 drm_err(&dev_priv->drm,
181 "Timeout waiting for HS/LP CTRL FIFO !full\n");
182 }
183
184 intel_de_write(dev_priv, ctrl_reg,
185 header[2] << 16 | header[1] << 8 | header[0]);
186
187 /* ->rx_len is set only for reads */
188 if (msg->rx_len) {
189 data_mask = GEN_READ_DATA_AVAIL;
190 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
191 data_mask, 50))
192 drm_err(&dev_priv->drm,
193 "Timeout waiting for read data.\n");
194
195 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
196 }
197
198 /* XXX: fix for reads and writes */
199 return 4 + packet.payload_length;
200}
201
202static int intel_dsi_host_attach(struct mipi_dsi_host *host,
203 struct mipi_dsi_device *dsi)
204{
205 return 0;
206}
207
208static int intel_dsi_host_detach(struct mipi_dsi_host *host,
209 struct mipi_dsi_device *dsi)
210{
211 return 0;
212}
213
214static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
215 .attach = intel_dsi_host_attach,
216 .detach = intel_dsi_host_detach,
217 .transfer = intel_dsi_host_transfer,
218};
219
220/*
221 * send a video mode command
222 *
223 * XXX: commands with data in MIPI_DPI_DATA?
224 */
225static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
226 enum port port)
227{
228 struct drm_encoder *encoder = &intel_dsi->base.base;
229 struct drm_device *dev = encoder->dev;
230 struct drm_i915_private *dev_priv = to_i915(dev);
231 u32 mask;
232
233 /* XXX: pipe, hs */
234 if (hs)
235 cmd &= ~DPI_LP_MODE;
236 else
237 cmd |= DPI_LP_MODE;
238
239 /* clear bit */
240 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
241
242 /* XXX: old code skips write if control unchanged */
243 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
244 drm_dbg_kms(&dev_priv->drm,
245 "Same special packet %02x twice in a row.\n", cmd);
246
247 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
248
249 mask = SPL_PKT_SENT_INTERRUPT;
250 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
251 drm_err(&dev_priv->drm,
252 "Video mode command 0x%08x send failed.\n", cmd);
253
254 return 0;
255}
256
257static void band_gap_reset(struct drm_i915_private *dev_priv)
258{
259 vlv_flisdsi_get(dev_priv);
260
261 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
263 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
264 udelay(150);
265 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
266 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
267
268 vlv_flisdsi_put(dev_priv);
269}
270
271static int intel_dsi_compute_config(struct intel_encoder *encoder,
272 struct intel_crtc_state *pipe_config,
273 struct drm_connector_state *conn_state)
274{
275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
276 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
277 base);
278 struct intel_connector *intel_connector = intel_dsi->attached_connector;
279 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
280 int ret;
281
282 drm_dbg_kms(&dev_priv->drm, "\n");
283 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
284 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
285
286 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
287 if (ret)
288 return ret;
289
290 ret = intel_panel_fitting(pipe_config, conn_state);
291 if (ret)
292 return ret;
293
294 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
295 return -EINVAL;
296
297 /* DSI uses short packets for sync events, so clear mode flags for DSI */
298 adjusted_mode->flags = 0;
299
300 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
301 pipe_config->pipe_bpp = 24;
302 else
303 pipe_config->pipe_bpp = 18;
304
305 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
306 /* Enable Frame time stamp based scanline reporting */
307 pipe_config->mode_flags |=
308 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
309
310 /* Dual link goes to DSI transcoder A. */
311 if (intel_dsi->ports == BIT(PORT_C))
312 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
313 else
314 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
315
316 ret = bxt_dsi_pll_compute(encoder, pipe_config);
317 if (ret)
318 return -EINVAL;
319 } else {
320 ret = vlv_dsi_pll_compute(encoder, pipe_config);
321 if (ret)
322 return -EINVAL;
323 }
324
325 pipe_config->clock_set = true;
326
327 return 0;
328}
329
330static bool glk_dsi_enable_io(struct intel_encoder *encoder)
331{
332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
333 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
334 enum port port;
335 bool cold_boot = false;
336
337 /* Set the MIPI mode
338 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
339 * Power ON MIPI IO first and then write into IO reset and LP wake bits
340 */
341 for_each_dsi_port(port, intel_dsi->ports)
342 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE);
343
344 /* Put the IO into reset */
345 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
346
347 /* Program LP Wake */
348 for_each_dsi_port(port, intel_dsi->ports) {
349 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
350 intel_de_rmw(dev_priv, MIPI_CTRL(port),
351 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
352 }
353
354 /* Wait for Pwr ACK */
355 for_each_dsi_port(port, intel_dsi->ports) {
356 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
357 GLK_MIPIIO_PORT_POWERED, 20))
358 drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
359 }
360
361 /* Check for cold boot scenario */
362 for_each_dsi_port(port, intel_dsi->ports) {
363 cold_boot |=
364 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
365 }
366
367 return cold_boot;
368}
369
370static void glk_dsi_device_ready(struct intel_encoder *encoder)
371{
372 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
373 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
374 enum port port;
375
376 /* Wait for MIPI PHY status bit to set */
377 for_each_dsi_port(port, intel_dsi->ports) {
378 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
379 GLK_PHY_STATUS_PORT_READY, 20))
380 drm_err(&dev_priv->drm, "PHY is not ON\n");
381 }
382
383 /* Get IO out of reset */
384 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
385
386 /* Get IO out of Low power state*/
387 for_each_dsi_port(port, intel_dsi->ports) {
388 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
389 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
390 ULPS_STATE_MASK, DEVICE_READY);
391 usleep_range(10, 15);
392 } else {
393 /* Enter ULPS */
394 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
395 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
396
397 /* Wait for ULPS active */
398 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
399 GLK_ULPS_NOT_ACTIVE, 20))
400 drm_err(&dev_priv->drm, "ULPS not active\n");
401
402 /* Exit ULPS */
403 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
404 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
405
406 /* Enter Normal Mode */
407 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
408 ULPS_STATE_MASK,
409 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
410
411 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0);
412 }
413 }
414
415 /* Wait for Stop state */
416 for_each_dsi_port(port, intel_dsi->ports) {
417 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
418 GLK_DATA_LANE_STOP_STATE, 20))
419 drm_err(&dev_priv->drm,
420 "Date lane not in STOP state\n");
421 }
422
423 /* Wait for AFE LATCH */
424 for_each_dsi_port(port, intel_dsi->ports) {
425 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
426 AFE_LATCHOUT, 20))
427 drm_err(&dev_priv->drm,
428 "D-PHY not entering LP-11 state\n");
429 }
430}
431
432static void bxt_dsi_device_ready(struct intel_encoder *encoder)
433{
434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
435 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
436 enum port port;
437 u32 val;
438
439 drm_dbg_kms(&dev_priv->drm, "\n");
440
441 /* Enable MIPI PHY transparent latch */
442 for_each_dsi_port(port, intel_dsi->ports) {
443 intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
444 usleep_range(2000, 2500);
445 }
446
447 /* Clear ULPS and set device ready */
448 for_each_dsi_port(port, intel_dsi->ports) {
449 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
450 val &= ~ULPS_STATE_MASK;
451 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
452 usleep_range(2000, 2500);
453 val |= DEVICE_READY;
454 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
455 }
456}
457
458static void vlv_dsi_device_ready(struct intel_encoder *encoder)
459{
460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
461 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
462 enum port port;
463
464 drm_dbg_kms(&dev_priv->drm, "\n");
465
466 vlv_flisdsi_get(dev_priv);
467 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
468 * needed everytime after power gate */
469 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
470 vlv_flisdsi_put(dev_priv);
471
472 /* bandgap reset is needed after everytime we do power gate */
473 band_gap_reset(dev_priv);
474
475 for_each_dsi_port(port, intel_dsi->ports) {
476
477 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
478 ULPS_STATE_ENTER);
479 usleep_range(2500, 3000);
480
481 /* Enable MIPI PHY transparent latch
482 * Common bit for both MIPI Port A & MIPI Port C
483 * No similar bit in MIPI Port C reg
484 */
485 intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
486 usleep_range(1000, 1500);
487
488 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
489 ULPS_STATE_EXIT);
490 usleep_range(2500, 3000);
491
492 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
493 DEVICE_READY);
494 usleep_range(2500, 3000);
495 }
496}
497
498static void intel_dsi_device_ready(struct intel_encoder *encoder)
499{
500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
501
502 if (IS_GEMINILAKE(dev_priv))
503 glk_dsi_device_ready(encoder);
504 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
505 bxt_dsi_device_ready(encoder);
506 else
507 vlv_dsi_device_ready(encoder);
508}
509
510static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
511{
512 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
513 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
514 enum port port;
515
516 /* Enter ULPS */
517 for_each_dsi_port(port, intel_dsi->ports)
518 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
519 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
520
521 /* Wait for MIPI PHY status bit to unset */
522 for_each_dsi_port(port, intel_dsi->ports) {
523 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
524 GLK_PHY_STATUS_PORT_READY, 20))
525 drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
526 }
527
528 /* Wait for Pwr ACK bit to unset */
529 for_each_dsi_port(port, intel_dsi->ports) {
530 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
531 GLK_MIPIIO_PORT_POWERED, 20))
532 drm_err(&dev_priv->drm,
533 "MIPI IO Port is not powergated\n");
534 }
535}
536
537static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
538{
539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
541 enum port port;
542
543 /* Put the IO into reset */
544 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
545
546 /* Wait for MIPI PHY status bit to unset */
547 for_each_dsi_port(port, intel_dsi->ports) {
548 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
549 GLK_PHY_STATUS_PORT_READY, 20))
550 drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
551 }
552
553 /* Clear MIPI mode */
554 for_each_dsi_port(port, intel_dsi->ports)
555 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0);
556}
557
558static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
559{
560 glk_dsi_enter_low_power_mode(encoder);
561 glk_dsi_disable_mipi_io(encoder);
562}
563
564static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port)
565{
566 return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ?
567 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
568}
569
570static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
571{
572 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
573 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
574 enum port port;
575
576 drm_dbg_kms(&dev_priv->drm, "\n");
577 for_each_dsi_port(port, intel_dsi->ports) {
578 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
579 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
580 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
581
582 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
583 DEVICE_READY | ULPS_STATE_ENTER);
584 usleep_range(2000, 2500);
585
586 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
587 DEVICE_READY | ULPS_STATE_EXIT);
588 usleep_range(2000, 2500);
589
590 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
591 DEVICE_READY | ULPS_STATE_ENTER);
592 usleep_range(2000, 2500);
593
594 /*
595 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
596 * Port A only. MIPI Port C has no similar bit for checking.
597 */
598 if ((IS_BROXTON(dev_priv) || port == PORT_A) &&
599 intel_de_wait_for_clear(dev_priv, port_ctrl,
600 AFE_LATCHOUT, 30))
601 drm_err(&dev_priv->drm, "DSI LP not going Low\n");
602
603 /* Disable MIPI PHY transparent latch */
604 intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0);
605 usleep_range(1000, 1500);
606
607 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
608 usleep_range(2000, 2500);
609 }
610}
611
612static void intel_dsi_port_enable(struct intel_encoder *encoder,
613 const struct intel_crtc_state *crtc_state)
614{
615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
616 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
617 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
618 enum port port;
619
620 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
621 u32 temp = intel_dsi->pixel_overlap;
622
623 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
624 for_each_dsi_port(port, intel_dsi->ports)
625 intel_de_rmw(dev_priv, MIPI_CTRL(port),
626 BXT_PIXEL_OVERLAP_CNT_MASK,
627 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
628 } else {
629 intel_de_rmw(dev_priv, VLV_CHICKEN_3,
630 PIXEL_OVERLAP_CNT_MASK,
631 temp << PIXEL_OVERLAP_CNT_SHIFT);
632 }
633 }
634
635 for_each_dsi_port(port, intel_dsi->ports) {
636 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
637 u32 temp;
638
639 temp = intel_de_read(dev_priv, port_ctrl);
640
641 temp &= ~LANE_CONFIGURATION_MASK;
642 temp &= ~DUAL_LINK_MODE_MASK;
643
644 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
645 temp |= (intel_dsi->dual_link - 1)
646 << DUAL_LINK_MODE_SHIFT;
647 if (IS_BROXTON(dev_priv))
648 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
649 else
650 temp |= crtc->pipe ?
651 LANE_CONFIGURATION_DUAL_LINK_B :
652 LANE_CONFIGURATION_DUAL_LINK_A;
653 }
654
655 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
656 temp |= DITHERING_ENABLE;
657
658 /* assert ip_tg_enable signal */
659 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
660 intel_de_posting_read(dev_priv, port_ctrl);
661 }
662}
663
664static void intel_dsi_port_disable(struct intel_encoder *encoder)
665{
666 struct drm_device *dev = encoder->base.dev;
667 struct drm_i915_private *dev_priv = to_i915(dev);
668 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
669 enum port port;
670
671 for_each_dsi_port(port, intel_dsi->ports) {
672 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
673
674 /* de-assert ip_tg_enable signal */
675 intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0);
676 intel_de_posting_read(dev_priv, port_ctrl);
677 }
678}
679static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
680 const struct intel_crtc_state *pipe_config);
681static void intel_dsi_unprepare(struct intel_encoder *encoder);
682
683/*
684 * Panel enable/disable sequences from the VBT spec.
685 *
686 * Note the spec has AssertReset / DeassertReset swapped from their
687 * usual naming. We use the normal names to avoid confusion (so below
688 * they are swapped compared to the spec).
689 *
690 * Steps starting with MIPI refer to VBT sequences, note that for v2
691 * VBTs several steps which have a VBT in v2 are expected to be handled
692 * directly by the driver, by directly driving gpios for example.
693 *
694 * v2 video mode seq v3 video mode seq command mode seq
695 * - power on - MIPIPanelPowerOn - power on
696 * - wait t1+t2 - wait t1+t2
697 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
698 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
699 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
700 * - MIPITearOn
701 * - MIPIDisplayOn
702 * - turn on DPI - turn on DPI - set pipe to dsr mode
703 * - MIPIDisplayOn - MIPIDisplayOn
704 * - wait t5 - wait t5
705 * - backlight on - MIPIBacklightOn - backlight on
706 * ... ... ... issue mem cmds ...
707 * - backlight off - MIPIBacklightOff - backlight off
708 * - wait t6 - wait t6
709 * - MIPIDisplayOff
710 * - turn off DPI - turn off DPI - disable pipe dsr mode
711 * - MIPITearOff
712 * - MIPIDisplayOff - MIPIDisplayOff
713 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
714 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
715 * - wait t3 - wait t3
716 * - power off - MIPIPanelPowerOff - power off
717 * - wait t4 - wait t4
718 */
719
720/*
721 * DSI port enable has to be done before pipe and plane enable, so we do it in
722 * the pre_enable hook instead of the enable hook.
723 */
724static void intel_dsi_pre_enable(struct intel_atomic_state *state,
725 struct intel_encoder *encoder,
726 const struct intel_crtc_state *pipe_config,
727 const struct drm_connector_state *conn_state)
728{
729 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
730 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
731 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
732 enum pipe pipe = crtc->pipe;
733 enum port port;
734 bool glk_cold_boot = false;
735
736 drm_dbg_kms(&dev_priv->drm, "\n");
737
738 intel_dsi_wait_panel_power_cycle(intel_dsi);
739
740 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
741
742 /*
743 * The BIOS may leave the PLL in a wonky state where it doesn't
744 * lock. It needs to be fully powered down to fix it.
745 */
746 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
747 bxt_dsi_pll_disable(encoder);
748 bxt_dsi_pll_enable(encoder, pipe_config);
749 } else {
750 vlv_dsi_pll_disable(encoder);
751 vlv_dsi_pll_enable(encoder, pipe_config);
752 }
753
754 if (IS_BROXTON(dev_priv)) {
755 /* Add MIPI IO reset programming for modeset */
756 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
757
758 /* Power up DSI regulator */
759 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
760 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
761 }
762
763 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
764 /* Disable DPOunit clock gating, can stall pipe */
765 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
766 0, DPOUNIT_CLOCK_GATE_DISABLE);
767 }
768
769 if (!IS_GEMINILAKE(dev_priv))
770 intel_dsi_prepare(encoder, pipe_config);
771
772 /* Give the panel time to power-on and then deassert its reset */
773 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
774 msleep(intel_dsi->panel_on_delay);
775 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
776
777 if (IS_GEMINILAKE(dev_priv)) {
778 glk_cold_boot = glk_dsi_enable_io(encoder);
779
780 /* Prepare port in cold boot(s3/s4) scenario */
781 if (glk_cold_boot)
782 intel_dsi_prepare(encoder, pipe_config);
783 }
784
785 /* Put device in ready state (LP-11) */
786 intel_dsi_device_ready(encoder);
787
788 /* Prepare port in normal boot scenario */
789 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
790 intel_dsi_prepare(encoder, pipe_config);
791
792 /* Send initialization commands in LP mode */
793 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
794
795 /*
796 * Enable port in pre-enable phase itself because as per hw team
797 * recommendation, port should be enabled before plane & pipe
798 */
799 if (is_cmd_mode(intel_dsi)) {
800 for_each_dsi_port(port, intel_dsi->ports)
801 intel_de_write(dev_priv,
802 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
803 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
804 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
805 } else {
806 msleep(20); /* XXX */
807 for_each_dsi_port(port, intel_dsi->ports)
808 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
809 msleep(100);
810
811 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
812
813 intel_dsi_port_enable(encoder, pipe_config);
814 }
815
816 intel_backlight_enable(pipe_config, conn_state);
817 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
818}
819
820static void bxt_dsi_enable(struct intel_atomic_state *state,
821 struct intel_encoder *encoder,
822 const struct intel_crtc_state *crtc_state,
823 const struct drm_connector_state *conn_state)
824{
825 intel_crtc_vblank_on(crtc_state);
826}
827
828/*
829 * DSI port disable has to be done after pipe and plane disable, so we do it in
830 * the post_disable hook.
831 */
832static void intel_dsi_disable(struct intel_atomic_state *state,
833 struct intel_encoder *encoder,
834 const struct intel_crtc_state *old_crtc_state,
835 const struct drm_connector_state *old_conn_state)
836{
837 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
838 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
839 enum port port;
840
841 drm_dbg_kms(&i915->drm, "\n");
842
843 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
844 intel_backlight_disable(old_conn_state);
845
846 /*
847 * According to the spec we should send SHUTDOWN before
848 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
849 * has shown that the v3 sequence works for v2 VBTs too
850 */
851 if (is_vid_mode(intel_dsi)) {
852 /* Send Shutdown command to the panel in LP mode */
853 for_each_dsi_port(port, intel_dsi->ports)
854 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
855 msleep(10);
856 }
857}
858
859static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
860{
861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
862
863 if (IS_GEMINILAKE(dev_priv))
864 glk_dsi_clear_device_ready(encoder);
865 else
866 vlv_dsi_clear_device_ready(encoder);
867}
868
869static void intel_dsi_post_disable(struct intel_atomic_state *state,
870 struct intel_encoder *encoder,
871 const struct intel_crtc_state *old_crtc_state,
872 const struct drm_connector_state *old_conn_state)
873{
874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
875 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
876 enum port port;
877
878 drm_dbg_kms(&dev_priv->drm, "\n");
879
880 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
881 intel_crtc_vblank_off(old_crtc_state);
882
883 skl_scaler_disable(old_crtc_state);
884 }
885
886 if (is_vid_mode(intel_dsi)) {
887 for_each_dsi_port(port, intel_dsi->ports)
888 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
889
890 intel_dsi_port_disable(encoder);
891 usleep_range(2000, 5000);
892 }
893
894 intel_dsi_unprepare(encoder);
895
896 /*
897 * if disable packets are sent before sending shutdown packet then in
898 * some next enable sequence send turn on packet error is observed
899 */
900 if (is_cmd_mode(intel_dsi))
901 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
902 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
903
904 /* Transition to LP-00 */
905 intel_dsi_clear_device_ready(encoder);
906
907 if (IS_BROXTON(dev_priv)) {
908 /* Power down DSI regulator to save power */
909 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
910 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
911 HS_IO_CTRL_SELECT);
912
913 /* Add MIPI IO reset programming for modeset */
914 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
915 }
916
917 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
918 bxt_dsi_pll_disable(encoder);
919 } else {
920 vlv_dsi_pll_disable(encoder);
921
922 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
923 DPOUNIT_CLOCK_GATE_DISABLE, 0);
924 }
925
926 /* Assert reset */
927 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
928
929 msleep(intel_dsi->panel_off_delay);
930 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
931
932 intel_dsi->panel_power_off_time = ktime_get_boottime();
933}
934
935static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
936 enum pipe *pipe)
937{
938 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
939 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
940 intel_wakeref_t wakeref;
941 enum port port;
942 bool active = false;
943
944 drm_dbg_kms(&dev_priv->drm, "\n");
945
946 wakeref = intel_display_power_get_if_enabled(dev_priv,
947 encoder->power_domain);
948 if (!wakeref)
949 return false;
950
951 /*
952 * On Broxton the PLL needs to be enabled with a valid divider
953 * configuration, otherwise accessing DSI registers will hang the
954 * machine. See BSpec North Display Engine registers/MIPI[BXT].
955 */
956 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
957 !bxt_dsi_pll_is_enabled(dev_priv))
958 goto out_put_power;
959
960 /* XXX: this only works for one DSI output */
961 for_each_dsi_port(port, intel_dsi->ports) {
962 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
963 bool enabled = intel_de_read(dev_priv, port_ctrl) & DPI_ENABLE;
964
965 /*
966 * Due to some hardware limitations on VLV/CHV, the DPI enable
967 * bit in port C control register does not get set. As a
968 * workaround, check pipe B conf instead.
969 */
970 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
971 port == PORT_C)
972 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
973
974 /* Try command mode if video mode not enabled */
975 if (!enabled) {
976 u32 tmp = intel_de_read(dev_priv,
977 MIPI_DSI_FUNC_PRG(port));
978 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
979 }
980
981 if (!enabled)
982 continue;
983
984 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
985 continue;
986
987 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
988 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
989 tmp &= BXT_PIPE_SELECT_MASK;
990 tmp >>= BXT_PIPE_SELECT_SHIFT;
991
992 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
993 continue;
994
995 *pipe = tmp;
996 } else {
997 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
998 }
999
1000 active = true;
1001 break;
1002 }
1003
1004out_put_power:
1005 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1006
1007 return active;
1008}
1009
1010static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1011 struct intel_crtc_state *pipe_config)
1012{
1013 struct drm_device *dev = encoder->base.dev;
1014 struct drm_i915_private *dev_priv = to_i915(dev);
1015 struct drm_display_mode *adjusted_mode =
1016 &pipe_config->hw.adjusted_mode;
1017 struct drm_display_mode *adjusted_mode_sw;
1018 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1019 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1020 unsigned int lane_count = intel_dsi->lane_count;
1021 unsigned int bpp, fmt;
1022 enum port port;
1023 u16 hactive, hfp, hsync, hbp, vfp, vsync;
1024 u16 hfp_sw, hsync_sw, hbp_sw;
1025 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1026 crtc_hblank_start_sw, crtc_hblank_end_sw;
1027
1028 /* FIXME: hw readout should not depend on SW state */
1029 adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1030
1031 /*
1032 * Atleast one port is active as encoder->get_config called only if
1033 * encoder->get_hw_state() returns true.
1034 */
1035 for_each_dsi_port(port, intel_dsi->ports) {
1036 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1037 break;
1038 }
1039
1040 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1041 bpp = mipi_dsi_pixel_format_to_bpp(
1042 pixel_format_from_register_bits(fmt));
1043
1044 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1045
1046 /* Enable Frame time stamo based scanline reporting */
1047 pipe_config->mode_flags |=
1048 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1049
1050 /* In terms of pixels */
1051 adjusted_mode->crtc_hdisplay =
1052 intel_de_read(dev_priv,
1053 BXT_MIPI_TRANS_HACTIVE(port));
1054 adjusted_mode->crtc_vdisplay =
1055 intel_de_read(dev_priv,
1056 BXT_MIPI_TRANS_VACTIVE(port));
1057 adjusted_mode->crtc_vtotal =
1058 intel_de_read(dev_priv,
1059 BXT_MIPI_TRANS_VTOTAL(port));
1060
1061 hactive = adjusted_mode->crtc_hdisplay;
1062 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1063
1064 /*
1065 * Meaningful for video mode non-burst sync pulse mode only,
1066 * can be zero for non-burst sync events and burst modes
1067 */
1068 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1069 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1070
1071 /* harizontal values are in terms of high speed byte clock */
1072 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1073 intel_dsi->burst_mode_ratio);
1074 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1075 intel_dsi->burst_mode_ratio);
1076 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1077 intel_dsi->burst_mode_ratio);
1078
1079 if (intel_dsi->dual_link) {
1080 hfp *= 2;
1081 hsync *= 2;
1082 hbp *= 2;
1083 }
1084
1085 /* vertical values are in terms of lines */
1086 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1087 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1088
1089 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1090 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1091 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1092 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1093 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1094
1095 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1096 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1097 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1098 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1099
1100 /*
1101 * In BXT DSI there is no regs programmed with few horizontal timings
1102 * in Pixels but txbyteclkhs.. So retrieval process adds some
1103 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1104 * Actually here for the given adjusted_mode, we are calculating the
1105 * value programmed to the port and then back to the horizontal timing
1106 * param in pixels. This is the expected value, including roundup errors
1107 * And if that is same as retrieved value from port, then
1108 * (HW state) adjusted_mode's horizontal timings are corrected to
1109 * match with SW state to nullify the errors.
1110 */
1111 /* Calculating the value programmed to the Port register */
1112 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1113 adjusted_mode_sw->crtc_hdisplay;
1114 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1115 adjusted_mode_sw->crtc_hsync_start;
1116 hbp_sw = adjusted_mode_sw->crtc_htotal -
1117 adjusted_mode_sw->crtc_hsync_end;
1118
1119 if (intel_dsi->dual_link) {
1120 hfp_sw /= 2;
1121 hsync_sw /= 2;
1122 hbp_sw /= 2;
1123 }
1124
1125 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1126 intel_dsi->burst_mode_ratio);
1127 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1128 intel_dsi->burst_mode_ratio);
1129 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1130 intel_dsi->burst_mode_ratio);
1131
1132 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1133 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1134 intel_dsi->burst_mode_ratio);
1135 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1136 intel_dsi->burst_mode_ratio);
1137 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1138 intel_dsi->burst_mode_ratio);
1139
1140 if (intel_dsi->dual_link) {
1141 hfp_sw *= 2;
1142 hsync_sw *= 2;
1143 hbp_sw *= 2;
1144 }
1145
1146 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1147 hsync_sw + hbp_sw;
1148 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1149 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1150 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1151 crtc_hblank_end_sw = crtc_htotal_sw;
1152
1153 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1154 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1155
1156 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1157 adjusted_mode->crtc_hsync_start =
1158 adjusted_mode_sw->crtc_hsync_start;
1159
1160 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1161 adjusted_mode->crtc_hsync_end =
1162 adjusted_mode_sw->crtc_hsync_end;
1163
1164 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1165 adjusted_mode->crtc_hblank_start =
1166 adjusted_mode_sw->crtc_hblank_start;
1167
1168 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1169 adjusted_mode->crtc_hblank_end =
1170 adjusted_mode_sw->crtc_hblank_end;
1171}
1172
1173static void intel_dsi_get_config(struct intel_encoder *encoder,
1174 struct intel_crtc_state *pipe_config)
1175{
1176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1177 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1178 u32 pclk;
1179
1180 drm_dbg_kms(&dev_priv->drm, "\n");
1181
1182 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1183
1184 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1185 bxt_dsi_get_pipe_config(encoder, pipe_config);
1186 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1187 } else {
1188 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1189 }
1190
1191 pipe_config->port_clock = pclk;
1192
1193 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
1194 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1195 if (intel_dsi->dual_link)
1196 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1197}
1198
1199/* return txclkesc cycles in terms of divider and duration in us */
1200static u16 txclkesc(u32 divider, unsigned int us)
1201{
1202 switch (divider) {
1203 case ESCAPE_CLOCK_DIVIDER_1:
1204 default:
1205 return 20 * us;
1206 case ESCAPE_CLOCK_DIVIDER_2:
1207 return 10 * us;
1208 case ESCAPE_CLOCK_DIVIDER_4:
1209 return 5 * us;
1210 }
1211}
1212
1213static void set_dsi_timings(struct drm_encoder *encoder,
1214 const struct drm_display_mode *adjusted_mode)
1215{
1216 struct drm_device *dev = encoder->dev;
1217 struct drm_i915_private *dev_priv = to_i915(dev);
1218 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1219 enum port port;
1220 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1221 unsigned int lane_count = intel_dsi->lane_count;
1222
1223 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1224
1225 hactive = adjusted_mode->crtc_hdisplay;
1226 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1227 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1228 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1229
1230 if (intel_dsi->dual_link) {
1231 hactive /= 2;
1232 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1233 hactive += intel_dsi->pixel_overlap;
1234 hfp /= 2;
1235 hsync /= 2;
1236 hbp /= 2;
1237 }
1238
1239 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1240 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1241 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1242
1243 /* horizontal values are in terms of high speed byte clock */
1244 hactive = txbyteclkhs(hactive, bpp, lane_count,
1245 intel_dsi->burst_mode_ratio);
1246 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1247 hsync = txbyteclkhs(hsync, bpp, lane_count,
1248 intel_dsi->burst_mode_ratio);
1249 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1250
1251 for_each_dsi_port(port, intel_dsi->ports) {
1252 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1253 /*
1254 * Program hdisplay and vdisplay on MIPI transcoder.
1255 * This is different from calculated hactive and
1256 * vactive, as they are calculated per channel basis,
1257 * whereas these values should be based on resolution.
1258 */
1259 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1260 adjusted_mode->crtc_hdisplay);
1261 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1262 adjusted_mode->crtc_vdisplay);
1263 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1264 adjusted_mode->crtc_vtotal);
1265 }
1266
1267 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1268 hactive);
1269 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1270
1271 /* meaningful for video mode non-burst sync pulse mode only,
1272 * can be zero for non-burst sync events and burst modes */
1273 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1274 hsync);
1275 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1276
1277 /* vertical values are in terms of lines */
1278 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1279 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1280 vsync);
1281 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1282 }
1283}
1284
1285static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1286{
1287 switch (fmt) {
1288 case MIPI_DSI_FMT_RGB888:
1289 return VID_MODE_FORMAT_RGB888;
1290 case MIPI_DSI_FMT_RGB666:
1291 return VID_MODE_FORMAT_RGB666;
1292 case MIPI_DSI_FMT_RGB666_PACKED:
1293 return VID_MODE_FORMAT_RGB666_PACKED;
1294 case MIPI_DSI_FMT_RGB565:
1295 return VID_MODE_FORMAT_RGB565;
1296 default:
1297 MISSING_CASE(fmt);
1298 return VID_MODE_FORMAT_RGB666;
1299 }
1300}
1301
1302static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1303 const struct intel_crtc_state *pipe_config)
1304{
1305 struct drm_encoder *encoder = &intel_encoder->base;
1306 struct drm_device *dev = encoder->dev;
1307 struct drm_i915_private *dev_priv = to_i915(dev);
1308 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1309 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1310 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1311 enum port port;
1312 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1313 u32 val, tmp;
1314 u16 mode_hdisplay;
1315
1316 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe));
1317
1318 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1319
1320 if (intel_dsi->dual_link) {
1321 mode_hdisplay /= 2;
1322 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1323 mode_hdisplay += intel_dsi->pixel_overlap;
1324 }
1325
1326 for_each_dsi_port(port, intel_dsi->ports) {
1327 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1328 /*
1329 * escape clock divider, 20MHz, shared for A and C.
1330 * device ready must be off when doing this! txclkesc?
1331 */
1332 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1333 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1334 intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1335 tmp | ESCAPE_CLOCK_DIVIDER_1);
1336
1337 /* read request priority is per pipe */
1338 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1339 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1340 intel_de_write(dev_priv, MIPI_CTRL(port),
1341 tmp | READ_REQUEST_PRIORITY_HIGH);
1342 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1343 enum pipe pipe = crtc->pipe;
1344
1345 intel_de_rmw(dev_priv, MIPI_CTRL(port),
1346 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
1347 }
1348
1349 /* XXX: why here, why like this? handling in irq handler?! */
1350 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1351 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1352
1353 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1354 intel_dsi->dphy_reg);
1355
1356 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1357 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1358 }
1359
1360 set_dsi_timings(encoder, adjusted_mode);
1361
1362 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1363 if (is_cmd_mode(intel_dsi)) {
1364 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1365 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1366 } else {
1367 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1368 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1369 }
1370
1371 tmp = 0;
1372 if (intel_dsi->eotp_pkt == 0)
1373 tmp |= EOT_DISABLE;
1374 if (intel_dsi->clock_stop)
1375 tmp |= CLOCKSTOP;
1376
1377 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1378 tmp |= BXT_DPHY_DEFEATURE_EN;
1379 if (!is_cmd_mode(intel_dsi))
1380 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1381 }
1382
1383 for_each_dsi_port(port, intel_dsi->ports) {
1384 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1385
1386 /* timeouts for recovery. one frame IIUC. if counter expires,
1387 * EOT and stop state. */
1388
1389 /*
1390 * In burst mode, value greater than one DPI line Time in byte
1391 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1392 * said value is recommended.
1393 *
1394 * In non-burst mode, Value greater than one DPI frame time in
1395 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1396 * said value is recommended.
1397 *
1398 * In DBI only mode, value greater than one DBI frame time in
1399 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1400 * said value is recommended.
1401 */
1402
1403 if (is_vid_mode(intel_dsi) &&
1404 intel_dsi->video_mode == BURST_MODE) {
1405 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1406 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1407 } else {
1408 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1409 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1410 }
1411 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1412 intel_dsi->lp_rx_timeout);
1413 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1414 intel_dsi->turn_arnd_val);
1415 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1416 intel_dsi->rst_timer_val);
1417
1418 /* dphy stuff */
1419
1420 /* in terms of low power clock */
1421 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1422 txclkesc(intel_dsi->escape_clk_div, 100));
1423
1424 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1425 !intel_dsi->dual_link) {
1426 /*
1427 * BXT spec says write MIPI_INIT_COUNT for
1428 * both the ports, even if only one is
1429 * getting used. So write the other port
1430 * if not in dual link mode.
1431 */
1432 intel_de_write(dev_priv,
1433 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1434 intel_dsi->init_count);
1435 }
1436
1437 /* recovery disables */
1438 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1439
1440 /* in terms of low power clock */
1441 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1442 intel_dsi->init_count);
1443
1444 /* in terms of txbyteclkhs. actual high to low switch +
1445 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1446 *
1447 * XXX: write MIPI_STOP_STATE_STALL?
1448 */
1449 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1450 intel_dsi->hs_to_lp_count);
1451
1452 /* XXX: low power clock equivalence in terms of byte clock.
1453 * the number of byte clocks occupied in one low power clock.
1454 * based on txbyteclkhs and txclkesc.
1455 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1456 * ) / 105.???
1457 */
1458 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1459 intel_dsi->lp_byte_clk);
1460
1461 if (IS_GEMINILAKE(dev_priv)) {
1462 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1463 intel_dsi->lp_byte_clk);
1464 /* Shadow of DPHY reg */
1465 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1466 intel_dsi->dphy_reg);
1467 }
1468
1469 /* the bw essential for transmitting 16 long packets containing
1470 * 252 bytes meant for dcs write memory command is programmed in
1471 * this register in terms of byte clocks. based on dsi transfer
1472 * rate and the number of lanes configured the time taken to
1473 * transmit 16 long packets in a dsi stream varies. */
1474 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1475 intel_dsi->bw_timer);
1476
1477 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1478 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1479
1480 if (is_vid_mode(intel_dsi)) {
1481 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1482
1483 /*
1484 * Some panels might have resolution which is not a
1485 * multiple of 64 like 1366 x 768. Enable RANDOM
1486 * resolution support for such panels by default.
1487 */
1488 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1489
1490 switch (intel_dsi->video_mode) {
1491 default:
1492 MISSING_CASE(intel_dsi->video_mode);
1493 fallthrough;
1494 case NON_BURST_SYNC_EVENTS:
1495 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1496 break;
1497 case NON_BURST_SYNC_PULSE:
1498 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1499 break;
1500 case BURST_MODE:
1501 fmt |= VIDEO_MODE_BURST;
1502 break;
1503 }
1504
1505 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt);
1506 }
1507 }
1508}
1509
1510static void intel_dsi_unprepare(struct intel_encoder *encoder)
1511{
1512 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1513 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1514 enum port port;
1515
1516 if (IS_GEMINILAKE(dev_priv))
1517 return;
1518
1519 for_each_dsi_port(port, intel_dsi->ports) {
1520 /* Panel commands can be sent when clock is in LP11 */
1521 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1522
1523 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1524 bxt_dsi_reset_clocks(encoder, port);
1525 else
1526 vlv_dsi_reset_clocks(encoder, port);
1527 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1528
1529 intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0);
1530
1531 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1532 }
1533}
1534
1535static const struct drm_encoder_funcs intel_dsi_funcs = {
1536 .destroy = intel_encoder_destroy,
1537};
1538
1539static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,
1540 struct drm_display_mode *mode)
1541{
1542 struct drm_i915_private *i915 = to_i915(connector->dev);
1543
1544 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1545 enum drm_mode_status status;
1546
1547 status = intel_cpu_transcoder_mode_valid(i915, mode);
1548 if (status != MODE_OK)
1549 return status;
1550 }
1551
1552 return intel_dsi_mode_valid(connector, mode);
1553}
1554
1555static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1556 .get_modes = intel_dsi_get_modes,
1557 .mode_valid = vlv_dsi_mode_valid,
1558 .atomic_check = intel_digital_connector_atomic_check,
1559};
1560
1561static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1562 .detect = intel_panel_detect,
1563 .late_register = intel_connector_register,
1564 .early_unregister = intel_connector_unregister,
1565 .destroy = intel_connector_destroy,
1566 .fill_modes = drm_helper_probe_single_connector_modes,
1567 .atomic_get_property = intel_digital_connector_atomic_get_property,
1568 .atomic_set_property = intel_digital_connector_atomic_set_property,
1569 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1570 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1571};
1572
1573static void vlv_dsi_add_properties(struct intel_connector *connector)
1574{
1575 const struct drm_display_mode *fixed_mode =
1576 intel_panel_preferred_fixed_mode(connector);
1577
1578 intel_attach_scaling_mode_property(&connector->base);
1579
1580 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1581 intel_dsi_get_panel_orientation(connector),
1582 fixed_mode->hdisplay,
1583 fixed_mode->vdisplay);
1584}
1585
1586#define NS_KHZ_RATIO 1000000
1587
1588#define PREPARE_CNT_MAX 0x3F
1589#define EXIT_ZERO_CNT_MAX 0x3F
1590#define CLK_ZERO_CNT_MAX 0xFF
1591#define TRAIL_CNT_MAX 0x1F
1592
1593static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1594{
1595 struct drm_device *dev = intel_dsi->base.base.dev;
1596 struct drm_i915_private *dev_priv = to_i915(dev);
1597 struct intel_connector *connector = intel_dsi->attached_connector;
1598 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1599 u32 tlpx_ns, extra_byte_count, tlpx_ui;
1600 u32 ui_num, ui_den;
1601 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1602 u32 ths_prepare_ns, tclk_trail_ns;
1603 u32 tclk_prepare_clkzero, ths_prepare_hszero;
1604 u32 lp_to_hs_switch, hs_to_lp_switch;
1605 u32 mul;
1606
1607 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1608
1609 switch (intel_dsi->lane_count) {
1610 case 1:
1611 case 2:
1612 extra_byte_count = 2;
1613 break;
1614 case 3:
1615 extra_byte_count = 4;
1616 break;
1617 case 4:
1618 default:
1619 extra_byte_count = 3;
1620 break;
1621 }
1622
1623 /* in Kbps */
1624 ui_num = NS_KHZ_RATIO;
1625 ui_den = intel_dsi_bitrate(intel_dsi);
1626
1627 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1628 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1629
1630 /*
1631 * B060
1632 * LP byte clock = TLPX/ (8UI)
1633 */
1634 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1635
1636 /* DDR clock period = 2 * UI
1637 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1638 * UI(nsec) = 10^6 / bitrate
1639 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1640 * DDR clock count = ns_value / DDR clock period
1641 *
1642 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1643 * HS byte clock count for other platform in HS ddr clock count
1644 */
1645 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1646 ths_prepare_ns = max(mipi_config->ths_prepare,
1647 mipi_config->tclk_prepare);
1648
1649 /* prepare count */
1650 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1651
1652 if (prepare_cnt > PREPARE_CNT_MAX) {
1653 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1654 prepare_cnt);
1655 prepare_cnt = PREPARE_CNT_MAX;
1656 }
1657
1658 /* exit zero count */
1659 exit_zero_cnt = DIV_ROUND_UP(
1660 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1661 ui_num * mul
1662 );
1663
1664 /*
1665 * Exit zero is unified val ths_zero and ths_exit
1666 * minimum value for ths_exit = 110ns
1667 * min (exit_zero_cnt * 2) = 110/UI
1668 * exit_zero_cnt = 55/UI
1669 */
1670 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1671 exit_zero_cnt += 1;
1672
1673 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1674 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1675 exit_zero_cnt);
1676 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1677 }
1678
1679 /* clk zero count */
1680 clk_zero_cnt = DIV_ROUND_UP(
1681 (tclk_prepare_clkzero - ths_prepare_ns)
1682 * ui_den, ui_num * mul);
1683
1684 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1685 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1686 clk_zero_cnt);
1687 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1688 }
1689
1690 /* trail count */
1691 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1692 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1693
1694 if (trail_cnt > TRAIL_CNT_MAX) {
1695 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1696 trail_cnt);
1697 trail_cnt = TRAIL_CNT_MAX;
1698 }
1699
1700 /* B080 */
1701 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1702 clk_zero_cnt << 8 | prepare_cnt;
1703
1704 /*
1705 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1706 * mul + 10UI + Extra Byte Count
1707 *
1708 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1709 * Extra Byte Count is calculated according to number of lanes.
1710 * High Low Switch Count is the Max of LP to HS and
1711 * HS to LP switch count
1712 *
1713 */
1714 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1715
1716 /* B044 */
1717 /* FIXME:
1718 * The comment above does not match with the code */
1719 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1720 exit_zero_cnt * mul + 10, 8);
1721
1722 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1723
1724 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1725 intel_dsi->hs_to_lp_count += extra_byte_count;
1726
1727 /* B088 */
1728 /* LP -> HS for clock lanes
1729 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1730 * extra byte count
1731 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1732 * 2(in UI) + extra byte count
1733 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1734 * 8 + extra byte count
1735 */
1736 intel_dsi->clk_lp_to_hs_count =
1737 DIV_ROUND_UP(
1738 4 * tlpx_ui + prepare_cnt * 2 +
1739 clk_zero_cnt * 2,
1740 8);
1741
1742 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1743
1744 /* HS->LP for Clock Lanes
1745 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1746 * Extra byte count
1747 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1748 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1749 * Extra byte count
1750 */
1751 intel_dsi->clk_hs_to_lp_count =
1752 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1753 8);
1754 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1755
1756 intel_dsi_log_params(intel_dsi);
1757}
1758
1759typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
1760
1761/*
1762 * Vtotal is wrong on the Asus TF103C leading to the last line of the display
1763 * being shown as the first line. The factory installed Android has a hardcoded
1764 * modeline, causing it to not suffer from this BIOS bug.
1765 *
1766 * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa
1767 * Fixed mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa
1768 *
1769 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381
1770 */
1771static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi)
1772{
1773 /* Cast away the const as we want to fixup the mode */
1774 struct drm_display_mode *fixed_mode = (struct drm_display_mode *)
1775 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1776
1777 if (fixed_mode->vtotal == 820)
1778 fixed_mode->vtotal -= 4;
1779}
1780
1781/*
1782 * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems:
1783 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7
1784 * which under Linux become bus 0 - 6. And the MIPI sequence reference
1785 * to bus 3 is indented for I2C3 which is bus 2 under Linux.
1786 *
1787 * Note mipi_exec_i2c() cannot just subtract 1 from the bus
1788 * given in the I2C MIPI sequence element. Since on other
1789 * devices the I2C bus-numbers used in the MIPI sequences do
1790 * actually start at 0.
1791 *
1792 * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is
1793 * especially a problem on the 8" 830 version which uses a 10:16
1794 * portrait screen where as the bogus size is 16:10.
1795 *
1796 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379
1797 */
1798static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi)
1799{
1800 const struct drm_display_mode *fixed_mode =
1801 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1802 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info;
1803
1804 intel_dsi->i2c_bus_num = 2;
1805
1806 /*
1807 * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830
1808 * uses a 1200x1920 portrait screen.
1809 */
1810 if (fixed_mode->hdisplay == 1920) {
1811 info->width_mm = 216;
1812 info->height_mm = 135;
1813 } else {
1814 info->width_mm = 107;
1815 info->height_mm = 171;
1816 }
1817}
1818
1819/*
1820 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems:
1821 * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c()
1822 * to not work. Fix this by setting i2c_bus_num.
1823 * 2. There is no backlight off MIPI sequence, causing the backlight to stay on.
1824 * Add a backlight off sequence mirroring the existing backlight on sequence.
1825 *
1826 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380
1827 */
1828static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi)
1829{
1830 static const u8 backlight_off_sequence[16] = {
1831 /* Header Seq-id 7, length after header 11 bytes */
1832 0x07, 0x0b, 0x00, 0x00, 0x00,
1833 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */
1834 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00,
1835 /* MIPI_SEQ_ELEM_END */
1836 0x00
1837 };
1838 struct intel_connector *connector = intel_dsi->attached_connector;
1839
1840 intel_dsi->i2c_bus_num = 0;
1841 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence;
1842}
1843
1844static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = {
1845 {
1846 /* Asus Transformer Pad TF103C */
1847 .matches = {
1848 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
1849 DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"),
1850 },
1851 .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup,
1852 },
1853 {
1854 /*
1855 * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10"
1856 * Lenovo Yoga Tablet 2 use the same mainboard)
1857 */
1858 .matches = {
1859 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."),
1860 DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"),
1861 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
1862 /* Partial match on beginning of BIOS version */
1863 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
1864 },
1865 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup,
1866 },
1867 {
1868 /* Lenovo Yoga Tab 3 Pro YT3-X90F */
1869 .matches = {
1870 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
1871 DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
1872 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
1873 },
1874 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup,
1875 },
1876 { }
1877};
1878
1879void vlv_dsi_init(struct drm_i915_private *dev_priv)
1880{
1881 struct intel_dsi *intel_dsi;
1882 struct intel_encoder *intel_encoder;
1883 struct drm_encoder *encoder;
1884 struct intel_connector *intel_connector;
1885 struct drm_connector *connector;
1886 struct drm_display_mode *current_mode;
1887 const struct dmi_system_id *dmi_id;
1888 enum port port;
1889 enum pipe pipe;
1890
1891 drm_dbg_kms(&dev_priv->drm, "\n");
1892
1893 /* There is no detection method for MIPI so rely on VBT */
1894 if (!intel_bios_is_dsi_present(dev_priv, &port))
1895 return;
1896
1897 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1898 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1899 else
1900 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1901
1902 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1903 if (!intel_dsi)
1904 return;
1905
1906 intel_connector = intel_connector_alloc();
1907 if (!intel_connector) {
1908 kfree(intel_dsi);
1909 return;
1910 }
1911
1912 intel_encoder = &intel_dsi->base;
1913 encoder = &intel_encoder->base;
1914 intel_dsi->attached_connector = intel_connector;
1915
1916 connector = &intel_connector->base;
1917
1918 drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1919 "DSI %c", port_name(port));
1920
1921 intel_encoder->compute_config = intel_dsi_compute_config;
1922 intel_encoder->pre_enable = intel_dsi_pre_enable;
1923 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1924 intel_encoder->enable = bxt_dsi_enable;
1925 intel_encoder->disable = intel_dsi_disable;
1926 intel_encoder->post_disable = intel_dsi_post_disable;
1927 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1928 intel_encoder->get_config = intel_dsi_get_config;
1929 intel_encoder->update_pipe = intel_backlight_update;
1930 intel_encoder->shutdown = intel_dsi_shutdown;
1931
1932 intel_connector->get_hw_state = intel_connector_get_hw_state;
1933
1934 intel_encoder->port = port;
1935 intel_encoder->type = INTEL_OUTPUT_DSI;
1936 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1937 intel_encoder->cloneable = 0;
1938
1939 /*
1940 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1941 * port C. BXT isn't limited like this.
1942 */
1943 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1944 intel_encoder->pipe_mask = ~0;
1945 else if (port == PORT_A)
1946 intel_encoder->pipe_mask = BIT(PIPE_A);
1947 else
1948 intel_encoder->pipe_mask = BIT(PIPE_B);
1949
1950 intel_dsi->panel_power_off_time = ktime_get_boottime();
1951
1952 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL);
1953
1954 if (intel_connector->panel.vbt.dsi.config->dual_link)
1955 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1956 else
1957 intel_dsi->ports = BIT(port);
1958
1959 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1960 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1961
1962 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1963 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1964
1965 /* Create a DSI host (and a device) for each port. */
1966 for_each_dsi_port(port, intel_dsi->ports) {
1967 struct intel_dsi_host *host;
1968
1969 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1970 port);
1971 if (!host)
1972 goto err;
1973
1974 intel_dsi->dsi_hosts[port] = host;
1975 }
1976
1977 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1978 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1979 goto err;
1980 }
1981
1982 /* Use clock read-back from current hw-state for fastboot */
1983 current_mode = intel_encoder_current_mode(intel_encoder);
1984 if (current_mode) {
1985 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1986 intel_dsi->pclk, current_mode->clock);
1987 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1988 current_mode->clock)) {
1989 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1990 intel_dsi->pclk = current_mode->clock;
1991 }
1992
1993 kfree(current_mode);
1994 }
1995
1996 vlv_dphy_param_init(intel_dsi);
1997
1998 intel_dsi_vbt_gpio_init(intel_dsi,
1999 intel_dsi_get_hw_state(intel_encoder, &pipe));
2000
2001 drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs,
2002 DRM_MODE_CONNECTOR_DSI);
2003
2004 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
2005
2006 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
2007
2008 intel_connector_attach_encoder(intel_connector, intel_encoder);
2009
2010 mutex_lock(&dev_priv->drm.mode_config.mutex);
2011 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
2012 mutex_unlock(&dev_priv->drm.mode_config.mutex);
2013
2014 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2015 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
2016 goto err_cleanup_connector;
2017 }
2018
2019 dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table);
2020 if (dmi_id) {
2021 vlv_dsi_dmi_quirk_func quirk_func =
2022 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data;
2023
2024 quirk_func(intel_dsi);
2025 }
2026
2027 intel_panel_init(intel_connector, NULL);
2028
2029 intel_backlight_setup(intel_connector, INVALID_PIPE);
2030
2031 vlv_dsi_add_properties(intel_connector);
2032
2033 return;
2034
2035err_cleanup_connector:
2036 drm_connector_cleanup(&intel_connector->base);
2037err:
2038 drm_encoder_cleanup(&intel_encoder->base);
2039 kfree(intel_dsi);
2040 kfree(intel_connector);
2041}