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1/*
2 * SH7785 Setup
3 *
4 * Copyright (C) 2007 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14#include <linux/io.h>
15#include <linux/mm.h>
16#include <linux/sh_dma.h>
17#include <linux/sh_timer.h>
18#include <linux/sh_intc.h>
19#include <asm/mmzone.h>
20#include <cpu/dma-register.h>
21
22static struct plat_sci_port scif0_platform_data = {
23 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
25 .type = PORT_SCIF,
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
27};
28
29static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffea0000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0x700)),
32};
33
34static struct platform_device scif0_device = {
35 .name = "sh-sci",
36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
39 .dev = {
40 .platform_data = &scif0_platform_data,
41 },
42};
43
44static struct plat_sci_port scif1_platform_data = {
45 .flags = UPF_BOOT_AUTOCONF,
46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
47 .type = PORT_SCIF,
48 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
49};
50
51static struct resource scif1_resources[] = {
52 DEFINE_RES_MEM(0xffeb0000, 0x100),
53 DEFINE_RES_IRQ(evt2irq(0x780)),
54};
55
56static struct platform_device scif1_device = {
57 .name = "sh-sci",
58 .id = 1,
59 .resource = scif1_resources,
60 .num_resources = ARRAY_SIZE(scif1_resources),
61 .dev = {
62 .platform_data = &scif1_platform_data,
63 },
64};
65
66static struct plat_sci_port scif2_platform_data = {
67 .flags = UPF_BOOT_AUTOCONF,
68 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
69 .type = PORT_SCIF,
70 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
71};
72
73static struct resource scif2_resources[] = {
74 DEFINE_RES_MEM(0xffec0000, 0x100),
75 DEFINE_RES_IRQ(evt2irq(0x980)),
76};
77
78static struct platform_device scif2_device = {
79 .name = "sh-sci",
80 .id = 2,
81 .resource = scif2_resources,
82 .num_resources = ARRAY_SIZE(scif2_resources),
83 .dev = {
84 .platform_data = &scif2_platform_data,
85 },
86};
87
88static struct plat_sci_port scif3_platform_data = {
89 .flags = UPF_BOOT_AUTOCONF,
90 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
91 .type = PORT_SCIF,
92 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
93};
94
95static struct resource scif3_resources[] = {
96 DEFINE_RES_MEM(0xffed0000, 0x100),
97 DEFINE_RES_IRQ(evt2irq(0x9a0)),
98};
99
100static struct platform_device scif3_device = {
101 .name = "sh-sci",
102 .id = 3,
103 .resource = scif3_resources,
104 .num_resources = ARRAY_SIZE(scif3_resources),
105 .dev = {
106 .platform_data = &scif3_platform_data,
107 },
108};
109
110static struct plat_sci_port scif4_platform_data = {
111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
113 .type = PORT_SCIF,
114 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
115};
116
117static struct resource scif4_resources[] = {
118 DEFINE_RES_MEM(0xffee0000, 0x100),
119 DEFINE_RES_IRQ(evt2irq(0x9c0)),
120};
121
122static struct platform_device scif4_device = {
123 .name = "sh-sci",
124 .id = 4,
125 .resource = scif4_resources,
126 .num_resources = ARRAY_SIZE(scif4_resources),
127 .dev = {
128 .platform_data = &scif4_platform_data,
129 },
130};
131
132static struct plat_sci_port scif5_platform_data = {
133 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
135 .type = PORT_SCIF,
136 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
137};
138
139static struct resource scif5_resources[] = {
140 DEFINE_RES_MEM(0xffef0000, 0x100),
141 DEFINE_RES_IRQ(evt2irq(0x9e0)),
142};
143
144static struct platform_device scif5_device = {
145 .name = "sh-sci",
146 .id = 5,
147 .resource = scif5_resources,
148 .num_resources = ARRAY_SIZE(scif5_resources),
149 .dev = {
150 .platform_data = &scif5_platform_data,
151 },
152};
153
154static struct sh_timer_config tmu0_platform_data = {
155 .channels_mask = 7,
156};
157
158static struct resource tmu0_resources[] = {
159 DEFINE_RES_MEM(0xffd80000, 0x30),
160 DEFINE_RES_IRQ(evt2irq(0x580)),
161 DEFINE_RES_IRQ(evt2irq(0x5a0)),
162 DEFINE_RES_IRQ(evt2irq(0x5c0)),
163};
164
165static struct platform_device tmu0_device = {
166 .name = "sh-tmu",
167 .id = 0,
168 .dev = {
169 .platform_data = &tmu0_platform_data,
170 },
171 .resource = tmu0_resources,
172 .num_resources = ARRAY_SIZE(tmu0_resources),
173};
174
175static struct sh_timer_config tmu1_platform_data = {
176 .channels_mask = 7,
177};
178
179static struct resource tmu1_resources[] = {
180 DEFINE_RES_MEM(0xffdc0000, 0x2c),
181 DEFINE_RES_IRQ(evt2irq(0xe00)),
182 DEFINE_RES_IRQ(evt2irq(0xe20)),
183 DEFINE_RES_IRQ(evt2irq(0xe40)),
184};
185
186static struct platform_device tmu1_device = {
187 .name = "sh-tmu",
188 .id = 1,
189 .dev = {
190 .platform_data = &tmu1_platform_data,
191 },
192 .resource = tmu1_resources,
193 .num_resources = ARRAY_SIZE(tmu1_resources),
194};
195
196/* DMA */
197static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
198 {
199 .offset = 0,
200 .dmars = 0,
201 .dmars_bit = 0,
202 }, {
203 .offset = 0x10,
204 .dmars = 0,
205 .dmars_bit = 8,
206 }, {
207 .offset = 0x20,
208 .dmars = 4,
209 .dmars_bit = 0,
210 }, {
211 .offset = 0x30,
212 .dmars = 4,
213 .dmars_bit = 8,
214 }, {
215 .offset = 0x50,
216 .dmars = 8,
217 .dmars_bit = 0,
218 }, {
219 .offset = 0x60,
220 .dmars = 8,
221 .dmars_bit = 8,
222 }
223};
224
225static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
226 {
227 .offset = 0,
228 }, {
229 .offset = 0x10,
230 }, {
231 .offset = 0x20,
232 }, {
233 .offset = 0x30,
234 }, {
235 .offset = 0x50,
236 }, {
237 .offset = 0x60,
238 }
239};
240
241static const unsigned int ts_shift[] = TS_SHIFT;
242
243static struct sh_dmae_pdata dma0_platform_data = {
244 .channel = sh7785_dmae0_channels,
245 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
246 .ts_low_shift = CHCR_TS_LOW_SHIFT,
247 .ts_low_mask = CHCR_TS_LOW_MASK,
248 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
249 .ts_high_mask = CHCR_TS_HIGH_MASK,
250 .ts_shift = ts_shift,
251 .ts_shift_num = ARRAY_SIZE(ts_shift),
252 .dmaor_init = DMAOR_INIT,
253};
254
255static struct sh_dmae_pdata dma1_platform_data = {
256 .channel = sh7785_dmae1_channels,
257 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
258 .ts_low_shift = CHCR_TS_LOW_SHIFT,
259 .ts_low_mask = CHCR_TS_LOW_MASK,
260 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
261 .ts_high_mask = CHCR_TS_HIGH_MASK,
262 .ts_shift = ts_shift,
263 .ts_shift_num = ARRAY_SIZE(ts_shift),
264 .dmaor_init = DMAOR_INIT,
265};
266
267static struct resource sh7785_dmae0_resources[] = {
268 [0] = {
269 /* Channel registers and DMAOR */
270 .start = 0xfc808020,
271 .end = 0xfc80808f,
272 .flags = IORESOURCE_MEM,
273 },
274 [1] = {
275 /* DMARSx */
276 .start = 0xfc809000,
277 .end = 0xfc80900b,
278 .flags = IORESOURCE_MEM,
279 },
280 {
281 /*
282 * Real DMA error vector is 0x6e0, and channel
283 * vectors are 0x620-0x6c0
284 */
285 .name = "error_irq",
286 .start = evt2irq(0x620),
287 .end = evt2irq(0x620),
288 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
289 },
290};
291
292static struct resource sh7785_dmae1_resources[] = {
293 [0] = {
294 /* Channel registers and DMAOR */
295 .start = 0xfcc08020,
296 .end = 0xfcc0808f,
297 .flags = IORESOURCE_MEM,
298 },
299 /* DMAC1 has no DMARS */
300 {
301 /*
302 * Real DMA error vector is 0x940, and channel
303 * vectors are 0x880-0x920
304 */
305 .name = "error_irq",
306 .start = evt2irq(0x880),
307 .end = evt2irq(0x880),
308 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
309 },
310};
311
312static struct platform_device dma0_device = {
313 .name = "sh-dma-engine",
314 .id = 0,
315 .resource = sh7785_dmae0_resources,
316 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
317 .dev = {
318 .platform_data = &dma0_platform_data,
319 },
320};
321
322static struct platform_device dma1_device = {
323 .name = "sh-dma-engine",
324 .id = 1,
325 .resource = sh7785_dmae1_resources,
326 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
327 .dev = {
328 .platform_data = &dma1_platform_data,
329 },
330};
331
332static struct platform_device *sh7785_devices[] __initdata = {
333 &scif0_device,
334 &scif1_device,
335 &scif2_device,
336 &scif3_device,
337 &scif4_device,
338 &scif5_device,
339 &tmu0_device,
340 &tmu1_device,
341 &dma0_device,
342 &dma1_device,
343};
344
345static int __init sh7785_devices_setup(void)
346{
347 return platform_add_devices(sh7785_devices,
348 ARRAY_SIZE(sh7785_devices));
349}
350arch_initcall(sh7785_devices_setup);
351
352static struct platform_device *sh7785_early_devices[] __initdata = {
353 &scif0_device,
354 &scif1_device,
355 &scif2_device,
356 &scif3_device,
357 &scif4_device,
358 &scif5_device,
359 &tmu0_device,
360 &tmu1_device,
361};
362
363void __init plat_early_device_setup(void)
364{
365 early_platform_add_devices(sh7785_early_devices,
366 ARRAY_SIZE(sh7785_early_devices));
367}
368
369enum {
370 UNUSED = 0,
371
372 /* interrupt sources */
373
374 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
375 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
376 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
377 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
378
379 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
380 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
381 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
382 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
383
384 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
385 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
386 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
387 SCIF2, SCIF3, SCIF4, SCIF5,
388 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
389 SIOF, MMCIF, DU, GDTA,
390 TMU3, TMU4, TMU5,
391 SSI0, SSI1,
392 HAC0, HAC1,
393 FLCTL, GPIO,
394
395 /* interrupt groups */
396
397 TMU012, TMU345
398};
399
400static struct intc_vect vectors[] __initdata = {
401 INTC_VECT(WDT, 0x560),
402 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
403 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
404 INTC_VECT(HUDI, 0x600),
405 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
406 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
407 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
408 INTC_VECT(DMAC0, 0x6e0),
409 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
410 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
411 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
412 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
413 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
414 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
415 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
416 INTC_VECT(DMAC1, 0x940),
417 INTC_VECT(HSPI, 0x960),
418 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
419 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
420 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
421 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
422 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
423 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
424 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
425 INTC_VECT(SIOF, 0xc00),
426 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
427 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
428 INTC_VECT(DU, 0xd80),
429 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
430 INTC_VECT(GDTA, 0xde0),
431 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
432 INTC_VECT(TMU5, 0xe40),
433 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
434 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
435 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
436 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
437 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
438 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
439};
440
441static struct intc_group groups[] __initdata = {
442 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
443 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
444};
445
446static struct intc_mask_reg mask_registers[] __initdata = {
447 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
448 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
449
450 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
451 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
452 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
453 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
454 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
455 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
456 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
457 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
458 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
459
460 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
461 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
462 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
463 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
464 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
465};
466
467static struct intc_prio_reg prio_registers[] __initdata = {
468 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
469 IRQ4, IRQ5, IRQ6, IRQ7 } },
470 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
471 TMU2, TMU2_TICPI } },
472 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
473 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
474 SCIF2, SCIF3 } },
475 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
476 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
477 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
478 PCISERR, PCIINTA } },
479 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
480 PCIINTD, PCIC5 } },
481 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
482 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
483 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
484};
485
486static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
487 mask_registers, prio_registers, NULL);
488
489/* Support for external interrupt pins in IRQ mode */
490
491static struct intc_vect vectors_irq0123[] __initdata = {
492 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
493 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
494};
495
496static struct intc_vect vectors_irq4567[] __initdata = {
497 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
498 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
499};
500
501static struct intc_sense_reg sense_registers[] __initdata = {
502 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
503 IRQ4, IRQ5, IRQ6, IRQ7 } },
504};
505
506static struct intc_mask_reg ack_registers[] __initdata = {
507 { 0xffd00024, 0, 32, /* INTREQ */
508 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
509};
510
511static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
512 vectors_irq0123, NULL, mask_registers,
513 prio_registers, sense_registers, ack_registers);
514
515static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
516 vectors_irq4567, NULL, mask_registers,
517 prio_registers, sense_registers, ack_registers);
518
519/* External interrupt pins in IRL mode */
520
521static struct intc_vect vectors_irl0123[] __initdata = {
522 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
523 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
524 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
525 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
526 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
527 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
528 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
529 INTC_VECT(IRL0_HHHL, 0x3c0),
530};
531
532static struct intc_vect vectors_irl4567[] __initdata = {
533 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
534 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
535 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
536 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
537 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
538 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
539 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
540 INTC_VECT(IRL4_HHHL, 0xcc0),
541};
542
543static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
544 NULL, mask_registers, NULL, NULL);
545
546static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
547 NULL, mask_registers, NULL, NULL);
548
549#define INTC_ICR0 0xffd00000
550#define INTC_INTMSK0 0xffd00044
551#define INTC_INTMSK1 0xffd00048
552#define INTC_INTMSK2 0xffd40080
553#define INTC_INTMSKCLR1 0xffd00068
554#define INTC_INTMSKCLR2 0xffd40084
555
556void __init plat_irq_setup(void)
557{
558 /* disable IRQ3-0 + IRQ7-4 */
559 __raw_writel(0xff000000, INTC_INTMSK0);
560
561 /* disable IRL3-0 + IRL7-4 */
562 __raw_writel(0xc0000000, INTC_INTMSK1);
563 __raw_writel(0xfffefffe, INTC_INTMSK2);
564
565 /* select IRL mode for IRL3-0 + IRL7-4 */
566 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
567
568 /* disable holding function, ie enable "SH-4 Mode" */
569 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
570
571 register_intc_controller(&intc_desc);
572}
573
574void __init plat_irq_setup_pins(int mode)
575{
576 switch (mode) {
577 case IRQ_MODE_IRQ7654:
578 /* select IRQ mode for IRL7-4 */
579 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
580 register_intc_controller(&intc_desc_irq4567);
581 break;
582 case IRQ_MODE_IRQ3210:
583 /* select IRQ mode for IRL3-0 */
584 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
585 register_intc_controller(&intc_desc_irq0123);
586 break;
587 case IRQ_MODE_IRL7654:
588 /* enable IRL7-4 but don't provide any masking */
589 __raw_writel(0x40000000, INTC_INTMSKCLR1);
590 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
591 break;
592 case IRQ_MODE_IRL3210:
593 /* enable IRL0-3 but don't provide any masking */
594 __raw_writel(0x80000000, INTC_INTMSKCLR1);
595 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
596 break;
597 case IRQ_MODE_IRL7654_MASK:
598 /* enable IRL7-4 and mask using cpu intc controller */
599 __raw_writel(0x40000000, INTC_INTMSKCLR1);
600 register_intc_controller(&intc_desc_irl4567);
601 break;
602 case IRQ_MODE_IRL3210_MASK:
603 /* enable IRL0-3 and mask using cpu intc controller */
604 __raw_writel(0x80000000, INTC_INTMSKCLR1);
605 register_intc_controller(&intc_desc_irl0123);
606 break;
607 default:
608 BUG();
609 }
610}
611
612void __init plat_mem_setup(void)
613{
614 /* Register the URAM space as Node 1 */
615 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
616}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH7785 Setup
4 *
5 * Copyright (C) 2007 Paul Mundt
6 */
7#include <linux/platform_device.h>
8#include <linux/init.h>
9#include <linux/serial.h>
10#include <linux/serial_sci.h>
11#include <linux/io.h>
12#include <linux/mm.h>
13#include <linux/sh_dma.h>
14#include <linux/sh_timer.h>
15#include <linux/sh_intc.h>
16#include <asm/mmzone.h>
17#include <asm/platform_early.h>
18#include <cpu/dma-register.h>
19
20static struct plat_sci_port scif0_platform_data = {
21 .scscr = SCSCR_REIE | SCSCR_CKE1,
22 .type = PORT_SCIF,
23 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
24};
25
26static struct resource scif0_resources[] = {
27 DEFINE_RES_MEM(0xffea0000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
29};
30
31static struct platform_device scif0_device = {
32 .name = "sh-sci",
33 .id = 0,
34 .resource = scif0_resources,
35 .num_resources = ARRAY_SIZE(scif0_resources),
36 .dev = {
37 .platform_data = &scif0_platform_data,
38 },
39};
40
41static struct plat_sci_port scif1_platform_data = {
42 .scscr = SCSCR_REIE | SCSCR_CKE1,
43 .type = PORT_SCIF,
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
45};
46
47static struct resource scif1_resources[] = {
48 DEFINE_RES_MEM(0xffeb0000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x780)),
50};
51
52static struct platform_device scif1_device = {
53 .name = "sh-sci",
54 .id = 1,
55 .resource = scif1_resources,
56 .num_resources = ARRAY_SIZE(scif1_resources),
57 .dev = {
58 .platform_data = &scif1_platform_data,
59 },
60};
61
62static struct plat_sci_port scif2_platform_data = {
63 .scscr = SCSCR_REIE | SCSCR_CKE1,
64 .type = PORT_SCIF,
65 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
66};
67
68static struct resource scif2_resources[] = {
69 DEFINE_RES_MEM(0xffec0000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0x980)),
71};
72
73static struct platform_device scif2_device = {
74 .name = "sh-sci",
75 .id = 2,
76 .resource = scif2_resources,
77 .num_resources = ARRAY_SIZE(scif2_resources),
78 .dev = {
79 .platform_data = &scif2_platform_data,
80 },
81};
82
83static struct plat_sci_port scif3_platform_data = {
84 .scscr = SCSCR_REIE | SCSCR_CKE1,
85 .type = PORT_SCIF,
86 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
87};
88
89static struct resource scif3_resources[] = {
90 DEFINE_RES_MEM(0xffed0000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0x9a0)),
92};
93
94static struct platform_device scif3_device = {
95 .name = "sh-sci",
96 .id = 3,
97 .resource = scif3_resources,
98 .num_resources = ARRAY_SIZE(scif3_resources),
99 .dev = {
100 .platform_data = &scif3_platform_data,
101 },
102};
103
104static struct plat_sci_port scif4_platform_data = {
105 .scscr = SCSCR_REIE | SCSCR_CKE1,
106 .type = PORT_SCIF,
107 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
108};
109
110static struct resource scif4_resources[] = {
111 DEFINE_RES_MEM(0xffee0000, 0x100),
112 DEFINE_RES_IRQ(evt2irq(0x9c0)),
113};
114
115static struct platform_device scif4_device = {
116 .name = "sh-sci",
117 .id = 4,
118 .resource = scif4_resources,
119 .num_resources = ARRAY_SIZE(scif4_resources),
120 .dev = {
121 .platform_data = &scif4_platform_data,
122 },
123};
124
125static struct plat_sci_port scif5_platform_data = {
126 .scscr = SCSCR_REIE | SCSCR_CKE1,
127 .type = PORT_SCIF,
128 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
129};
130
131static struct resource scif5_resources[] = {
132 DEFINE_RES_MEM(0xffef0000, 0x100),
133 DEFINE_RES_IRQ(evt2irq(0x9e0)),
134};
135
136static struct platform_device scif5_device = {
137 .name = "sh-sci",
138 .id = 5,
139 .resource = scif5_resources,
140 .num_resources = ARRAY_SIZE(scif5_resources),
141 .dev = {
142 .platform_data = &scif5_platform_data,
143 },
144};
145
146static struct sh_timer_config tmu0_platform_data = {
147 .channels_mask = 7,
148};
149
150static struct resource tmu0_resources[] = {
151 DEFINE_RES_MEM(0xffd80000, 0x30),
152 DEFINE_RES_IRQ(evt2irq(0x580)),
153 DEFINE_RES_IRQ(evt2irq(0x5a0)),
154 DEFINE_RES_IRQ(evt2irq(0x5c0)),
155};
156
157static struct platform_device tmu0_device = {
158 .name = "sh-tmu",
159 .id = 0,
160 .dev = {
161 .platform_data = &tmu0_platform_data,
162 },
163 .resource = tmu0_resources,
164 .num_resources = ARRAY_SIZE(tmu0_resources),
165};
166
167static struct sh_timer_config tmu1_platform_data = {
168 .channels_mask = 7,
169};
170
171static struct resource tmu1_resources[] = {
172 DEFINE_RES_MEM(0xffdc0000, 0x2c),
173 DEFINE_RES_IRQ(evt2irq(0xe00)),
174 DEFINE_RES_IRQ(evt2irq(0xe20)),
175 DEFINE_RES_IRQ(evt2irq(0xe40)),
176};
177
178static struct platform_device tmu1_device = {
179 .name = "sh-tmu",
180 .id = 1,
181 .dev = {
182 .platform_data = &tmu1_platform_data,
183 },
184 .resource = tmu1_resources,
185 .num_resources = ARRAY_SIZE(tmu1_resources),
186};
187
188/* DMA */
189static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
190 {
191 .offset = 0,
192 .dmars = 0,
193 .dmars_bit = 0,
194 }, {
195 .offset = 0x10,
196 .dmars = 0,
197 .dmars_bit = 8,
198 }, {
199 .offset = 0x20,
200 .dmars = 4,
201 .dmars_bit = 0,
202 }, {
203 .offset = 0x30,
204 .dmars = 4,
205 .dmars_bit = 8,
206 }, {
207 .offset = 0x50,
208 .dmars = 8,
209 .dmars_bit = 0,
210 }, {
211 .offset = 0x60,
212 .dmars = 8,
213 .dmars_bit = 8,
214 }
215};
216
217static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
218 {
219 .offset = 0,
220 }, {
221 .offset = 0x10,
222 }, {
223 .offset = 0x20,
224 }, {
225 .offset = 0x30,
226 }, {
227 .offset = 0x50,
228 }, {
229 .offset = 0x60,
230 }
231};
232
233static const unsigned int ts_shift[] = TS_SHIFT;
234
235static struct sh_dmae_pdata dma0_platform_data = {
236 .channel = sh7785_dmae0_channels,
237 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
238 .ts_low_shift = CHCR_TS_LOW_SHIFT,
239 .ts_low_mask = CHCR_TS_LOW_MASK,
240 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
241 .ts_high_mask = CHCR_TS_HIGH_MASK,
242 .ts_shift = ts_shift,
243 .ts_shift_num = ARRAY_SIZE(ts_shift),
244 .dmaor_init = DMAOR_INIT,
245};
246
247static struct sh_dmae_pdata dma1_platform_data = {
248 .channel = sh7785_dmae1_channels,
249 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
250 .ts_low_shift = CHCR_TS_LOW_SHIFT,
251 .ts_low_mask = CHCR_TS_LOW_MASK,
252 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
253 .ts_high_mask = CHCR_TS_HIGH_MASK,
254 .ts_shift = ts_shift,
255 .ts_shift_num = ARRAY_SIZE(ts_shift),
256 .dmaor_init = DMAOR_INIT,
257};
258
259static struct resource sh7785_dmae0_resources[] = {
260 [0] = {
261 /* Channel registers and DMAOR */
262 .start = 0xfc808020,
263 .end = 0xfc80808f,
264 .flags = IORESOURCE_MEM,
265 },
266 [1] = {
267 /* DMARSx */
268 .start = 0xfc809000,
269 .end = 0xfc80900b,
270 .flags = IORESOURCE_MEM,
271 },
272 {
273 /*
274 * Real DMA error vector is 0x6e0, and channel
275 * vectors are 0x620-0x6c0
276 */
277 .name = "error_irq",
278 .start = evt2irq(0x620),
279 .end = evt2irq(0x620),
280 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
281 },
282};
283
284static struct resource sh7785_dmae1_resources[] = {
285 [0] = {
286 /* Channel registers and DMAOR */
287 .start = 0xfcc08020,
288 .end = 0xfcc0808f,
289 .flags = IORESOURCE_MEM,
290 },
291 /* DMAC1 has no DMARS */
292 {
293 /*
294 * Real DMA error vector is 0x940, and channel
295 * vectors are 0x880-0x920
296 */
297 .name = "error_irq",
298 .start = evt2irq(0x880),
299 .end = evt2irq(0x880),
300 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
301 },
302};
303
304static struct platform_device dma0_device = {
305 .name = "sh-dma-engine",
306 .id = 0,
307 .resource = sh7785_dmae0_resources,
308 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
309 .dev = {
310 .platform_data = &dma0_platform_data,
311 },
312};
313
314static struct platform_device dma1_device = {
315 .name = "sh-dma-engine",
316 .id = 1,
317 .resource = sh7785_dmae1_resources,
318 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
319 .dev = {
320 .platform_data = &dma1_platform_data,
321 },
322};
323
324static struct platform_device *sh7785_devices[] __initdata = {
325 &scif0_device,
326 &scif1_device,
327 &scif2_device,
328 &scif3_device,
329 &scif4_device,
330 &scif5_device,
331 &tmu0_device,
332 &tmu1_device,
333 &dma0_device,
334 &dma1_device,
335};
336
337static int __init sh7785_devices_setup(void)
338{
339 return platform_add_devices(sh7785_devices,
340 ARRAY_SIZE(sh7785_devices));
341}
342arch_initcall(sh7785_devices_setup);
343
344static struct platform_device *sh7785_early_devices[] __initdata = {
345 &scif0_device,
346 &scif1_device,
347 &scif2_device,
348 &scif3_device,
349 &scif4_device,
350 &scif5_device,
351 &tmu0_device,
352 &tmu1_device,
353};
354
355void __init plat_early_device_setup(void)
356{
357 sh_early_platform_add_devices(sh7785_early_devices,
358 ARRAY_SIZE(sh7785_early_devices));
359}
360
361enum {
362 UNUSED = 0,
363
364 /* interrupt sources */
365
366 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
367 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
368 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
369 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
370
371 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
372 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
373 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
374 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
375
376 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
377 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
378 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
379 SCIF2, SCIF3, SCIF4, SCIF5,
380 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
381 SIOF, MMCIF, DU, GDTA,
382 TMU3, TMU4, TMU5,
383 SSI0, SSI1,
384 HAC0, HAC1,
385 FLCTL, GPIO,
386
387 /* interrupt groups */
388
389 TMU012, TMU345
390};
391
392static struct intc_vect vectors[] __initdata = {
393 INTC_VECT(WDT, 0x560),
394 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
395 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
396 INTC_VECT(HUDI, 0x600),
397 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
398 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
399 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
400 INTC_VECT(DMAC0, 0x6e0),
401 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
402 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
403 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
404 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
405 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
406 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
407 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
408 INTC_VECT(DMAC1, 0x940),
409 INTC_VECT(HSPI, 0x960),
410 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
411 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
412 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
413 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
414 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
415 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
416 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
417 INTC_VECT(SIOF, 0xc00),
418 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
419 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
420 INTC_VECT(DU, 0xd80),
421 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
422 INTC_VECT(GDTA, 0xde0),
423 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
424 INTC_VECT(TMU5, 0xe40),
425 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
426 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
427 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
428 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
429 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
430 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
431};
432
433static struct intc_group groups[] __initdata = {
434 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
435 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
436};
437
438static struct intc_mask_reg mask_registers[] __initdata = {
439 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
440 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
441
442 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
443 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
444 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
445 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
446 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
447 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
448 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
449 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
450 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
451
452 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
453 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
454 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
455 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
456 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
457};
458
459static struct intc_prio_reg prio_registers[] __initdata = {
460 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
461 IRQ4, IRQ5, IRQ6, IRQ7 } },
462 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
463 TMU2, TMU2_TICPI } },
464 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
465 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
466 SCIF2, SCIF3 } },
467 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
468 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
469 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
470 PCISERR, PCIINTA } },
471 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
472 PCIINTD, PCIC5 } },
473 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
474 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
475 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
476};
477
478static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
479 mask_registers, prio_registers, NULL);
480
481/* Support for external interrupt pins in IRQ mode */
482
483static struct intc_vect vectors_irq0123[] __initdata = {
484 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
485 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
486};
487
488static struct intc_vect vectors_irq4567[] __initdata = {
489 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
490 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
491};
492
493static struct intc_sense_reg sense_registers[] __initdata = {
494 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
495 IRQ4, IRQ5, IRQ6, IRQ7 } },
496};
497
498static struct intc_mask_reg ack_registers[] __initdata = {
499 { 0xffd00024, 0, 32, /* INTREQ */
500 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
501};
502
503static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
504 vectors_irq0123, NULL, mask_registers,
505 prio_registers, sense_registers, ack_registers);
506
507static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
508 vectors_irq4567, NULL, mask_registers,
509 prio_registers, sense_registers, ack_registers);
510
511/* External interrupt pins in IRL mode */
512
513static struct intc_vect vectors_irl0123[] __initdata = {
514 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
515 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
516 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
517 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
518 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
519 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
520 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
521 INTC_VECT(IRL0_HHHL, 0x3c0),
522};
523
524static struct intc_vect vectors_irl4567[] __initdata = {
525 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
526 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
527 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
528 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
529 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
530 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
531 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
532 INTC_VECT(IRL4_HHHL, 0xcc0),
533};
534
535static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
536 NULL, mask_registers, NULL, NULL);
537
538static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
539 NULL, mask_registers, NULL, NULL);
540
541#define INTC_ICR0 0xffd00000
542#define INTC_INTMSK0 0xffd00044
543#define INTC_INTMSK1 0xffd00048
544#define INTC_INTMSK2 0xffd40080
545#define INTC_INTMSKCLR1 0xffd00068
546#define INTC_INTMSKCLR2 0xffd40084
547
548void __init plat_irq_setup(void)
549{
550 /* disable IRQ3-0 + IRQ7-4 */
551 __raw_writel(0xff000000, INTC_INTMSK0);
552
553 /* disable IRL3-0 + IRL7-4 */
554 __raw_writel(0xc0000000, INTC_INTMSK1);
555 __raw_writel(0xfffefffe, INTC_INTMSK2);
556
557 /* select IRL mode for IRL3-0 + IRL7-4 */
558 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
559
560 /* disable holding function, ie enable "SH-4 Mode" */
561 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
562
563 register_intc_controller(&intc_desc);
564}
565
566void __init plat_irq_setup_pins(int mode)
567{
568 switch (mode) {
569 case IRQ_MODE_IRQ7654:
570 /* select IRQ mode for IRL7-4 */
571 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
572 register_intc_controller(&intc_desc_irq4567);
573 break;
574 case IRQ_MODE_IRQ3210:
575 /* select IRQ mode for IRL3-0 */
576 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
577 register_intc_controller(&intc_desc_irq0123);
578 break;
579 case IRQ_MODE_IRL7654:
580 /* enable IRL7-4 but don't provide any masking */
581 __raw_writel(0x40000000, INTC_INTMSKCLR1);
582 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
583 break;
584 case IRQ_MODE_IRL3210:
585 /* enable IRL0-3 but don't provide any masking */
586 __raw_writel(0x80000000, INTC_INTMSKCLR1);
587 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
588 break;
589 case IRQ_MODE_IRL7654_MASK:
590 /* enable IRL7-4 and mask using cpu intc controller */
591 __raw_writel(0x40000000, INTC_INTMSKCLR1);
592 register_intc_controller(&intc_desc_irl4567);
593 break;
594 case IRQ_MODE_IRL3210_MASK:
595 /* enable IRL0-3 and mask using cpu intc controller */
596 __raw_writel(0x80000000, INTC_INTMSKCLR1);
597 register_intc_controller(&intc_desc_irl0123);
598 break;
599 default:
600 BUG();
601 }
602}
603
604void __init plat_mem_setup(void)
605{
606 /* Register the URAM space as Node 1 */
607 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
608}