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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "radeon.h"
30#include <drm/radeon_drm.h>
31#include "radeon_asic.h"
32
33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h>
35#include <linux/pm_runtime.h>
36
37#include "radeon_kfd.h"
38
39#if defined(CONFIG_VGA_SWITCHEROO)
40bool radeon_has_atpx(void);
41#else
42static inline bool radeon_has_atpx(void) { return false; }
43#endif
44
45/**
46 * radeon_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * It calls radeon_modeset_fini() to tear down the
52 * displays, and radeon_device_fini() to tear down
53 * the rest of the device (CP, writeback, etc.).
54 * Returns 0 on success.
55 */
56int radeon_driver_unload_kms(struct drm_device *dev)
57{
58 struct radeon_device *rdev = dev->dev_private;
59
60 if (rdev == NULL)
61 return 0;
62
63 if (rdev->rmmio == NULL)
64 goto done_free;
65
66 pm_runtime_get_sync(dev->dev);
67
68 radeon_kfd_device_fini(rdev);
69
70 radeon_acpi_fini(rdev);
71
72 radeon_modeset_fini(rdev);
73 radeon_device_fini(rdev);
74
75done_free:
76 kfree(rdev);
77 dev->dev_private = NULL;
78 return 0;
79}
80
81/**
82 * radeon_driver_load_kms - Main load function for KMS.
83 *
84 * @dev: drm dev pointer
85 * @flags: device flags
86 *
87 * This is the main load function for KMS (all asics).
88 * It calls radeon_device_init() to set up the non-display
89 * parts of the chip (asic init, CP, writeback, etc.), and
90 * radeon_modeset_init() to set up the display parts
91 * (crtcs, encoders, hotplug detect, etc.).
92 * Returns 0 on success, error on failure.
93 */
94int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
95{
96 struct radeon_device *rdev;
97 int r, acpi_status;
98
99 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
100 if (rdev == NULL) {
101 return -ENOMEM;
102 }
103 dev->dev_private = (void *)rdev;
104
105 /* update BUS flag */
106 if (drm_pci_device_is_agp(dev)) {
107 flags |= RADEON_IS_AGP;
108 } else if (pci_is_pcie(dev->pdev)) {
109 flags |= RADEON_IS_PCIE;
110 } else {
111 flags |= RADEON_IS_PCI;
112 }
113
114 if ((radeon_runtime_pm != 0) &&
115 radeon_has_atpx() &&
116 ((flags & RADEON_IS_IGP) == 0))
117 flags |= RADEON_IS_PX;
118
119 /* radeon_device_init should report only fatal error
120 * like memory allocation failure or iomapping failure,
121 * or memory manager initialization failure, it must
122 * properly initialize the GPU MC controller and permit
123 * VRAM allocation
124 */
125 r = radeon_device_init(rdev, dev, dev->pdev, flags);
126 if (r) {
127 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
128 goto out;
129 }
130
131 /* Again modeset_init should fail only on fatal error
132 * otherwise it should provide enough functionalities
133 * for shadowfb to run
134 */
135 r = radeon_modeset_init(rdev);
136 if (r)
137 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
138
139 /* Call ACPI methods: require modeset init
140 * but failure is not fatal
141 */
142 if (!r) {
143 acpi_status = radeon_acpi_init(rdev);
144 if (acpi_status)
145 dev_dbg(&dev->pdev->dev,
146 "Error during ACPI methods call\n");
147 }
148
149 radeon_kfd_device_probe(rdev);
150 radeon_kfd_device_init(rdev);
151
152 if (radeon_is_px(dev)) {
153 pm_runtime_use_autosuspend(dev->dev);
154 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
155 pm_runtime_set_active(dev->dev);
156 pm_runtime_allow(dev->dev);
157 pm_runtime_mark_last_busy(dev->dev);
158 pm_runtime_put_autosuspend(dev->dev);
159 }
160
161out:
162 if (r)
163 radeon_driver_unload_kms(dev);
164
165
166 return r;
167}
168
169/**
170 * radeon_set_filp_rights - Set filp right.
171 *
172 * @dev: drm dev pointer
173 * @owner: drm file
174 * @applier: drm file
175 * @value: value
176 *
177 * Sets the filp rights for the device (all asics).
178 */
179static void radeon_set_filp_rights(struct drm_device *dev,
180 struct drm_file **owner,
181 struct drm_file *applier,
182 uint32_t *value)
183{
184 struct radeon_device *rdev = dev->dev_private;
185
186 mutex_lock(&rdev->gem.mutex);
187 if (*value == 1) {
188 /* wants rights */
189 if (!*owner)
190 *owner = applier;
191 } else if (*value == 0) {
192 /* revokes rights */
193 if (*owner == applier)
194 *owner = NULL;
195 }
196 *value = *owner == applier ? 1 : 0;
197 mutex_unlock(&rdev->gem.mutex);
198}
199
200/*
201 * Userspace get information ioctl
202 */
203/**
204 * radeon_info_ioctl - answer a device specific request.
205 *
206 * @rdev: radeon device pointer
207 * @data: request object
208 * @filp: drm filp
209 *
210 * This function is used to pass device specific parameters to the userspace
211 * drivers. Examples include: pci device id, pipeline parms, tiling params,
212 * etc. (all asics).
213 * Returns 0 on success, -EINVAL on failure.
214 */
215static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
216{
217 struct radeon_device *rdev = dev->dev_private;
218 struct drm_radeon_info *info = data;
219 struct radeon_mode_info *minfo = &rdev->mode_info;
220 uint32_t *value, value_tmp, *value_ptr, value_size;
221 uint64_t value64;
222 struct drm_crtc *crtc;
223 int i, found;
224
225 value_ptr = (uint32_t *)((unsigned long)info->value);
226 value = &value_tmp;
227 value_size = sizeof(uint32_t);
228
229 switch (info->request) {
230 case RADEON_INFO_DEVICE_ID:
231 *value = dev->pdev->device;
232 break;
233 case RADEON_INFO_NUM_GB_PIPES:
234 *value = rdev->num_gb_pipes;
235 break;
236 case RADEON_INFO_NUM_Z_PIPES:
237 *value = rdev->num_z_pipes;
238 break;
239 case RADEON_INFO_ACCEL_WORKING:
240 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
241 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
242 *value = false;
243 else
244 *value = rdev->accel_working;
245 break;
246 case RADEON_INFO_CRTC_FROM_ID:
247 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
248 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
249 return -EFAULT;
250 }
251 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
252 crtc = (struct drm_crtc *)minfo->crtcs[i];
253 if (crtc && crtc->base.id == *value) {
254 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
255 *value = radeon_crtc->crtc_id;
256 found = 1;
257 break;
258 }
259 }
260 if (!found) {
261 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
262 return -EINVAL;
263 }
264 break;
265 case RADEON_INFO_ACCEL_WORKING2:
266 if (rdev->family == CHIP_HAWAII) {
267 if (rdev->accel_working) {
268 if (rdev->new_fw)
269 *value = 3;
270 else
271 *value = 2;
272 } else {
273 *value = 0;
274 }
275 } else {
276 *value = rdev->accel_working;
277 }
278 break;
279 case RADEON_INFO_TILING_CONFIG:
280 if (rdev->family >= CHIP_BONAIRE)
281 *value = rdev->config.cik.tile_config;
282 else if (rdev->family >= CHIP_TAHITI)
283 *value = rdev->config.si.tile_config;
284 else if (rdev->family >= CHIP_CAYMAN)
285 *value = rdev->config.cayman.tile_config;
286 else if (rdev->family >= CHIP_CEDAR)
287 *value = rdev->config.evergreen.tile_config;
288 else if (rdev->family >= CHIP_RV770)
289 *value = rdev->config.rv770.tile_config;
290 else if (rdev->family >= CHIP_R600)
291 *value = rdev->config.r600.tile_config;
292 else {
293 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
294 return -EINVAL;
295 }
296 break;
297 case RADEON_INFO_WANT_HYPERZ:
298 /* The "value" here is both an input and output parameter.
299 * If the input value is 1, filp requests hyper-z access.
300 * If the input value is 0, filp revokes its hyper-z access.
301 *
302 * When returning, the value is 1 if filp owns hyper-z access,
303 * 0 otherwise. */
304 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
305 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
306 return -EFAULT;
307 }
308 if (*value >= 2) {
309 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
310 return -EINVAL;
311 }
312 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
313 break;
314 case RADEON_INFO_WANT_CMASK:
315 /* The same logic as Hyper-Z. */
316 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
317 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
318 return -EFAULT;
319 }
320 if (*value >= 2) {
321 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
322 return -EINVAL;
323 }
324 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
325 break;
326 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
327 /* return clock value in KHz */
328 if (rdev->asic->get_xclk)
329 *value = radeon_get_xclk(rdev) * 10;
330 else
331 *value = rdev->clock.spll.reference_freq * 10;
332 break;
333 case RADEON_INFO_NUM_BACKENDS:
334 if (rdev->family >= CHIP_BONAIRE)
335 *value = rdev->config.cik.max_backends_per_se *
336 rdev->config.cik.max_shader_engines;
337 else if (rdev->family >= CHIP_TAHITI)
338 *value = rdev->config.si.max_backends_per_se *
339 rdev->config.si.max_shader_engines;
340 else if (rdev->family >= CHIP_CAYMAN)
341 *value = rdev->config.cayman.max_backends_per_se *
342 rdev->config.cayman.max_shader_engines;
343 else if (rdev->family >= CHIP_CEDAR)
344 *value = rdev->config.evergreen.max_backends;
345 else if (rdev->family >= CHIP_RV770)
346 *value = rdev->config.rv770.max_backends;
347 else if (rdev->family >= CHIP_R600)
348 *value = rdev->config.r600.max_backends;
349 else {
350 return -EINVAL;
351 }
352 break;
353 case RADEON_INFO_NUM_TILE_PIPES:
354 if (rdev->family >= CHIP_BONAIRE)
355 *value = rdev->config.cik.max_tile_pipes;
356 else if (rdev->family >= CHIP_TAHITI)
357 *value = rdev->config.si.max_tile_pipes;
358 else if (rdev->family >= CHIP_CAYMAN)
359 *value = rdev->config.cayman.max_tile_pipes;
360 else if (rdev->family >= CHIP_CEDAR)
361 *value = rdev->config.evergreen.max_tile_pipes;
362 else if (rdev->family >= CHIP_RV770)
363 *value = rdev->config.rv770.max_tile_pipes;
364 else if (rdev->family >= CHIP_R600)
365 *value = rdev->config.r600.max_tile_pipes;
366 else {
367 return -EINVAL;
368 }
369 break;
370 case RADEON_INFO_FUSION_GART_WORKING:
371 *value = 1;
372 break;
373 case RADEON_INFO_BACKEND_MAP:
374 if (rdev->family >= CHIP_BONAIRE)
375 *value = rdev->config.cik.backend_map;
376 else if (rdev->family >= CHIP_TAHITI)
377 *value = rdev->config.si.backend_map;
378 else if (rdev->family >= CHIP_CAYMAN)
379 *value = rdev->config.cayman.backend_map;
380 else if (rdev->family >= CHIP_CEDAR)
381 *value = rdev->config.evergreen.backend_map;
382 else if (rdev->family >= CHIP_RV770)
383 *value = rdev->config.rv770.backend_map;
384 else if (rdev->family >= CHIP_R600)
385 *value = rdev->config.r600.backend_map;
386 else {
387 return -EINVAL;
388 }
389 break;
390 case RADEON_INFO_VA_START:
391 /* this is where we report if vm is supported or not */
392 if (rdev->family < CHIP_CAYMAN)
393 return -EINVAL;
394 *value = RADEON_VA_RESERVED_SIZE;
395 break;
396 case RADEON_INFO_IB_VM_MAX_SIZE:
397 /* this is where we report if vm is supported or not */
398 if (rdev->family < CHIP_CAYMAN)
399 return -EINVAL;
400 *value = RADEON_IB_VM_MAX_SIZE;
401 break;
402 case RADEON_INFO_MAX_PIPES:
403 if (rdev->family >= CHIP_BONAIRE)
404 *value = rdev->config.cik.max_cu_per_sh;
405 else if (rdev->family >= CHIP_TAHITI)
406 *value = rdev->config.si.max_cu_per_sh;
407 else if (rdev->family >= CHIP_CAYMAN)
408 *value = rdev->config.cayman.max_pipes_per_simd;
409 else if (rdev->family >= CHIP_CEDAR)
410 *value = rdev->config.evergreen.max_pipes;
411 else if (rdev->family >= CHIP_RV770)
412 *value = rdev->config.rv770.max_pipes;
413 else if (rdev->family >= CHIP_R600)
414 *value = rdev->config.r600.max_pipes;
415 else {
416 return -EINVAL;
417 }
418 break;
419 case RADEON_INFO_TIMESTAMP:
420 if (rdev->family < CHIP_R600) {
421 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
422 return -EINVAL;
423 }
424 value = (uint32_t*)&value64;
425 value_size = sizeof(uint64_t);
426 value64 = radeon_get_gpu_clock_counter(rdev);
427 break;
428 case RADEON_INFO_MAX_SE:
429 if (rdev->family >= CHIP_BONAIRE)
430 *value = rdev->config.cik.max_shader_engines;
431 else if (rdev->family >= CHIP_TAHITI)
432 *value = rdev->config.si.max_shader_engines;
433 else if (rdev->family >= CHIP_CAYMAN)
434 *value = rdev->config.cayman.max_shader_engines;
435 else if (rdev->family >= CHIP_CEDAR)
436 *value = rdev->config.evergreen.num_ses;
437 else
438 *value = 1;
439 break;
440 case RADEON_INFO_MAX_SH_PER_SE:
441 if (rdev->family >= CHIP_BONAIRE)
442 *value = rdev->config.cik.max_sh_per_se;
443 else if (rdev->family >= CHIP_TAHITI)
444 *value = rdev->config.si.max_sh_per_se;
445 else
446 return -EINVAL;
447 break;
448 case RADEON_INFO_FASTFB_WORKING:
449 *value = rdev->fastfb_working;
450 break;
451 case RADEON_INFO_RING_WORKING:
452 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
453 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
454 return -EFAULT;
455 }
456 switch (*value) {
457 case RADEON_CS_RING_GFX:
458 case RADEON_CS_RING_COMPUTE:
459 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
460 break;
461 case RADEON_CS_RING_DMA:
462 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
463 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
464 break;
465 case RADEON_CS_RING_UVD:
466 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
467 break;
468 case RADEON_CS_RING_VCE:
469 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
470 break;
471 default:
472 return -EINVAL;
473 }
474 break;
475 case RADEON_INFO_SI_TILE_MODE_ARRAY:
476 if (rdev->family >= CHIP_BONAIRE) {
477 value = rdev->config.cik.tile_mode_array;
478 value_size = sizeof(uint32_t)*32;
479 } else if (rdev->family >= CHIP_TAHITI) {
480 value = rdev->config.si.tile_mode_array;
481 value_size = sizeof(uint32_t)*32;
482 } else {
483 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
484 return -EINVAL;
485 }
486 break;
487 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
488 if (rdev->family >= CHIP_BONAIRE) {
489 value = rdev->config.cik.macrotile_mode_array;
490 value_size = sizeof(uint32_t)*16;
491 } else {
492 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
493 return -EINVAL;
494 }
495 break;
496 case RADEON_INFO_SI_CP_DMA_COMPUTE:
497 *value = 1;
498 break;
499 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
500 if (rdev->family >= CHIP_BONAIRE) {
501 *value = rdev->config.cik.backend_enable_mask;
502 } else if (rdev->family >= CHIP_TAHITI) {
503 *value = rdev->config.si.backend_enable_mask;
504 } else {
505 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
506 }
507 break;
508 case RADEON_INFO_MAX_SCLK:
509 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
510 rdev->pm.dpm_enabled)
511 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
512 else
513 *value = rdev->pm.default_sclk * 10;
514 break;
515 case RADEON_INFO_VCE_FW_VERSION:
516 *value = rdev->vce.fw_version;
517 break;
518 case RADEON_INFO_VCE_FB_VERSION:
519 *value = rdev->vce.fb_version;
520 break;
521 case RADEON_INFO_NUM_BYTES_MOVED:
522 value = (uint32_t*)&value64;
523 value_size = sizeof(uint64_t);
524 value64 = atomic64_read(&rdev->num_bytes_moved);
525 break;
526 case RADEON_INFO_VRAM_USAGE:
527 value = (uint32_t*)&value64;
528 value_size = sizeof(uint64_t);
529 value64 = atomic64_read(&rdev->vram_usage);
530 break;
531 case RADEON_INFO_GTT_USAGE:
532 value = (uint32_t*)&value64;
533 value_size = sizeof(uint64_t);
534 value64 = atomic64_read(&rdev->gtt_usage);
535 break;
536 case RADEON_INFO_ACTIVE_CU_COUNT:
537 if (rdev->family >= CHIP_BONAIRE)
538 *value = rdev->config.cik.active_cus;
539 else if (rdev->family >= CHIP_TAHITI)
540 *value = rdev->config.si.active_cus;
541 else if (rdev->family >= CHIP_CAYMAN)
542 *value = rdev->config.cayman.active_simds;
543 else if (rdev->family >= CHIP_CEDAR)
544 *value = rdev->config.evergreen.active_simds;
545 else if (rdev->family >= CHIP_RV770)
546 *value = rdev->config.rv770.active_simds;
547 else if (rdev->family >= CHIP_R600)
548 *value = rdev->config.r600.active_simds;
549 else
550 *value = 1;
551 break;
552 case RADEON_INFO_CURRENT_GPU_TEMP:
553 /* get temperature in millidegrees C */
554 if (rdev->asic->pm.get_temperature)
555 *value = radeon_get_temperature(rdev);
556 else
557 *value = 0;
558 break;
559 case RADEON_INFO_CURRENT_GPU_SCLK:
560 /* get sclk in Mhz */
561 if (rdev->pm.dpm_enabled)
562 *value = radeon_dpm_get_current_sclk(rdev) / 100;
563 else
564 *value = rdev->pm.current_sclk / 100;
565 break;
566 case RADEON_INFO_CURRENT_GPU_MCLK:
567 /* get mclk in Mhz */
568 if (rdev->pm.dpm_enabled)
569 *value = radeon_dpm_get_current_mclk(rdev) / 100;
570 else
571 *value = rdev->pm.current_mclk / 100;
572 break;
573 case RADEON_INFO_READ_REG:
574 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
575 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
576 return -EFAULT;
577 }
578 if (radeon_get_allowed_info_register(rdev, *value, value))
579 return -EINVAL;
580 break;
581 case RADEON_INFO_VA_UNMAP_WORKING:
582 *value = true;
583 break;
584 case RADEON_INFO_GPU_RESET_COUNTER:
585 *value = atomic_read(&rdev->gpu_reset_counter);
586 break;
587 default:
588 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
589 return -EINVAL;
590 }
591 if (copy_to_user(value_ptr, (char*)value, value_size)) {
592 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
593 return -EFAULT;
594 }
595 return 0;
596}
597
598
599/*
600 * Outdated mess for old drm with Xorg being in charge (void function now).
601 */
602/**
603 * radeon_driver_lastclose_kms - drm callback for last close
604 *
605 * @dev: drm dev pointer
606 *
607 * Switch vga_switcheroo state after last close (all asics).
608 */
609void radeon_driver_lastclose_kms(struct drm_device *dev)
610{
611 struct radeon_device *rdev = dev->dev_private;
612
613 radeon_fbdev_restore_mode(rdev);
614 vga_switcheroo_process_delayed_switch();
615}
616
617/**
618 * radeon_driver_open_kms - drm callback for open
619 *
620 * @dev: drm dev pointer
621 * @file_priv: drm file
622 *
623 * On device open, init vm on cayman+ (all asics).
624 * Returns 0 on success, error on failure.
625 */
626int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
627{
628 struct radeon_device *rdev = dev->dev_private;
629 int r;
630
631 file_priv->driver_priv = NULL;
632
633 r = pm_runtime_get_sync(dev->dev);
634 if (r < 0)
635 return r;
636
637 /* new gpu have virtual address space support */
638 if (rdev->family >= CHIP_CAYMAN) {
639 struct radeon_fpriv *fpriv;
640 struct radeon_vm *vm;
641 int r;
642
643 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
644 if (unlikely(!fpriv)) {
645 return -ENOMEM;
646 }
647
648 if (rdev->accel_working) {
649 vm = &fpriv->vm;
650 r = radeon_vm_init(rdev, vm);
651 if (r) {
652 kfree(fpriv);
653 return r;
654 }
655
656 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
657 if (r) {
658 radeon_vm_fini(rdev, vm);
659 kfree(fpriv);
660 return r;
661 }
662
663 /* map the ib pool buffer read only into
664 * virtual address space */
665 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
666 rdev->ring_tmp_bo.bo);
667 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
668 RADEON_VA_IB_OFFSET,
669 RADEON_VM_PAGE_READABLE |
670 RADEON_VM_PAGE_SNOOPED);
671 if (r) {
672 radeon_vm_fini(rdev, vm);
673 kfree(fpriv);
674 return r;
675 }
676 }
677 file_priv->driver_priv = fpriv;
678 }
679
680 pm_runtime_mark_last_busy(dev->dev);
681 pm_runtime_put_autosuspend(dev->dev);
682 return 0;
683}
684
685/**
686 * radeon_driver_postclose_kms - drm callback for post close
687 *
688 * @dev: drm dev pointer
689 * @file_priv: drm file
690 *
691 * On device post close, tear down vm on cayman+ (all asics).
692 */
693void radeon_driver_postclose_kms(struct drm_device *dev,
694 struct drm_file *file_priv)
695{
696 struct radeon_device *rdev = dev->dev_private;
697
698 /* new gpu have virtual address space support */
699 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
700 struct radeon_fpriv *fpriv = file_priv->driver_priv;
701 struct radeon_vm *vm = &fpriv->vm;
702 int r;
703
704 if (rdev->accel_working) {
705 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
706 if (!r) {
707 if (vm->ib_bo_va)
708 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
709 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
710 }
711 radeon_vm_fini(rdev, vm);
712 }
713
714 kfree(fpriv);
715 file_priv->driver_priv = NULL;
716 }
717}
718
719/**
720 * radeon_driver_preclose_kms - drm callback for pre close
721 *
722 * @dev: drm dev pointer
723 * @file_priv: drm file
724 *
725 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
726 * (all asics).
727 */
728void radeon_driver_preclose_kms(struct drm_device *dev,
729 struct drm_file *file_priv)
730{
731 struct radeon_device *rdev = dev->dev_private;
732
733 mutex_lock(&rdev->gem.mutex);
734 if (rdev->hyperz_filp == file_priv)
735 rdev->hyperz_filp = NULL;
736 if (rdev->cmask_filp == file_priv)
737 rdev->cmask_filp = NULL;
738 mutex_unlock(&rdev->gem.mutex);
739
740 radeon_uvd_free_handles(rdev, file_priv);
741 radeon_vce_free_handles(rdev, file_priv);
742}
743
744/*
745 * VBlank related functions.
746 */
747/**
748 * radeon_get_vblank_counter_kms - get frame count
749 *
750 * @dev: drm dev pointer
751 * @pipe: crtc to get the frame count from
752 *
753 * Gets the frame count on the requested crtc (all asics).
754 * Returns frame count on success, -EINVAL on failure.
755 */
756u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
757{
758 int vpos, hpos, stat;
759 u32 count;
760 struct radeon_device *rdev = dev->dev_private;
761
762 if (pipe >= rdev->num_crtc) {
763 DRM_ERROR("Invalid crtc %u\n", pipe);
764 return -EINVAL;
765 }
766
767 /* The hw increments its frame counter at start of vsync, not at start
768 * of vblank, as is required by DRM core vblank counter handling.
769 * Cook the hw count here to make it appear to the caller as if it
770 * incremented at start of vblank. We measure distance to start of
771 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
772 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
773 * result by 1 to give the proper appearance to caller.
774 */
775 if (rdev->mode_info.crtcs[pipe]) {
776 /* Repeat readout if needed to provide stable result if
777 * we cross start of vsync during the queries.
778 */
779 do {
780 count = radeon_get_vblank_counter(rdev, pipe);
781 /* Ask radeon_get_crtc_scanoutpos to return vpos as
782 * distance to start of vblank, instead of regular
783 * vertical scanout pos.
784 */
785 stat = radeon_get_crtc_scanoutpos(
786 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
787 &vpos, &hpos, NULL, NULL,
788 &rdev->mode_info.crtcs[pipe]->base.hwmode);
789 } while (count != radeon_get_vblank_counter(rdev, pipe));
790
791 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
792 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
793 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
794 }
795 else {
796 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
797 pipe, vpos);
798
799 /* Bump counter if we are at >= leading edge of vblank,
800 * but before vsync where vpos would turn negative and
801 * the hw counter really increments.
802 */
803 if (vpos >= 0)
804 count++;
805 }
806 }
807 else {
808 /* Fallback to use value as is. */
809 count = radeon_get_vblank_counter(rdev, pipe);
810 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
811 }
812
813 return count;
814}
815
816/**
817 * radeon_enable_vblank_kms - enable vblank interrupt
818 *
819 * @dev: drm dev pointer
820 * @crtc: crtc to enable vblank interrupt for
821 *
822 * Enable the interrupt on the requested crtc (all asics).
823 * Returns 0 on success, -EINVAL on failure.
824 */
825int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
826{
827 struct radeon_device *rdev = dev->dev_private;
828 unsigned long irqflags;
829 int r;
830
831 if (crtc < 0 || crtc >= rdev->num_crtc) {
832 DRM_ERROR("Invalid crtc %d\n", crtc);
833 return -EINVAL;
834 }
835
836 spin_lock_irqsave(&rdev->irq.lock, irqflags);
837 rdev->irq.crtc_vblank_int[crtc] = true;
838 r = radeon_irq_set(rdev);
839 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
840 return r;
841}
842
843/**
844 * radeon_disable_vblank_kms - disable vblank interrupt
845 *
846 * @dev: drm dev pointer
847 * @crtc: crtc to disable vblank interrupt for
848 *
849 * Disable the interrupt on the requested crtc (all asics).
850 */
851void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
852{
853 struct radeon_device *rdev = dev->dev_private;
854 unsigned long irqflags;
855
856 if (crtc < 0 || crtc >= rdev->num_crtc) {
857 DRM_ERROR("Invalid crtc %d\n", crtc);
858 return;
859 }
860
861 spin_lock_irqsave(&rdev->irq.lock, irqflags);
862 rdev->irq.crtc_vblank_int[crtc] = false;
863 radeon_irq_set(rdev);
864 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
865}
866
867/**
868 * radeon_get_vblank_timestamp_kms - get vblank timestamp
869 *
870 * @dev: drm dev pointer
871 * @crtc: crtc to get the timestamp for
872 * @max_error: max error
873 * @vblank_time: time value
874 * @flags: flags passed to the driver
875 *
876 * Gets the timestamp on the requested crtc based on the
877 * scanout position. (all asics).
878 * Returns postive status flags on success, negative error on failure.
879 */
880int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
881 int *max_error,
882 struct timeval *vblank_time,
883 unsigned flags)
884{
885 struct drm_crtc *drmcrtc;
886 struct radeon_device *rdev = dev->dev_private;
887
888 if (crtc < 0 || crtc >= dev->num_crtcs) {
889 DRM_ERROR("Invalid crtc %d\n", crtc);
890 return -EINVAL;
891 }
892
893 /* Get associated drm_crtc: */
894 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
895 if (!drmcrtc)
896 return -EINVAL;
897
898 /* Helper routine in DRM core does all the work: */
899 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
900 vblank_time, flags,
901 &drmcrtc->hwmode);
902}
903
904const struct drm_ioctl_desc radeon_ioctls_kms[] = {
905 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
906 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
907 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
908 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
909 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
910 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
911 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
912 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
913 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
914 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
915 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
916 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
917 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
918 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
919 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
920 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
921 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
922 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
923 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
924 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
925 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
926 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
927 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
928 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
929 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
930 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
931 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
932 /* KMS */
933 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
934 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
935 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
936 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
937 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
938 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
939 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
940 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
941 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
942 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
943 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
944 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
945 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
946 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
947 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
948};
949int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/pci.h>
30#include <linux/pm_runtime.h>
31#include <linux/slab.h>
32#include <linux/uaccess.h>
33#include <linux/vga_switcheroo.h>
34
35#include <drm/drm_file.h>
36#include <drm/drm_ioctl.h>
37#include <drm/radeon_drm.h>
38
39#include "radeon.h"
40#include "radeon_asic.h"
41#include "radeon_drv.h"
42#include "radeon_kms.h"
43
44#if defined(CONFIG_VGA_SWITCHEROO)
45bool radeon_has_atpx(void);
46#else
47static inline bool radeon_has_atpx(void) { return false; }
48#endif
49
50/**
51 * radeon_driver_unload_kms - Main unload function for KMS.
52 *
53 * @dev: drm dev pointer
54 *
55 * This is the main unload function for KMS (all asics).
56 * It calls radeon_modeset_fini() to tear down the
57 * displays, and radeon_device_fini() to tear down
58 * the rest of the device (CP, writeback, etc.).
59 * Returns 0 on success.
60 */
61void radeon_driver_unload_kms(struct drm_device *dev)
62{
63 struct radeon_device *rdev = dev->dev_private;
64
65 if (rdev == NULL)
66 return;
67
68 if (rdev->rmmio == NULL)
69 goto done_free;
70
71 if (radeon_is_px(dev)) {
72 pm_runtime_get_sync(dev->dev);
73 pm_runtime_forbid(dev->dev);
74 }
75
76 radeon_acpi_fini(rdev);
77
78 radeon_modeset_fini(rdev);
79 radeon_device_fini(rdev);
80
81 if (rdev->agp)
82 arch_phys_wc_del(rdev->agp->agp_mtrr);
83 kfree(rdev->agp);
84 rdev->agp = NULL;
85
86done_free:
87 kfree(rdev);
88 dev->dev_private = NULL;
89}
90
91/**
92 * radeon_driver_load_kms - Main load function for KMS.
93 *
94 * @dev: drm dev pointer
95 * @flags: device flags
96 *
97 * This is the main load function for KMS (all asics).
98 * It calls radeon_device_init() to set up the non-display
99 * parts of the chip (asic init, CP, writeback, etc.), and
100 * radeon_modeset_init() to set up the display parts
101 * (crtcs, encoders, hotplug detect, etc.).
102 * Returns 0 on success, error on failure.
103 */
104int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
105{
106 struct pci_dev *pdev = to_pci_dev(dev->dev);
107 struct radeon_device *rdev;
108 int r, acpi_status;
109
110 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
111 if (rdev == NULL) {
112 return -ENOMEM;
113 }
114 dev->dev_private = (void *)rdev;
115
116#ifdef __alpha__
117 rdev->hose = pdev->sysdata;
118#endif
119
120 if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
121 rdev->agp = radeon_agp_head_init(dev);
122 if (rdev->agp) {
123 rdev->agp->agp_mtrr = arch_phys_wc_add(
124 rdev->agp->agp_info.aper_base,
125 rdev->agp->agp_info.aper_size *
126 1024 * 1024);
127 }
128
129 /* update BUS flag */
130 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
131 flags |= RADEON_IS_AGP;
132 } else if (pci_is_pcie(pdev)) {
133 flags |= RADEON_IS_PCIE;
134 } else {
135 flags |= RADEON_IS_PCI;
136 }
137
138 if ((radeon_runtime_pm != 0) &&
139 radeon_has_atpx() &&
140 ((flags & RADEON_IS_IGP) == 0) &&
141 !pci_is_thunderbolt_attached(pdev))
142 flags |= RADEON_IS_PX;
143
144 /* radeon_device_init should report only fatal error
145 * like memory allocation failure or iomapping failure,
146 * or memory manager initialization failure, it must
147 * properly initialize the GPU MC controller and permit
148 * VRAM allocation
149 */
150 r = radeon_device_init(rdev, dev, pdev, flags);
151 if (r) {
152 dev_err(dev->dev, "Fatal error during GPU init\n");
153 goto out;
154 }
155
156 /* Again modeset_init should fail only on fatal error
157 * otherwise it should provide enough functionalities
158 * for shadowfb to run
159 */
160 r = radeon_modeset_init(rdev);
161 if (r)
162 dev_err(dev->dev, "Fatal error during modeset init\n");
163
164 /* Call ACPI methods: require modeset init
165 * but failure is not fatal
166 */
167 if (!r) {
168 acpi_status = radeon_acpi_init(rdev);
169 if (acpi_status)
170 dev_dbg(dev->dev, "Error during ACPI methods call\n");
171 }
172
173 if (radeon_is_px(dev)) {
174 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
175 pm_runtime_use_autosuspend(dev->dev);
176 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
177 pm_runtime_set_active(dev->dev);
178 pm_runtime_allow(dev->dev);
179 pm_runtime_mark_last_busy(dev->dev);
180 pm_runtime_put_autosuspend(dev->dev);
181 }
182
183out:
184 if (r)
185 radeon_driver_unload_kms(dev);
186
187
188 return r;
189}
190
191/**
192 * radeon_set_filp_rights - Set filp right.
193 *
194 * @dev: drm dev pointer
195 * @owner: drm file
196 * @applier: drm file
197 * @value: value
198 *
199 * Sets the filp rights for the device (all asics).
200 */
201static void radeon_set_filp_rights(struct drm_device *dev,
202 struct drm_file **owner,
203 struct drm_file *applier,
204 uint32_t *value)
205{
206 struct radeon_device *rdev = dev->dev_private;
207
208 mutex_lock(&rdev->gem.mutex);
209 if (*value == 1) {
210 /* wants rights */
211 if (!*owner)
212 *owner = applier;
213 } else if (*value == 0) {
214 /* revokes rights */
215 if (*owner == applier)
216 *owner = NULL;
217 }
218 *value = *owner == applier ? 1 : 0;
219 mutex_unlock(&rdev->gem.mutex);
220}
221
222/*
223 * Userspace get information ioctl
224 */
225/**
226 * radeon_info_ioctl - answer a device specific request.
227 *
228 * @dev: drm device pointer
229 * @data: request object
230 * @filp: drm filp
231 *
232 * This function is used to pass device specific parameters to the userspace
233 * drivers. Examples include: pci device id, pipeline parms, tiling params,
234 * etc. (all asics).
235 * Returns 0 on success, -EINVAL on failure.
236 */
237int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
238{
239 struct radeon_device *rdev = dev->dev_private;
240 struct drm_radeon_info *info = data;
241 struct radeon_mode_info *minfo = &rdev->mode_info;
242 uint32_t *value, value_tmp, *value_ptr, value_size;
243 struct ttm_resource_manager *man;
244 uint64_t value64;
245 struct drm_crtc *crtc;
246 int i, found;
247
248 value_ptr = (uint32_t *)((unsigned long)info->value);
249 value = &value_tmp;
250 value_size = sizeof(uint32_t);
251
252 switch (info->request) {
253 case RADEON_INFO_DEVICE_ID:
254 *value = to_pci_dev(dev->dev)->device;
255 break;
256 case RADEON_INFO_NUM_GB_PIPES:
257 *value = rdev->num_gb_pipes;
258 break;
259 case RADEON_INFO_NUM_Z_PIPES:
260 *value = rdev->num_z_pipes;
261 break;
262 case RADEON_INFO_ACCEL_WORKING:
263 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
264 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
265 *value = false;
266 else
267 *value = rdev->accel_working;
268 break;
269 case RADEON_INFO_CRTC_FROM_ID:
270 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
271 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
272 return -EFAULT;
273 }
274 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
275 crtc = (struct drm_crtc *)minfo->crtcs[i];
276 if (crtc && crtc->base.id == *value) {
277 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
278 *value = radeon_crtc->crtc_id;
279 found = 1;
280 break;
281 }
282 }
283 if (!found) {
284 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
285 return -EINVAL;
286 }
287 break;
288 case RADEON_INFO_ACCEL_WORKING2:
289 if (rdev->family == CHIP_HAWAII) {
290 if (rdev->accel_working) {
291 if (rdev->new_fw)
292 *value = 3;
293 else
294 *value = 2;
295 } else {
296 *value = 0;
297 }
298 } else {
299 *value = rdev->accel_working;
300 }
301 break;
302 case RADEON_INFO_TILING_CONFIG:
303 if (rdev->family >= CHIP_BONAIRE)
304 *value = rdev->config.cik.tile_config;
305 else if (rdev->family >= CHIP_TAHITI)
306 *value = rdev->config.si.tile_config;
307 else if (rdev->family >= CHIP_CAYMAN)
308 *value = rdev->config.cayman.tile_config;
309 else if (rdev->family >= CHIP_CEDAR)
310 *value = rdev->config.evergreen.tile_config;
311 else if (rdev->family >= CHIP_RV770)
312 *value = rdev->config.rv770.tile_config;
313 else if (rdev->family >= CHIP_R600)
314 *value = rdev->config.r600.tile_config;
315 else {
316 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
317 return -EINVAL;
318 }
319 break;
320 case RADEON_INFO_WANT_HYPERZ:
321 /* The "value" here is both an input and output parameter.
322 * If the input value is 1, filp requests hyper-z access.
323 * If the input value is 0, filp revokes its hyper-z access.
324 *
325 * When returning, the value is 1 if filp owns hyper-z access,
326 * 0 otherwise. */
327 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
328 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
329 return -EFAULT;
330 }
331 if (*value >= 2) {
332 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
333 return -EINVAL;
334 }
335 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
336 break;
337 case RADEON_INFO_WANT_CMASK:
338 /* The same logic as Hyper-Z. */
339 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
340 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
341 return -EFAULT;
342 }
343 if (*value >= 2) {
344 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
345 return -EINVAL;
346 }
347 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
348 break;
349 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
350 /* return clock value in KHz */
351 if (rdev->asic->get_xclk)
352 *value = radeon_get_xclk(rdev) * 10;
353 else
354 *value = rdev->clock.spll.reference_freq * 10;
355 break;
356 case RADEON_INFO_NUM_BACKENDS:
357 if (rdev->family >= CHIP_BONAIRE)
358 *value = rdev->config.cik.max_backends_per_se *
359 rdev->config.cik.max_shader_engines;
360 else if (rdev->family >= CHIP_TAHITI)
361 *value = rdev->config.si.max_backends_per_se *
362 rdev->config.si.max_shader_engines;
363 else if (rdev->family >= CHIP_CAYMAN)
364 *value = rdev->config.cayman.max_backends_per_se *
365 rdev->config.cayman.max_shader_engines;
366 else if (rdev->family >= CHIP_CEDAR)
367 *value = rdev->config.evergreen.max_backends;
368 else if (rdev->family >= CHIP_RV770)
369 *value = rdev->config.rv770.max_backends;
370 else if (rdev->family >= CHIP_R600)
371 *value = rdev->config.r600.max_backends;
372 else {
373 return -EINVAL;
374 }
375 break;
376 case RADEON_INFO_NUM_TILE_PIPES:
377 if (rdev->family >= CHIP_BONAIRE)
378 *value = rdev->config.cik.max_tile_pipes;
379 else if (rdev->family >= CHIP_TAHITI)
380 *value = rdev->config.si.max_tile_pipes;
381 else if (rdev->family >= CHIP_CAYMAN)
382 *value = rdev->config.cayman.max_tile_pipes;
383 else if (rdev->family >= CHIP_CEDAR)
384 *value = rdev->config.evergreen.max_tile_pipes;
385 else if (rdev->family >= CHIP_RV770)
386 *value = rdev->config.rv770.max_tile_pipes;
387 else if (rdev->family >= CHIP_R600)
388 *value = rdev->config.r600.max_tile_pipes;
389 else {
390 return -EINVAL;
391 }
392 break;
393 case RADEON_INFO_FUSION_GART_WORKING:
394 *value = 1;
395 break;
396 case RADEON_INFO_BACKEND_MAP:
397 if (rdev->family >= CHIP_BONAIRE)
398 *value = rdev->config.cik.backend_map;
399 else if (rdev->family >= CHIP_TAHITI)
400 *value = rdev->config.si.backend_map;
401 else if (rdev->family >= CHIP_CAYMAN)
402 *value = rdev->config.cayman.backend_map;
403 else if (rdev->family >= CHIP_CEDAR)
404 *value = rdev->config.evergreen.backend_map;
405 else if (rdev->family >= CHIP_RV770)
406 *value = rdev->config.rv770.backend_map;
407 else if (rdev->family >= CHIP_R600)
408 *value = rdev->config.r600.backend_map;
409 else {
410 return -EINVAL;
411 }
412 break;
413 case RADEON_INFO_VA_START:
414 /* this is where we report if vm is supported or not */
415 if (rdev->family < CHIP_CAYMAN)
416 return -EINVAL;
417 *value = RADEON_VA_RESERVED_SIZE;
418 break;
419 case RADEON_INFO_IB_VM_MAX_SIZE:
420 /* this is where we report if vm is supported or not */
421 if (rdev->family < CHIP_CAYMAN)
422 return -EINVAL;
423 *value = RADEON_IB_VM_MAX_SIZE;
424 break;
425 case RADEON_INFO_MAX_PIPES:
426 if (rdev->family >= CHIP_BONAIRE)
427 *value = rdev->config.cik.max_cu_per_sh;
428 else if (rdev->family >= CHIP_TAHITI)
429 *value = rdev->config.si.max_cu_per_sh;
430 else if (rdev->family >= CHIP_CAYMAN)
431 *value = rdev->config.cayman.max_pipes_per_simd;
432 else if (rdev->family >= CHIP_CEDAR)
433 *value = rdev->config.evergreen.max_pipes;
434 else if (rdev->family >= CHIP_RV770)
435 *value = rdev->config.rv770.max_pipes;
436 else if (rdev->family >= CHIP_R600)
437 *value = rdev->config.r600.max_pipes;
438 else {
439 return -EINVAL;
440 }
441 break;
442 case RADEON_INFO_TIMESTAMP:
443 if (rdev->family < CHIP_R600) {
444 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
445 return -EINVAL;
446 }
447 value = (uint32_t *)&value64;
448 value_size = sizeof(uint64_t);
449 value64 = radeon_get_gpu_clock_counter(rdev);
450 break;
451 case RADEON_INFO_MAX_SE:
452 if (rdev->family >= CHIP_BONAIRE)
453 *value = rdev->config.cik.max_shader_engines;
454 else if (rdev->family >= CHIP_TAHITI)
455 *value = rdev->config.si.max_shader_engines;
456 else if (rdev->family >= CHIP_CAYMAN)
457 *value = rdev->config.cayman.max_shader_engines;
458 else if (rdev->family >= CHIP_CEDAR)
459 *value = rdev->config.evergreen.num_ses;
460 else
461 *value = 1;
462 break;
463 case RADEON_INFO_MAX_SH_PER_SE:
464 if (rdev->family >= CHIP_BONAIRE)
465 *value = rdev->config.cik.max_sh_per_se;
466 else if (rdev->family >= CHIP_TAHITI)
467 *value = rdev->config.si.max_sh_per_se;
468 else
469 return -EINVAL;
470 break;
471 case RADEON_INFO_FASTFB_WORKING:
472 *value = rdev->fastfb_working;
473 break;
474 case RADEON_INFO_RING_WORKING:
475 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
476 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
477 return -EFAULT;
478 }
479 switch (*value) {
480 case RADEON_CS_RING_GFX:
481 case RADEON_CS_RING_COMPUTE:
482 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
483 break;
484 case RADEON_CS_RING_DMA:
485 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
486 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
487 break;
488 case RADEON_CS_RING_UVD:
489 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
490 break;
491 case RADEON_CS_RING_VCE:
492 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
493 break;
494 default:
495 return -EINVAL;
496 }
497 break;
498 case RADEON_INFO_SI_TILE_MODE_ARRAY:
499 if (rdev->family >= CHIP_BONAIRE) {
500 value = rdev->config.cik.tile_mode_array;
501 value_size = sizeof(uint32_t)*32;
502 } else if (rdev->family >= CHIP_TAHITI) {
503 value = rdev->config.si.tile_mode_array;
504 value_size = sizeof(uint32_t)*32;
505 } else {
506 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
507 return -EINVAL;
508 }
509 break;
510 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
511 if (rdev->family >= CHIP_BONAIRE) {
512 value = rdev->config.cik.macrotile_mode_array;
513 value_size = sizeof(uint32_t)*16;
514 } else {
515 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
516 return -EINVAL;
517 }
518 break;
519 case RADEON_INFO_SI_CP_DMA_COMPUTE:
520 *value = 1;
521 break;
522 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
523 if (rdev->family >= CHIP_BONAIRE) {
524 *value = rdev->config.cik.backend_enable_mask;
525 } else if (rdev->family >= CHIP_TAHITI) {
526 *value = rdev->config.si.backend_enable_mask;
527 } else {
528 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
529 return -EINVAL;
530 }
531 break;
532 case RADEON_INFO_MAX_SCLK:
533 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
534 rdev->pm.dpm_enabled)
535 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
536 else
537 *value = rdev->pm.default_sclk * 10;
538 break;
539 case RADEON_INFO_VCE_FW_VERSION:
540 *value = rdev->vce.fw_version;
541 break;
542 case RADEON_INFO_VCE_FB_VERSION:
543 *value = rdev->vce.fb_version;
544 break;
545 case RADEON_INFO_NUM_BYTES_MOVED:
546 value = (uint32_t *)&value64;
547 value_size = sizeof(uint64_t);
548 value64 = atomic64_read(&rdev->num_bytes_moved);
549 break;
550 case RADEON_INFO_VRAM_USAGE:
551 value = (uint32_t *)&value64;
552 value_size = sizeof(uint64_t);
553 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
554 value64 = ttm_resource_manager_usage(man);
555 break;
556 case RADEON_INFO_GTT_USAGE:
557 value = (uint32_t *)&value64;
558 value_size = sizeof(uint64_t);
559 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT);
560 value64 = ttm_resource_manager_usage(man);
561 break;
562 case RADEON_INFO_ACTIVE_CU_COUNT:
563 if (rdev->family >= CHIP_BONAIRE)
564 *value = rdev->config.cik.active_cus;
565 else if (rdev->family >= CHIP_TAHITI)
566 *value = rdev->config.si.active_cus;
567 else if (rdev->family >= CHIP_CAYMAN)
568 *value = rdev->config.cayman.active_simds;
569 else if (rdev->family >= CHIP_CEDAR)
570 *value = rdev->config.evergreen.active_simds;
571 else if (rdev->family >= CHIP_RV770)
572 *value = rdev->config.rv770.active_simds;
573 else if (rdev->family >= CHIP_R600)
574 *value = rdev->config.r600.active_simds;
575 else
576 *value = 1;
577 break;
578 case RADEON_INFO_CURRENT_GPU_TEMP:
579 /* get temperature in millidegrees C */
580 if (rdev->asic->pm.get_temperature)
581 *value = radeon_get_temperature(rdev);
582 else
583 *value = 0;
584 break;
585 case RADEON_INFO_CURRENT_GPU_SCLK:
586 /* get sclk in Mhz */
587 if (rdev->pm.dpm_enabled)
588 *value = radeon_dpm_get_current_sclk(rdev) / 100;
589 else
590 *value = rdev->pm.current_sclk / 100;
591 break;
592 case RADEON_INFO_CURRENT_GPU_MCLK:
593 /* get mclk in Mhz */
594 if (rdev->pm.dpm_enabled)
595 *value = radeon_dpm_get_current_mclk(rdev) / 100;
596 else
597 *value = rdev->pm.current_mclk / 100;
598 break;
599 case RADEON_INFO_READ_REG:
600 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
601 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
602 return -EFAULT;
603 }
604 if (radeon_get_allowed_info_register(rdev, *value, value))
605 return -EINVAL;
606 break;
607 case RADEON_INFO_VA_UNMAP_WORKING:
608 *value = true;
609 break;
610 case RADEON_INFO_GPU_RESET_COUNTER:
611 *value = atomic_read(&rdev->gpu_reset_counter);
612 break;
613 default:
614 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
615 return -EINVAL;
616 }
617 if (copy_to_user(value_ptr, (char *)value, value_size)) {
618 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
619 return -EFAULT;
620 }
621 return 0;
622}
623
624/**
625 * radeon_driver_open_kms - drm callback for open
626 *
627 * @dev: drm dev pointer
628 * @file_priv: drm file
629 *
630 * On device open, init vm on cayman+ (all asics).
631 * Returns 0 on success, error on failure.
632 */
633int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
634{
635 struct radeon_device *rdev = dev->dev_private;
636 struct radeon_fpriv *fpriv;
637 struct radeon_vm *vm;
638 int r;
639
640 file_priv->driver_priv = NULL;
641
642 r = pm_runtime_get_sync(dev->dev);
643 if (r < 0) {
644 pm_runtime_put_autosuspend(dev->dev);
645 return r;
646 }
647
648 /* new gpu have virtual address space support */
649 if (rdev->family >= CHIP_CAYMAN) {
650
651 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
652 if (unlikely(!fpriv)) {
653 r = -ENOMEM;
654 goto err_suspend;
655 }
656
657 if (rdev->accel_working) {
658 vm = &fpriv->vm;
659 r = radeon_vm_init(rdev, vm);
660 if (r)
661 goto err_fpriv;
662
663 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
664 if (r)
665 goto err_vm_fini;
666
667 /* map the ib pool buffer read only into
668 * virtual address space */
669 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
670 rdev->ring_tmp_bo.bo);
671 if (!vm->ib_bo_va) {
672 r = -ENOMEM;
673 goto err_vm_fini;
674 }
675
676 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
677 RADEON_VA_IB_OFFSET,
678 RADEON_VM_PAGE_READABLE |
679 RADEON_VM_PAGE_SNOOPED);
680 if (r)
681 goto err_vm_fini;
682 }
683 file_priv->driver_priv = fpriv;
684 }
685
686 pm_runtime_mark_last_busy(dev->dev);
687 pm_runtime_put_autosuspend(dev->dev);
688 return 0;
689
690err_vm_fini:
691 radeon_vm_fini(rdev, vm);
692err_fpriv:
693 kfree(fpriv);
694
695err_suspend:
696 pm_runtime_mark_last_busy(dev->dev);
697 pm_runtime_put_autosuspend(dev->dev);
698 return r;
699}
700
701/**
702 * radeon_driver_postclose_kms - drm callback for post close
703 *
704 * @dev: drm dev pointer
705 * @file_priv: drm file
706 *
707 * On device close, tear down hyperz and cmask filps on r1xx-r5xx
708 * (all asics). And tear down vm on cayman+ (all asics).
709 */
710void radeon_driver_postclose_kms(struct drm_device *dev,
711 struct drm_file *file_priv)
712{
713 struct radeon_device *rdev = dev->dev_private;
714
715 pm_runtime_get_sync(dev->dev);
716
717 mutex_lock(&rdev->gem.mutex);
718 if (rdev->hyperz_filp == file_priv)
719 rdev->hyperz_filp = NULL;
720 if (rdev->cmask_filp == file_priv)
721 rdev->cmask_filp = NULL;
722 mutex_unlock(&rdev->gem.mutex);
723
724 radeon_uvd_free_handles(rdev, file_priv);
725 radeon_vce_free_handles(rdev, file_priv);
726
727 /* new gpu have virtual address space support */
728 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
729 struct radeon_fpriv *fpriv = file_priv->driver_priv;
730 struct radeon_vm *vm = &fpriv->vm;
731 int r;
732
733 if (rdev->accel_working) {
734 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
735 if (!r) {
736 if (vm->ib_bo_va)
737 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
738 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
739 }
740 radeon_vm_fini(rdev, vm);
741 }
742
743 kfree(fpriv);
744 file_priv->driver_priv = NULL;
745 }
746 pm_runtime_mark_last_busy(dev->dev);
747 pm_runtime_put_autosuspend(dev->dev);
748}
749
750/*
751 * VBlank related functions.
752 */
753/**
754 * radeon_get_vblank_counter_kms - get frame count
755 *
756 * @crtc: crtc to get the frame count from
757 *
758 * Gets the frame count on the requested crtc (all asics).
759 * Returns frame count on success, -EINVAL on failure.
760 */
761u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc)
762{
763 struct drm_device *dev = crtc->dev;
764 unsigned int pipe = crtc->index;
765 int vpos, hpos, stat;
766 u32 count;
767 struct radeon_device *rdev = dev->dev_private;
768
769 if (pipe >= rdev->num_crtc) {
770 DRM_ERROR("Invalid crtc %u\n", pipe);
771 return -EINVAL;
772 }
773
774 /* The hw increments its frame counter at start of vsync, not at start
775 * of vblank, as is required by DRM core vblank counter handling.
776 * Cook the hw count here to make it appear to the caller as if it
777 * incremented at start of vblank. We measure distance to start of
778 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
779 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
780 * result by 1 to give the proper appearance to caller.
781 */
782 if (rdev->mode_info.crtcs[pipe]) {
783 /* Repeat readout if needed to provide stable result if
784 * we cross start of vsync during the queries.
785 */
786 do {
787 count = radeon_get_vblank_counter(rdev, pipe);
788 /* Ask radeon_get_crtc_scanoutpos to return vpos as
789 * distance to start of vblank, instead of regular
790 * vertical scanout pos.
791 */
792 stat = radeon_get_crtc_scanoutpos(
793 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
794 &vpos, &hpos, NULL, NULL,
795 &rdev->mode_info.crtcs[pipe]->base.hwmode);
796 } while (count != radeon_get_vblank_counter(rdev, pipe));
797
798 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
799 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
800 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
801 }
802 else {
803 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
804 pipe, vpos);
805
806 /* Bump counter if we are at >= leading edge of vblank,
807 * but before vsync where vpos would turn negative and
808 * the hw counter really increments.
809 */
810 if (vpos >= 0)
811 count++;
812 }
813 }
814 else {
815 /* Fallback to use value as is. */
816 count = radeon_get_vblank_counter(rdev, pipe);
817 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
818 }
819
820 return count;
821}
822
823/**
824 * radeon_enable_vblank_kms - enable vblank interrupt
825 *
826 * @crtc: crtc to enable vblank interrupt for
827 *
828 * Enable the interrupt on the requested crtc (all asics).
829 * Returns 0 on success, -EINVAL on failure.
830 */
831int radeon_enable_vblank_kms(struct drm_crtc *crtc)
832{
833 struct drm_device *dev = crtc->dev;
834 unsigned int pipe = crtc->index;
835 struct radeon_device *rdev = dev->dev_private;
836 unsigned long irqflags;
837 int r;
838
839 if (pipe >= rdev->num_crtc) {
840 DRM_ERROR("Invalid crtc %d\n", pipe);
841 return -EINVAL;
842 }
843
844 spin_lock_irqsave(&rdev->irq.lock, irqflags);
845 rdev->irq.crtc_vblank_int[pipe] = true;
846 r = radeon_irq_set(rdev);
847 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
848 return r;
849}
850
851/**
852 * radeon_disable_vblank_kms - disable vblank interrupt
853 *
854 * @crtc: crtc to disable vblank interrupt for
855 *
856 * Disable the interrupt on the requested crtc (all asics).
857 */
858void radeon_disable_vblank_kms(struct drm_crtc *crtc)
859{
860 struct drm_device *dev = crtc->dev;
861 unsigned int pipe = crtc->index;
862 struct radeon_device *rdev = dev->dev_private;
863 unsigned long irqflags;
864
865 if (pipe >= rdev->num_crtc) {
866 DRM_ERROR("Invalid crtc %d\n", pipe);
867 return;
868 }
869
870 spin_lock_irqsave(&rdev->irq.lock, irqflags);
871 rdev->irq.crtc_vblank_int[pipe] = false;
872 radeon_irq_set(rdev);
873 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
874}