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1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
25#include <linux/gpio/consumer.h>
26#include <linux/module.h>
27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_mipi_dsi.h>
34#include <drm/drm_panel.h>
35
36#include <video/display_timing.h>
37#include <video/videomode.h>
38
39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
44
45 unsigned int bpc;
46
47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
61 * video data
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
66 */
67 struct {
68 unsigned int prepare;
69 unsigned int enable;
70 unsigned int disable;
71 unsigned int unprepare;
72 } delay;
73
74 u32 bus_format;
75};
76
77struct panel_simple {
78 struct drm_panel base;
79 bool prepared;
80 bool enabled;
81
82 const struct panel_desc *desc;
83
84 struct backlight_device *backlight;
85 struct regulator *supply;
86 struct i2c_adapter *ddc;
87
88 struct gpio_desc *enable_gpio;
89};
90
91static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
92{
93 return container_of(panel, struct panel_simple, base);
94}
95
96static int panel_simple_get_fixed_modes(struct panel_simple *panel)
97{
98 struct drm_connector *connector = panel->base.connector;
99 struct drm_device *drm = panel->base.drm;
100 struct drm_display_mode *mode;
101 unsigned int i, num = 0;
102
103 if (!panel->desc)
104 return 0;
105
106 for (i = 0; i < panel->desc->num_timings; i++) {
107 const struct display_timing *dt = &panel->desc->timings[i];
108 struct videomode vm;
109
110 videomode_from_timing(dt, &vm);
111 mode = drm_mode_create(drm);
112 if (!mode) {
113 dev_err(drm->dev, "failed to add mode %ux%u\n",
114 dt->hactive.typ, dt->vactive.typ);
115 continue;
116 }
117
118 drm_display_mode_from_videomode(&vm, mode);
119 drm_mode_set_name(mode);
120
121 drm_mode_probed_add(connector, mode);
122 num++;
123 }
124
125 for (i = 0; i < panel->desc->num_modes; i++) {
126 const struct drm_display_mode *m = &panel->desc->modes[i];
127
128 mode = drm_mode_duplicate(drm, m);
129 if (!mode) {
130 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
131 m->hdisplay, m->vdisplay, m->vrefresh);
132 continue;
133 }
134
135 drm_mode_set_name(mode);
136
137 drm_mode_probed_add(connector, mode);
138 num++;
139 }
140
141 connector->display_info.bpc = panel->desc->bpc;
142 connector->display_info.width_mm = panel->desc->size.width;
143 connector->display_info.height_mm = panel->desc->size.height;
144 if (panel->desc->bus_format)
145 drm_display_info_set_bus_formats(&connector->display_info,
146 &panel->desc->bus_format, 1);
147
148 return num;
149}
150
151static int panel_simple_disable(struct drm_panel *panel)
152{
153 struct panel_simple *p = to_panel_simple(panel);
154
155 if (!p->enabled)
156 return 0;
157
158 if (p->backlight) {
159 p->backlight->props.power = FB_BLANK_POWERDOWN;
160 backlight_update_status(p->backlight);
161 }
162
163 if (p->desc->delay.disable)
164 msleep(p->desc->delay.disable);
165
166 p->enabled = false;
167
168 return 0;
169}
170
171static int panel_simple_unprepare(struct drm_panel *panel)
172{
173 struct panel_simple *p = to_panel_simple(panel);
174
175 if (!p->prepared)
176 return 0;
177
178 if (p->enable_gpio)
179 gpiod_set_value_cansleep(p->enable_gpio, 0);
180
181 regulator_disable(p->supply);
182
183 if (p->desc->delay.unprepare)
184 msleep(p->desc->delay.unprepare);
185
186 p->prepared = false;
187
188 return 0;
189}
190
191static int panel_simple_prepare(struct drm_panel *panel)
192{
193 struct panel_simple *p = to_panel_simple(panel);
194 int err;
195
196 if (p->prepared)
197 return 0;
198
199 err = regulator_enable(p->supply);
200 if (err < 0) {
201 dev_err(panel->dev, "failed to enable supply: %d\n", err);
202 return err;
203 }
204
205 if (p->enable_gpio)
206 gpiod_set_value_cansleep(p->enable_gpio, 1);
207
208 if (p->desc->delay.prepare)
209 msleep(p->desc->delay.prepare);
210
211 p->prepared = true;
212
213 return 0;
214}
215
216static int panel_simple_enable(struct drm_panel *panel)
217{
218 struct panel_simple *p = to_panel_simple(panel);
219
220 if (p->enabled)
221 return 0;
222
223 if (p->desc->delay.enable)
224 msleep(p->desc->delay.enable);
225
226 if (p->backlight) {
227 p->backlight->props.power = FB_BLANK_UNBLANK;
228 backlight_update_status(p->backlight);
229 }
230
231 p->enabled = true;
232
233 return 0;
234}
235
236static int panel_simple_get_modes(struct drm_panel *panel)
237{
238 struct panel_simple *p = to_panel_simple(panel);
239 int num = 0;
240
241 /* probe EDID if a DDC bus is available */
242 if (p->ddc) {
243 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
244 drm_mode_connector_update_edid_property(panel->connector, edid);
245 if (edid) {
246 num += drm_add_edid_modes(panel->connector, edid);
247 kfree(edid);
248 }
249 }
250
251 /* add hard-coded panel modes */
252 num += panel_simple_get_fixed_modes(p);
253
254 return num;
255}
256
257static int panel_simple_get_timings(struct drm_panel *panel,
258 unsigned int num_timings,
259 struct display_timing *timings)
260{
261 struct panel_simple *p = to_panel_simple(panel);
262 unsigned int i;
263
264 if (p->desc->num_timings < num_timings)
265 num_timings = p->desc->num_timings;
266
267 if (timings)
268 for (i = 0; i < num_timings; i++)
269 timings[i] = p->desc->timings[i];
270
271 return p->desc->num_timings;
272}
273
274static const struct drm_panel_funcs panel_simple_funcs = {
275 .disable = panel_simple_disable,
276 .unprepare = panel_simple_unprepare,
277 .prepare = panel_simple_prepare,
278 .enable = panel_simple_enable,
279 .get_modes = panel_simple_get_modes,
280 .get_timings = panel_simple_get_timings,
281};
282
283static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
284{
285 struct device_node *backlight, *ddc;
286 struct panel_simple *panel;
287 int err;
288
289 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
290 if (!panel)
291 return -ENOMEM;
292
293 panel->enabled = false;
294 panel->prepared = false;
295 panel->desc = desc;
296
297 panel->supply = devm_regulator_get(dev, "power");
298 if (IS_ERR(panel->supply))
299 return PTR_ERR(panel->supply);
300
301 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
302 GPIOD_OUT_LOW);
303 if (IS_ERR(panel->enable_gpio)) {
304 err = PTR_ERR(panel->enable_gpio);
305 dev_err(dev, "failed to request GPIO: %d\n", err);
306 return err;
307 }
308
309 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
310 if (backlight) {
311 panel->backlight = of_find_backlight_by_node(backlight);
312 of_node_put(backlight);
313
314 if (!panel->backlight)
315 return -EPROBE_DEFER;
316 }
317
318 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
319 if (ddc) {
320 panel->ddc = of_find_i2c_adapter_by_node(ddc);
321 of_node_put(ddc);
322
323 if (!panel->ddc) {
324 err = -EPROBE_DEFER;
325 goto free_backlight;
326 }
327 }
328
329 drm_panel_init(&panel->base);
330 panel->base.dev = dev;
331 panel->base.funcs = &panel_simple_funcs;
332
333 err = drm_panel_add(&panel->base);
334 if (err < 0)
335 goto free_ddc;
336
337 dev_set_drvdata(dev, panel);
338
339 return 0;
340
341free_ddc:
342 if (panel->ddc)
343 put_device(&panel->ddc->dev);
344free_backlight:
345 if (panel->backlight)
346 put_device(&panel->backlight->dev);
347
348 return err;
349}
350
351static int panel_simple_remove(struct device *dev)
352{
353 struct panel_simple *panel = dev_get_drvdata(dev);
354
355 drm_panel_detach(&panel->base);
356 drm_panel_remove(&panel->base);
357
358 panel_simple_disable(&panel->base);
359
360 if (panel->ddc)
361 put_device(&panel->ddc->dev);
362
363 if (panel->backlight)
364 put_device(&panel->backlight->dev);
365
366 return 0;
367}
368
369static void panel_simple_shutdown(struct device *dev)
370{
371 struct panel_simple *panel = dev_get_drvdata(dev);
372
373 panel_simple_disable(&panel->base);
374}
375
376static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
377 .clock = 33333,
378 .hdisplay = 800,
379 .hsync_start = 800 + 0,
380 .hsync_end = 800 + 0 + 255,
381 .htotal = 800 + 0 + 255 + 0,
382 .vdisplay = 480,
383 .vsync_start = 480 + 2,
384 .vsync_end = 480 + 2 + 45,
385 .vtotal = 480 + 2 + 45 + 0,
386 .vrefresh = 60,
387 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
388};
389
390static const struct panel_desc ampire_am800480r3tmqwa1h = {
391 .modes = &ire_am800480r3tmqwa1h_mode,
392 .num_modes = 1,
393 .bpc = 6,
394 .size = {
395 .width = 152,
396 .height = 91,
397 },
398 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
399};
400
401static const struct drm_display_mode auo_b101aw03_mode = {
402 .clock = 51450,
403 .hdisplay = 1024,
404 .hsync_start = 1024 + 156,
405 .hsync_end = 1024 + 156 + 8,
406 .htotal = 1024 + 156 + 8 + 156,
407 .vdisplay = 600,
408 .vsync_start = 600 + 16,
409 .vsync_end = 600 + 16 + 6,
410 .vtotal = 600 + 16 + 6 + 16,
411 .vrefresh = 60,
412};
413
414static const struct panel_desc auo_b101aw03 = {
415 .modes = &auo_b101aw03_mode,
416 .num_modes = 1,
417 .bpc = 6,
418 .size = {
419 .width = 223,
420 .height = 125,
421 },
422};
423
424static const struct drm_display_mode auo_b101ean01_mode = {
425 .clock = 72500,
426 .hdisplay = 1280,
427 .hsync_start = 1280 + 119,
428 .hsync_end = 1280 + 119 + 32,
429 .htotal = 1280 + 119 + 32 + 21,
430 .vdisplay = 800,
431 .vsync_start = 800 + 4,
432 .vsync_end = 800 + 4 + 20,
433 .vtotal = 800 + 4 + 20 + 8,
434 .vrefresh = 60,
435};
436
437static const struct panel_desc auo_b101ean01 = {
438 .modes = &auo_b101ean01_mode,
439 .num_modes = 1,
440 .bpc = 6,
441 .size = {
442 .width = 217,
443 .height = 136,
444 },
445};
446
447static const struct drm_display_mode auo_b101xtn01_mode = {
448 .clock = 72000,
449 .hdisplay = 1366,
450 .hsync_start = 1366 + 20,
451 .hsync_end = 1366 + 20 + 70,
452 .htotal = 1366 + 20 + 70,
453 .vdisplay = 768,
454 .vsync_start = 768 + 14,
455 .vsync_end = 768 + 14 + 42,
456 .vtotal = 768 + 14 + 42,
457 .vrefresh = 60,
458 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
459};
460
461static const struct panel_desc auo_b101xtn01 = {
462 .modes = &auo_b101xtn01_mode,
463 .num_modes = 1,
464 .bpc = 6,
465 .size = {
466 .width = 223,
467 .height = 125,
468 },
469};
470
471static const struct drm_display_mode auo_b116xw03_mode = {
472 .clock = 70589,
473 .hdisplay = 1366,
474 .hsync_start = 1366 + 40,
475 .hsync_end = 1366 + 40 + 40,
476 .htotal = 1366 + 40 + 40 + 32,
477 .vdisplay = 768,
478 .vsync_start = 768 + 10,
479 .vsync_end = 768 + 10 + 12,
480 .vtotal = 768 + 10 + 12 + 6,
481 .vrefresh = 60,
482};
483
484static const struct panel_desc auo_b116xw03 = {
485 .modes = &auo_b116xw03_mode,
486 .num_modes = 1,
487 .bpc = 6,
488 .size = {
489 .width = 256,
490 .height = 144,
491 },
492};
493
494static const struct drm_display_mode auo_b133xtn01_mode = {
495 .clock = 69500,
496 .hdisplay = 1366,
497 .hsync_start = 1366 + 48,
498 .hsync_end = 1366 + 48 + 32,
499 .htotal = 1366 + 48 + 32 + 20,
500 .vdisplay = 768,
501 .vsync_start = 768 + 3,
502 .vsync_end = 768 + 3 + 6,
503 .vtotal = 768 + 3 + 6 + 13,
504 .vrefresh = 60,
505};
506
507static const struct panel_desc auo_b133xtn01 = {
508 .modes = &auo_b133xtn01_mode,
509 .num_modes = 1,
510 .bpc = 6,
511 .size = {
512 .width = 293,
513 .height = 165,
514 },
515};
516
517static const struct drm_display_mode auo_b133htn01_mode = {
518 .clock = 150660,
519 .hdisplay = 1920,
520 .hsync_start = 1920 + 172,
521 .hsync_end = 1920 + 172 + 80,
522 .htotal = 1920 + 172 + 80 + 60,
523 .vdisplay = 1080,
524 .vsync_start = 1080 + 25,
525 .vsync_end = 1080 + 25 + 10,
526 .vtotal = 1080 + 25 + 10 + 10,
527 .vrefresh = 60,
528};
529
530static const struct panel_desc auo_b133htn01 = {
531 .modes = &auo_b133htn01_mode,
532 .num_modes = 1,
533 .bpc = 6,
534 .size = {
535 .width = 293,
536 .height = 165,
537 },
538 .delay = {
539 .prepare = 105,
540 .enable = 20,
541 .unprepare = 50,
542 },
543};
544
545static const struct drm_display_mode avic_tm070ddh03_mode = {
546 .clock = 51200,
547 .hdisplay = 1024,
548 .hsync_start = 1024 + 160,
549 .hsync_end = 1024 + 160 + 4,
550 .htotal = 1024 + 160 + 4 + 156,
551 .vdisplay = 600,
552 .vsync_start = 600 + 17,
553 .vsync_end = 600 + 17 + 1,
554 .vtotal = 600 + 17 + 1 + 17,
555 .vrefresh = 60,
556};
557
558static const struct panel_desc avic_tm070ddh03 = {
559 .modes = &avic_tm070ddh03_mode,
560 .num_modes = 1,
561 .bpc = 8,
562 .size = {
563 .width = 154,
564 .height = 90,
565 },
566 .delay = {
567 .prepare = 20,
568 .enable = 200,
569 .disable = 200,
570 },
571};
572
573static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
574 .clock = 72070,
575 .hdisplay = 1366,
576 .hsync_start = 1366 + 58,
577 .hsync_end = 1366 + 58 + 58,
578 .htotal = 1366 + 58 + 58 + 58,
579 .vdisplay = 768,
580 .vsync_start = 768 + 4,
581 .vsync_end = 768 + 4 + 4,
582 .vtotal = 768 + 4 + 4 + 4,
583 .vrefresh = 60,
584};
585
586static const struct panel_desc chunghwa_claa101wa01a = {
587 .modes = &chunghwa_claa101wa01a_mode,
588 .num_modes = 1,
589 .bpc = 6,
590 .size = {
591 .width = 220,
592 .height = 120,
593 },
594};
595
596static const struct drm_display_mode chunghwa_claa101wb01_mode = {
597 .clock = 69300,
598 .hdisplay = 1366,
599 .hsync_start = 1366 + 48,
600 .hsync_end = 1366 + 48 + 32,
601 .htotal = 1366 + 48 + 32 + 20,
602 .vdisplay = 768,
603 .vsync_start = 768 + 16,
604 .vsync_end = 768 + 16 + 8,
605 .vtotal = 768 + 16 + 8 + 16,
606 .vrefresh = 60,
607};
608
609static const struct panel_desc chunghwa_claa101wb01 = {
610 .modes = &chunghwa_claa101wb01_mode,
611 .num_modes = 1,
612 .bpc = 6,
613 .size = {
614 .width = 223,
615 .height = 125,
616 },
617};
618
619static const struct drm_display_mode edt_et057090dhu_mode = {
620 .clock = 25175,
621 .hdisplay = 640,
622 .hsync_start = 640 + 16,
623 .hsync_end = 640 + 16 + 30,
624 .htotal = 640 + 16 + 30 + 114,
625 .vdisplay = 480,
626 .vsync_start = 480 + 10,
627 .vsync_end = 480 + 10 + 3,
628 .vtotal = 480 + 10 + 3 + 32,
629 .vrefresh = 60,
630 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
631};
632
633static const struct panel_desc edt_et057090dhu = {
634 .modes = &edt_et057090dhu_mode,
635 .num_modes = 1,
636 .bpc = 6,
637 .size = {
638 .width = 115,
639 .height = 86,
640 },
641};
642
643static const struct drm_display_mode edt_etm0700g0dh6_mode = {
644 .clock = 33260,
645 .hdisplay = 800,
646 .hsync_start = 800 + 40,
647 .hsync_end = 800 + 40 + 128,
648 .htotal = 800 + 40 + 128 + 88,
649 .vdisplay = 480,
650 .vsync_start = 480 + 10,
651 .vsync_end = 480 + 10 + 2,
652 .vtotal = 480 + 10 + 2 + 33,
653 .vrefresh = 60,
654 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
655};
656
657static const struct panel_desc edt_etm0700g0dh6 = {
658 .modes = &edt_etm0700g0dh6_mode,
659 .num_modes = 1,
660 .bpc = 6,
661 .size = {
662 .width = 152,
663 .height = 91,
664 },
665};
666
667static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
668 .clock = 32260,
669 .hdisplay = 800,
670 .hsync_start = 800 + 168,
671 .hsync_end = 800 + 168 + 64,
672 .htotal = 800 + 168 + 64 + 88,
673 .vdisplay = 480,
674 .vsync_start = 480 + 37,
675 .vsync_end = 480 + 37 + 2,
676 .vtotal = 480 + 37 + 2 + 8,
677 .vrefresh = 60,
678};
679
680static const struct panel_desc foxlink_fl500wvr00_a0t = {
681 .modes = &foxlink_fl500wvr00_a0t_mode,
682 .num_modes = 1,
683 .bpc = 8,
684 .size = {
685 .width = 108,
686 .height = 65,
687 },
688 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
689};
690
691static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
692 .clock = 9000,
693 .hdisplay = 480,
694 .hsync_start = 480 + 5,
695 .hsync_end = 480 + 5 + 1,
696 .htotal = 480 + 5 + 1 + 40,
697 .vdisplay = 272,
698 .vsync_start = 272 + 8,
699 .vsync_end = 272 + 8 + 1,
700 .vtotal = 272 + 8 + 1 + 8,
701 .vrefresh = 60,
702};
703
704static const struct panel_desc giantplus_gpg482739qs5 = {
705 .modes = &giantplus_gpg482739qs5_mode,
706 .num_modes = 1,
707 .bpc = 8,
708 .size = {
709 .width = 95,
710 .height = 54,
711 },
712 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
713};
714
715static const struct display_timing hannstar_hsd070pww1_timing = {
716 .pixelclock = { 64300000, 71100000, 82000000 },
717 .hactive = { 1280, 1280, 1280 },
718 .hfront_porch = { 1, 1, 10 },
719 .hback_porch = { 1, 1, 10 },
720 /*
721 * According to the data sheet, the minimum horizontal blanking interval
722 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
723 * minimum working horizontal blanking interval to be 60 clocks.
724 */
725 .hsync_len = { 58, 158, 661 },
726 .vactive = { 800, 800, 800 },
727 .vfront_porch = { 1, 1, 10 },
728 .vback_porch = { 1, 1, 10 },
729 .vsync_len = { 1, 21, 203 },
730 .flags = DISPLAY_FLAGS_DE_HIGH,
731};
732
733static const struct panel_desc hannstar_hsd070pww1 = {
734 .timings = &hannstar_hsd070pww1_timing,
735 .num_timings = 1,
736 .bpc = 6,
737 .size = {
738 .width = 151,
739 .height = 94,
740 },
741 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
742};
743
744static const struct display_timing hannstar_hsd100pxn1_timing = {
745 .pixelclock = { 55000000, 65000000, 75000000 },
746 .hactive = { 1024, 1024, 1024 },
747 .hfront_porch = { 40, 40, 40 },
748 .hback_porch = { 220, 220, 220 },
749 .hsync_len = { 20, 60, 100 },
750 .vactive = { 768, 768, 768 },
751 .vfront_porch = { 7, 7, 7 },
752 .vback_porch = { 21, 21, 21 },
753 .vsync_len = { 10, 10, 10 },
754 .flags = DISPLAY_FLAGS_DE_HIGH,
755};
756
757static const struct panel_desc hannstar_hsd100pxn1 = {
758 .timings = &hannstar_hsd100pxn1_timing,
759 .num_timings = 1,
760 .bpc = 6,
761 .size = {
762 .width = 203,
763 .height = 152,
764 },
765 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
766};
767
768static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
769 .clock = 33333,
770 .hdisplay = 800,
771 .hsync_start = 800 + 85,
772 .hsync_end = 800 + 85 + 86,
773 .htotal = 800 + 85 + 86 + 85,
774 .vdisplay = 480,
775 .vsync_start = 480 + 16,
776 .vsync_end = 480 + 16 + 13,
777 .vtotal = 480 + 16 + 13 + 16,
778 .vrefresh = 60,
779};
780
781static const struct panel_desc hitachi_tx23d38vm0caa = {
782 .modes = &hitachi_tx23d38vm0caa_mode,
783 .num_modes = 1,
784 .bpc = 6,
785 .size = {
786 .width = 195,
787 .height = 117,
788 },
789};
790
791static const struct drm_display_mode innolux_at043tn24_mode = {
792 .clock = 9000,
793 .hdisplay = 480,
794 .hsync_start = 480 + 2,
795 .hsync_end = 480 + 2 + 41,
796 .htotal = 480 + 2 + 41 + 2,
797 .vdisplay = 272,
798 .vsync_start = 272 + 2,
799 .vsync_end = 272 + 2 + 11,
800 .vtotal = 272 + 2 + 11 + 2,
801 .vrefresh = 60,
802 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
803};
804
805static const struct panel_desc innolux_at043tn24 = {
806 .modes = &innolux_at043tn24_mode,
807 .num_modes = 1,
808 .bpc = 8,
809 .size = {
810 .width = 95,
811 .height = 54,
812 },
813 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
814};
815
816static const struct drm_display_mode innolux_g121i1_l01_mode = {
817 .clock = 71000,
818 .hdisplay = 1280,
819 .hsync_start = 1280 + 64,
820 .hsync_end = 1280 + 64 + 32,
821 .htotal = 1280 + 64 + 32 + 64,
822 .vdisplay = 800,
823 .vsync_start = 800 + 9,
824 .vsync_end = 800 + 9 + 6,
825 .vtotal = 800 + 9 + 6 + 9,
826 .vrefresh = 60,
827};
828
829static const struct panel_desc innolux_g121i1_l01 = {
830 .modes = &innolux_g121i1_l01_mode,
831 .num_modes = 1,
832 .bpc = 6,
833 .size = {
834 .width = 261,
835 .height = 163,
836 },
837};
838
839static const struct drm_display_mode innolux_g121x1_l03_mode = {
840 .clock = 65000,
841 .hdisplay = 1024,
842 .hsync_start = 1024 + 0,
843 .hsync_end = 1024 + 1,
844 .htotal = 1024 + 0 + 1 + 320,
845 .vdisplay = 768,
846 .vsync_start = 768 + 38,
847 .vsync_end = 768 + 38 + 1,
848 .vtotal = 768 + 38 + 1 + 0,
849 .vrefresh = 60,
850 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
851};
852
853static const struct panel_desc innolux_g121x1_l03 = {
854 .modes = &innolux_g121x1_l03_mode,
855 .num_modes = 1,
856 .bpc = 6,
857 .size = {
858 .width = 246,
859 .height = 185,
860 },
861 .delay = {
862 .enable = 200,
863 .unprepare = 200,
864 .disable = 400,
865 },
866};
867
868static const struct drm_display_mode innolux_n116bge_mode = {
869 .clock = 76420,
870 .hdisplay = 1366,
871 .hsync_start = 1366 + 136,
872 .hsync_end = 1366 + 136 + 30,
873 .htotal = 1366 + 136 + 30 + 60,
874 .vdisplay = 768,
875 .vsync_start = 768 + 8,
876 .vsync_end = 768 + 8 + 12,
877 .vtotal = 768 + 8 + 12 + 12,
878 .vrefresh = 60,
879 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
880};
881
882static const struct panel_desc innolux_n116bge = {
883 .modes = &innolux_n116bge_mode,
884 .num_modes = 1,
885 .bpc = 6,
886 .size = {
887 .width = 256,
888 .height = 144,
889 },
890};
891
892static const struct drm_display_mode innolux_n156bge_l21_mode = {
893 .clock = 69300,
894 .hdisplay = 1366,
895 .hsync_start = 1366 + 16,
896 .hsync_end = 1366 + 16 + 34,
897 .htotal = 1366 + 16 + 34 + 50,
898 .vdisplay = 768,
899 .vsync_start = 768 + 2,
900 .vsync_end = 768 + 2 + 6,
901 .vtotal = 768 + 2 + 6 + 12,
902 .vrefresh = 60,
903};
904
905static const struct panel_desc innolux_n156bge_l21 = {
906 .modes = &innolux_n156bge_l21_mode,
907 .num_modes = 1,
908 .bpc = 6,
909 .size = {
910 .width = 344,
911 .height = 193,
912 },
913};
914
915static const struct drm_display_mode innolux_zj070na_01p_mode = {
916 .clock = 51501,
917 .hdisplay = 1024,
918 .hsync_start = 1024 + 128,
919 .hsync_end = 1024 + 128 + 64,
920 .htotal = 1024 + 128 + 64 + 128,
921 .vdisplay = 600,
922 .vsync_start = 600 + 16,
923 .vsync_end = 600 + 16 + 4,
924 .vtotal = 600 + 16 + 4 + 16,
925 .vrefresh = 60,
926};
927
928static const struct panel_desc innolux_zj070na_01p = {
929 .modes = &innolux_zj070na_01p_mode,
930 .num_modes = 1,
931 .bpc = 6,
932 .size = {
933 .width = 1024,
934 .height = 600,
935 },
936};
937
938static const struct display_timing kyo_tcg121xglp_timing = {
939 .pixelclock = { 52000000, 65000000, 71000000 },
940 .hactive = { 1024, 1024, 1024 },
941 .hfront_porch = { 2, 2, 2 },
942 .hback_porch = { 2, 2, 2 },
943 .hsync_len = { 86, 124, 244 },
944 .vactive = { 768, 768, 768 },
945 .vfront_porch = { 2, 2, 2 },
946 .vback_porch = { 2, 2, 2 },
947 .vsync_len = { 6, 34, 73 },
948 .flags = DISPLAY_FLAGS_DE_HIGH,
949};
950
951static const struct panel_desc kyo_tcg121xglp = {
952 .timings = &kyo_tcg121xglp_timing,
953 .num_timings = 1,
954 .bpc = 8,
955 .size = {
956 .width = 246,
957 .height = 184,
958 },
959 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
960};
961
962static const struct drm_display_mode lg_lb070wv8_mode = {
963 .clock = 33246,
964 .hdisplay = 800,
965 .hsync_start = 800 + 88,
966 .hsync_end = 800 + 88 + 80,
967 .htotal = 800 + 88 + 80 + 88,
968 .vdisplay = 480,
969 .vsync_start = 480 + 10,
970 .vsync_end = 480 + 10 + 25,
971 .vtotal = 480 + 10 + 25 + 10,
972 .vrefresh = 60,
973};
974
975static const struct panel_desc lg_lb070wv8 = {
976 .modes = &lg_lb070wv8_mode,
977 .num_modes = 1,
978 .bpc = 16,
979 .size = {
980 .width = 151,
981 .height = 91,
982 },
983 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
984};
985
986static const struct drm_display_mode lg_lp120up1_mode = {
987 .clock = 162300,
988 .hdisplay = 1920,
989 .hsync_start = 1920 + 40,
990 .hsync_end = 1920 + 40 + 40,
991 .htotal = 1920 + 40 + 40+ 80,
992 .vdisplay = 1280,
993 .vsync_start = 1280 + 4,
994 .vsync_end = 1280 + 4 + 4,
995 .vtotal = 1280 + 4 + 4 + 12,
996 .vrefresh = 60,
997};
998
999static const struct panel_desc lg_lp120up1 = {
1000 .modes = &lg_lp120up1_mode,
1001 .num_modes = 1,
1002 .bpc = 8,
1003 .size = {
1004 .width = 267,
1005 .height = 183,
1006 },
1007};
1008
1009static const struct drm_display_mode lg_lp129qe_mode = {
1010 .clock = 285250,
1011 .hdisplay = 2560,
1012 .hsync_start = 2560 + 48,
1013 .hsync_end = 2560 + 48 + 32,
1014 .htotal = 2560 + 48 + 32 + 80,
1015 .vdisplay = 1700,
1016 .vsync_start = 1700 + 3,
1017 .vsync_end = 1700 + 3 + 10,
1018 .vtotal = 1700 + 3 + 10 + 36,
1019 .vrefresh = 60,
1020};
1021
1022static const struct panel_desc lg_lp129qe = {
1023 .modes = &lg_lp129qe_mode,
1024 .num_modes = 1,
1025 .bpc = 8,
1026 .size = {
1027 .width = 272,
1028 .height = 181,
1029 },
1030};
1031
1032static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1033 .clock = 10870,
1034 .hdisplay = 480,
1035 .hsync_start = 480 + 2,
1036 .hsync_end = 480 + 2 + 41,
1037 .htotal = 480 + 2 + 41 + 2,
1038 .vdisplay = 272,
1039 .vsync_start = 272 + 2,
1040 .vsync_end = 272 + 2 + 4,
1041 .vtotal = 272 + 2 + 4 + 2,
1042 .vrefresh = 74,
1043 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1044};
1045
1046static const struct panel_desc nec_nl4827hc19_05b = {
1047 .modes = &nec_nl4827hc19_05b_mode,
1048 .num_modes = 1,
1049 .bpc = 8,
1050 .size = {
1051 .width = 95,
1052 .height = 54,
1053 },
1054 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1055};
1056
1057static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1058 .pixelclock = { 30000000, 30000000, 40000000 },
1059 .hactive = { 800, 800, 800 },
1060 .hfront_porch = { 40, 40, 40 },
1061 .hback_porch = { 40, 40, 40 },
1062 .hsync_len = { 1, 48, 48 },
1063 .vactive = { 480, 480, 480 },
1064 .vfront_porch = { 13, 13, 13 },
1065 .vback_porch = { 29, 29, 29 },
1066 .vsync_len = { 3, 3, 3 },
1067 .flags = DISPLAY_FLAGS_DE_HIGH,
1068};
1069
1070static const struct panel_desc okaya_rs800480t_7x0gp = {
1071 .timings = &okaya_rs800480t_7x0gp_timing,
1072 .num_timings = 1,
1073 .bpc = 6,
1074 .size = {
1075 .width = 154,
1076 .height = 87,
1077 },
1078 .delay = {
1079 .prepare = 41,
1080 .enable = 50,
1081 .unprepare = 41,
1082 .disable = 50,
1083 },
1084 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1085};
1086
1087static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1088 .clock = 25000,
1089 .hdisplay = 480,
1090 .hsync_start = 480 + 10,
1091 .hsync_end = 480 + 10 + 10,
1092 .htotal = 480 + 10 + 10 + 15,
1093 .vdisplay = 800,
1094 .vsync_start = 800 + 3,
1095 .vsync_end = 800 + 3 + 3,
1096 .vtotal = 800 + 3 + 3 + 3,
1097 .vrefresh = 60,
1098};
1099
1100static const struct panel_desc ortustech_com43h4m85ulc = {
1101 .modes = &ortustech_com43h4m85ulc_mode,
1102 .num_modes = 1,
1103 .bpc = 8,
1104 .size = {
1105 .width = 56,
1106 .height = 93,
1107 },
1108 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1109};
1110
1111static const struct drm_display_mode qd43003c0_40_mode = {
1112 .clock = 9000,
1113 .hdisplay = 480,
1114 .hsync_start = 480 + 8,
1115 .hsync_end = 480 + 8 + 4,
1116 .htotal = 480 + 8 + 4 + 39,
1117 .vdisplay = 272,
1118 .vsync_start = 272 + 4,
1119 .vsync_end = 272 + 4 + 10,
1120 .vtotal = 272 + 4 + 10 + 2,
1121 .vrefresh = 60,
1122};
1123
1124static const struct panel_desc qd43003c0_40 = {
1125 .modes = &qd43003c0_40_mode,
1126 .num_modes = 1,
1127 .bpc = 8,
1128 .size = {
1129 .width = 95,
1130 .height = 53,
1131 },
1132 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1133};
1134
1135static const struct drm_display_mode samsung_ltn101nt05_mode = {
1136 .clock = 54030,
1137 .hdisplay = 1024,
1138 .hsync_start = 1024 + 24,
1139 .hsync_end = 1024 + 24 + 136,
1140 .htotal = 1024 + 24 + 136 + 160,
1141 .vdisplay = 600,
1142 .vsync_start = 600 + 3,
1143 .vsync_end = 600 + 3 + 6,
1144 .vtotal = 600 + 3 + 6 + 61,
1145 .vrefresh = 60,
1146};
1147
1148static const struct panel_desc samsung_ltn101nt05 = {
1149 .modes = &samsung_ltn101nt05_mode,
1150 .num_modes = 1,
1151 .bpc = 6,
1152 .size = {
1153 .width = 1024,
1154 .height = 600,
1155 },
1156};
1157
1158static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1159 .clock = 76300,
1160 .hdisplay = 1366,
1161 .hsync_start = 1366 + 64,
1162 .hsync_end = 1366 + 64 + 48,
1163 .htotal = 1366 + 64 + 48 + 128,
1164 .vdisplay = 768,
1165 .vsync_start = 768 + 2,
1166 .vsync_end = 768 + 2 + 5,
1167 .vtotal = 768 + 2 + 5 + 17,
1168 .vrefresh = 60,
1169};
1170
1171static const struct panel_desc samsung_ltn140at29_301 = {
1172 .modes = &samsung_ltn140at29_301_mode,
1173 .num_modes = 1,
1174 .bpc = 6,
1175 .size = {
1176 .width = 320,
1177 .height = 187,
1178 },
1179};
1180
1181static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1182 .clock = 33300,
1183 .hdisplay = 800,
1184 .hsync_start = 800 + 1,
1185 .hsync_end = 800 + 1 + 64,
1186 .htotal = 800 + 1 + 64 + 64,
1187 .vdisplay = 480,
1188 .vsync_start = 480 + 1,
1189 .vsync_end = 480 + 1 + 23,
1190 .vtotal = 480 + 1 + 23 + 22,
1191 .vrefresh = 60,
1192};
1193
1194static const struct panel_desc shelly_sca07010_bfn_lnn = {
1195 .modes = &shelly_sca07010_bfn_lnn_mode,
1196 .num_modes = 1,
1197 .size = {
1198 .width = 152,
1199 .height = 91,
1200 },
1201 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1202};
1203
1204static const struct display_timing urt_umsh_8596md_timing = {
1205 .pixelclock = { 33260000, 33260000, 33260000 },
1206 .hactive = { 800, 800, 800 },
1207 .hfront_porch = { 41, 41, 41 },
1208 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1209 .hsync_len = { 71, 128, 128 },
1210 .vactive = { 480, 480, 480 },
1211 .vfront_porch = { 10, 10, 10 },
1212 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1213 .vsync_len = { 2, 2, 2 },
1214 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1215 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1216};
1217
1218static const struct panel_desc urt_umsh_8596md_lvds = {
1219 .timings = &urt_umsh_8596md_timing,
1220 .num_timings = 1,
1221 .bpc = 6,
1222 .size = {
1223 .width = 152,
1224 .height = 91,
1225 },
1226 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1227};
1228
1229static const struct panel_desc urt_umsh_8596md_parallel = {
1230 .timings = &urt_umsh_8596md_timing,
1231 .num_timings = 1,
1232 .bpc = 6,
1233 .size = {
1234 .width = 152,
1235 .height = 91,
1236 },
1237 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1238};
1239
1240static const struct of_device_id platform_of_match[] = {
1241 {
1242 .compatible = "ampire,am800480r3tmqwa1h",
1243 .data = &ire_am800480r3tmqwa1h,
1244 }, {
1245 .compatible = "auo,b101aw03",
1246 .data = &auo_b101aw03,
1247 }, {
1248 .compatible = "auo,b101ean01",
1249 .data = &auo_b101ean01,
1250 }, {
1251 .compatible = "auo,b101xtn01",
1252 .data = &auo_b101xtn01,
1253 }, {
1254 .compatible = "auo,b116xw03",
1255 .data = &auo_b116xw03,
1256 }, {
1257 .compatible = "auo,b133htn01",
1258 .data = &auo_b133htn01,
1259 }, {
1260 .compatible = "auo,b133xtn01",
1261 .data = &auo_b133xtn01,
1262 }, {
1263 .compatible = "avic,tm070ddh03",
1264 .data = &avic_tm070ddh03,
1265 }, {
1266 .compatible = "chunghwa,claa101wa01a",
1267 .data = &chunghwa_claa101wa01a
1268 }, {
1269 .compatible = "chunghwa,claa101wb01",
1270 .data = &chunghwa_claa101wb01
1271 }, {
1272 .compatible = "edt,et057090dhu",
1273 .data = &edt_et057090dhu,
1274 }, {
1275 .compatible = "edt,et070080dh6",
1276 .data = &edt_etm0700g0dh6,
1277 }, {
1278 .compatible = "edt,etm0700g0dh6",
1279 .data = &edt_etm0700g0dh6,
1280 }, {
1281 .compatible = "foxlink,fl500wvr00-a0t",
1282 .data = &foxlink_fl500wvr00_a0t,
1283 }, {
1284 .compatible = "giantplus,gpg482739qs5",
1285 .data = &giantplus_gpg482739qs5
1286 }, {
1287 .compatible = "hannstar,hsd070pww1",
1288 .data = &hannstar_hsd070pww1,
1289 }, {
1290 .compatible = "hannstar,hsd100pxn1",
1291 .data = &hannstar_hsd100pxn1,
1292 }, {
1293 .compatible = "hit,tx23d38vm0caa",
1294 .data = &hitachi_tx23d38vm0caa
1295 }, {
1296 .compatible = "innolux,at043tn24",
1297 .data = &innolux_at043tn24,
1298 }, {
1299 .compatible ="innolux,g121i1-l01",
1300 .data = &innolux_g121i1_l01
1301 }, {
1302 .compatible = "innolux,g121x1-l03",
1303 .data = &innolux_g121x1_l03,
1304 }, {
1305 .compatible = "innolux,n116bge",
1306 .data = &innolux_n116bge,
1307 }, {
1308 .compatible = "innolux,n156bge-l21",
1309 .data = &innolux_n156bge_l21,
1310 }, {
1311 .compatible = "innolux,zj070na-01p",
1312 .data = &innolux_zj070na_01p,
1313 }, {
1314 .compatible = "kyo,tcg121xglp",
1315 .data = &kyo_tcg121xglp,
1316 }, {
1317 .compatible = "lg,lb070wv8",
1318 .data = &lg_lb070wv8,
1319 }, {
1320 .compatible = "lg,lp120up1",
1321 .data = &lg_lp120up1,
1322 }, {
1323 .compatible = "lg,lp129qe",
1324 .data = &lg_lp129qe,
1325 }, {
1326 .compatible = "nec,nl4827hc19-05b",
1327 .data = &nec_nl4827hc19_05b,
1328 }, {
1329 .compatible = "okaya,rs800480t-7x0gp",
1330 .data = &okaya_rs800480t_7x0gp,
1331 }, {
1332 .compatible = "ortustech,com43h4m85ulc",
1333 .data = &ortustech_com43h4m85ulc,
1334 }, {
1335 .compatible = "qiaodian,qd43003c0-40",
1336 .data = &qd43003c0_40,
1337 }, {
1338 .compatible = "samsung,ltn101nt05",
1339 .data = &samsung_ltn101nt05,
1340 }, {
1341 .compatible = "samsung,ltn140at29-301",
1342 .data = &samsung_ltn140at29_301,
1343 }, {
1344 .compatible = "shelly,sca07010-bfn-lnn",
1345 .data = &shelly_sca07010_bfn_lnn,
1346 }, {
1347 .compatible = "urt,umsh-8596md-t",
1348 .data = &urt_umsh_8596md_parallel,
1349 }, {
1350 .compatible = "urt,umsh-8596md-1t",
1351 .data = &urt_umsh_8596md_parallel,
1352 }, {
1353 .compatible = "urt,umsh-8596md-7t",
1354 .data = &urt_umsh_8596md_parallel,
1355 }, {
1356 .compatible = "urt,umsh-8596md-11t",
1357 .data = &urt_umsh_8596md_lvds,
1358 }, {
1359 .compatible = "urt,umsh-8596md-19t",
1360 .data = &urt_umsh_8596md_lvds,
1361 }, {
1362 .compatible = "urt,umsh-8596md-20t",
1363 .data = &urt_umsh_8596md_parallel,
1364 }, {
1365 /* sentinel */
1366 }
1367};
1368MODULE_DEVICE_TABLE(of, platform_of_match);
1369
1370static int panel_simple_platform_probe(struct platform_device *pdev)
1371{
1372 const struct of_device_id *id;
1373
1374 id = of_match_node(platform_of_match, pdev->dev.of_node);
1375 if (!id)
1376 return -ENODEV;
1377
1378 return panel_simple_probe(&pdev->dev, id->data);
1379}
1380
1381static int panel_simple_platform_remove(struct platform_device *pdev)
1382{
1383 return panel_simple_remove(&pdev->dev);
1384}
1385
1386static void panel_simple_platform_shutdown(struct platform_device *pdev)
1387{
1388 panel_simple_shutdown(&pdev->dev);
1389}
1390
1391static struct platform_driver panel_simple_platform_driver = {
1392 .driver = {
1393 .name = "panel-simple",
1394 .of_match_table = platform_of_match,
1395 },
1396 .probe = panel_simple_platform_probe,
1397 .remove = panel_simple_platform_remove,
1398 .shutdown = panel_simple_platform_shutdown,
1399};
1400
1401struct panel_desc_dsi {
1402 struct panel_desc desc;
1403
1404 unsigned long flags;
1405 enum mipi_dsi_pixel_format format;
1406 unsigned int lanes;
1407};
1408
1409static const struct drm_display_mode auo_b080uan01_mode = {
1410 .clock = 154500,
1411 .hdisplay = 1200,
1412 .hsync_start = 1200 + 62,
1413 .hsync_end = 1200 + 62 + 4,
1414 .htotal = 1200 + 62 + 4 + 62,
1415 .vdisplay = 1920,
1416 .vsync_start = 1920 + 9,
1417 .vsync_end = 1920 + 9 + 2,
1418 .vtotal = 1920 + 9 + 2 + 8,
1419 .vrefresh = 60,
1420};
1421
1422static const struct panel_desc_dsi auo_b080uan01 = {
1423 .desc = {
1424 .modes = &auo_b080uan01_mode,
1425 .num_modes = 1,
1426 .bpc = 8,
1427 .size = {
1428 .width = 108,
1429 .height = 272,
1430 },
1431 },
1432 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1433 .format = MIPI_DSI_FMT_RGB888,
1434 .lanes = 4,
1435};
1436
1437static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1438 .clock = 160000,
1439 .hdisplay = 1200,
1440 .hsync_start = 1200 + 120,
1441 .hsync_end = 1200 + 120 + 20,
1442 .htotal = 1200 + 120 + 20 + 21,
1443 .vdisplay = 1920,
1444 .vsync_start = 1920 + 21,
1445 .vsync_end = 1920 + 21 + 3,
1446 .vtotal = 1920 + 21 + 3 + 18,
1447 .vrefresh = 60,
1448 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1449};
1450
1451static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1452 .desc = {
1453 .modes = &boe_tv080wum_nl0_mode,
1454 .num_modes = 1,
1455 .size = {
1456 .width = 107,
1457 .height = 172,
1458 },
1459 },
1460 .flags = MIPI_DSI_MODE_VIDEO |
1461 MIPI_DSI_MODE_VIDEO_BURST |
1462 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1463 .format = MIPI_DSI_FMT_RGB888,
1464 .lanes = 4,
1465};
1466
1467static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1468 .clock = 71000,
1469 .hdisplay = 800,
1470 .hsync_start = 800 + 32,
1471 .hsync_end = 800 + 32 + 1,
1472 .htotal = 800 + 32 + 1 + 57,
1473 .vdisplay = 1280,
1474 .vsync_start = 1280 + 28,
1475 .vsync_end = 1280 + 28 + 1,
1476 .vtotal = 1280 + 28 + 1 + 14,
1477 .vrefresh = 60,
1478};
1479
1480static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1481 .desc = {
1482 .modes = &lg_ld070wx3_sl01_mode,
1483 .num_modes = 1,
1484 .bpc = 8,
1485 .size = {
1486 .width = 94,
1487 .height = 151,
1488 },
1489 },
1490 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1491 .format = MIPI_DSI_FMT_RGB888,
1492 .lanes = 4,
1493};
1494
1495static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1496 .clock = 67000,
1497 .hdisplay = 720,
1498 .hsync_start = 720 + 12,
1499 .hsync_end = 720 + 12 + 4,
1500 .htotal = 720 + 12 + 4 + 112,
1501 .vdisplay = 1280,
1502 .vsync_start = 1280 + 8,
1503 .vsync_end = 1280 + 8 + 4,
1504 .vtotal = 1280 + 8 + 4 + 12,
1505 .vrefresh = 60,
1506};
1507
1508static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1509 .desc = {
1510 .modes = &lg_lh500wx1_sd03_mode,
1511 .num_modes = 1,
1512 .bpc = 8,
1513 .size = {
1514 .width = 62,
1515 .height = 110,
1516 },
1517 },
1518 .flags = MIPI_DSI_MODE_VIDEO,
1519 .format = MIPI_DSI_FMT_RGB888,
1520 .lanes = 4,
1521};
1522
1523static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1524 .clock = 157200,
1525 .hdisplay = 1920,
1526 .hsync_start = 1920 + 154,
1527 .hsync_end = 1920 + 154 + 16,
1528 .htotal = 1920 + 154 + 16 + 32,
1529 .vdisplay = 1200,
1530 .vsync_start = 1200 + 17,
1531 .vsync_end = 1200 + 17 + 2,
1532 .vtotal = 1200 + 17 + 2 + 16,
1533 .vrefresh = 60,
1534};
1535
1536static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1537 .desc = {
1538 .modes = &panasonic_vvx10f004b00_mode,
1539 .num_modes = 1,
1540 .bpc = 8,
1541 .size = {
1542 .width = 217,
1543 .height = 136,
1544 },
1545 },
1546 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1547 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1548 .format = MIPI_DSI_FMT_RGB888,
1549 .lanes = 4,
1550};
1551
1552
1553static const struct of_device_id dsi_of_match[] = {
1554 {
1555 .compatible = "auo,b080uan01",
1556 .data = &auo_b080uan01
1557 }, {
1558 .compatible = "boe,tv080wum-nl0",
1559 .data = &boe_tv080wum_nl0
1560 }, {
1561 .compatible = "lg,ld070wx3-sl01",
1562 .data = &lg_ld070wx3_sl01
1563 }, {
1564 .compatible = "lg,lh500wx1-sd03",
1565 .data = &lg_lh500wx1_sd03
1566 }, {
1567 .compatible = "panasonic,vvx10f004b00",
1568 .data = &panasonic_vvx10f004b00
1569 }, {
1570 /* sentinel */
1571 }
1572};
1573MODULE_DEVICE_TABLE(of, dsi_of_match);
1574
1575static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1576{
1577 const struct panel_desc_dsi *desc;
1578 const struct of_device_id *id;
1579 int err;
1580
1581 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1582 if (!id)
1583 return -ENODEV;
1584
1585 desc = id->data;
1586
1587 err = panel_simple_probe(&dsi->dev, &desc->desc);
1588 if (err < 0)
1589 return err;
1590
1591 dsi->mode_flags = desc->flags;
1592 dsi->format = desc->format;
1593 dsi->lanes = desc->lanes;
1594
1595 return mipi_dsi_attach(dsi);
1596}
1597
1598static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1599{
1600 int err;
1601
1602 err = mipi_dsi_detach(dsi);
1603 if (err < 0)
1604 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1605
1606 return panel_simple_remove(&dsi->dev);
1607}
1608
1609static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1610{
1611 panel_simple_shutdown(&dsi->dev);
1612}
1613
1614static struct mipi_dsi_driver panel_simple_dsi_driver = {
1615 .driver = {
1616 .name = "panel-simple-dsi",
1617 .of_match_table = dsi_of_match,
1618 },
1619 .probe = panel_simple_dsi_probe,
1620 .remove = panel_simple_dsi_remove,
1621 .shutdown = panel_simple_dsi_shutdown,
1622};
1623
1624static int __init panel_simple_init(void)
1625{
1626 int err;
1627
1628 err = platform_driver_register(&panel_simple_platform_driver);
1629 if (err < 0)
1630 return err;
1631
1632 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1633 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1634 if (err < 0)
1635 return err;
1636 }
1637
1638 return 0;
1639}
1640module_init(panel_simple_init);
1641
1642static void __exit panel_simple_exit(void)
1643{
1644 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1645 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1646
1647 platform_driver_unregister(&panel_simple_platform_driver);
1648}
1649module_exit(panel_simple_exit);
1650
1651MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1652MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1653MODULE_LICENSE("GPL and additional rights");
1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/delay.h>
25#include <linux/gpio/consumer.h>
26#include <linux/i2c.h>
27#include <linux/media-bus-format.h>
28#include <linux/module.h>
29#include <linux/of_platform.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32#include <linux/regulator/consumer.h>
33
34#include <video/display_timing.h>
35#include <video/of_display_timing.h>
36#include <video/videomode.h>
37
38#include <drm/drm_crtc.h>
39#include <drm/drm_device.h>
40#include <drm/drm_edid.h>
41#include <drm/drm_mipi_dsi.h>
42#include <drm/drm_panel.h>
43#include <drm/drm_of.h>
44
45/**
46 * struct panel_desc - Describes a simple panel.
47 */
48struct panel_desc {
49 /**
50 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 *
52 * If only one mode then this can just be the address of the mode.
53 * NOTE: cannot be used with "timings" and also if this is specified
54 * then you cannot override the mode in the device tree.
55 */
56 const struct drm_display_mode *modes;
57
58 /** @num_modes: Number of elements in modes array. */
59 unsigned int num_modes;
60
61 /**
62 * @timings: Pointer to array of display timings
63 *
64 * NOTE: cannot be used with "modes" and also these will be used to
65 * validate a device tree override if one is present.
66 */
67 const struct display_timing *timings;
68
69 /** @num_timings: Number of elements in timings array. */
70 unsigned int num_timings;
71
72 /** @bpc: Bits per color. */
73 unsigned int bpc;
74
75 /** @size: Structure containing the physical size of this panel. */
76 struct {
77 /**
78 * @size.width: Width (in mm) of the active display area.
79 */
80 unsigned int width;
81
82 /**
83 * @size.height: Height (in mm) of the active display area.
84 */
85 unsigned int height;
86 } size;
87
88 /** @delay: Structure containing various delay values for this panel. */
89 struct {
90 /**
91 * @delay.prepare: Time for the panel to become ready.
92 *
93 * The time (in milliseconds) that it takes for the panel to
94 * become ready and start receiving video data
95 */
96 unsigned int prepare;
97
98 /**
99 * @delay.enable: Time for the panel to display a valid frame.
100 *
101 * The time (in milliseconds) that it takes for the panel to
102 * display the first valid frame after starting to receive
103 * video data.
104 */
105 unsigned int enable;
106
107 /**
108 * @delay.disable: Time for the panel to turn the display off.
109 *
110 * The time (in milliseconds) that it takes for the panel to
111 * turn the display off (no content is visible).
112 */
113 unsigned int disable;
114
115 /**
116 * @delay.unprepare: Time to power down completely.
117 *
118 * The time (in milliseconds) that it takes for the panel
119 * to power itself down completely.
120 *
121 * This time is used to prevent a future "prepare" from
122 * starting until at least this many milliseconds has passed.
123 * If at prepare time less time has passed since unprepare
124 * finished, the driver waits for the remaining time.
125 */
126 unsigned int unprepare;
127 } delay;
128
129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
130 u32 bus_format;
131
132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
133 u32 bus_flags;
134
135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
136 int connector_type;
137};
138
139struct panel_simple {
140 struct drm_panel base;
141 bool enabled;
142
143 bool prepared;
144
145 ktime_t unprepared_time;
146
147 const struct panel_desc *desc;
148
149 struct regulator *supply;
150 struct i2c_adapter *ddc;
151
152 struct gpio_desc *enable_gpio;
153
154 struct edid *edid;
155
156 struct drm_display_mode override_mode;
157
158 enum drm_panel_orientation orientation;
159};
160
161static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
162{
163 return container_of(panel, struct panel_simple, base);
164}
165
166static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
167 struct drm_connector *connector)
168{
169 struct drm_display_mode *mode;
170 unsigned int i, num = 0;
171
172 for (i = 0; i < panel->desc->num_timings; i++) {
173 const struct display_timing *dt = &panel->desc->timings[i];
174 struct videomode vm;
175
176 videomode_from_timing(dt, &vm);
177 mode = drm_mode_create(connector->dev);
178 if (!mode) {
179 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
180 dt->hactive.typ, dt->vactive.typ);
181 continue;
182 }
183
184 drm_display_mode_from_videomode(&vm, mode);
185
186 mode->type |= DRM_MODE_TYPE_DRIVER;
187
188 if (panel->desc->num_timings == 1)
189 mode->type |= DRM_MODE_TYPE_PREFERRED;
190
191 drm_mode_probed_add(connector, mode);
192 num++;
193 }
194
195 return num;
196}
197
198static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
199 struct drm_connector *connector)
200{
201 struct drm_display_mode *mode;
202 unsigned int i, num = 0;
203
204 for (i = 0; i < panel->desc->num_modes; i++) {
205 const struct drm_display_mode *m = &panel->desc->modes[i];
206
207 mode = drm_mode_duplicate(connector->dev, m);
208 if (!mode) {
209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
210 m->hdisplay, m->vdisplay,
211 drm_mode_vrefresh(m));
212 continue;
213 }
214
215 mode->type |= DRM_MODE_TYPE_DRIVER;
216
217 if (panel->desc->num_modes == 1)
218 mode->type |= DRM_MODE_TYPE_PREFERRED;
219
220 drm_mode_set_name(mode);
221
222 drm_mode_probed_add(connector, mode);
223 num++;
224 }
225
226 return num;
227}
228
229static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
230 struct drm_connector *connector)
231{
232 struct drm_display_mode *mode;
233 bool has_override = panel->override_mode.type;
234 unsigned int num = 0;
235
236 if (!panel->desc)
237 return 0;
238
239 if (has_override) {
240 mode = drm_mode_duplicate(connector->dev,
241 &panel->override_mode);
242 if (mode) {
243 drm_mode_probed_add(connector, mode);
244 num = 1;
245 } else {
246 dev_err(panel->base.dev, "failed to add override mode\n");
247 }
248 }
249
250 /* Only add timings if override was not there or failed to validate */
251 if (num == 0 && panel->desc->num_timings)
252 num = panel_simple_get_timings_modes(panel, connector);
253
254 /*
255 * Only add fixed modes if timings/override added no mode.
256 *
257 * We should only ever have either the display timings specified
258 * or a fixed mode. Anything else is rather bogus.
259 */
260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
261 if (num == 0)
262 num = panel_simple_get_display_modes(panel, connector);
263
264 connector->display_info.bpc = panel->desc->bpc;
265 connector->display_info.width_mm = panel->desc->size.width;
266 connector->display_info.height_mm = panel->desc->size.height;
267 if (panel->desc->bus_format)
268 drm_display_info_set_bus_formats(&connector->display_info,
269 &panel->desc->bus_format, 1);
270 connector->display_info.bus_flags = panel->desc->bus_flags;
271
272 return num;
273}
274
275static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
276{
277 ktime_t now_ktime, min_ktime;
278
279 if (!min_ms)
280 return;
281
282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
283 now_ktime = ktime_get_boottime();
284
285 if (ktime_before(now_ktime, min_ktime))
286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
287}
288
289static int panel_simple_disable(struct drm_panel *panel)
290{
291 struct panel_simple *p = to_panel_simple(panel);
292
293 if (!p->enabled)
294 return 0;
295
296 if (p->desc->delay.disable)
297 msleep(p->desc->delay.disable);
298
299 p->enabled = false;
300
301 return 0;
302}
303
304static int panel_simple_suspend(struct device *dev)
305{
306 struct panel_simple *p = dev_get_drvdata(dev);
307
308 gpiod_set_value_cansleep(p->enable_gpio, 0);
309 regulator_disable(p->supply);
310 p->unprepared_time = ktime_get_boottime();
311
312 kfree(p->edid);
313 p->edid = NULL;
314
315 return 0;
316}
317
318static int panel_simple_unprepare(struct drm_panel *panel)
319{
320 struct panel_simple *p = to_panel_simple(panel);
321 int ret;
322
323 /* Unpreparing when already unprepared is a no-op */
324 if (!p->prepared)
325 return 0;
326
327 pm_runtime_mark_last_busy(panel->dev);
328 ret = pm_runtime_put_autosuspend(panel->dev);
329 if (ret < 0)
330 return ret;
331 p->prepared = false;
332
333 return 0;
334}
335
336static int panel_simple_resume(struct device *dev)
337{
338 struct panel_simple *p = dev_get_drvdata(dev);
339 int err;
340
341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
342
343 err = regulator_enable(p->supply);
344 if (err < 0) {
345 dev_err(dev, "failed to enable supply: %d\n", err);
346 return err;
347 }
348
349 gpiod_set_value_cansleep(p->enable_gpio, 1);
350
351 if (p->desc->delay.prepare)
352 msleep(p->desc->delay.prepare);
353
354 return 0;
355}
356
357static int panel_simple_prepare(struct drm_panel *panel)
358{
359 struct panel_simple *p = to_panel_simple(panel);
360 int ret;
361
362 /* Preparing when already prepared is a no-op */
363 if (p->prepared)
364 return 0;
365
366 ret = pm_runtime_get_sync(panel->dev);
367 if (ret < 0) {
368 pm_runtime_put_autosuspend(panel->dev);
369 return ret;
370 }
371
372 p->prepared = true;
373
374 return 0;
375}
376
377static int panel_simple_enable(struct drm_panel *panel)
378{
379 struct panel_simple *p = to_panel_simple(panel);
380
381 if (p->enabled)
382 return 0;
383
384 if (p->desc->delay.enable)
385 msleep(p->desc->delay.enable);
386
387 p->enabled = true;
388
389 return 0;
390}
391
392static int panel_simple_get_modes(struct drm_panel *panel,
393 struct drm_connector *connector)
394{
395 struct panel_simple *p = to_panel_simple(panel);
396 int num = 0;
397
398 /* probe EDID if a DDC bus is available */
399 if (p->ddc) {
400 pm_runtime_get_sync(panel->dev);
401
402 if (!p->edid)
403 p->edid = drm_get_edid(connector, p->ddc);
404
405 if (p->edid)
406 num += drm_add_edid_modes(connector, p->edid);
407
408 pm_runtime_mark_last_busy(panel->dev);
409 pm_runtime_put_autosuspend(panel->dev);
410 }
411
412 /* add hard-coded panel modes */
413 num += panel_simple_get_non_edid_modes(p, connector);
414
415 /*
416 * TODO: Remove once all drm drivers call
417 * drm_connector_set_orientation_from_panel()
418 */
419 drm_connector_set_panel_orientation(connector, p->orientation);
420
421 return num;
422}
423
424static int panel_simple_get_timings(struct drm_panel *panel,
425 unsigned int num_timings,
426 struct display_timing *timings)
427{
428 struct panel_simple *p = to_panel_simple(panel);
429 unsigned int i;
430
431 if (p->desc->num_timings < num_timings)
432 num_timings = p->desc->num_timings;
433
434 if (timings)
435 for (i = 0; i < num_timings; i++)
436 timings[i] = p->desc->timings[i];
437
438 return p->desc->num_timings;
439}
440
441static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
442{
443 struct panel_simple *p = to_panel_simple(panel);
444
445 return p->orientation;
446}
447
448static const struct drm_panel_funcs panel_simple_funcs = {
449 .disable = panel_simple_disable,
450 .unprepare = panel_simple_unprepare,
451 .prepare = panel_simple_prepare,
452 .enable = panel_simple_enable,
453 .get_modes = panel_simple_get_modes,
454 .get_orientation = panel_simple_get_orientation,
455 .get_timings = panel_simple_get_timings,
456};
457
458static struct panel_desc panel_dpi;
459
460static int panel_dpi_probe(struct device *dev,
461 struct panel_simple *panel)
462{
463 struct display_timing *timing;
464 const struct device_node *np;
465 struct panel_desc *desc;
466 unsigned int bus_flags;
467 struct videomode vm;
468 int ret;
469
470 np = dev->of_node;
471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
472 if (!desc)
473 return -ENOMEM;
474
475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
476 if (!timing)
477 return -ENOMEM;
478
479 ret = of_get_display_timing(np, "panel-timing", timing);
480 if (ret < 0) {
481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
482 np);
483 return ret;
484 }
485
486 desc->timings = timing;
487 desc->num_timings = 1;
488
489 of_property_read_u32(np, "width-mm", &desc->size.width);
490 of_property_read_u32(np, "height-mm", &desc->size.height);
491
492 /* Extract bus_flags from display_timing */
493 bus_flags = 0;
494 vm.flags = timing->flags;
495 drm_bus_flags_from_videomode(&vm, &bus_flags);
496 desc->bus_flags = bus_flags;
497
498 /* We do not know the connector for the DT node, so guess it */
499 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
500
501 panel->desc = desc;
502
503 return 0;
504}
505
506#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
507 (to_check->field.typ >= bounds->field.min && \
508 to_check->field.typ <= bounds->field.max)
509static void panel_simple_parse_panel_timing_node(struct device *dev,
510 struct panel_simple *panel,
511 const struct display_timing *ot)
512{
513 const struct panel_desc *desc = panel->desc;
514 struct videomode vm;
515 unsigned int i;
516
517 if (WARN_ON(desc->num_modes)) {
518 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
519 return;
520 }
521 if (WARN_ON(!desc->num_timings)) {
522 dev_err(dev, "Reject override mode: no timings specified\n");
523 return;
524 }
525
526 for (i = 0; i < panel->desc->num_timings; i++) {
527 const struct display_timing *dt = &panel->desc->timings[i];
528
529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
537 continue;
538
539 if (ot->flags != dt->flags)
540 continue;
541
542 videomode_from_timing(ot, &vm);
543 drm_display_mode_from_videomode(&vm, &panel->override_mode);
544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
545 DRM_MODE_TYPE_PREFERRED;
546 break;
547 }
548
549 if (WARN_ON(!panel->override_mode.type))
550 dev_err(dev, "Reject override mode: No display_timing found\n");
551}
552
553static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev,
554 struct panel_simple *panel)
555{
556 int ret, bpc;
557
558 ret = drm_of_lvds_get_data_mapping(dev->of_node);
559 if (ret < 0) {
560 if (ret == -EINVAL)
561 dev_warn(dev, "Ignore invalid data-mapping property\n");
562
563 /*
564 * Ignore non-existing or malformatted property, fallback to
565 * default data-mapping, and return 0.
566 */
567 return 0;
568 }
569
570 switch (ret) {
571 default:
572 WARN_ON(1);
573 fallthrough;
574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
575 fallthrough;
576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
577 bpc = 8;
578 break;
579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
580 bpc = 6;
581 }
582
583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) {
584 struct panel_desc *override_desc;
585
586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL);
587 if (!override_desc)
588 return -ENOMEM;
589
590 override_desc->bus_format = ret;
591 override_desc->bpc = bpc;
592 panel->desc = override_desc;
593 }
594
595 return 0;
596}
597
598static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
599{
600 struct panel_simple *panel;
601 struct display_timing dt;
602 struct device_node *ddc;
603 int connector_type;
604 u32 bus_flags;
605 int err;
606
607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
608 if (!panel)
609 return -ENOMEM;
610
611 panel->enabled = false;
612 panel->desc = desc;
613
614 panel->supply = devm_regulator_get(dev, "power");
615 if (IS_ERR(panel->supply))
616 return PTR_ERR(panel->supply);
617
618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
619 GPIOD_OUT_LOW);
620 if (IS_ERR(panel->enable_gpio))
621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
622 "failed to request GPIO\n");
623
624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
625 if (err) {
626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
627 return err;
628 }
629
630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
631 if (ddc) {
632 panel->ddc = of_find_i2c_adapter_by_node(ddc);
633 of_node_put(ddc);
634
635 if (!panel->ddc)
636 return -EPROBE_DEFER;
637 }
638
639 if (desc == &panel_dpi) {
640 /* Handle the generic panel-dpi binding */
641 err = panel_dpi_probe(dev, panel);
642 if (err)
643 goto free_ddc;
644 desc = panel->desc;
645 } else {
646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
647 panel_simple_parse_panel_timing_node(dev, panel, &dt);
648 }
649
650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
651 /* Optional data-mapping property for overriding bus format */
652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel);
653 if (err)
654 goto free_ddc;
655 }
656
657 connector_type = desc->connector_type;
658 /* Catch common mistakes for panels. */
659 switch (connector_type) {
660 case 0:
661 dev_warn(dev, "Specify missing connector_type\n");
662 connector_type = DRM_MODE_CONNECTOR_DPI;
663 break;
664 case DRM_MODE_CONNECTOR_LVDS:
665 WARN_ON(desc->bus_flags &
666 ~(DRM_BUS_FLAG_DE_LOW |
667 DRM_BUS_FLAG_DE_HIGH |
668 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
669 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
674 desc->bpc != 6);
675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
677 desc->bpc != 8);
678 break;
679 case DRM_MODE_CONNECTOR_eDP:
680 dev_warn(dev, "eDP panels moved to panel-edp\n");
681 err = -EINVAL;
682 goto free_ddc;
683 case DRM_MODE_CONNECTOR_DSI:
684 if (desc->bpc != 6 && desc->bpc != 8)
685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
686 break;
687 case DRM_MODE_CONNECTOR_DPI:
688 bus_flags = DRM_BUS_FLAG_DE_LOW |
689 DRM_BUS_FLAG_DE_HIGH |
690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
692 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
693 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
696 if (desc->bus_flags & ~bus_flags)
697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
698 if (!(desc->bus_flags & bus_flags))
699 dev_warn(dev, "Specify missing bus_flags\n");
700 if (desc->bus_format == 0)
701 dev_warn(dev, "Specify missing bus_format\n");
702 if (desc->bpc != 6 && desc->bpc != 8)
703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
704 break;
705 default:
706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
707 connector_type = DRM_MODE_CONNECTOR_DPI;
708 break;
709 }
710
711 dev_set_drvdata(dev, panel);
712
713 /*
714 * We use runtime PM for prepare / unprepare since those power the panel
715 * on and off and those can be very slow operations. This is important
716 * to optimize powering the panel on briefly to read the EDID before
717 * fully enabling the panel.
718 */
719 pm_runtime_enable(dev);
720 pm_runtime_set_autosuspend_delay(dev, 1000);
721 pm_runtime_use_autosuspend(dev);
722
723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
724
725 err = drm_panel_of_backlight(&panel->base);
726 if (err) {
727 dev_err_probe(dev, err, "Could not find backlight\n");
728 goto disable_pm_runtime;
729 }
730
731 drm_panel_add(&panel->base);
732
733 return 0;
734
735disable_pm_runtime:
736 pm_runtime_dont_use_autosuspend(dev);
737 pm_runtime_disable(dev);
738free_ddc:
739 if (panel->ddc)
740 put_device(&panel->ddc->dev);
741
742 return err;
743}
744
745static void panel_simple_remove(struct device *dev)
746{
747 struct panel_simple *panel = dev_get_drvdata(dev);
748
749 drm_panel_remove(&panel->base);
750 drm_panel_disable(&panel->base);
751 drm_panel_unprepare(&panel->base);
752
753 pm_runtime_dont_use_autosuspend(dev);
754 pm_runtime_disable(dev);
755 if (panel->ddc)
756 put_device(&panel->ddc->dev);
757}
758
759static void panel_simple_shutdown(struct device *dev)
760{
761 struct panel_simple *panel = dev_get_drvdata(dev);
762
763 drm_panel_disable(&panel->base);
764 drm_panel_unprepare(&panel->base);
765}
766
767static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
768 .clock = 71100,
769 .hdisplay = 1280,
770 .hsync_start = 1280 + 40,
771 .hsync_end = 1280 + 40 + 80,
772 .htotal = 1280 + 40 + 80 + 40,
773 .vdisplay = 800,
774 .vsync_start = 800 + 3,
775 .vsync_end = 800 + 3 + 10,
776 .vtotal = 800 + 3 + 10 + 10,
777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
778};
779
780static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
781 .modes = &ire_am_1280800n3tzqw_t00h_mode,
782 .num_modes = 1,
783 .bpc = 8,
784 .size = {
785 .width = 217,
786 .height = 136,
787 },
788 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
790 .connector_type = DRM_MODE_CONNECTOR_LVDS,
791};
792
793static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
794 .clock = 9000,
795 .hdisplay = 480,
796 .hsync_start = 480 + 2,
797 .hsync_end = 480 + 2 + 41,
798 .htotal = 480 + 2 + 41 + 2,
799 .vdisplay = 272,
800 .vsync_start = 272 + 2,
801 .vsync_end = 272 + 2 + 10,
802 .vtotal = 272 + 2 + 10 + 2,
803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
804};
805
806static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
807 .modes = &ire_am_480272h3tmqw_t01h_mode,
808 .num_modes = 1,
809 .bpc = 8,
810 .size = {
811 .width = 99,
812 .height = 58,
813 },
814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
815};
816
817static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
818 .clock = 33333,
819 .hdisplay = 800,
820 .hsync_start = 800 + 0,
821 .hsync_end = 800 + 0 + 255,
822 .htotal = 800 + 0 + 255 + 0,
823 .vdisplay = 480,
824 .vsync_start = 480 + 2,
825 .vsync_end = 480 + 2 + 45,
826 .vtotal = 480 + 2 + 45 + 0,
827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
828};
829
830static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
831 .pixelclock = { 29930000, 33260000, 36590000 },
832 .hactive = { 800, 800, 800 },
833 .hfront_porch = { 1, 40, 168 },
834 .hback_porch = { 88, 88, 88 },
835 .hsync_len = { 1, 128, 128 },
836 .vactive = { 480, 480, 480 },
837 .vfront_porch = { 1, 35, 37 },
838 .vback_porch = { 8, 8, 8 },
839 .vsync_len = { 1, 2, 2 },
840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
842 DISPLAY_FLAGS_SYNC_POSEDGE,
843};
844
845static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
846 .timings = &ire_am_800480l1tmqw_t00h_timing,
847 .num_timings = 1,
848 .bpc = 8,
849 .size = {
850 .width = 111,
851 .height = 67,
852 },
853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
854 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
857 .connector_type = DRM_MODE_CONNECTOR_DPI,
858};
859
860static const struct panel_desc ampire_am800480r3tmqwa1h = {
861 .modes = &ire_am800480r3tmqwa1h_mode,
862 .num_modes = 1,
863 .bpc = 6,
864 .size = {
865 .width = 152,
866 .height = 91,
867 },
868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
869};
870
871static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
872 .pixelclock = { 34500000, 39600000, 50400000 },
873 .hactive = { 800, 800, 800 },
874 .hfront_porch = { 12, 112, 312 },
875 .hback_porch = { 87, 87, 48 },
876 .hsync_len = { 1, 1, 40 },
877 .vactive = { 600, 600, 600 },
878 .vfront_porch = { 1, 21, 61 },
879 .vback_porch = { 38, 38, 19 },
880 .vsync_len = { 1, 1, 20 },
881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
883 DISPLAY_FLAGS_SYNC_POSEDGE,
884};
885
886static const struct panel_desc ampire_am800600p5tmqwtb8h = {
887 .timings = &ire_am800600p5tmqw_tb8h_timing,
888 .num_timings = 1,
889 .bpc = 6,
890 .size = {
891 .width = 162,
892 .height = 122,
893 },
894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
895 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
898 .connector_type = DRM_MODE_CONNECTOR_DPI,
899};
900
901static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
902 .pixelclock = { 26400000, 33300000, 46800000 },
903 .hactive = { 800, 800, 800 },
904 .hfront_porch = { 16, 210, 354 },
905 .hback_porch = { 45, 36, 6 },
906 .hsync_len = { 1, 10, 40 },
907 .vactive = { 480, 480, 480 },
908 .vfront_porch = { 7, 22, 147 },
909 .vback_porch = { 22, 13, 3 },
910 .vsync_len = { 1, 10, 20 },
911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
913};
914
915static const struct panel_desc armadeus_st0700_adapt = {
916 .timings = &santek_st0700i5y_rbslw_f_timing,
917 .num_timings = 1,
918 .bpc = 6,
919 .size = {
920 .width = 154,
921 .height = 86,
922 },
923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
925};
926
927static const struct drm_display_mode auo_b101aw03_mode = {
928 .clock = 51450,
929 .hdisplay = 1024,
930 .hsync_start = 1024 + 156,
931 .hsync_end = 1024 + 156 + 8,
932 .htotal = 1024 + 156 + 8 + 156,
933 .vdisplay = 600,
934 .vsync_start = 600 + 16,
935 .vsync_end = 600 + 16 + 6,
936 .vtotal = 600 + 16 + 6 + 16,
937};
938
939static const struct panel_desc auo_b101aw03 = {
940 .modes = &auo_b101aw03_mode,
941 .num_modes = 1,
942 .bpc = 6,
943 .size = {
944 .width = 223,
945 .height = 125,
946 },
947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
948 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
949 .connector_type = DRM_MODE_CONNECTOR_LVDS,
950};
951
952static const struct drm_display_mode auo_b101xtn01_mode = {
953 .clock = 72000,
954 .hdisplay = 1366,
955 .hsync_start = 1366 + 20,
956 .hsync_end = 1366 + 20 + 70,
957 .htotal = 1366 + 20 + 70,
958 .vdisplay = 768,
959 .vsync_start = 768 + 14,
960 .vsync_end = 768 + 14 + 42,
961 .vtotal = 768 + 14 + 42,
962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
963};
964
965static const struct panel_desc auo_b101xtn01 = {
966 .modes = &auo_b101xtn01_mode,
967 .num_modes = 1,
968 .bpc = 6,
969 .size = {
970 .width = 223,
971 .height = 125,
972 },
973};
974
975static const struct drm_display_mode auo_b116xw03_mode = {
976 .clock = 70589,
977 .hdisplay = 1366,
978 .hsync_start = 1366 + 40,
979 .hsync_end = 1366 + 40 + 40,
980 .htotal = 1366 + 40 + 40 + 32,
981 .vdisplay = 768,
982 .vsync_start = 768 + 10,
983 .vsync_end = 768 + 10 + 12,
984 .vtotal = 768 + 10 + 12 + 6,
985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
986};
987
988static const struct panel_desc auo_b116xw03 = {
989 .modes = &auo_b116xw03_mode,
990 .num_modes = 1,
991 .bpc = 6,
992 .size = {
993 .width = 256,
994 .height = 144,
995 },
996 .delay = {
997 .prepare = 1,
998 .enable = 200,
999 .disable = 200,
1000 .unprepare = 500,
1001 },
1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1004 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1005};
1006
1007static const struct display_timing auo_g070vvn01_timings = {
1008 .pixelclock = { 33300000, 34209000, 45000000 },
1009 .hactive = { 800, 800, 800 },
1010 .hfront_porch = { 20, 40, 200 },
1011 .hback_porch = { 87, 40, 1 },
1012 .hsync_len = { 1, 48, 87 },
1013 .vactive = { 480, 480, 480 },
1014 .vfront_porch = { 5, 13, 200 },
1015 .vback_porch = { 31, 31, 29 },
1016 .vsync_len = { 1, 1, 3 },
1017};
1018
1019static const struct panel_desc auo_g070vvn01 = {
1020 .timings = &auo_g070vvn01_timings,
1021 .num_timings = 1,
1022 .bpc = 8,
1023 .size = {
1024 .width = 152,
1025 .height = 91,
1026 },
1027 .delay = {
1028 .prepare = 200,
1029 .enable = 50,
1030 .disable = 50,
1031 .unprepare = 1000,
1032 },
1033};
1034
1035static const struct drm_display_mode auo_g101evn010_mode = {
1036 .clock = 68930,
1037 .hdisplay = 1280,
1038 .hsync_start = 1280 + 82,
1039 .hsync_end = 1280 + 82 + 2,
1040 .htotal = 1280 + 82 + 2 + 84,
1041 .vdisplay = 800,
1042 .vsync_start = 800 + 8,
1043 .vsync_end = 800 + 8 + 2,
1044 .vtotal = 800 + 8 + 2 + 6,
1045};
1046
1047static const struct panel_desc auo_g101evn010 = {
1048 .modes = &auo_g101evn010_mode,
1049 .num_modes = 1,
1050 .bpc = 6,
1051 .size = {
1052 .width = 216,
1053 .height = 135,
1054 },
1055 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1056 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1057};
1058
1059static const struct drm_display_mode auo_g104sn02_mode = {
1060 .clock = 40000,
1061 .hdisplay = 800,
1062 .hsync_start = 800 + 40,
1063 .hsync_end = 800 + 40 + 216,
1064 .htotal = 800 + 40 + 216 + 128,
1065 .vdisplay = 600,
1066 .vsync_start = 600 + 10,
1067 .vsync_end = 600 + 10 + 35,
1068 .vtotal = 600 + 10 + 35 + 2,
1069};
1070
1071static const struct panel_desc auo_g104sn02 = {
1072 .modes = &auo_g104sn02_mode,
1073 .num_modes = 1,
1074 .bpc = 8,
1075 .size = {
1076 .width = 211,
1077 .height = 158,
1078 },
1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1080 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1081};
1082
1083static const struct display_timing auo_g121ean01_timing = {
1084 .pixelclock = { 60000000, 74400000, 90000000 },
1085 .hactive = { 1280, 1280, 1280 },
1086 .hfront_porch = { 20, 50, 100 },
1087 .hback_porch = { 20, 50, 100 },
1088 .hsync_len = { 30, 100, 200 },
1089 .vactive = { 800, 800, 800 },
1090 .vfront_porch = { 2, 10, 25 },
1091 .vback_porch = { 2, 10, 25 },
1092 .vsync_len = { 4, 18, 50 },
1093};
1094
1095static const struct panel_desc auo_g121ean01 = {
1096 .timings = &auo_g121ean01_timing,
1097 .num_timings = 1,
1098 .bpc = 8,
1099 .size = {
1100 .width = 261,
1101 .height = 163,
1102 },
1103 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1104 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1105};
1106
1107static const struct display_timing auo_g133han01_timings = {
1108 .pixelclock = { 134000000, 141200000, 149000000 },
1109 .hactive = { 1920, 1920, 1920 },
1110 .hfront_porch = { 39, 58, 77 },
1111 .hback_porch = { 59, 88, 117 },
1112 .hsync_len = { 28, 42, 56 },
1113 .vactive = { 1080, 1080, 1080 },
1114 .vfront_porch = { 3, 8, 11 },
1115 .vback_porch = { 5, 14, 19 },
1116 .vsync_len = { 4, 14, 19 },
1117};
1118
1119static const struct panel_desc auo_g133han01 = {
1120 .timings = &auo_g133han01_timings,
1121 .num_timings = 1,
1122 .bpc = 8,
1123 .size = {
1124 .width = 293,
1125 .height = 165,
1126 },
1127 .delay = {
1128 .prepare = 200,
1129 .enable = 50,
1130 .disable = 50,
1131 .unprepare = 1000,
1132 },
1133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1134 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1135};
1136
1137static const struct display_timing auo_g156han04_timings = {
1138 .pixelclock = { 137000000, 141000000, 146000000 },
1139 .hactive = { 1920, 1920, 1920 },
1140 .hfront_porch = { 60, 60, 60 },
1141 .hback_porch = { 90, 92, 111 },
1142 .hsync_len = { 32, 32, 32 },
1143 .vactive = { 1080, 1080, 1080 },
1144 .vfront_porch = { 12, 12, 12 },
1145 .vback_porch = { 24, 36, 56 },
1146 .vsync_len = { 8, 8, 8 },
1147};
1148
1149static const struct panel_desc auo_g156han04 = {
1150 .timings = &auo_g156han04_timings,
1151 .num_timings = 1,
1152 .bpc = 8,
1153 .size = {
1154 .width = 344,
1155 .height = 194,
1156 },
1157 .delay = {
1158 .prepare = 50, /* T2 */
1159 .enable = 200, /* T3 */
1160 .disable = 110, /* T10 */
1161 .unprepare = 1000, /* T13 */
1162 },
1163 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1164 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1165 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1166};
1167
1168static const struct drm_display_mode auo_g156xtn01_mode = {
1169 .clock = 76000,
1170 .hdisplay = 1366,
1171 .hsync_start = 1366 + 33,
1172 .hsync_end = 1366 + 33 + 67,
1173 .htotal = 1560,
1174 .vdisplay = 768,
1175 .vsync_start = 768 + 4,
1176 .vsync_end = 768 + 4 + 4,
1177 .vtotal = 806,
1178};
1179
1180static const struct panel_desc auo_g156xtn01 = {
1181 .modes = &auo_g156xtn01_mode,
1182 .num_modes = 1,
1183 .bpc = 8,
1184 .size = {
1185 .width = 344,
1186 .height = 194,
1187 },
1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1189 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1190};
1191
1192static const struct display_timing auo_g185han01_timings = {
1193 .pixelclock = { 120000000, 144000000, 175000000 },
1194 .hactive = { 1920, 1920, 1920 },
1195 .hfront_porch = { 36, 120, 148 },
1196 .hback_porch = { 24, 88, 108 },
1197 .hsync_len = { 20, 48, 64 },
1198 .vactive = { 1080, 1080, 1080 },
1199 .vfront_porch = { 6, 10, 40 },
1200 .vback_porch = { 2, 5, 20 },
1201 .vsync_len = { 2, 5, 20 },
1202};
1203
1204static const struct panel_desc auo_g185han01 = {
1205 .timings = &auo_g185han01_timings,
1206 .num_timings = 1,
1207 .bpc = 8,
1208 .size = {
1209 .width = 409,
1210 .height = 230,
1211 },
1212 .delay = {
1213 .prepare = 50,
1214 .enable = 200,
1215 .disable = 110,
1216 .unprepare = 1000,
1217 },
1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1219 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1220};
1221
1222static const struct display_timing auo_g190ean01_timings = {
1223 .pixelclock = { 90000000, 108000000, 135000000 },
1224 .hactive = { 1280, 1280, 1280 },
1225 .hfront_porch = { 126, 184, 1266 },
1226 .hback_porch = { 84, 122, 844 },
1227 .hsync_len = { 70, 102, 704 },
1228 .vactive = { 1024, 1024, 1024 },
1229 .vfront_porch = { 4, 26, 76 },
1230 .vback_porch = { 2, 8, 25 },
1231 .vsync_len = { 2, 8, 25 },
1232};
1233
1234static const struct panel_desc auo_g190ean01 = {
1235 .timings = &auo_g190ean01_timings,
1236 .num_timings = 1,
1237 .bpc = 8,
1238 .size = {
1239 .width = 376,
1240 .height = 301,
1241 },
1242 .delay = {
1243 .prepare = 50,
1244 .enable = 200,
1245 .disable = 110,
1246 .unprepare = 1000,
1247 },
1248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1249 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1250};
1251
1252static const struct display_timing auo_p320hvn03_timings = {
1253 .pixelclock = { 106000000, 148500000, 164000000 },
1254 .hactive = { 1920, 1920, 1920 },
1255 .hfront_porch = { 25, 50, 130 },
1256 .hback_porch = { 25, 50, 130 },
1257 .hsync_len = { 20, 40, 105 },
1258 .vactive = { 1080, 1080, 1080 },
1259 .vfront_porch = { 8, 17, 150 },
1260 .vback_porch = { 8, 17, 150 },
1261 .vsync_len = { 4, 11, 100 },
1262};
1263
1264static const struct panel_desc auo_p320hvn03 = {
1265 .timings = &auo_p320hvn03_timings,
1266 .num_timings = 1,
1267 .bpc = 8,
1268 .size = {
1269 .width = 698,
1270 .height = 393,
1271 },
1272 .delay = {
1273 .prepare = 1,
1274 .enable = 450,
1275 .unprepare = 500,
1276 },
1277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1278 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1279};
1280
1281static const struct drm_display_mode auo_t215hvn01_mode = {
1282 .clock = 148800,
1283 .hdisplay = 1920,
1284 .hsync_start = 1920 + 88,
1285 .hsync_end = 1920 + 88 + 44,
1286 .htotal = 1920 + 88 + 44 + 148,
1287 .vdisplay = 1080,
1288 .vsync_start = 1080 + 4,
1289 .vsync_end = 1080 + 4 + 5,
1290 .vtotal = 1080 + 4 + 5 + 36,
1291};
1292
1293static const struct panel_desc auo_t215hvn01 = {
1294 .modes = &auo_t215hvn01_mode,
1295 .num_modes = 1,
1296 .bpc = 8,
1297 .size = {
1298 .width = 430,
1299 .height = 270,
1300 },
1301 .delay = {
1302 .disable = 5,
1303 .unprepare = 1000,
1304 },
1305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1306 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1307};
1308
1309static const struct drm_display_mode avic_tm070ddh03_mode = {
1310 .clock = 51200,
1311 .hdisplay = 1024,
1312 .hsync_start = 1024 + 160,
1313 .hsync_end = 1024 + 160 + 4,
1314 .htotal = 1024 + 160 + 4 + 156,
1315 .vdisplay = 600,
1316 .vsync_start = 600 + 17,
1317 .vsync_end = 600 + 17 + 1,
1318 .vtotal = 600 + 17 + 1 + 17,
1319};
1320
1321static const struct panel_desc avic_tm070ddh03 = {
1322 .modes = &avic_tm070ddh03_mode,
1323 .num_modes = 1,
1324 .bpc = 8,
1325 .size = {
1326 .width = 154,
1327 .height = 90,
1328 },
1329 .delay = {
1330 .prepare = 20,
1331 .enable = 200,
1332 .disable = 200,
1333 },
1334};
1335
1336static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1337 .clock = 30000,
1338 .hdisplay = 800,
1339 .hsync_start = 800 + 40,
1340 .hsync_end = 800 + 40 + 48,
1341 .htotal = 800 + 40 + 48 + 40,
1342 .vdisplay = 480,
1343 .vsync_start = 480 + 13,
1344 .vsync_end = 480 + 13 + 3,
1345 .vtotal = 480 + 13 + 3 + 29,
1346};
1347
1348static const struct panel_desc bananapi_s070wv20_ct16 = {
1349 .modes = &bananapi_s070wv20_ct16_mode,
1350 .num_modes = 1,
1351 .bpc = 6,
1352 .size = {
1353 .width = 154,
1354 .height = 86,
1355 },
1356};
1357
1358static const struct drm_display_mode boe_bp101wx1_100_mode = {
1359 .clock = 78945,
1360 .hdisplay = 1280,
1361 .hsync_start = 1280 + 0,
1362 .hsync_end = 1280 + 0 + 2,
1363 .htotal = 1280 + 62 + 0 + 2,
1364 .vdisplay = 800,
1365 .vsync_start = 800 + 8,
1366 .vsync_end = 800 + 8 + 2,
1367 .vtotal = 800 + 6 + 8 + 2,
1368};
1369
1370static const struct panel_desc boe_bp082wx1_100 = {
1371 .modes = &boe_bp101wx1_100_mode,
1372 .num_modes = 1,
1373 .bpc = 8,
1374 .size = {
1375 .width = 177,
1376 .height = 110,
1377 },
1378 .delay = {
1379 .enable = 50,
1380 .disable = 50,
1381 },
1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1383 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1384 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1385};
1386
1387static const struct panel_desc boe_bp101wx1_100 = {
1388 .modes = &boe_bp101wx1_100_mode,
1389 .num_modes = 1,
1390 .bpc = 8,
1391 .size = {
1392 .width = 217,
1393 .height = 136,
1394 },
1395 .delay = {
1396 .enable = 50,
1397 .disable = 50,
1398 },
1399 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1400 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1401 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1402};
1403
1404static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1405 .pixelclock = { 69922000, 71000000, 72293000 },
1406 .hactive = { 1280, 1280, 1280 },
1407 .hfront_porch = { 48, 48, 48 },
1408 .hback_porch = { 80, 80, 80 },
1409 .hsync_len = { 32, 32, 32 },
1410 .vactive = { 800, 800, 800 },
1411 .vfront_porch = { 3, 3, 3 },
1412 .vback_porch = { 14, 14, 14 },
1413 .vsync_len = { 6, 6, 6 },
1414};
1415
1416static const struct panel_desc boe_ev121wxm_n10_1850 = {
1417 .timings = &boe_ev121wxm_n10_1850_timing,
1418 .num_timings = 1,
1419 .bpc = 8,
1420 .size = {
1421 .width = 261,
1422 .height = 163,
1423 },
1424 .delay = {
1425 .prepare = 9,
1426 .enable = 300,
1427 .unprepare = 300,
1428 .disable = 560,
1429 },
1430 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1431 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1432 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1433};
1434
1435static const struct drm_display_mode boe_hv070wsa_mode = {
1436 .clock = 42105,
1437 .hdisplay = 1024,
1438 .hsync_start = 1024 + 30,
1439 .hsync_end = 1024 + 30 + 30,
1440 .htotal = 1024 + 30 + 30 + 30,
1441 .vdisplay = 600,
1442 .vsync_start = 600 + 10,
1443 .vsync_end = 600 + 10 + 10,
1444 .vtotal = 600 + 10 + 10 + 10,
1445};
1446
1447static const struct panel_desc boe_hv070wsa = {
1448 .modes = &boe_hv070wsa_mode,
1449 .num_modes = 1,
1450 .bpc = 8,
1451 .size = {
1452 .width = 154,
1453 .height = 90,
1454 },
1455 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1456 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1457 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1458};
1459
1460static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1461 .clock = 9000,
1462 .hdisplay = 480,
1463 .hsync_start = 480 + 5,
1464 .hsync_end = 480 + 5 + 5,
1465 .htotal = 480 + 5 + 5 + 40,
1466 .vdisplay = 272,
1467 .vsync_start = 272 + 8,
1468 .vsync_end = 272 + 8 + 8,
1469 .vtotal = 272 + 8 + 8 + 8,
1470 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1471};
1472
1473static const struct panel_desc cdtech_s043wq26h_ct7 = {
1474 .modes = &cdtech_s043wq26h_ct7_mode,
1475 .num_modes = 1,
1476 .bpc = 8,
1477 .size = {
1478 .width = 95,
1479 .height = 54,
1480 },
1481 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1482};
1483
1484/* S070PWS19HP-FC21 2017/04/22 */
1485static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1486 .clock = 51200,
1487 .hdisplay = 1024,
1488 .hsync_start = 1024 + 160,
1489 .hsync_end = 1024 + 160 + 20,
1490 .htotal = 1024 + 160 + 20 + 140,
1491 .vdisplay = 600,
1492 .vsync_start = 600 + 12,
1493 .vsync_end = 600 + 12 + 3,
1494 .vtotal = 600 + 12 + 3 + 20,
1495 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1496};
1497
1498static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1499 .modes = &cdtech_s070pws19hp_fc21_mode,
1500 .num_modes = 1,
1501 .bpc = 6,
1502 .size = {
1503 .width = 154,
1504 .height = 86,
1505 },
1506 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1507 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1508 .connector_type = DRM_MODE_CONNECTOR_DPI,
1509};
1510
1511/* S070SWV29HG-DC44 2017/09/21 */
1512static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1513 .clock = 33300,
1514 .hdisplay = 800,
1515 .hsync_start = 800 + 210,
1516 .hsync_end = 800 + 210 + 2,
1517 .htotal = 800 + 210 + 2 + 44,
1518 .vdisplay = 480,
1519 .vsync_start = 480 + 22,
1520 .vsync_end = 480 + 22 + 2,
1521 .vtotal = 480 + 22 + 2 + 21,
1522 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1523};
1524
1525static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1526 .modes = &cdtech_s070swv29hg_dc44_mode,
1527 .num_modes = 1,
1528 .bpc = 6,
1529 .size = {
1530 .width = 154,
1531 .height = 86,
1532 },
1533 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1534 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1535 .connector_type = DRM_MODE_CONNECTOR_DPI,
1536};
1537
1538static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1539 .clock = 35000,
1540 .hdisplay = 800,
1541 .hsync_start = 800 + 40,
1542 .hsync_end = 800 + 40 + 40,
1543 .htotal = 800 + 40 + 40 + 48,
1544 .vdisplay = 480,
1545 .vsync_start = 480 + 29,
1546 .vsync_end = 480 + 29 + 13,
1547 .vtotal = 480 + 29 + 13 + 3,
1548 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1549};
1550
1551static const struct panel_desc cdtech_s070wv95_ct16 = {
1552 .modes = &cdtech_s070wv95_ct16_mode,
1553 .num_modes = 1,
1554 .bpc = 8,
1555 .size = {
1556 .width = 154,
1557 .height = 85,
1558 },
1559};
1560
1561static const struct display_timing chefree_ch101olhlwh_002_timing = {
1562 .pixelclock = { 68900000, 71100000, 73400000 },
1563 .hactive = { 1280, 1280, 1280 },
1564 .hfront_porch = { 65, 80, 95 },
1565 .hback_porch = { 64, 79, 94 },
1566 .hsync_len = { 1, 1, 1 },
1567 .vactive = { 800, 800, 800 },
1568 .vfront_porch = { 7, 11, 14 },
1569 .vback_porch = { 7, 11, 14 },
1570 .vsync_len = { 1, 1, 1 },
1571 .flags = DISPLAY_FLAGS_DE_HIGH,
1572};
1573
1574static const struct panel_desc chefree_ch101olhlwh_002 = {
1575 .timings = &chefree_ch101olhlwh_002_timing,
1576 .num_timings = 1,
1577 .bpc = 8,
1578 .size = {
1579 .width = 217,
1580 .height = 135,
1581 },
1582 .delay = {
1583 .enable = 200,
1584 .disable = 200,
1585 },
1586 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1587 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1588 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1589};
1590
1591static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1592 .clock = 66770,
1593 .hdisplay = 800,
1594 .hsync_start = 800 + 49,
1595 .hsync_end = 800 + 49 + 33,
1596 .htotal = 800 + 49 + 33 + 17,
1597 .vdisplay = 1280,
1598 .vsync_start = 1280 + 1,
1599 .vsync_end = 1280 + 1 + 7,
1600 .vtotal = 1280 + 1 + 7 + 15,
1601 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1602};
1603
1604static const struct panel_desc chunghwa_claa070wp03xg = {
1605 .modes = &chunghwa_claa070wp03xg_mode,
1606 .num_modes = 1,
1607 .bpc = 6,
1608 .size = {
1609 .width = 94,
1610 .height = 150,
1611 },
1612 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1613 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1614 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1615};
1616
1617static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1618 .clock = 72070,
1619 .hdisplay = 1366,
1620 .hsync_start = 1366 + 58,
1621 .hsync_end = 1366 + 58 + 58,
1622 .htotal = 1366 + 58 + 58 + 58,
1623 .vdisplay = 768,
1624 .vsync_start = 768 + 4,
1625 .vsync_end = 768 + 4 + 4,
1626 .vtotal = 768 + 4 + 4 + 4,
1627};
1628
1629static const struct panel_desc chunghwa_claa101wa01a = {
1630 .modes = &chunghwa_claa101wa01a_mode,
1631 .num_modes = 1,
1632 .bpc = 6,
1633 .size = {
1634 .width = 220,
1635 .height = 120,
1636 },
1637 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1638 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1639 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1640};
1641
1642static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1643 .clock = 69300,
1644 .hdisplay = 1366,
1645 .hsync_start = 1366 + 48,
1646 .hsync_end = 1366 + 48 + 32,
1647 .htotal = 1366 + 48 + 32 + 20,
1648 .vdisplay = 768,
1649 .vsync_start = 768 + 16,
1650 .vsync_end = 768 + 16 + 8,
1651 .vtotal = 768 + 16 + 8 + 16,
1652};
1653
1654static const struct panel_desc chunghwa_claa101wb01 = {
1655 .modes = &chunghwa_claa101wb01_mode,
1656 .num_modes = 1,
1657 .bpc = 6,
1658 .size = {
1659 .width = 223,
1660 .height = 125,
1661 },
1662 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1663 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1664 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1665};
1666
1667static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1668 .pixelclock = { 5000000, 9000000, 12000000 },
1669 .hactive = { 480, 480, 480 },
1670 .hfront_porch = { 12, 12, 12 },
1671 .hback_porch = { 12, 12, 12 },
1672 .hsync_len = { 21, 21, 21 },
1673 .vactive = { 272, 272, 272 },
1674 .vfront_porch = { 4, 4, 4 },
1675 .vback_porch = { 4, 4, 4 },
1676 .vsync_len = { 8, 8, 8 },
1677};
1678
1679static const struct panel_desc dataimage_fg040346dsswbg04 = {
1680 .timings = &dataimage_fg040346dsswbg04_timing,
1681 .num_timings = 1,
1682 .bpc = 8,
1683 .size = {
1684 .width = 95,
1685 .height = 54,
1686 },
1687 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1688 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1689 .connector_type = DRM_MODE_CONNECTOR_DPI,
1690};
1691
1692static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1693 .pixelclock = { 68900000, 71110000, 73400000 },
1694 .hactive = { 1280, 1280, 1280 },
1695 .vactive = { 800, 800, 800 },
1696 .hback_porch = { 100, 100, 100 },
1697 .hfront_porch = { 100, 100, 100 },
1698 .vback_porch = { 5, 5, 5 },
1699 .vfront_porch = { 5, 5, 5 },
1700 .hsync_len = { 24, 24, 24 },
1701 .vsync_len = { 3, 3, 3 },
1702 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1703 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1704};
1705
1706static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1707 .timings = &dataimage_fg1001l0dsswmg01_timing,
1708 .num_timings = 1,
1709 .bpc = 8,
1710 .size = {
1711 .width = 217,
1712 .height = 136,
1713 },
1714};
1715
1716static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1717 .clock = 33260,
1718 .hdisplay = 800,
1719 .hsync_start = 800 + 40,
1720 .hsync_end = 800 + 40 + 128,
1721 .htotal = 800 + 40 + 128 + 88,
1722 .vdisplay = 480,
1723 .vsync_start = 480 + 10,
1724 .vsync_end = 480 + 10 + 2,
1725 .vtotal = 480 + 10 + 2 + 33,
1726 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1727};
1728
1729static const struct panel_desc dataimage_scf0700c48ggu18 = {
1730 .modes = &dataimage_scf0700c48ggu18_mode,
1731 .num_modes = 1,
1732 .bpc = 8,
1733 .size = {
1734 .width = 152,
1735 .height = 91,
1736 },
1737 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1738 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1739};
1740
1741static const struct display_timing dlc_dlc0700yzg_1_timing = {
1742 .pixelclock = { 45000000, 51200000, 57000000 },
1743 .hactive = { 1024, 1024, 1024 },
1744 .hfront_porch = { 100, 106, 113 },
1745 .hback_porch = { 100, 106, 113 },
1746 .hsync_len = { 100, 108, 114 },
1747 .vactive = { 600, 600, 600 },
1748 .vfront_porch = { 8, 11, 15 },
1749 .vback_porch = { 8, 11, 15 },
1750 .vsync_len = { 9, 13, 15 },
1751 .flags = DISPLAY_FLAGS_DE_HIGH,
1752};
1753
1754static const struct panel_desc dlc_dlc0700yzg_1 = {
1755 .timings = &dlc_dlc0700yzg_1_timing,
1756 .num_timings = 1,
1757 .bpc = 6,
1758 .size = {
1759 .width = 154,
1760 .height = 86,
1761 },
1762 .delay = {
1763 .prepare = 30,
1764 .enable = 200,
1765 .disable = 200,
1766 },
1767 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1768 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1769};
1770
1771static const struct display_timing dlc_dlc1010gig_timing = {
1772 .pixelclock = { 68900000, 71100000, 73400000 },
1773 .hactive = { 1280, 1280, 1280 },
1774 .hfront_porch = { 43, 53, 63 },
1775 .hback_porch = { 43, 53, 63 },
1776 .hsync_len = { 44, 54, 64 },
1777 .vactive = { 800, 800, 800 },
1778 .vfront_porch = { 5, 8, 11 },
1779 .vback_porch = { 5, 8, 11 },
1780 .vsync_len = { 5, 7, 11 },
1781 .flags = DISPLAY_FLAGS_DE_HIGH,
1782};
1783
1784static const struct panel_desc dlc_dlc1010gig = {
1785 .timings = &dlc_dlc1010gig_timing,
1786 .num_timings = 1,
1787 .bpc = 8,
1788 .size = {
1789 .width = 216,
1790 .height = 135,
1791 },
1792 .delay = {
1793 .prepare = 60,
1794 .enable = 150,
1795 .disable = 100,
1796 .unprepare = 60,
1797 },
1798 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1799 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1800};
1801
1802static const struct drm_display_mode edt_et035012dm6_mode = {
1803 .clock = 6500,
1804 .hdisplay = 320,
1805 .hsync_start = 320 + 20,
1806 .hsync_end = 320 + 20 + 30,
1807 .htotal = 320 + 20 + 68,
1808 .vdisplay = 240,
1809 .vsync_start = 240 + 4,
1810 .vsync_end = 240 + 4 + 4,
1811 .vtotal = 240 + 4 + 4 + 14,
1812 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1813};
1814
1815static const struct panel_desc edt_et035012dm6 = {
1816 .modes = &edt_et035012dm6_mode,
1817 .num_modes = 1,
1818 .bpc = 8,
1819 .size = {
1820 .width = 70,
1821 .height = 52,
1822 },
1823 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1824 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1825};
1826
1827static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1828 .clock = 6520,
1829 .hdisplay = 320,
1830 .hsync_start = 320 + 20,
1831 .hsync_end = 320 + 20 + 68,
1832 .htotal = 320 + 20 + 68,
1833 .vdisplay = 240,
1834 .vsync_start = 240 + 4,
1835 .vsync_end = 240 + 4 + 18,
1836 .vtotal = 240 + 4 + 18,
1837 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1838};
1839
1840static const struct panel_desc edt_etm0350g0dh6 = {
1841 .modes = &edt_etm0350g0dh6_mode,
1842 .num_modes = 1,
1843 .bpc = 6,
1844 .size = {
1845 .width = 70,
1846 .height = 53,
1847 },
1848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1849 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1850 .connector_type = DRM_MODE_CONNECTOR_DPI,
1851};
1852
1853static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1854 .clock = 10870,
1855 .hdisplay = 480,
1856 .hsync_start = 480 + 8,
1857 .hsync_end = 480 + 8 + 4,
1858 .htotal = 480 + 8 + 4 + 41,
1859
1860 /*
1861 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1862 * fb_align
1863 */
1864
1865 .vdisplay = 288,
1866 .vsync_start = 288 + 2,
1867 .vsync_end = 288 + 2 + 4,
1868 .vtotal = 288 + 2 + 4 + 10,
1869};
1870
1871static const struct panel_desc edt_etm043080dh6gp = {
1872 .modes = &edt_etm043080dh6gp_mode,
1873 .num_modes = 1,
1874 .bpc = 8,
1875 .size = {
1876 .width = 100,
1877 .height = 65,
1878 },
1879 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1880 .connector_type = DRM_MODE_CONNECTOR_DPI,
1881};
1882
1883static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1884 .clock = 9000,
1885 .hdisplay = 480,
1886 .hsync_start = 480 + 2,
1887 .hsync_end = 480 + 2 + 41,
1888 .htotal = 480 + 2 + 41 + 2,
1889 .vdisplay = 272,
1890 .vsync_start = 272 + 2,
1891 .vsync_end = 272 + 2 + 10,
1892 .vtotal = 272 + 2 + 10 + 2,
1893 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1894};
1895
1896static const struct panel_desc edt_etm0430g0dh6 = {
1897 .modes = &edt_etm0430g0dh6_mode,
1898 .num_modes = 1,
1899 .bpc = 6,
1900 .size = {
1901 .width = 95,
1902 .height = 54,
1903 },
1904 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1905 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1906 .connector_type = DRM_MODE_CONNECTOR_DPI,
1907};
1908
1909static const struct drm_display_mode edt_et057090dhu_mode = {
1910 .clock = 25175,
1911 .hdisplay = 640,
1912 .hsync_start = 640 + 16,
1913 .hsync_end = 640 + 16 + 30,
1914 .htotal = 640 + 16 + 30 + 114,
1915 .vdisplay = 480,
1916 .vsync_start = 480 + 10,
1917 .vsync_end = 480 + 10 + 3,
1918 .vtotal = 480 + 10 + 3 + 32,
1919 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1920};
1921
1922static const struct panel_desc edt_et057090dhu = {
1923 .modes = &edt_et057090dhu_mode,
1924 .num_modes = 1,
1925 .bpc = 6,
1926 .size = {
1927 .width = 115,
1928 .height = 86,
1929 },
1930 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1931 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1932 .connector_type = DRM_MODE_CONNECTOR_DPI,
1933};
1934
1935static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1936 .clock = 33260,
1937 .hdisplay = 800,
1938 .hsync_start = 800 + 40,
1939 .hsync_end = 800 + 40 + 128,
1940 .htotal = 800 + 40 + 128 + 88,
1941 .vdisplay = 480,
1942 .vsync_start = 480 + 10,
1943 .vsync_end = 480 + 10 + 2,
1944 .vtotal = 480 + 10 + 2 + 33,
1945 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1946};
1947
1948static const struct panel_desc edt_etm0700g0dh6 = {
1949 .modes = &edt_etm0700g0dh6_mode,
1950 .num_modes = 1,
1951 .bpc = 6,
1952 .size = {
1953 .width = 152,
1954 .height = 91,
1955 },
1956 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1957 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1958 .connector_type = DRM_MODE_CONNECTOR_DPI,
1959};
1960
1961static const struct panel_desc edt_etm0700g0bdh6 = {
1962 .modes = &edt_etm0700g0dh6_mode,
1963 .num_modes = 1,
1964 .bpc = 6,
1965 .size = {
1966 .width = 152,
1967 .height = 91,
1968 },
1969 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1970 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1971 .connector_type = DRM_MODE_CONNECTOR_DPI,
1972};
1973
1974static const struct display_timing edt_etml0700y5dha_timing = {
1975 .pixelclock = { 40800000, 51200000, 67200000 },
1976 .hactive = { 1024, 1024, 1024 },
1977 .hfront_porch = { 30, 106, 125 },
1978 .hback_porch = { 30, 106, 125 },
1979 .hsync_len = { 30, 108, 126 },
1980 .vactive = { 600, 600, 600 },
1981 .vfront_porch = { 3, 12, 67},
1982 .vback_porch = { 3, 12, 67 },
1983 .vsync_len = { 4, 11, 66 },
1984 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1985 DISPLAY_FLAGS_DE_HIGH,
1986};
1987
1988static const struct panel_desc edt_etml0700y5dha = {
1989 .timings = &edt_etml0700y5dha_timing,
1990 .num_timings = 1,
1991 .bpc = 8,
1992 .size = {
1993 .width = 155,
1994 .height = 86,
1995 },
1996 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1997 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1998};
1999
2000static const struct display_timing edt_etml1010g3dra_timing = {
2001 .pixelclock = { 66300000, 72400000, 78900000 },
2002 .hactive = { 1280, 1280, 1280 },
2003 .hfront_porch = { 12, 72, 132 },
2004 .hback_porch = { 86, 86, 86 },
2005 .hsync_len = { 2, 2, 2 },
2006 .vactive = { 800, 800, 800 },
2007 .vfront_porch = { 1, 15, 49 },
2008 .vback_porch = { 21, 21, 21 },
2009 .vsync_len = { 2, 2, 2 },
2010 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
2011 DISPLAY_FLAGS_DE_HIGH,
2012};
2013
2014static const struct panel_desc edt_etml1010g3dra = {
2015 .timings = &edt_etml1010g3dra_timing,
2016 .num_timings = 1,
2017 .bpc = 8,
2018 .size = {
2019 .width = 216,
2020 .height = 135,
2021 },
2022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2023 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2024 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2025};
2026
2027static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2028 .clock = 25175,
2029 .hdisplay = 640,
2030 .hsync_start = 640,
2031 .hsync_end = 640 + 16,
2032 .htotal = 640 + 16 + 30 + 114,
2033 .vdisplay = 480,
2034 .vsync_start = 480 + 10,
2035 .vsync_end = 480 + 10 + 3,
2036 .vtotal = 480 + 10 + 3 + 35,
2037 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2038};
2039
2040static const struct panel_desc edt_etmv570g2dhu = {
2041 .modes = &edt_etmv570g2dhu_mode,
2042 .num_modes = 1,
2043 .bpc = 6,
2044 .size = {
2045 .width = 115,
2046 .height = 86,
2047 },
2048 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2049 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2050 .connector_type = DRM_MODE_CONNECTOR_DPI,
2051};
2052
2053static const struct display_timing eink_vb3300_kca_timing = {
2054 .pixelclock = { 40000000, 40000000, 40000000 },
2055 .hactive = { 334, 334, 334 },
2056 .hfront_porch = { 1, 1, 1 },
2057 .hback_porch = { 1, 1, 1 },
2058 .hsync_len = { 1, 1, 1 },
2059 .vactive = { 1405, 1405, 1405 },
2060 .vfront_porch = { 1, 1, 1 },
2061 .vback_porch = { 1, 1, 1 },
2062 .vsync_len = { 1, 1, 1 },
2063 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2064 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2065};
2066
2067static const struct panel_desc eink_vb3300_kca = {
2068 .timings = &eink_vb3300_kca_timing,
2069 .num_timings = 1,
2070 .bpc = 6,
2071 .size = {
2072 .width = 157,
2073 .height = 209,
2074 },
2075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2076 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2077 .connector_type = DRM_MODE_CONNECTOR_DPI,
2078};
2079
2080static const struct display_timing evervision_vgg644804_timing = {
2081 .pixelclock = { 25175000, 25175000, 25175000 },
2082 .hactive = { 640, 640, 640 },
2083 .hfront_porch = { 16, 16, 16 },
2084 .hback_porch = { 82, 114, 170 },
2085 .hsync_len = { 5, 30, 30 },
2086 .vactive = { 480, 480, 480 },
2087 .vfront_porch = { 10, 10, 10 },
2088 .vback_porch = { 30, 32, 34 },
2089 .vsync_len = { 1, 3, 5 },
2090 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2091 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2092 DISPLAY_FLAGS_SYNC_POSEDGE,
2093};
2094
2095static const struct panel_desc evervision_vgg644804 = {
2096 .timings = &evervision_vgg644804_timing,
2097 .num_timings = 1,
2098 .bpc = 8,
2099 .size = {
2100 .width = 115,
2101 .height = 86,
2102 },
2103 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2104 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2105};
2106
2107static const struct display_timing evervision_vgg804821_timing = {
2108 .pixelclock = { 27600000, 33300000, 50000000 },
2109 .hactive = { 800, 800, 800 },
2110 .hfront_porch = { 40, 66, 70 },
2111 .hback_porch = { 40, 67, 70 },
2112 .hsync_len = { 40, 67, 70 },
2113 .vactive = { 480, 480, 480 },
2114 .vfront_porch = { 6, 10, 10 },
2115 .vback_porch = { 7, 11, 11 },
2116 .vsync_len = { 7, 11, 11 },
2117 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2118 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2119 DISPLAY_FLAGS_SYNC_NEGEDGE,
2120};
2121
2122static const struct panel_desc evervision_vgg804821 = {
2123 .timings = &evervision_vgg804821_timing,
2124 .num_timings = 1,
2125 .bpc = 8,
2126 .size = {
2127 .width = 108,
2128 .height = 64,
2129 },
2130 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2131 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2132};
2133
2134static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2135 .clock = 32260,
2136 .hdisplay = 800,
2137 .hsync_start = 800 + 168,
2138 .hsync_end = 800 + 168 + 64,
2139 .htotal = 800 + 168 + 64 + 88,
2140 .vdisplay = 480,
2141 .vsync_start = 480 + 37,
2142 .vsync_end = 480 + 37 + 2,
2143 .vtotal = 480 + 37 + 2 + 8,
2144};
2145
2146static const struct panel_desc foxlink_fl500wvr00_a0t = {
2147 .modes = &foxlink_fl500wvr00_a0t_mode,
2148 .num_modes = 1,
2149 .bpc = 8,
2150 .size = {
2151 .width = 108,
2152 .height = 65,
2153 },
2154 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2155};
2156
2157static const struct drm_display_mode frida_frd350h54004_modes[] = {
2158 { /* 60 Hz */
2159 .clock = 6000,
2160 .hdisplay = 320,
2161 .hsync_start = 320 + 44,
2162 .hsync_end = 320 + 44 + 16,
2163 .htotal = 320 + 44 + 16 + 20,
2164 .vdisplay = 240,
2165 .vsync_start = 240 + 2,
2166 .vsync_end = 240 + 2 + 6,
2167 .vtotal = 240 + 2 + 6 + 2,
2168 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2169 },
2170 { /* 50 Hz */
2171 .clock = 5400,
2172 .hdisplay = 320,
2173 .hsync_start = 320 + 56,
2174 .hsync_end = 320 + 56 + 16,
2175 .htotal = 320 + 56 + 16 + 40,
2176 .vdisplay = 240,
2177 .vsync_start = 240 + 2,
2178 .vsync_end = 240 + 2 + 6,
2179 .vtotal = 240 + 2 + 6 + 2,
2180 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2181 },
2182};
2183
2184static const struct panel_desc frida_frd350h54004 = {
2185 .modes = frida_frd350h54004_modes,
2186 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2187 .bpc = 8,
2188 .size = {
2189 .width = 77,
2190 .height = 64,
2191 },
2192 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2193 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2194 .connector_type = DRM_MODE_CONNECTOR_DPI,
2195};
2196
2197static const struct drm_display_mode friendlyarm_hd702e_mode = {
2198 .clock = 67185,
2199 .hdisplay = 800,
2200 .hsync_start = 800 + 20,
2201 .hsync_end = 800 + 20 + 24,
2202 .htotal = 800 + 20 + 24 + 20,
2203 .vdisplay = 1280,
2204 .vsync_start = 1280 + 4,
2205 .vsync_end = 1280 + 4 + 8,
2206 .vtotal = 1280 + 4 + 8 + 4,
2207 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2208};
2209
2210static const struct panel_desc friendlyarm_hd702e = {
2211 .modes = &friendlyarm_hd702e_mode,
2212 .num_modes = 1,
2213 .size = {
2214 .width = 94,
2215 .height = 151,
2216 },
2217};
2218
2219static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2220 .clock = 9000,
2221 .hdisplay = 480,
2222 .hsync_start = 480 + 5,
2223 .hsync_end = 480 + 5 + 1,
2224 .htotal = 480 + 5 + 1 + 40,
2225 .vdisplay = 272,
2226 .vsync_start = 272 + 8,
2227 .vsync_end = 272 + 8 + 1,
2228 .vtotal = 272 + 8 + 1 + 8,
2229};
2230
2231static const struct panel_desc giantplus_gpg482739qs5 = {
2232 .modes = &giantplus_gpg482739qs5_mode,
2233 .num_modes = 1,
2234 .bpc = 8,
2235 .size = {
2236 .width = 95,
2237 .height = 54,
2238 },
2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2240};
2241
2242static const struct display_timing giantplus_gpm940b0_timing = {
2243 .pixelclock = { 13500000, 27000000, 27500000 },
2244 .hactive = { 320, 320, 320 },
2245 .hfront_porch = { 14, 686, 718 },
2246 .hback_porch = { 50, 70, 255 },
2247 .hsync_len = { 1, 1, 1 },
2248 .vactive = { 240, 240, 240 },
2249 .vfront_porch = { 1, 1, 179 },
2250 .vback_porch = { 1, 21, 31 },
2251 .vsync_len = { 1, 1, 6 },
2252 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2253};
2254
2255static const struct panel_desc giantplus_gpm940b0 = {
2256 .timings = &giantplus_gpm940b0_timing,
2257 .num_timings = 1,
2258 .bpc = 8,
2259 .size = {
2260 .width = 60,
2261 .height = 45,
2262 },
2263 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2264 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2265};
2266
2267static const struct display_timing hannstar_hsd070pww1_timing = {
2268 .pixelclock = { 64300000, 71100000, 82000000 },
2269 .hactive = { 1280, 1280, 1280 },
2270 .hfront_porch = { 1, 1, 10 },
2271 .hback_porch = { 1, 1, 10 },
2272 /*
2273 * According to the data sheet, the minimum horizontal blanking interval
2274 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2275 * minimum working horizontal blanking interval to be 60 clocks.
2276 */
2277 .hsync_len = { 58, 158, 661 },
2278 .vactive = { 800, 800, 800 },
2279 .vfront_porch = { 1, 1, 10 },
2280 .vback_porch = { 1, 1, 10 },
2281 .vsync_len = { 1, 21, 203 },
2282 .flags = DISPLAY_FLAGS_DE_HIGH,
2283};
2284
2285static const struct panel_desc hannstar_hsd070pww1 = {
2286 .timings = &hannstar_hsd070pww1_timing,
2287 .num_timings = 1,
2288 .bpc = 6,
2289 .size = {
2290 .width = 151,
2291 .height = 94,
2292 },
2293 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2294 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2295};
2296
2297static const struct display_timing hannstar_hsd100pxn1_timing = {
2298 .pixelclock = { 55000000, 65000000, 75000000 },
2299 .hactive = { 1024, 1024, 1024 },
2300 .hfront_porch = { 40, 40, 40 },
2301 .hback_porch = { 220, 220, 220 },
2302 .hsync_len = { 20, 60, 100 },
2303 .vactive = { 768, 768, 768 },
2304 .vfront_porch = { 7, 7, 7 },
2305 .vback_porch = { 21, 21, 21 },
2306 .vsync_len = { 10, 10, 10 },
2307 .flags = DISPLAY_FLAGS_DE_HIGH,
2308};
2309
2310static const struct panel_desc hannstar_hsd100pxn1 = {
2311 .timings = &hannstar_hsd100pxn1_timing,
2312 .num_timings = 1,
2313 .bpc = 6,
2314 .size = {
2315 .width = 203,
2316 .height = 152,
2317 },
2318 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2319 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2320};
2321
2322static const struct display_timing hannstar_hsd101pww2_timing = {
2323 .pixelclock = { 64300000, 71100000, 82000000 },
2324 .hactive = { 1280, 1280, 1280 },
2325 .hfront_porch = { 1, 1, 10 },
2326 .hback_porch = { 1, 1, 10 },
2327 .hsync_len = { 58, 158, 661 },
2328 .vactive = { 800, 800, 800 },
2329 .vfront_porch = { 1, 1, 10 },
2330 .vback_porch = { 1, 1, 10 },
2331 .vsync_len = { 1, 21, 203 },
2332 .flags = DISPLAY_FLAGS_DE_HIGH,
2333};
2334
2335static const struct panel_desc hannstar_hsd101pww2 = {
2336 .timings = &hannstar_hsd101pww2_timing,
2337 .num_timings = 1,
2338 .bpc = 8,
2339 .size = {
2340 .width = 217,
2341 .height = 136,
2342 },
2343 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2344 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2345};
2346
2347static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2348 .clock = 33333,
2349 .hdisplay = 800,
2350 .hsync_start = 800 + 85,
2351 .hsync_end = 800 + 85 + 86,
2352 .htotal = 800 + 85 + 86 + 85,
2353 .vdisplay = 480,
2354 .vsync_start = 480 + 16,
2355 .vsync_end = 480 + 16 + 13,
2356 .vtotal = 480 + 16 + 13 + 16,
2357};
2358
2359static const struct panel_desc hitachi_tx23d38vm0caa = {
2360 .modes = &hitachi_tx23d38vm0caa_mode,
2361 .num_modes = 1,
2362 .bpc = 6,
2363 .size = {
2364 .width = 195,
2365 .height = 117,
2366 },
2367 .delay = {
2368 .enable = 160,
2369 .disable = 160,
2370 },
2371};
2372
2373static const struct drm_display_mode innolux_at043tn24_mode = {
2374 .clock = 9000,
2375 .hdisplay = 480,
2376 .hsync_start = 480 + 2,
2377 .hsync_end = 480 + 2 + 41,
2378 .htotal = 480 + 2 + 41 + 2,
2379 .vdisplay = 272,
2380 .vsync_start = 272 + 2,
2381 .vsync_end = 272 + 2 + 10,
2382 .vtotal = 272 + 2 + 10 + 2,
2383 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2384};
2385
2386static const struct panel_desc innolux_at043tn24 = {
2387 .modes = &innolux_at043tn24_mode,
2388 .num_modes = 1,
2389 .bpc = 8,
2390 .size = {
2391 .width = 95,
2392 .height = 54,
2393 },
2394 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2395 .connector_type = DRM_MODE_CONNECTOR_DPI,
2396 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2397};
2398
2399static const struct drm_display_mode innolux_at070tn92_mode = {
2400 .clock = 33333,
2401 .hdisplay = 800,
2402 .hsync_start = 800 + 210,
2403 .hsync_end = 800 + 210 + 20,
2404 .htotal = 800 + 210 + 20 + 46,
2405 .vdisplay = 480,
2406 .vsync_start = 480 + 22,
2407 .vsync_end = 480 + 22 + 10,
2408 .vtotal = 480 + 22 + 23 + 10,
2409};
2410
2411static const struct panel_desc innolux_at070tn92 = {
2412 .modes = &innolux_at070tn92_mode,
2413 .num_modes = 1,
2414 .size = {
2415 .width = 154,
2416 .height = 86,
2417 },
2418 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2419};
2420
2421static const struct display_timing innolux_g070ace_l01_timing = {
2422 .pixelclock = { 25200000, 35000000, 35700000 },
2423 .hactive = { 800, 800, 800 },
2424 .hfront_porch = { 30, 32, 87 },
2425 .hback_porch = { 30, 32, 87 },
2426 .hsync_len = { 1, 1, 1 },
2427 .vactive = { 480, 480, 480 },
2428 .vfront_porch = { 3, 3, 3 },
2429 .vback_porch = { 13, 13, 13 },
2430 .vsync_len = { 1, 1, 4 },
2431 .flags = DISPLAY_FLAGS_DE_HIGH,
2432};
2433
2434static const struct panel_desc innolux_g070ace_l01 = {
2435 .timings = &innolux_g070ace_l01_timing,
2436 .num_timings = 1,
2437 .bpc = 8,
2438 .size = {
2439 .width = 152,
2440 .height = 91,
2441 },
2442 .delay = {
2443 .prepare = 10,
2444 .enable = 50,
2445 .disable = 50,
2446 .unprepare = 500,
2447 },
2448 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2449 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2450 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2451};
2452
2453static const struct display_timing innolux_g070y2_l01_timing = {
2454 .pixelclock = { 28000000, 29500000, 32000000 },
2455 .hactive = { 800, 800, 800 },
2456 .hfront_porch = { 61, 91, 141 },
2457 .hback_porch = { 60, 90, 140 },
2458 .hsync_len = { 12, 12, 12 },
2459 .vactive = { 480, 480, 480 },
2460 .vfront_porch = { 4, 9, 30 },
2461 .vback_porch = { 4, 8, 28 },
2462 .vsync_len = { 2, 2, 2 },
2463 .flags = DISPLAY_FLAGS_DE_HIGH,
2464};
2465
2466static const struct panel_desc innolux_g070y2_l01 = {
2467 .timings = &innolux_g070y2_l01_timing,
2468 .num_timings = 1,
2469 .bpc = 8,
2470 .size = {
2471 .width = 152,
2472 .height = 91,
2473 },
2474 .delay = {
2475 .prepare = 10,
2476 .enable = 100,
2477 .disable = 100,
2478 .unprepare = 800,
2479 },
2480 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2481 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2482 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2483};
2484
2485static const struct drm_display_mode innolux_g070y2_t02_mode = {
2486 .clock = 33333,
2487 .hdisplay = 800,
2488 .hsync_start = 800 + 210,
2489 .hsync_end = 800 + 210 + 20,
2490 .htotal = 800 + 210 + 20 + 46,
2491 .vdisplay = 480,
2492 .vsync_start = 480 + 22,
2493 .vsync_end = 480 + 22 + 10,
2494 .vtotal = 480 + 22 + 23 + 10,
2495};
2496
2497static const struct panel_desc innolux_g070y2_t02 = {
2498 .modes = &innolux_g070y2_t02_mode,
2499 .num_modes = 1,
2500 .bpc = 8,
2501 .size = {
2502 .width = 152,
2503 .height = 92,
2504 },
2505 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2506 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2507 .connector_type = DRM_MODE_CONNECTOR_DPI,
2508};
2509
2510static const struct display_timing innolux_g101ice_l01_timing = {
2511 .pixelclock = { 60400000, 71100000, 74700000 },
2512 .hactive = { 1280, 1280, 1280 },
2513 .hfront_porch = { 30, 60, 70 },
2514 .hback_porch = { 30, 60, 70 },
2515 .hsync_len = { 22, 40, 60 },
2516 .vactive = { 800, 800, 800 },
2517 .vfront_porch = { 3, 8, 14 },
2518 .vback_porch = { 3, 8, 14 },
2519 .vsync_len = { 4, 7, 12 },
2520 .flags = DISPLAY_FLAGS_DE_HIGH,
2521};
2522
2523static const struct panel_desc innolux_g101ice_l01 = {
2524 .timings = &innolux_g101ice_l01_timing,
2525 .num_timings = 1,
2526 .bpc = 8,
2527 .size = {
2528 .width = 217,
2529 .height = 135,
2530 },
2531 .delay = {
2532 .enable = 200,
2533 .disable = 200,
2534 },
2535 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2536 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2537 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2538};
2539
2540static const struct display_timing innolux_g121i1_l01_timing = {
2541 .pixelclock = { 67450000, 71000000, 74550000 },
2542 .hactive = { 1280, 1280, 1280 },
2543 .hfront_porch = { 40, 80, 160 },
2544 .hback_porch = { 39, 79, 159 },
2545 .hsync_len = { 1, 1, 1 },
2546 .vactive = { 800, 800, 800 },
2547 .vfront_porch = { 5, 11, 100 },
2548 .vback_porch = { 4, 11, 99 },
2549 .vsync_len = { 1, 1, 1 },
2550};
2551
2552static const struct panel_desc innolux_g121i1_l01 = {
2553 .timings = &innolux_g121i1_l01_timing,
2554 .num_timings = 1,
2555 .bpc = 6,
2556 .size = {
2557 .width = 261,
2558 .height = 163,
2559 },
2560 .delay = {
2561 .enable = 200,
2562 .disable = 20,
2563 },
2564 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2565 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2566};
2567
2568static const struct drm_display_mode innolux_g121x1_l03_mode = {
2569 .clock = 65000,
2570 .hdisplay = 1024,
2571 .hsync_start = 1024 + 0,
2572 .hsync_end = 1024 + 1,
2573 .htotal = 1024 + 0 + 1 + 320,
2574 .vdisplay = 768,
2575 .vsync_start = 768 + 38,
2576 .vsync_end = 768 + 38 + 1,
2577 .vtotal = 768 + 38 + 1 + 0,
2578 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2579};
2580
2581static const struct panel_desc innolux_g121x1_l03 = {
2582 .modes = &innolux_g121x1_l03_mode,
2583 .num_modes = 1,
2584 .bpc = 6,
2585 .size = {
2586 .width = 246,
2587 .height = 185,
2588 },
2589 .delay = {
2590 .enable = 200,
2591 .unprepare = 200,
2592 .disable = 400,
2593 },
2594 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2595 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2596 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2597};
2598
2599static const struct display_timing innolux_g156hce_l01_timings = {
2600 .pixelclock = { 120000000, 141860000, 150000000 },
2601 .hactive = { 1920, 1920, 1920 },
2602 .hfront_porch = { 80, 90, 100 },
2603 .hback_porch = { 80, 90, 100 },
2604 .hsync_len = { 20, 30, 30 },
2605 .vactive = { 1080, 1080, 1080 },
2606 .vfront_porch = { 3, 10, 20 },
2607 .vback_porch = { 3, 10, 20 },
2608 .vsync_len = { 4, 10, 10 },
2609};
2610
2611static const struct panel_desc innolux_g156hce_l01 = {
2612 .timings = &innolux_g156hce_l01_timings,
2613 .num_timings = 1,
2614 .bpc = 8,
2615 .size = {
2616 .width = 344,
2617 .height = 194,
2618 },
2619 .delay = {
2620 .prepare = 1, /* T1+T2 */
2621 .enable = 450, /* T5 */
2622 .disable = 200, /* T6 */
2623 .unprepare = 10, /* T3+T7 */
2624 },
2625 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2626 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2627 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2628};
2629
2630static const struct drm_display_mode innolux_n156bge_l21_mode = {
2631 .clock = 69300,
2632 .hdisplay = 1366,
2633 .hsync_start = 1366 + 16,
2634 .hsync_end = 1366 + 16 + 34,
2635 .htotal = 1366 + 16 + 34 + 50,
2636 .vdisplay = 768,
2637 .vsync_start = 768 + 2,
2638 .vsync_end = 768 + 2 + 6,
2639 .vtotal = 768 + 2 + 6 + 12,
2640};
2641
2642static const struct panel_desc innolux_n156bge_l21 = {
2643 .modes = &innolux_n156bge_l21_mode,
2644 .num_modes = 1,
2645 .bpc = 6,
2646 .size = {
2647 .width = 344,
2648 .height = 193,
2649 },
2650 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2651 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2652 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2653};
2654
2655static const struct drm_display_mode innolux_zj070na_01p_mode = {
2656 .clock = 51501,
2657 .hdisplay = 1024,
2658 .hsync_start = 1024 + 128,
2659 .hsync_end = 1024 + 128 + 64,
2660 .htotal = 1024 + 128 + 64 + 128,
2661 .vdisplay = 600,
2662 .vsync_start = 600 + 16,
2663 .vsync_end = 600 + 16 + 4,
2664 .vtotal = 600 + 16 + 4 + 16,
2665};
2666
2667static const struct panel_desc innolux_zj070na_01p = {
2668 .modes = &innolux_zj070na_01p_mode,
2669 .num_modes = 1,
2670 .bpc = 6,
2671 .size = {
2672 .width = 154,
2673 .height = 90,
2674 },
2675};
2676
2677static const struct display_timing koe_tx14d24vm1bpa_timing = {
2678 .pixelclock = { 5580000, 5850000, 6200000 },
2679 .hactive = { 320, 320, 320 },
2680 .hfront_porch = { 30, 30, 30 },
2681 .hback_porch = { 30, 30, 30 },
2682 .hsync_len = { 1, 5, 17 },
2683 .vactive = { 240, 240, 240 },
2684 .vfront_porch = { 6, 6, 6 },
2685 .vback_porch = { 5, 5, 5 },
2686 .vsync_len = { 1, 2, 11 },
2687 .flags = DISPLAY_FLAGS_DE_HIGH,
2688};
2689
2690static const struct panel_desc koe_tx14d24vm1bpa = {
2691 .timings = &koe_tx14d24vm1bpa_timing,
2692 .num_timings = 1,
2693 .bpc = 6,
2694 .size = {
2695 .width = 115,
2696 .height = 86,
2697 },
2698};
2699
2700static const struct display_timing koe_tx26d202vm0bwa_timing = {
2701 .pixelclock = { 151820000, 156720000, 159780000 },
2702 .hactive = { 1920, 1920, 1920 },
2703 .hfront_porch = { 105, 130, 142 },
2704 .hback_porch = { 45, 70, 82 },
2705 .hsync_len = { 30, 30, 30 },
2706 .vactive = { 1200, 1200, 1200},
2707 .vfront_porch = { 3, 5, 10 },
2708 .vback_porch = { 2, 5, 10 },
2709 .vsync_len = { 5, 5, 5 },
2710};
2711
2712static const struct panel_desc koe_tx26d202vm0bwa = {
2713 .timings = &koe_tx26d202vm0bwa_timing,
2714 .num_timings = 1,
2715 .bpc = 8,
2716 .size = {
2717 .width = 217,
2718 .height = 136,
2719 },
2720 .delay = {
2721 .prepare = 1000,
2722 .enable = 1000,
2723 .unprepare = 1000,
2724 .disable = 1000,
2725 },
2726 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2727 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2728 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2729};
2730
2731static const struct display_timing koe_tx31d200vm0baa_timing = {
2732 .pixelclock = { 39600000, 43200000, 48000000 },
2733 .hactive = { 1280, 1280, 1280 },
2734 .hfront_porch = { 16, 36, 56 },
2735 .hback_porch = { 16, 36, 56 },
2736 .hsync_len = { 8, 8, 8 },
2737 .vactive = { 480, 480, 480 },
2738 .vfront_porch = { 6, 21, 33 },
2739 .vback_porch = { 6, 21, 33 },
2740 .vsync_len = { 8, 8, 8 },
2741 .flags = DISPLAY_FLAGS_DE_HIGH,
2742};
2743
2744static const struct panel_desc koe_tx31d200vm0baa = {
2745 .timings = &koe_tx31d200vm0baa_timing,
2746 .num_timings = 1,
2747 .bpc = 6,
2748 .size = {
2749 .width = 292,
2750 .height = 109,
2751 },
2752 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2753 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2754};
2755
2756static const struct display_timing kyo_tcg121xglp_timing = {
2757 .pixelclock = { 52000000, 65000000, 71000000 },
2758 .hactive = { 1024, 1024, 1024 },
2759 .hfront_porch = { 2, 2, 2 },
2760 .hback_porch = { 2, 2, 2 },
2761 .hsync_len = { 86, 124, 244 },
2762 .vactive = { 768, 768, 768 },
2763 .vfront_porch = { 2, 2, 2 },
2764 .vback_porch = { 2, 2, 2 },
2765 .vsync_len = { 6, 34, 73 },
2766 .flags = DISPLAY_FLAGS_DE_HIGH,
2767};
2768
2769static const struct panel_desc kyo_tcg121xglp = {
2770 .timings = &kyo_tcg121xglp_timing,
2771 .num_timings = 1,
2772 .bpc = 8,
2773 .size = {
2774 .width = 246,
2775 .height = 184,
2776 },
2777 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2778 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2779};
2780
2781static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2782 .clock = 7000,
2783 .hdisplay = 320,
2784 .hsync_start = 320 + 20,
2785 .hsync_end = 320 + 20 + 30,
2786 .htotal = 320 + 20 + 30 + 38,
2787 .vdisplay = 240,
2788 .vsync_start = 240 + 4,
2789 .vsync_end = 240 + 4 + 3,
2790 .vtotal = 240 + 4 + 3 + 15,
2791};
2792
2793static const struct panel_desc lemaker_bl035_rgb_002 = {
2794 .modes = &lemaker_bl035_rgb_002_mode,
2795 .num_modes = 1,
2796 .size = {
2797 .width = 70,
2798 .height = 52,
2799 },
2800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2801 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2802};
2803
2804static const struct display_timing lg_lb070wv8_timing = {
2805 .pixelclock = { 31950000, 33260000, 34600000 },
2806 .hactive = { 800, 800, 800 },
2807 .hfront_porch = { 88, 88, 88 },
2808 .hback_porch = { 88, 88, 88 },
2809 .hsync_len = { 80, 80, 80 },
2810 .vactive = { 480, 480, 480 },
2811 .vfront_porch = { 10, 10, 10 },
2812 .vback_porch = { 10, 10, 10 },
2813 .vsync_len = { 25, 25, 25 },
2814};
2815
2816static const struct panel_desc lg_lb070wv8 = {
2817 .timings = &lg_lb070wv8_timing,
2818 .num_timings = 1,
2819 .bpc = 8,
2820 .size = {
2821 .width = 151,
2822 .height = 91,
2823 },
2824 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2825 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2826};
2827
2828static const struct display_timing logictechno_lt161010_2nh_timing = {
2829 .pixelclock = { 26400000, 33300000, 46800000 },
2830 .hactive = { 800, 800, 800 },
2831 .hfront_porch = { 16, 210, 354 },
2832 .hback_porch = { 46, 46, 46 },
2833 .hsync_len = { 1, 20, 40 },
2834 .vactive = { 480, 480, 480 },
2835 .vfront_porch = { 7, 22, 147 },
2836 .vback_porch = { 23, 23, 23 },
2837 .vsync_len = { 1, 10, 20 },
2838 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2839 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2840 DISPLAY_FLAGS_SYNC_POSEDGE,
2841};
2842
2843static const struct panel_desc logictechno_lt161010_2nh = {
2844 .timings = &logictechno_lt161010_2nh_timing,
2845 .num_timings = 1,
2846 .bpc = 6,
2847 .size = {
2848 .width = 154,
2849 .height = 86,
2850 },
2851 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2852 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2853 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2854 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2855 .connector_type = DRM_MODE_CONNECTOR_DPI,
2856};
2857
2858static const struct display_timing logictechno_lt170410_2whc_timing = {
2859 .pixelclock = { 68900000, 71100000, 73400000 },
2860 .hactive = { 1280, 1280, 1280 },
2861 .hfront_porch = { 23, 60, 71 },
2862 .hback_porch = { 23, 60, 71 },
2863 .hsync_len = { 15, 40, 47 },
2864 .vactive = { 800, 800, 800 },
2865 .vfront_porch = { 5, 7, 10 },
2866 .vback_porch = { 5, 7, 10 },
2867 .vsync_len = { 6, 9, 12 },
2868 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2869 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2870 DISPLAY_FLAGS_SYNC_POSEDGE,
2871};
2872
2873static const struct panel_desc logictechno_lt170410_2whc = {
2874 .timings = &logictechno_lt170410_2whc_timing,
2875 .num_timings = 1,
2876 .bpc = 8,
2877 .size = {
2878 .width = 217,
2879 .height = 136,
2880 },
2881 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2882 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2883 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2884};
2885
2886static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2887 .clock = 33000,
2888 .hdisplay = 800,
2889 .hsync_start = 800 + 112,
2890 .hsync_end = 800 + 112 + 3,
2891 .htotal = 800 + 112 + 3 + 85,
2892 .vdisplay = 480,
2893 .vsync_start = 480 + 38,
2894 .vsync_end = 480 + 38 + 3,
2895 .vtotal = 480 + 38 + 3 + 29,
2896 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2897};
2898
2899static const struct panel_desc logictechno_lttd800480070_l2rt = {
2900 .modes = &logictechno_lttd800480070_l2rt_mode,
2901 .num_modes = 1,
2902 .bpc = 8,
2903 .size = {
2904 .width = 154,
2905 .height = 86,
2906 },
2907 .delay = {
2908 .prepare = 45,
2909 .enable = 100,
2910 .disable = 100,
2911 .unprepare = 45
2912 },
2913 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2914 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2915 .connector_type = DRM_MODE_CONNECTOR_DPI,
2916};
2917
2918static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2919 .clock = 33000,
2920 .hdisplay = 800,
2921 .hsync_start = 800 + 154,
2922 .hsync_end = 800 + 154 + 3,
2923 .htotal = 800 + 154 + 3 + 43,
2924 .vdisplay = 480,
2925 .vsync_start = 480 + 47,
2926 .vsync_end = 480 + 47 + 3,
2927 .vtotal = 480 + 47 + 3 + 20,
2928 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2929};
2930
2931static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2932 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2933 .num_modes = 1,
2934 .bpc = 8,
2935 .size = {
2936 .width = 154,
2937 .height = 86,
2938 },
2939 .delay = {
2940 .prepare = 45,
2941 .enable = 100,
2942 .disable = 100,
2943 .unprepare = 45
2944 },
2945 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2946 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2947 .connector_type = DRM_MODE_CONNECTOR_DPI,
2948};
2949
2950static const struct drm_display_mode logicpd_type_28_mode = {
2951 .clock = 9107,
2952 .hdisplay = 480,
2953 .hsync_start = 480 + 3,
2954 .hsync_end = 480 + 3 + 42,
2955 .htotal = 480 + 3 + 42 + 2,
2956
2957 .vdisplay = 272,
2958 .vsync_start = 272 + 2,
2959 .vsync_end = 272 + 2 + 11,
2960 .vtotal = 272 + 2 + 11 + 3,
2961 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2962};
2963
2964static const struct panel_desc logicpd_type_28 = {
2965 .modes = &logicpd_type_28_mode,
2966 .num_modes = 1,
2967 .bpc = 8,
2968 .size = {
2969 .width = 105,
2970 .height = 67,
2971 },
2972 .delay = {
2973 .prepare = 200,
2974 .enable = 200,
2975 .unprepare = 200,
2976 .disable = 200,
2977 },
2978 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2979 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2980 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2981 .connector_type = DRM_MODE_CONNECTOR_DPI,
2982};
2983
2984static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2985 .clock = 30400,
2986 .hdisplay = 800,
2987 .hsync_start = 800 + 0,
2988 .hsync_end = 800 + 1,
2989 .htotal = 800 + 0 + 1 + 160,
2990 .vdisplay = 480,
2991 .vsync_start = 480 + 0,
2992 .vsync_end = 480 + 48 + 1,
2993 .vtotal = 480 + 48 + 1 + 0,
2994 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2995};
2996
2997static const struct panel_desc mitsubishi_aa070mc01 = {
2998 .modes = &mitsubishi_aa070mc01_mode,
2999 .num_modes = 1,
3000 .bpc = 8,
3001 .size = {
3002 .width = 152,
3003 .height = 91,
3004 },
3005
3006 .delay = {
3007 .enable = 200,
3008 .unprepare = 200,
3009 .disable = 400,
3010 },
3011 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3012 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3013 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3014};
3015
3016static const struct drm_display_mode mitsubishi_aa084xe01_mode = {
3017 .clock = 56234,
3018 .hdisplay = 1024,
3019 .hsync_start = 1024 + 24,
3020 .hsync_end = 1024 + 24 + 63,
3021 .htotal = 1024 + 24 + 63 + 1,
3022 .vdisplay = 768,
3023 .vsync_start = 768 + 3,
3024 .vsync_end = 768 + 3 + 6,
3025 .vtotal = 768 + 3 + 6 + 1,
3026 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3027};
3028
3029static const struct panel_desc mitsubishi_aa084xe01 = {
3030 .modes = &mitsubishi_aa084xe01_mode,
3031 .num_modes = 1,
3032 .bpc = 8,
3033 .size = {
3034 .width = 1024,
3035 .height = 768,
3036 },
3037 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3038 .connector_type = DRM_MODE_CONNECTOR_DPI,
3039 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3040};
3041
3042static const struct display_timing multi_inno_mi0700s4t_6_timing = {
3043 .pixelclock = { 29000000, 33000000, 38000000 },
3044 .hactive = { 800, 800, 800 },
3045 .hfront_porch = { 180, 210, 240 },
3046 .hback_porch = { 16, 16, 16 },
3047 .hsync_len = { 30, 30, 30 },
3048 .vactive = { 480, 480, 480 },
3049 .vfront_porch = { 12, 22, 32 },
3050 .vback_porch = { 10, 10, 10 },
3051 .vsync_len = { 13, 13, 13 },
3052 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3053 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3054 DISPLAY_FLAGS_SYNC_POSEDGE,
3055};
3056
3057static const struct panel_desc multi_inno_mi0700s4t_6 = {
3058 .timings = &multi_inno_mi0700s4t_6_timing,
3059 .num_timings = 1,
3060 .bpc = 8,
3061 .size = {
3062 .width = 154,
3063 .height = 86,
3064 },
3065 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3066 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3067 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3068 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3069 .connector_type = DRM_MODE_CONNECTOR_DPI,
3070};
3071
3072static const struct display_timing multi_inno_mi0800ft_9_timing = {
3073 .pixelclock = { 32000000, 40000000, 50000000 },
3074 .hactive = { 800, 800, 800 },
3075 .hfront_porch = { 16, 210, 354 },
3076 .hback_porch = { 6, 26, 45 },
3077 .hsync_len = { 1, 20, 40 },
3078 .vactive = { 600, 600, 600 },
3079 .vfront_porch = { 1, 12, 77 },
3080 .vback_porch = { 3, 13, 22 },
3081 .vsync_len = { 1, 10, 20 },
3082 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3083 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3084 DISPLAY_FLAGS_SYNC_POSEDGE,
3085};
3086
3087static const struct panel_desc multi_inno_mi0800ft_9 = {
3088 .timings = &multi_inno_mi0800ft_9_timing,
3089 .num_timings = 1,
3090 .bpc = 8,
3091 .size = {
3092 .width = 162,
3093 .height = 122,
3094 },
3095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3096 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3097 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3098 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3099 .connector_type = DRM_MODE_CONNECTOR_DPI,
3100};
3101
3102static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3103 .pixelclock = { 68900000, 70000000, 73400000 },
3104 .hactive = { 1280, 1280, 1280 },
3105 .hfront_porch = { 30, 60, 71 },
3106 .hback_porch = { 30, 60, 71 },
3107 .hsync_len = { 10, 10, 48 },
3108 .vactive = { 800, 800, 800 },
3109 .vfront_porch = { 5, 10, 10 },
3110 .vback_porch = { 5, 10, 10 },
3111 .vsync_len = { 5, 6, 13 },
3112 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3113 DISPLAY_FLAGS_DE_HIGH,
3114};
3115
3116static const struct panel_desc multi_inno_mi1010ait_1cp = {
3117 .timings = &multi_inno_mi1010ait_1cp_timing,
3118 .num_timings = 1,
3119 .bpc = 8,
3120 .size = {
3121 .width = 217,
3122 .height = 136,
3123 },
3124 .delay = {
3125 .enable = 50,
3126 .disable = 50,
3127 },
3128 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3129 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3130 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3131};
3132
3133static const struct display_timing nec_nl12880bc20_05_timing = {
3134 .pixelclock = { 67000000, 71000000, 75000000 },
3135 .hactive = { 1280, 1280, 1280 },
3136 .hfront_porch = { 2, 30, 30 },
3137 .hback_porch = { 6, 100, 100 },
3138 .hsync_len = { 2, 30, 30 },
3139 .vactive = { 800, 800, 800 },
3140 .vfront_porch = { 5, 5, 5 },
3141 .vback_porch = { 11, 11, 11 },
3142 .vsync_len = { 7, 7, 7 },
3143};
3144
3145static const struct panel_desc nec_nl12880bc20_05 = {
3146 .timings = &nec_nl12880bc20_05_timing,
3147 .num_timings = 1,
3148 .bpc = 8,
3149 .size = {
3150 .width = 261,
3151 .height = 163,
3152 },
3153 .delay = {
3154 .enable = 50,
3155 .disable = 50,
3156 },
3157 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3158 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3159};
3160
3161static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3162 .clock = 10870,
3163 .hdisplay = 480,
3164 .hsync_start = 480 + 2,
3165 .hsync_end = 480 + 2 + 41,
3166 .htotal = 480 + 2 + 41 + 2,
3167 .vdisplay = 272,
3168 .vsync_start = 272 + 2,
3169 .vsync_end = 272 + 2 + 4,
3170 .vtotal = 272 + 2 + 4 + 2,
3171 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3172};
3173
3174static const struct panel_desc nec_nl4827hc19_05b = {
3175 .modes = &nec_nl4827hc19_05b_mode,
3176 .num_modes = 1,
3177 .bpc = 8,
3178 .size = {
3179 .width = 95,
3180 .height = 54,
3181 },
3182 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3183 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3184};
3185
3186static const struct drm_display_mode netron_dy_e231732_mode = {
3187 .clock = 66000,
3188 .hdisplay = 1024,
3189 .hsync_start = 1024 + 160,
3190 .hsync_end = 1024 + 160 + 70,
3191 .htotal = 1024 + 160 + 70 + 90,
3192 .vdisplay = 600,
3193 .vsync_start = 600 + 127,
3194 .vsync_end = 600 + 127 + 20,
3195 .vtotal = 600 + 127 + 20 + 3,
3196};
3197
3198static const struct panel_desc netron_dy_e231732 = {
3199 .modes = &netron_dy_e231732_mode,
3200 .num_modes = 1,
3201 .size = {
3202 .width = 154,
3203 .height = 87,
3204 },
3205 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3206};
3207
3208static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3209 .clock = 9000,
3210 .hdisplay = 480,
3211 .hsync_start = 480 + 2,
3212 .hsync_end = 480 + 2 + 41,
3213 .htotal = 480 + 2 + 41 + 2,
3214 .vdisplay = 272,
3215 .vsync_start = 272 + 2,
3216 .vsync_end = 272 + 2 + 10,
3217 .vtotal = 272 + 2 + 10 + 2,
3218 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3219};
3220
3221static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3222 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3223 .num_modes = 1,
3224 .bpc = 8,
3225 .size = {
3226 .width = 95,
3227 .height = 54,
3228 },
3229 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3230 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3231 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3232 .connector_type = DRM_MODE_CONNECTOR_DPI,
3233};
3234
3235static const struct display_timing nlt_nl192108ac18_02d_timing = {
3236 .pixelclock = { 130000000, 148350000, 163000000 },
3237 .hactive = { 1920, 1920, 1920 },
3238 .hfront_porch = { 80, 100, 100 },
3239 .hback_porch = { 100, 120, 120 },
3240 .hsync_len = { 50, 60, 60 },
3241 .vactive = { 1080, 1080, 1080 },
3242 .vfront_porch = { 12, 30, 30 },
3243 .vback_porch = { 4, 10, 10 },
3244 .vsync_len = { 4, 5, 5 },
3245};
3246
3247static const struct panel_desc nlt_nl192108ac18_02d = {
3248 .timings = &nlt_nl192108ac18_02d_timing,
3249 .num_timings = 1,
3250 .bpc = 8,
3251 .size = {
3252 .width = 344,
3253 .height = 194,
3254 },
3255 .delay = {
3256 .unprepare = 500,
3257 },
3258 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3259 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3260};
3261
3262static const struct drm_display_mode nvd_9128_mode = {
3263 .clock = 29500,
3264 .hdisplay = 800,
3265 .hsync_start = 800 + 130,
3266 .hsync_end = 800 + 130 + 98,
3267 .htotal = 800 + 0 + 130 + 98,
3268 .vdisplay = 480,
3269 .vsync_start = 480 + 10,
3270 .vsync_end = 480 + 10 + 50,
3271 .vtotal = 480 + 0 + 10 + 50,
3272};
3273
3274static const struct panel_desc nvd_9128 = {
3275 .modes = &nvd_9128_mode,
3276 .num_modes = 1,
3277 .bpc = 8,
3278 .size = {
3279 .width = 156,
3280 .height = 88,
3281 },
3282 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3283 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3284};
3285
3286static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3287 .pixelclock = { 30000000, 30000000, 40000000 },
3288 .hactive = { 800, 800, 800 },
3289 .hfront_porch = { 40, 40, 40 },
3290 .hback_porch = { 40, 40, 40 },
3291 .hsync_len = { 1, 48, 48 },
3292 .vactive = { 480, 480, 480 },
3293 .vfront_porch = { 13, 13, 13 },
3294 .vback_porch = { 29, 29, 29 },
3295 .vsync_len = { 3, 3, 3 },
3296 .flags = DISPLAY_FLAGS_DE_HIGH,
3297};
3298
3299static const struct panel_desc okaya_rs800480t_7x0gp = {
3300 .timings = &okaya_rs800480t_7x0gp_timing,
3301 .num_timings = 1,
3302 .bpc = 6,
3303 .size = {
3304 .width = 154,
3305 .height = 87,
3306 },
3307 .delay = {
3308 .prepare = 41,
3309 .enable = 50,
3310 .unprepare = 41,
3311 .disable = 50,
3312 },
3313 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3314};
3315
3316static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3317 .clock = 9000,
3318 .hdisplay = 480,
3319 .hsync_start = 480 + 5,
3320 .hsync_end = 480 + 5 + 30,
3321 .htotal = 480 + 5 + 30 + 10,
3322 .vdisplay = 272,
3323 .vsync_start = 272 + 8,
3324 .vsync_end = 272 + 8 + 5,
3325 .vtotal = 272 + 8 + 5 + 3,
3326};
3327
3328static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3329 .modes = &olimex_lcd_olinuxino_43ts_mode,
3330 .num_modes = 1,
3331 .size = {
3332 .width = 95,
3333 .height = 54,
3334 },
3335 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3336};
3337
3338/*
3339 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3340 * pixel clocks, but this is the timing that was being used in the Adafruit
3341 * installation instructions.
3342 */
3343static const struct drm_display_mode ontat_yx700wv03_mode = {
3344 .clock = 29500,
3345 .hdisplay = 800,
3346 .hsync_start = 824,
3347 .hsync_end = 896,
3348 .htotal = 992,
3349 .vdisplay = 480,
3350 .vsync_start = 483,
3351 .vsync_end = 493,
3352 .vtotal = 500,
3353 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3354};
3355
3356/*
3357 * Specification at:
3358 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3359 */
3360static const struct panel_desc ontat_yx700wv03 = {
3361 .modes = &ontat_yx700wv03_mode,
3362 .num_modes = 1,
3363 .bpc = 8,
3364 .size = {
3365 .width = 154,
3366 .height = 83,
3367 },
3368 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3369};
3370
3371static const struct drm_display_mode ortustech_com37h3m_mode = {
3372 .clock = 22230,
3373 .hdisplay = 480,
3374 .hsync_start = 480 + 40,
3375 .hsync_end = 480 + 40 + 10,
3376 .htotal = 480 + 40 + 10 + 40,
3377 .vdisplay = 640,
3378 .vsync_start = 640 + 4,
3379 .vsync_end = 640 + 4 + 2,
3380 .vtotal = 640 + 4 + 2 + 4,
3381 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3382};
3383
3384static const struct panel_desc ortustech_com37h3m = {
3385 .modes = &ortustech_com37h3m_mode,
3386 .num_modes = 1,
3387 .bpc = 8,
3388 .size = {
3389 .width = 56, /* 56.16mm */
3390 .height = 75, /* 74.88mm */
3391 },
3392 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3393 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3394 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3395};
3396
3397static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3398 .clock = 25000,
3399 .hdisplay = 480,
3400 .hsync_start = 480 + 10,
3401 .hsync_end = 480 + 10 + 10,
3402 .htotal = 480 + 10 + 10 + 15,
3403 .vdisplay = 800,
3404 .vsync_start = 800 + 3,
3405 .vsync_end = 800 + 3 + 3,
3406 .vtotal = 800 + 3 + 3 + 3,
3407};
3408
3409static const struct panel_desc ortustech_com43h4m85ulc = {
3410 .modes = &ortustech_com43h4m85ulc_mode,
3411 .num_modes = 1,
3412 .bpc = 6,
3413 .size = {
3414 .width = 56,
3415 .height = 93,
3416 },
3417 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3418 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3419 .connector_type = DRM_MODE_CONNECTOR_DPI,
3420};
3421
3422static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3423 .clock = 33000,
3424 .hdisplay = 800,
3425 .hsync_start = 800 + 210,
3426 .hsync_end = 800 + 210 + 30,
3427 .htotal = 800 + 210 + 30 + 16,
3428 .vdisplay = 480,
3429 .vsync_start = 480 + 22,
3430 .vsync_end = 480 + 22 + 13,
3431 .vtotal = 480 + 22 + 13 + 10,
3432 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3433};
3434
3435static const struct panel_desc osddisplays_osd070t1718_19ts = {
3436 .modes = &osddisplays_osd070t1718_19ts_mode,
3437 .num_modes = 1,
3438 .bpc = 8,
3439 .size = {
3440 .width = 152,
3441 .height = 91,
3442 },
3443 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3444 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3445 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3446 .connector_type = DRM_MODE_CONNECTOR_DPI,
3447};
3448
3449static const struct drm_display_mode pda_91_00156_a0_mode = {
3450 .clock = 33300,
3451 .hdisplay = 800,
3452 .hsync_start = 800 + 1,
3453 .hsync_end = 800 + 1 + 64,
3454 .htotal = 800 + 1 + 64 + 64,
3455 .vdisplay = 480,
3456 .vsync_start = 480 + 1,
3457 .vsync_end = 480 + 1 + 23,
3458 .vtotal = 480 + 1 + 23 + 22,
3459};
3460
3461static const struct panel_desc pda_91_00156_a0 = {
3462 .modes = &pda_91_00156_a0_mode,
3463 .num_modes = 1,
3464 .size = {
3465 .width = 152,
3466 .height = 91,
3467 },
3468 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3469};
3470
3471static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3472 .clock = 24750,
3473 .hdisplay = 800,
3474 .hsync_start = 800 + 54,
3475 .hsync_end = 800 + 54 + 2,
3476 .htotal = 800 + 54 + 2 + 44,
3477 .vdisplay = 480,
3478 .vsync_start = 480 + 49,
3479 .vsync_end = 480 + 49 + 2,
3480 .vtotal = 480 + 49 + 2 + 22,
3481 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3482};
3483
3484static const struct panel_desc powertip_ph800480t013_idf02 = {
3485 .modes = &powertip_ph800480t013_idf02_mode,
3486 .num_modes = 1,
3487 .bpc = 8,
3488 .size = {
3489 .width = 152,
3490 .height = 91,
3491 },
3492 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3493 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3494 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3495 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3496 .connector_type = DRM_MODE_CONNECTOR_DPI,
3497};
3498
3499static const struct drm_display_mode qd43003c0_40_mode = {
3500 .clock = 9000,
3501 .hdisplay = 480,
3502 .hsync_start = 480 + 8,
3503 .hsync_end = 480 + 8 + 4,
3504 .htotal = 480 + 8 + 4 + 39,
3505 .vdisplay = 272,
3506 .vsync_start = 272 + 4,
3507 .vsync_end = 272 + 4 + 10,
3508 .vtotal = 272 + 4 + 10 + 2,
3509};
3510
3511static const struct panel_desc qd43003c0_40 = {
3512 .modes = &qd43003c0_40_mode,
3513 .num_modes = 1,
3514 .bpc = 8,
3515 .size = {
3516 .width = 95,
3517 .height = 53,
3518 },
3519 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3520};
3521
3522static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3523 { /* 60 Hz */
3524 .clock = 10800,
3525 .hdisplay = 480,
3526 .hsync_start = 480 + 77,
3527 .hsync_end = 480 + 77 + 41,
3528 .htotal = 480 + 77 + 41 + 2,
3529 .vdisplay = 272,
3530 .vsync_start = 272 + 16,
3531 .vsync_end = 272 + 16 + 10,
3532 .vtotal = 272 + 16 + 10 + 2,
3533 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3534 },
3535 { /* 50 Hz */
3536 .clock = 10800,
3537 .hdisplay = 480,
3538 .hsync_start = 480 + 17,
3539 .hsync_end = 480 + 17 + 41,
3540 .htotal = 480 + 17 + 41 + 2,
3541 .vdisplay = 272,
3542 .vsync_start = 272 + 116,
3543 .vsync_end = 272 + 116 + 10,
3544 .vtotal = 272 + 116 + 10 + 2,
3545 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3546 },
3547};
3548
3549static const struct panel_desc qishenglong_gopher2b_lcd = {
3550 .modes = qishenglong_gopher2b_lcd_modes,
3551 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3552 .bpc = 8,
3553 .size = {
3554 .width = 95,
3555 .height = 54,
3556 },
3557 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3558 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3559 .connector_type = DRM_MODE_CONNECTOR_DPI,
3560};
3561
3562static const struct display_timing rocktech_rk043fn48h_timing = {
3563 .pixelclock = { 6000000, 9000000, 12000000 },
3564 .hactive = { 480, 480, 480 },
3565 .hback_porch = { 8, 43, 43 },
3566 .hfront_porch = { 2, 8, 10 },
3567 .hsync_len = { 1, 1, 1 },
3568 .vactive = { 272, 272, 272 },
3569 .vback_porch = { 2, 12, 26 },
3570 .vfront_porch = { 1, 4, 4 },
3571 .vsync_len = { 1, 10, 10 },
3572 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3573 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3574 DISPLAY_FLAGS_SYNC_POSEDGE,
3575};
3576
3577static const struct panel_desc rocktech_rk043fn48h = {
3578 .timings = &rocktech_rk043fn48h_timing,
3579 .num_timings = 1,
3580 .bpc = 8,
3581 .size = {
3582 .width = 95,
3583 .height = 54,
3584 },
3585 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3586 .connector_type = DRM_MODE_CONNECTOR_DPI,
3587};
3588
3589static const struct display_timing rocktech_rk070er9427_timing = {
3590 .pixelclock = { 26400000, 33300000, 46800000 },
3591 .hactive = { 800, 800, 800 },
3592 .hfront_porch = { 16, 210, 354 },
3593 .hback_porch = { 46, 46, 46 },
3594 .hsync_len = { 1, 1, 1 },
3595 .vactive = { 480, 480, 480 },
3596 .vfront_porch = { 7, 22, 147 },
3597 .vback_porch = { 23, 23, 23 },
3598 .vsync_len = { 1, 1, 1 },
3599 .flags = DISPLAY_FLAGS_DE_HIGH,
3600};
3601
3602static const struct panel_desc rocktech_rk070er9427 = {
3603 .timings = &rocktech_rk070er9427_timing,
3604 .num_timings = 1,
3605 .bpc = 6,
3606 .size = {
3607 .width = 154,
3608 .height = 86,
3609 },
3610 .delay = {
3611 .prepare = 41,
3612 .enable = 50,
3613 .unprepare = 41,
3614 .disable = 50,
3615 },
3616 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3617};
3618
3619static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3620 .clock = 71100,
3621 .hdisplay = 1280,
3622 .hsync_start = 1280 + 48,
3623 .hsync_end = 1280 + 48 + 32,
3624 .htotal = 1280 + 48 + 32 + 80,
3625 .vdisplay = 800,
3626 .vsync_start = 800 + 2,
3627 .vsync_end = 800 + 2 + 5,
3628 .vtotal = 800 + 2 + 5 + 16,
3629};
3630
3631static const struct panel_desc rocktech_rk101ii01d_ct = {
3632 .modes = &rocktech_rk101ii01d_ct_mode,
3633 .bpc = 8,
3634 .num_modes = 1,
3635 .size = {
3636 .width = 217,
3637 .height = 136,
3638 },
3639 .delay = {
3640 .prepare = 50,
3641 .disable = 50,
3642 },
3643 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3644 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3645 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3646};
3647
3648static const struct display_timing samsung_ltl101al01_timing = {
3649 .pixelclock = { 66663000, 66663000, 66663000 },
3650 .hactive = { 1280, 1280, 1280 },
3651 .hfront_porch = { 18, 18, 18 },
3652 .hback_porch = { 36, 36, 36 },
3653 .hsync_len = { 16, 16, 16 },
3654 .vactive = { 800, 800, 800 },
3655 .vfront_porch = { 4, 4, 4 },
3656 .vback_porch = { 16, 16, 16 },
3657 .vsync_len = { 3, 3, 3 },
3658 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3659};
3660
3661static const struct panel_desc samsung_ltl101al01 = {
3662 .timings = &samsung_ltl101al01_timing,
3663 .num_timings = 1,
3664 .bpc = 8,
3665 .size = {
3666 .width = 217,
3667 .height = 135,
3668 },
3669 .delay = {
3670 .prepare = 40,
3671 .enable = 300,
3672 .disable = 200,
3673 .unprepare = 600,
3674 },
3675 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3676 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3677};
3678
3679static const struct drm_display_mode samsung_ltn101nt05_mode = {
3680 .clock = 54030,
3681 .hdisplay = 1024,
3682 .hsync_start = 1024 + 24,
3683 .hsync_end = 1024 + 24 + 136,
3684 .htotal = 1024 + 24 + 136 + 160,
3685 .vdisplay = 600,
3686 .vsync_start = 600 + 3,
3687 .vsync_end = 600 + 3 + 6,
3688 .vtotal = 600 + 3 + 6 + 61,
3689};
3690
3691static const struct panel_desc samsung_ltn101nt05 = {
3692 .modes = &samsung_ltn101nt05_mode,
3693 .num_modes = 1,
3694 .bpc = 6,
3695 .size = {
3696 .width = 223,
3697 .height = 125,
3698 },
3699 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3700 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3701 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3702};
3703
3704static const struct display_timing satoz_sat050at40h12r2_timing = {
3705 .pixelclock = {33300000, 33300000, 50000000},
3706 .hactive = {800, 800, 800},
3707 .hfront_porch = {16, 210, 354},
3708 .hback_porch = {46, 46, 46},
3709 .hsync_len = {1, 1, 40},
3710 .vactive = {480, 480, 480},
3711 .vfront_porch = {7, 22, 147},
3712 .vback_porch = {23, 23, 23},
3713 .vsync_len = {1, 1, 20},
3714};
3715
3716static const struct panel_desc satoz_sat050at40h12r2 = {
3717 .timings = &satoz_sat050at40h12r2_timing,
3718 .num_timings = 1,
3719 .bpc = 8,
3720 .size = {
3721 .width = 108,
3722 .height = 65,
3723 },
3724 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3725 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3726};
3727
3728static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3729 .clock = 33260,
3730 .hdisplay = 800,
3731 .hsync_start = 800 + 64,
3732 .hsync_end = 800 + 64 + 128,
3733 .htotal = 800 + 64 + 128 + 64,
3734 .vdisplay = 480,
3735 .vsync_start = 480 + 8,
3736 .vsync_end = 480 + 8 + 2,
3737 .vtotal = 480 + 8 + 2 + 35,
3738 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3739};
3740
3741static const struct panel_desc sharp_lq070y3dg3b = {
3742 .modes = &sharp_lq070y3dg3b_mode,
3743 .num_modes = 1,
3744 .bpc = 8,
3745 .size = {
3746 .width = 152, /* 152.4mm */
3747 .height = 91, /* 91.4mm */
3748 },
3749 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3750 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3751 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3752};
3753
3754static const struct drm_display_mode sharp_lq035q7db03_mode = {
3755 .clock = 5500,
3756 .hdisplay = 240,
3757 .hsync_start = 240 + 16,
3758 .hsync_end = 240 + 16 + 7,
3759 .htotal = 240 + 16 + 7 + 5,
3760 .vdisplay = 320,
3761 .vsync_start = 320 + 9,
3762 .vsync_end = 320 + 9 + 1,
3763 .vtotal = 320 + 9 + 1 + 7,
3764};
3765
3766static const struct panel_desc sharp_lq035q7db03 = {
3767 .modes = &sharp_lq035q7db03_mode,
3768 .num_modes = 1,
3769 .bpc = 6,
3770 .size = {
3771 .width = 54,
3772 .height = 72,
3773 },
3774 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3775};
3776
3777static const struct display_timing sharp_lq101k1ly04_timing = {
3778 .pixelclock = { 60000000, 65000000, 80000000 },
3779 .hactive = { 1280, 1280, 1280 },
3780 .hfront_porch = { 20, 20, 20 },
3781 .hback_porch = { 20, 20, 20 },
3782 .hsync_len = { 10, 10, 10 },
3783 .vactive = { 800, 800, 800 },
3784 .vfront_porch = { 4, 4, 4 },
3785 .vback_porch = { 4, 4, 4 },
3786 .vsync_len = { 4, 4, 4 },
3787 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3788};
3789
3790static const struct panel_desc sharp_lq101k1ly04 = {
3791 .timings = &sharp_lq101k1ly04_timing,
3792 .num_timings = 1,
3793 .bpc = 8,
3794 .size = {
3795 .width = 217,
3796 .height = 136,
3797 },
3798 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3799 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3800};
3801
3802static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3803 { /* 50 Hz */
3804 .clock = 3000,
3805 .hdisplay = 240,
3806 .hsync_start = 240 + 58,
3807 .hsync_end = 240 + 58 + 1,
3808 .htotal = 240 + 58 + 1 + 1,
3809 .vdisplay = 160,
3810 .vsync_start = 160 + 24,
3811 .vsync_end = 160 + 24 + 10,
3812 .vtotal = 160 + 24 + 10 + 6,
3813 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3814 },
3815 { /* 60 Hz */
3816 .clock = 3000,
3817 .hdisplay = 240,
3818 .hsync_start = 240 + 8,
3819 .hsync_end = 240 + 8 + 1,
3820 .htotal = 240 + 8 + 1 + 1,
3821 .vdisplay = 160,
3822 .vsync_start = 160 + 24,
3823 .vsync_end = 160 + 24 + 10,
3824 .vtotal = 160 + 24 + 10 + 6,
3825 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3826 },
3827};
3828
3829static const struct panel_desc sharp_ls020b1dd01d = {
3830 .modes = sharp_ls020b1dd01d_modes,
3831 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3832 .bpc = 6,
3833 .size = {
3834 .width = 42,
3835 .height = 28,
3836 },
3837 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3838 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3839 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3840 | DRM_BUS_FLAG_SHARP_SIGNALS,
3841};
3842
3843static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3844 .clock = 33300,
3845 .hdisplay = 800,
3846 .hsync_start = 800 + 1,
3847 .hsync_end = 800 + 1 + 64,
3848 .htotal = 800 + 1 + 64 + 64,
3849 .vdisplay = 480,
3850 .vsync_start = 480 + 1,
3851 .vsync_end = 480 + 1 + 23,
3852 .vtotal = 480 + 1 + 23 + 22,
3853};
3854
3855static const struct panel_desc shelly_sca07010_bfn_lnn = {
3856 .modes = &shelly_sca07010_bfn_lnn_mode,
3857 .num_modes = 1,
3858 .size = {
3859 .width = 152,
3860 .height = 91,
3861 },
3862 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3863};
3864
3865static const struct drm_display_mode starry_kr070pe2t_mode = {
3866 .clock = 33000,
3867 .hdisplay = 800,
3868 .hsync_start = 800 + 209,
3869 .hsync_end = 800 + 209 + 1,
3870 .htotal = 800 + 209 + 1 + 45,
3871 .vdisplay = 480,
3872 .vsync_start = 480 + 22,
3873 .vsync_end = 480 + 22 + 1,
3874 .vtotal = 480 + 22 + 1 + 22,
3875};
3876
3877static const struct panel_desc starry_kr070pe2t = {
3878 .modes = &starry_kr070pe2t_mode,
3879 .num_modes = 1,
3880 .bpc = 8,
3881 .size = {
3882 .width = 152,
3883 .height = 86,
3884 },
3885 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3886 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3887 .connector_type = DRM_MODE_CONNECTOR_DPI,
3888};
3889
3890static const struct display_timing startek_kd070wvfpa_mode = {
3891 .pixelclock = { 25200000, 27200000, 30500000 },
3892 .hactive = { 800, 800, 800 },
3893 .hfront_porch = { 19, 44, 115 },
3894 .hback_porch = { 5, 16, 101 },
3895 .hsync_len = { 1, 2, 100 },
3896 .vactive = { 480, 480, 480 },
3897 .vfront_porch = { 5, 43, 67 },
3898 .vback_porch = { 5, 5, 67 },
3899 .vsync_len = { 1, 2, 66 },
3900 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3901 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3902 DISPLAY_FLAGS_SYNC_POSEDGE,
3903};
3904
3905static const struct panel_desc startek_kd070wvfpa = {
3906 .timings = &startek_kd070wvfpa_mode,
3907 .num_timings = 1,
3908 .bpc = 8,
3909 .size = {
3910 .width = 152,
3911 .height = 91,
3912 },
3913 .delay = {
3914 .prepare = 20,
3915 .enable = 200,
3916 .disable = 200,
3917 },
3918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3919 .connector_type = DRM_MODE_CONNECTOR_DPI,
3920 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3921 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3922 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3923};
3924
3925static const struct display_timing tsd_tst043015cmhx_timing = {
3926 .pixelclock = { 5000000, 9000000, 12000000 },
3927 .hactive = { 480, 480, 480 },
3928 .hfront_porch = { 4, 5, 65 },
3929 .hback_porch = { 36, 40, 255 },
3930 .hsync_len = { 1, 1, 1 },
3931 .vactive = { 272, 272, 272 },
3932 .vfront_porch = { 2, 8, 97 },
3933 .vback_porch = { 3, 8, 31 },
3934 .vsync_len = { 1, 1, 1 },
3935
3936 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3937 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3938};
3939
3940static const struct panel_desc tsd_tst043015cmhx = {
3941 .timings = &tsd_tst043015cmhx_timing,
3942 .num_timings = 1,
3943 .bpc = 8,
3944 .size = {
3945 .width = 105,
3946 .height = 67,
3947 },
3948 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3949 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3950};
3951
3952static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3953 .clock = 30000,
3954 .hdisplay = 800,
3955 .hsync_start = 800 + 39,
3956 .hsync_end = 800 + 39 + 47,
3957 .htotal = 800 + 39 + 47 + 39,
3958 .vdisplay = 480,
3959 .vsync_start = 480 + 13,
3960 .vsync_end = 480 + 13 + 2,
3961 .vtotal = 480 + 13 + 2 + 29,
3962};
3963
3964static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3965 .modes = &tfc_s9700rtwv43tr_01b_mode,
3966 .num_modes = 1,
3967 .bpc = 8,
3968 .size = {
3969 .width = 155,
3970 .height = 90,
3971 },
3972 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3973 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3974};
3975
3976static const struct display_timing tianma_tm070jdhg30_timing = {
3977 .pixelclock = { 62600000, 68200000, 78100000 },
3978 .hactive = { 1280, 1280, 1280 },
3979 .hfront_porch = { 15, 64, 159 },
3980 .hback_porch = { 5, 5, 5 },
3981 .hsync_len = { 1, 1, 256 },
3982 .vactive = { 800, 800, 800 },
3983 .vfront_porch = { 3, 40, 99 },
3984 .vback_porch = { 2, 2, 2 },
3985 .vsync_len = { 1, 1, 128 },
3986 .flags = DISPLAY_FLAGS_DE_HIGH,
3987};
3988
3989static const struct panel_desc tianma_tm070jdhg30 = {
3990 .timings = &tianma_tm070jdhg30_timing,
3991 .num_timings = 1,
3992 .bpc = 8,
3993 .size = {
3994 .width = 151,
3995 .height = 95,
3996 },
3997 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3998 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3999 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4000};
4001
4002static const struct panel_desc tianma_tm070jvhg33 = {
4003 .timings = &tianma_tm070jdhg30_timing,
4004 .num_timings = 1,
4005 .bpc = 8,
4006 .size = {
4007 .width = 150,
4008 .height = 94,
4009 },
4010 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4011 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4012 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4013};
4014
4015static const struct display_timing tianma_tm070rvhg71_timing = {
4016 .pixelclock = { 27700000, 29200000, 39600000 },
4017 .hactive = { 800, 800, 800 },
4018 .hfront_porch = { 12, 40, 212 },
4019 .hback_porch = { 88, 88, 88 },
4020 .hsync_len = { 1, 1, 40 },
4021 .vactive = { 480, 480, 480 },
4022 .vfront_porch = { 1, 13, 88 },
4023 .vback_porch = { 32, 32, 32 },
4024 .vsync_len = { 1, 1, 3 },
4025 .flags = DISPLAY_FLAGS_DE_HIGH,
4026};
4027
4028static const struct panel_desc tianma_tm070rvhg71 = {
4029 .timings = &tianma_tm070rvhg71_timing,
4030 .num_timings = 1,
4031 .bpc = 8,
4032 .size = {
4033 .width = 154,
4034 .height = 86,
4035 },
4036 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4037 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4038};
4039
4040static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4041 {
4042 .clock = 10000,
4043 .hdisplay = 320,
4044 .hsync_start = 320 + 50,
4045 .hsync_end = 320 + 50 + 6,
4046 .htotal = 320 + 50 + 6 + 38,
4047 .vdisplay = 240,
4048 .vsync_start = 240 + 3,
4049 .vsync_end = 240 + 3 + 1,
4050 .vtotal = 240 + 3 + 1 + 17,
4051 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4052 },
4053};
4054
4055static const struct panel_desc ti_nspire_cx_lcd_panel = {
4056 .modes = ti_nspire_cx_lcd_mode,
4057 .num_modes = 1,
4058 .bpc = 8,
4059 .size = {
4060 .width = 65,
4061 .height = 49,
4062 },
4063 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4064 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4065};
4066
4067static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4068 {
4069 .clock = 10000,
4070 .hdisplay = 320,
4071 .hsync_start = 320 + 6,
4072 .hsync_end = 320 + 6 + 6,
4073 .htotal = 320 + 6 + 6 + 6,
4074 .vdisplay = 240,
4075 .vsync_start = 240 + 0,
4076 .vsync_end = 240 + 0 + 1,
4077 .vtotal = 240 + 0 + 1 + 0,
4078 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4079 },
4080};
4081
4082static const struct panel_desc ti_nspire_classic_lcd_panel = {
4083 .modes = ti_nspire_classic_lcd_mode,
4084 .num_modes = 1,
4085 /* The grayscale panel has 8 bit for the color .. Y (black) */
4086 .bpc = 8,
4087 .size = {
4088 .width = 71,
4089 .height = 53,
4090 },
4091 /* This is the grayscale bus format */
4092 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4093 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4094};
4095
4096static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4097 .clock = 79500,
4098 .hdisplay = 1280,
4099 .hsync_start = 1280 + 192,
4100 .hsync_end = 1280 + 192 + 128,
4101 .htotal = 1280 + 192 + 128 + 64,
4102 .vdisplay = 768,
4103 .vsync_start = 768 + 20,
4104 .vsync_end = 768 + 20 + 7,
4105 .vtotal = 768 + 20 + 7 + 3,
4106};
4107
4108static const struct panel_desc toshiba_lt089ac29000 = {
4109 .modes = &toshiba_lt089ac29000_mode,
4110 .num_modes = 1,
4111 .size = {
4112 .width = 194,
4113 .height = 116,
4114 },
4115 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4116 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4117 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4118};
4119
4120static const struct drm_display_mode tpk_f07a_0102_mode = {
4121 .clock = 33260,
4122 .hdisplay = 800,
4123 .hsync_start = 800 + 40,
4124 .hsync_end = 800 + 40 + 128,
4125 .htotal = 800 + 40 + 128 + 88,
4126 .vdisplay = 480,
4127 .vsync_start = 480 + 10,
4128 .vsync_end = 480 + 10 + 2,
4129 .vtotal = 480 + 10 + 2 + 33,
4130};
4131
4132static const struct panel_desc tpk_f07a_0102 = {
4133 .modes = &tpk_f07a_0102_mode,
4134 .num_modes = 1,
4135 .size = {
4136 .width = 152,
4137 .height = 91,
4138 },
4139 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4140};
4141
4142static const struct drm_display_mode tpk_f10a_0102_mode = {
4143 .clock = 45000,
4144 .hdisplay = 1024,
4145 .hsync_start = 1024 + 176,
4146 .hsync_end = 1024 + 176 + 5,
4147 .htotal = 1024 + 176 + 5 + 88,
4148 .vdisplay = 600,
4149 .vsync_start = 600 + 20,
4150 .vsync_end = 600 + 20 + 5,
4151 .vtotal = 600 + 20 + 5 + 25,
4152};
4153
4154static const struct panel_desc tpk_f10a_0102 = {
4155 .modes = &tpk_f10a_0102_mode,
4156 .num_modes = 1,
4157 .size = {
4158 .width = 223,
4159 .height = 125,
4160 },
4161};
4162
4163static const struct display_timing urt_umsh_8596md_timing = {
4164 .pixelclock = { 33260000, 33260000, 33260000 },
4165 .hactive = { 800, 800, 800 },
4166 .hfront_porch = { 41, 41, 41 },
4167 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4168 .hsync_len = { 71, 128, 128 },
4169 .vactive = { 480, 480, 480 },
4170 .vfront_porch = { 10, 10, 10 },
4171 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4172 .vsync_len = { 2, 2, 2 },
4173 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4174 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4175};
4176
4177static const struct panel_desc urt_umsh_8596md_lvds = {
4178 .timings = &urt_umsh_8596md_timing,
4179 .num_timings = 1,
4180 .bpc = 6,
4181 .size = {
4182 .width = 152,
4183 .height = 91,
4184 },
4185 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4186 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4187};
4188
4189static const struct panel_desc urt_umsh_8596md_parallel = {
4190 .timings = &urt_umsh_8596md_timing,
4191 .num_timings = 1,
4192 .bpc = 6,
4193 .size = {
4194 .width = 152,
4195 .height = 91,
4196 },
4197 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4198};
4199
4200static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4201 .clock = 60000,
4202 .hdisplay = 1024,
4203 .hsync_start = 1024 + 160,
4204 .hsync_end = 1024 + 160 + 100,
4205 .htotal = 1024 + 160 + 100 + 60,
4206 .vdisplay = 600,
4207 .vsync_start = 600 + 12,
4208 .vsync_end = 600 + 12 + 10,
4209 .vtotal = 600 + 12 + 10 + 13,
4210};
4211
4212static const struct panel_desc vivax_tpc9150_panel = {
4213 .modes = &vivax_tpc9150_panel_mode,
4214 .num_modes = 1,
4215 .bpc = 6,
4216 .size = {
4217 .width = 200,
4218 .height = 115,
4219 },
4220 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4221 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4222 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4223};
4224
4225static const struct drm_display_mode vl050_8048nt_c01_mode = {
4226 .clock = 33333,
4227 .hdisplay = 800,
4228 .hsync_start = 800 + 210,
4229 .hsync_end = 800 + 210 + 20,
4230 .htotal = 800 + 210 + 20 + 46,
4231 .vdisplay = 480,
4232 .vsync_start = 480 + 22,
4233 .vsync_end = 480 + 22 + 10,
4234 .vtotal = 480 + 22 + 10 + 23,
4235 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4236};
4237
4238static const struct panel_desc vl050_8048nt_c01 = {
4239 .modes = &vl050_8048nt_c01_mode,
4240 .num_modes = 1,
4241 .bpc = 8,
4242 .size = {
4243 .width = 120,
4244 .height = 76,
4245 },
4246 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4247 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4248};
4249
4250static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4251 .clock = 6410,
4252 .hdisplay = 320,
4253 .hsync_start = 320 + 20,
4254 .hsync_end = 320 + 20 + 30,
4255 .htotal = 320 + 20 + 30 + 38,
4256 .vdisplay = 240,
4257 .vsync_start = 240 + 4,
4258 .vsync_end = 240 + 4 + 3,
4259 .vtotal = 240 + 4 + 3 + 15,
4260 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4261};
4262
4263static const struct panel_desc winstar_wf35ltiacd = {
4264 .modes = &winstar_wf35ltiacd_mode,
4265 .num_modes = 1,
4266 .bpc = 8,
4267 .size = {
4268 .width = 70,
4269 .height = 53,
4270 },
4271 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4272};
4273
4274static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4275 .clock = 51200,
4276 .hdisplay = 1024,
4277 .hsync_start = 1024 + 100,
4278 .hsync_end = 1024 + 100 + 100,
4279 .htotal = 1024 + 100 + 100 + 120,
4280 .vdisplay = 600,
4281 .vsync_start = 600 + 10,
4282 .vsync_end = 600 + 10 + 10,
4283 .vtotal = 600 + 10 + 10 + 15,
4284 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4285};
4286
4287static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4288 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4289 .num_modes = 1,
4290 .bpc = 8,
4291 .size = {
4292 .width = 154,
4293 .height = 90,
4294 },
4295 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4297 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4298};
4299
4300static const struct drm_display_mode arm_rtsm_mode[] = {
4301 {
4302 .clock = 65000,
4303 .hdisplay = 1024,
4304 .hsync_start = 1024 + 24,
4305 .hsync_end = 1024 + 24 + 136,
4306 .htotal = 1024 + 24 + 136 + 160,
4307 .vdisplay = 768,
4308 .vsync_start = 768 + 3,
4309 .vsync_end = 768 + 3 + 6,
4310 .vtotal = 768 + 3 + 6 + 29,
4311 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4312 },
4313};
4314
4315static const struct panel_desc arm_rtsm = {
4316 .modes = arm_rtsm_mode,
4317 .num_modes = 1,
4318 .bpc = 8,
4319 .size = {
4320 .width = 400,
4321 .height = 300,
4322 },
4323 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4324};
4325
4326static const struct of_device_id platform_of_match[] = {
4327 {
4328 .compatible = "ampire,am-1280800n3tzqw-t00h",
4329 .data = &ire_am_1280800n3tzqw_t00h,
4330 }, {
4331 .compatible = "ampire,am-480272h3tmqw-t01h",
4332 .data = &ire_am_480272h3tmqw_t01h,
4333 }, {
4334 .compatible = "ampire,am-800480l1tmqw-t00h",
4335 .data = &ire_am_800480l1tmqw_t00h,
4336 }, {
4337 .compatible = "ampire,am800480r3tmqwa1h",
4338 .data = &ire_am800480r3tmqwa1h,
4339 }, {
4340 .compatible = "ampire,am800600p5tmqw-tb8h",
4341 .data = &ire_am800600p5tmqwtb8h,
4342 }, {
4343 .compatible = "arm,rtsm-display",
4344 .data = &arm_rtsm,
4345 }, {
4346 .compatible = "armadeus,st0700-adapt",
4347 .data = &armadeus_st0700_adapt,
4348 }, {
4349 .compatible = "auo,b101aw03",
4350 .data = &auo_b101aw03,
4351 }, {
4352 .compatible = "auo,b101xtn01",
4353 .data = &auo_b101xtn01,
4354 }, {
4355 .compatible = "auo,b116xw03",
4356 .data = &auo_b116xw03,
4357 }, {
4358 .compatible = "auo,g070vvn01",
4359 .data = &auo_g070vvn01,
4360 }, {
4361 .compatible = "auo,g101evn010",
4362 .data = &auo_g101evn010,
4363 }, {
4364 .compatible = "auo,g104sn02",
4365 .data = &auo_g104sn02,
4366 }, {
4367 .compatible = "auo,g121ean01",
4368 .data = &auo_g121ean01,
4369 }, {
4370 .compatible = "auo,g133han01",
4371 .data = &auo_g133han01,
4372 }, {
4373 .compatible = "auo,g156han04",
4374 .data = &auo_g156han04,
4375 }, {
4376 .compatible = "auo,g156xtn01",
4377 .data = &auo_g156xtn01,
4378 }, {
4379 .compatible = "auo,g185han01",
4380 .data = &auo_g185han01,
4381 }, {
4382 .compatible = "auo,g190ean01",
4383 .data = &auo_g190ean01,
4384 }, {
4385 .compatible = "auo,p320hvn03",
4386 .data = &auo_p320hvn03,
4387 }, {
4388 .compatible = "auo,t215hvn01",
4389 .data = &auo_t215hvn01,
4390 }, {
4391 .compatible = "avic,tm070ddh03",
4392 .data = &avic_tm070ddh03,
4393 }, {
4394 .compatible = "bananapi,s070wv20-ct16",
4395 .data = &bananapi_s070wv20_ct16,
4396 }, {
4397 .compatible = "boe,bp082wx1-100",
4398 .data = &boe_bp082wx1_100,
4399 }, {
4400 .compatible = "boe,bp101wx1-100",
4401 .data = &boe_bp101wx1_100,
4402 }, {
4403 .compatible = "boe,ev121wxm-n10-1850",
4404 .data = &boe_ev121wxm_n10_1850,
4405 }, {
4406 .compatible = "boe,hv070wsa-100",
4407 .data = &boe_hv070wsa
4408 }, {
4409 .compatible = "cdtech,s043wq26h-ct7",
4410 .data = &cdtech_s043wq26h_ct7,
4411 }, {
4412 .compatible = "cdtech,s070pws19hp-fc21",
4413 .data = &cdtech_s070pws19hp_fc21,
4414 }, {
4415 .compatible = "cdtech,s070swv29hg-dc44",
4416 .data = &cdtech_s070swv29hg_dc44,
4417 }, {
4418 .compatible = "cdtech,s070wv95-ct16",
4419 .data = &cdtech_s070wv95_ct16,
4420 }, {
4421 .compatible = "chefree,ch101olhlwh-002",
4422 .data = &chefree_ch101olhlwh_002,
4423 }, {
4424 .compatible = "chunghwa,claa070wp03xg",
4425 .data = &chunghwa_claa070wp03xg,
4426 }, {
4427 .compatible = "chunghwa,claa101wa01a",
4428 .data = &chunghwa_claa101wa01a
4429 }, {
4430 .compatible = "chunghwa,claa101wb01",
4431 .data = &chunghwa_claa101wb01
4432 }, {
4433 .compatible = "dataimage,fg040346dsswbg04",
4434 .data = &dataimage_fg040346dsswbg04,
4435 }, {
4436 .compatible = "dataimage,fg1001l0dsswmg01",
4437 .data = &dataimage_fg1001l0dsswmg01,
4438 }, {
4439 .compatible = "dataimage,scf0700c48ggu18",
4440 .data = &dataimage_scf0700c48ggu18,
4441 }, {
4442 .compatible = "dlc,dlc0700yzg-1",
4443 .data = &dlc_dlc0700yzg_1,
4444 }, {
4445 .compatible = "dlc,dlc1010gig",
4446 .data = &dlc_dlc1010gig,
4447 }, {
4448 .compatible = "edt,et035012dm6",
4449 .data = &edt_et035012dm6,
4450 }, {
4451 .compatible = "edt,etm0350g0dh6",
4452 .data = &edt_etm0350g0dh6,
4453 }, {
4454 .compatible = "edt,etm043080dh6gp",
4455 .data = &edt_etm043080dh6gp,
4456 }, {
4457 .compatible = "edt,etm0430g0dh6",
4458 .data = &edt_etm0430g0dh6,
4459 }, {
4460 .compatible = "edt,et057090dhu",
4461 .data = &edt_et057090dhu,
4462 }, {
4463 .compatible = "edt,et070080dh6",
4464 .data = &edt_etm0700g0dh6,
4465 }, {
4466 .compatible = "edt,etm0700g0dh6",
4467 .data = &edt_etm0700g0dh6,
4468 }, {
4469 .compatible = "edt,etm0700g0bdh6",
4470 .data = &edt_etm0700g0bdh6,
4471 }, {
4472 .compatible = "edt,etm0700g0edh6",
4473 .data = &edt_etm0700g0bdh6,
4474 }, {
4475 .compatible = "edt,etml0700y5dha",
4476 .data = &edt_etml0700y5dha,
4477 }, {
4478 .compatible = "edt,etml1010g3dra",
4479 .data = &edt_etml1010g3dra,
4480 }, {
4481 .compatible = "edt,etmv570g2dhu",
4482 .data = &edt_etmv570g2dhu,
4483 }, {
4484 .compatible = "eink,vb3300-kca",
4485 .data = &eink_vb3300_kca,
4486 }, {
4487 .compatible = "evervision,vgg644804",
4488 .data = &evervision_vgg644804,
4489 }, {
4490 .compatible = "evervision,vgg804821",
4491 .data = &evervision_vgg804821,
4492 }, {
4493 .compatible = "foxlink,fl500wvr00-a0t",
4494 .data = &foxlink_fl500wvr00_a0t,
4495 }, {
4496 .compatible = "frida,frd350h54004",
4497 .data = &frida_frd350h54004,
4498 }, {
4499 .compatible = "friendlyarm,hd702e",
4500 .data = &friendlyarm_hd702e,
4501 }, {
4502 .compatible = "giantplus,gpg482739qs5",
4503 .data = &giantplus_gpg482739qs5
4504 }, {
4505 .compatible = "giantplus,gpm940b0",
4506 .data = &giantplus_gpm940b0,
4507 }, {
4508 .compatible = "hannstar,hsd070pww1",
4509 .data = &hannstar_hsd070pww1,
4510 }, {
4511 .compatible = "hannstar,hsd100pxn1",
4512 .data = &hannstar_hsd100pxn1,
4513 }, {
4514 .compatible = "hannstar,hsd101pww2",
4515 .data = &hannstar_hsd101pww2,
4516 }, {
4517 .compatible = "hit,tx23d38vm0caa",
4518 .data = &hitachi_tx23d38vm0caa
4519 }, {
4520 .compatible = "innolux,at043tn24",
4521 .data = &innolux_at043tn24,
4522 }, {
4523 .compatible = "innolux,at070tn92",
4524 .data = &innolux_at070tn92,
4525 }, {
4526 .compatible = "innolux,g070ace-l01",
4527 .data = &innolux_g070ace_l01,
4528 }, {
4529 .compatible = "innolux,g070y2-l01",
4530 .data = &innolux_g070y2_l01,
4531 }, {
4532 .compatible = "innolux,g070y2-t02",
4533 .data = &innolux_g070y2_t02,
4534 }, {
4535 .compatible = "innolux,g101ice-l01",
4536 .data = &innolux_g101ice_l01
4537 }, {
4538 .compatible = "innolux,g121i1-l01",
4539 .data = &innolux_g121i1_l01
4540 }, {
4541 .compatible = "innolux,g121x1-l03",
4542 .data = &innolux_g121x1_l03,
4543 }, {
4544 .compatible = "innolux,g156hce-l01",
4545 .data = &innolux_g156hce_l01,
4546 }, {
4547 .compatible = "innolux,n156bge-l21",
4548 .data = &innolux_n156bge_l21,
4549 }, {
4550 .compatible = "innolux,zj070na-01p",
4551 .data = &innolux_zj070na_01p,
4552 }, {
4553 .compatible = "koe,tx14d24vm1bpa",
4554 .data = &koe_tx14d24vm1bpa,
4555 }, {
4556 .compatible = "koe,tx26d202vm0bwa",
4557 .data = &koe_tx26d202vm0bwa,
4558 }, {
4559 .compatible = "koe,tx31d200vm0baa",
4560 .data = &koe_tx31d200vm0baa,
4561 }, {
4562 .compatible = "kyo,tcg121xglp",
4563 .data = &kyo_tcg121xglp,
4564 }, {
4565 .compatible = "lemaker,bl035-rgb-002",
4566 .data = &lemaker_bl035_rgb_002,
4567 }, {
4568 .compatible = "lg,lb070wv8",
4569 .data = &lg_lb070wv8,
4570 }, {
4571 .compatible = "logicpd,type28",
4572 .data = &logicpd_type_28,
4573 }, {
4574 .compatible = "logictechno,lt161010-2nhc",
4575 .data = &logictechno_lt161010_2nh,
4576 }, {
4577 .compatible = "logictechno,lt161010-2nhr",
4578 .data = &logictechno_lt161010_2nh,
4579 }, {
4580 .compatible = "logictechno,lt170410-2whc",
4581 .data = &logictechno_lt170410_2whc,
4582 }, {
4583 .compatible = "logictechno,lttd800480070-l2rt",
4584 .data = &logictechno_lttd800480070_l2rt,
4585 }, {
4586 .compatible = "logictechno,lttd800480070-l6wh-rt",
4587 .data = &logictechno_lttd800480070_l6wh_rt,
4588 }, {
4589 .compatible = "mitsubishi,aa070mc01-ca1",
4590 .data = &mitsubishi_aa070mc01,
4591 }, {
4592 .compatible = "mitsubishi,aa084xe01",
4593 .data = &mitsubishi_aa084xe01,
4594 }, {
4595 .compatible = "multi-inno,mi0700s4t-6",
4596 .data = &multi_inno_mi0700s4t_6,
4597 }, {
4598 .compatible = "multi-inno,mi0800ft-9",
4599 .data = &multi_inno_mi0800ft_9,
4600 }, {
4601 .compatible = "multi-inno,mi1010ait-1cp",
4602 .data = &multi_inno_mi1010ait_1cp,
4603 }, {
4604 .compatible = "nec,nl12880bc20-05",
4605 .data = &nec_nl12880bc20_05,
4606 }, {
4607 .compatible = "nec,nl4827hc19-05b",
4608 .data = &nec_nl4827hc19_05b,
4609 }, {
4610 .compatible = "netron-dy,e231732",
4611 .data = &netron_dy_e231732,
4612 }, {
4613 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4614 .data = &newhaven_nhd_43_480272ef_atxl,
4615 }, {
4616 .compatible = "nlt,nl192108ac18-02d",
4617 .data = &nlt_nl192108ac18_02d,
4618 }, {
4619 .compatible = "nvd,9128",
4620 .data = &nvd_9128,
4621 }, {
4622 .compatible = "okaya,rs800480t-7x0gp",
4623 .data = &okaya_rs800480t_7x0gp,
4624 }, {
4625 .compatible = "olimex,lcd-olinuxino-43-ts",
4626 .data = &olimex_lcd_olinuxino_43ts,
4627 }, {
4628 .compatible = "ontat,yx700wv03",
4629 .data = &ontat_yx700wv03,
4630 }, {
4631 .compatible = "ortustech,com37h3m05dtc",
4632 .data = &ortustech_com37h3m,
4633 }, {
4634 .compatible = "ortustech,com37h3m99dtc",
4635 .data = &ortustech_com37h3m,
4636 }, {
4637 .compatible = "ortustech,com43h4m85ulc",
4638 .data = &ortustech_com43h4m85ulc,
4639 }, {
4640 .compatible = "osddisplays,osd070t1718-19ts",
4641 .data = &osddisplays_osd070t1718_19ts,
4642 }, {
4643 .compatible = "pda,91-00156-a0",
4644 .data = &pda_91_00156_a0,
4645 }, {
4646 .compatible = "powertip,ph800480t013-idf02",
4647 .data = &powertip_ph800480t013_idf02,
4648 }, {
4649 .compatible = "qiaodian,qd43003c0-40",
4650 .data = &qd43003c0_40,
4651 }, {
4652 .compatible = "qishenglong,gopher2b-lcd",
4653 .data = &qishenglong_gopher2b_lcd,
4654 }, {
4655 .compatible = "rocktech,rk043fn48h",
4656 .data = &rocktech_rk043fn48h,
4657 }, {
4658 .compatible = "rocktech,rk070er9427",
4659 .data = &rocktech_rk070er9427,
4660 }, {
4661 .compatible = "rocktech,rk101ii01d-ct",
4662 .data = &rocktech_rk101ii01d_ct,
4663 }, {
4664 .compatible = "samsung,ltl101al01",
4665 .data = &samsung_ltl101al01,
4666 }, {
4667 .compatible = "samsung,ltn101nt05",
4668 .data = &samsung_ltn101nt05,
4669 }, {
4670 .compatible = "satoz,sat050at40h12r2",
4671 .data = &satoz_sat050at40h12r2,
4672 }, {
4673 .compatible = "sharp,lq035q7db03",
4674 .data = &sharp_lq035q7db03,
4675 }, {
4676 .compatible = "sharp,lq070y3dg3b",
4677 .data = &sharp_lq070y3dg3b,
4678 }, {
4679 .compatible = "sharp,lq101k1ly04",
4680 .data = &sharp_lq101k1ly04,
4681 }, {
4682 .compatible = "sharp,ls020b1dd01d",
4683 .data = &sharp_ls020b1dd01d,
4684 }, {
4685 .compatible = "shelly,sca07010-bfn-lnn",
4686 .data = &shelly_sca07010_bfn_lnn,
4687 }, {
4688 .compatible = "starry,kr070pe2t",
4689 .data = &starry_kr070pe2t,
4690 }, {
4691 .compatible = "startek,kd070wvfpa",
4692 .data = &startek_kd070wvfpa,
4693 }, {
4694 .compatible = "team-source-display,tst043015cmhx",
4695 .data = &tsd_tst043015cmhx,
4696 }, {
4697 .compatible = "tfc,s9700rtwv43tr-01b",
4698 .data = &tfc_s9700rtwv43tr_01b,
4699 }, {
4700 .compatible = "tianma,tm070jdhg30",
4701 .data = &tianma_tm070jdhg30,
4702 }, {
4703 .compatible = "tianma,tm070jvhg33",
4704 .data = &tianma_tm070jvhg33,
4705 }, {
4706 .compatible = "tianma,tm070rvhg71",
4707 .data = &tianma_tm070rvhg71,
4708 }, {
4709 .compatible = "ti,nspire-cx-lcd-panel",
4710 .data = &ti_nspire_cx_lcd_panel,
4711 }, {
4712 .compatible = "ti,nspire-classic-lcd-panel",
4713 .data = &ti_nspire_classic_lcd_panel,
4714 }, {
4715 .compatible = "toshiba,lt089ac29000",
4716 .data = &toshiba_lt089ac29000,
4717 }, {
4718 .compatible = "tpk,f07a-0102",
4719 .data = &tpk_f07a_0102,
4720 }, {
4721 .compatible = "tpk,f10a-0102",
4722 .data = &tpk_f10a_0102,
4723 }, {
4724 .compatible = "urt,umsh-8596md-t",
4725 .data = &urt_umsh_8596md_parallel,
4726 }, {
4727 .compatible = "urt,umsh-8596md-1t",
4728 .data = &urt_umsh_8596md_parallel,
4729 }, {
4730 .compatible = "urt,umsh-8596md-7t",
4731 .data = &urt_umsh_8596md_parallel,
4732 }, {
4733 .compatible = "urt,umsh-8596md-11t",
4734 .data = &urt_umsh_8596md_lvds,
4735 }, {
4736 .compatible = "urt,umsh-8596md-19t",
4737 .data = &urt_umsh_8596md_lvds,
4738 }, {
4739 .compatible = "urt,umsh-8596md-20t",
4740 .data = &urt_umsh_8596md_parallel,
4741 }, {
4742 .compatible = "vivax,tpc9150-panel",
4743 .data = &vivax_tpc9150_panel,
4744 }, {
4745 .compatible = "vxt,vl050-8048nt-c01",
4746 .data = &vl050_8048nt_c01,
4747 }, {
4748 .compatible = "winstar,wf35ltiacd",
4749 .data = &winstar_wf35ltiacd,
4750 }, {
4751 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4752 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4753 }, {
4754 /* Must be the last entry */
4755 .compatible = "panel-dpi",
4756 .data = &panel_dpi,
4757 }, {
4758 /* sentinel */
4759 }
4760};
4761MODULE_DEVICE_TABLE(of, platform_of_match);
4762
4763static int panel_simple_platform_probe(struct platform_device *pdev)
4764{
4765 const struct panel_desc *desc;
4766
4767 desc = of_device_get_match_data(&pdev->dev);
4768 if (!desc)
4769 return -ENODEV;
4770
4771 return panel_simple_probe(&pdev->dev, desc);
4772}
4773
4774static void panel_simple_platform_remove(struct platform_device *pdev)
4775{
4776 panel_simple_remove(&pdev->dev);
4777}
4778
4779static void panel_simple_platform_shutdown(struct platform_device *pdev)
4780{
4781 panel_simple_shutdown(&pdev->dev);
4782}
4783
4784static const struct dev_pm_ops panel_simple_pm_ops = {
4785 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4786 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4787 pm_runtime_force_resume)
4788};
4789
4790static struct platform_driver panel_simple_platform_driver = {
4791 .driver = {
4792 .name = "panel-simple",
4793 .of_match_table = platform_of_match,
4794 .pm = &panel_simple_pm_ops,
4795 },
4796 .probe = panel_simple_platform_probe,
4797 .remove_new = panel_simple_platform_remove,
4798 .shutdown = panel_simple_platform_shutdown,
4799};
4800
4801struct panel_desc_dsi {
4802 struct panel_desc desc;
4803
4804 unsigned long flags;
4805 enum mipi_dsi_pixel_format format;
4806 unsigned int lanes;
4807};
4808
4809static const struct drm_display_mode auo_b080uan01_mode = {
4810 .clock = 154500,
4811 .hdisplay = 1200,
4812 .hsync_start = 1200 + 62,
4813 .hsync_end = 1200 + 62 + 4,
4814 .htotal = 1200 + 62 + 4 + 62,
4815 .vdisplay = 1920,
4816 .vsync_start = 1920 + 9,
4817 .vsync_end = 1920 + 9 + 2,
4818 .vtotal = 1920 + 9 + 2 + 8,
4819};
4820
4821static const struct panel_desc_dsi auo_b080uan01 = {
4822 .desc = {
4823 .modes = &auo_b080uan01_mode,
4824 .num_modes = 1,
4825 .bpc = 8,
4826 .size = {
4827 .width = 108,
4828 .height = 272,
4829 },
4830 .connector_type = DRM_MODE_CONNECTOR_DSI,
4831 },
4832 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4833 .format = MIPI_DSI_FMT_RGB888,
4834 .lanes = 4,
4835};
4836
4837static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4838 .clock = 160000,
4839 .hdisplay = 1200,
4840 .hsync_start = 1200 + 120,
4841 .hsync_end = 1200 + 120 + 20,
4842 .htotal = 1200 + 120 + 20 + 21,
4843 .vdisplay = 1920,
4844 .vsync_start = 1920 + 21,
4845 .vsync_end = 1920 + 21 + 3,
4846 .vtotal = 1920 + 21 + 3 + 18,
4847 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4848};
4849
4850static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4851 .desc = {
4852 .modes = &boe_tv080wum_nl0_mode,
4853 .num_modes = 1,
4854 .size = {
4855 .width = 107,
4856 .height = 172,
4857 },
4858 .connector_type = DRM_MODE_CONNECTOR_DSI,
4859 },
4860 .flags = MIPI_DSI_MODE_VIDEO |
4861 MIPI_DSI_MODE_VIDEO_BURST |
4862 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4863 .format = MIPI_DSI_FMT_RGB888,
4864 .lanes = 4,
4865};
4866
4867static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4868 .clock = 71000,
4869 .hdisplay = 800,
4870 .hsync_start = 800 + 32,
4871 .hsync_end = 800 + 32 + 1,
4872 .htotal = 800 + 32 + 1 + 57,
4873 .vdisplay = 1280,
4874 .vsync_start = 1280 + 28,
4875 .vsync_end = 1280 + 28 + 1,
4876 .vtotal = 1280 + 28 + 1 + 14,
4877};
4878
4879static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4880 .desc = {
4881 .modes = &lg_ld070wx3_sl01_mode,
4882 .num_modes = 1,
4883 .bpc = 8,
4884 .size = {
4885 .width = 94,
4886 .height = 151,
4887 },
4888 .connector_type = DRM_MODE_CONNECTOR_DSI,
4889 },
4890 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4891 .format = MIPI_DSI_FMT_RGB888,
4892 .lanes = 4,
4893};
4894
4895static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4896 .clock = 67000,
4897 .hdisplay = 720,
4898 .hsync_start = 720 + 12,
4899 .hsync_end = 720 + 12 + 4,
4900 .htotal = 720 + 12 + 4 + 112,
4901 .vdisplay = 1280,
4902 .vsync_start = 1280 + 8,
4903 .vsync_end = 1280 + 8 + 4,
4904 .vtotal = 1280 + 8 + 4 + 12,
4905};
4906
4907static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4908 .desc = {
4909 .modes = &lg_lh500wx1_sd03_mode,
4910 .num_modes = 1,
4911 .bpc = 8,
4912 .size = {
4913 .width = 62,
4914 .height = 110,
4915 },
4916 .connector_type = DRM_MODE_CONNECTOR_DSI,
4917 },
4918 .flags = MIPI_DSI_MODE_VIDEO,
4919 .format = MIPI_DSI_FMT_RGB888,
4920 .lanes = 4,
4921};
4922
4923static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4924 .clock = 157200,
4925 .hdisplay = 1920,
4926 .hsync_start = 1920 + 154,
4927 .hsync_end = 1920 + 154 + 16,
4928 .htotal = 1920 + 154 + 16 + 32,
4929 .vdisplay = 1200,
4930 .vsync_start = 1200 + 17,
4931 .vsync_end = 1200 + 17 + 2,
4932 .vtotal = 1200 + 17 + 2 + 16,
4933};
4934
4935static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4936 .desc = {
4937 .modes = &panasonic_vvx10f004b00_mode,
4938 .num_modes = 1,
4939 .bpc = 8,
4940 .size = {
4941 .width = 217,
4942 .height = 136,
4943 },
4944 .connector_type = DRM_MODE_CONNECTOR_DSI,
4945 },
4946 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4947 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4948 .format = MIPI_DSI_FMT_RGB888,
4949 .lanes = 4,
4950};
4951
4952static const struct drm_display_mode lg_acx467akm_7_mode = {
4953 .clock = 150000,
4954 .hdisplay = 1080,
4955 .hsync_start = 1080 + 2,
4956 .hsync_end = 1080 + 2 + 2,
4957 .htotal = 1080 + 2 + 2 + 2,
4958 .vdisplay = 1920,
4959 .vsync_start = 1920 + 2,
4960 .vsync_end = 1920 + 2 + 2,
4961 .vtotal = 1920 + 2 + 2 + 2,
4962};
4963
4964static const struct panel_desc_dsi lg_acx467akm_7 = {
4965 .desc = {
4966 .modes = &lg_acx467akm_7_mode,
4967 .num_modes = 1,
4968 .bpc = 8,
4969 .size = {
4970 .width = 62,
4971 .height = 110,
4972 },
4973 .connector_type = DRM_MODE_CONNECTOR_DSI,
4974 },
4975 .flags = 0,
4976 .format = MIPI_DSI_FMT_RGB888,
4977 .lanes = 4,
4978};
4979
4980static const struct drm_display_mode osd101t2045_53ts_mode = {
4981 .clock = 154500,
4982 .hdisplay = 1920,
4983 .hsync_start = 1920 + 112,
4984 .hsync_end = 1920 + 112 + 16,
4985 .htotal = 1920 + 112 + 16 + 32,
4986 .vdisplay = 1200,
4987 .vsync_start = 1200 + 16,
4988 .vsync_end = 1200 + 16 + 2,
4989 .vtotal = 1200 + 16 + 2 + 16,
4990 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4991};
4992
4993static const struct panel_desc_dsi osd101t2045_53ts = {
4994 .desc = {
4995 .modes = &osd101t2045_53ts_mode,
4996 .num_modes = 1,
4997 .bpc = 8,
4998 .size = {
4999 .width = 217,
5000 .height = 136,
5001 },
5002 .connector_type = DRM_MODE_CONNECTOR_DSI,
5003 },
5004 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5005 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5006 MIPI_DSI_MODE_NO_EOT_PACKET,
5007 .format = MIPI_DSI_FMT_RGB888,
5008 .lanes = 4,
5009};
5010
5011static const struct of_device_id dsi_of_match[] = {
5012 {
5013 .compatible = "auo,b080uan01",
5014 .data = &auo_b080uan01
5015 }, {
5016 .compatible = "boe,tv080wum-nl0",
5017 .data = &boe_tv080wum_nl0
5018 }, {
5019 .compatible = "lg,ld070wx3-sl01",
5020 .data = &lg_ld070wx3_sl01
5021 }, {
5022 .compatible = "lg,lh500wx1-sd03",
5023 .data = &lg_lh500wx1_sd03
5024 }, {
5025 .compatible = "panasonic,vvx10f004b00",
5026 .data = &panasonic_vvx10f004b00
5027 }, {
5028 .compatible = "lg,acx467akm-7",
5029 .data = &lg_acx467akm_7
5030 }, {
5031 .compatible = "osddisplays,osd101t2045-53ts",
5032 .data = &osd101t2045_53ts
5033 }, {
5034 /* sentinel */
5035 }
5036};
5037MODULE_DEVICE_TABLE(of, dsi_of_match);
5038
5039static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5040{
5041 const struct panel_desc_dsi *desc;
5042 int err;
5043
5044 desc = of_device_get_match_data(&dsi->dev);
5045 if (!desc)
5046 return -ENODEV;
5047
5048 err = panel_simple_probe(&dsi->dev, &desc->desc);
5049 if (err < 0)
5050 return err;
5051
5052 dsi->mode_flags = desc->flags;
5053 dsi->format = desc->format;
5054 dsi->lanes = desc->lanes;
5055
5056 err = mipi_dsi_attach(dsi);
5057 if (err) {
5058 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
5059
5060 drm_panel_remove(&panel->base);
5061 }
5062
5063 return err;
5064}
5065
5066static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5067{
5068 int err;
5069
5070 err = mipi_dsi_detach(dsi);
5071 if (err < 0)
5072 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5073
5074 panel_simple_remove(&dsi->dev);
5075}
5076
5077static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5078{
5079 panel_simple_shutdown(&dsi->dev);
5080}
5081
5082static struct mipi_dsi_driver panel_simple_dsi_driver = {
5083 .driver = {
5084 .name = "panel-simple-dsi",
5085 .of_match_table = dsi_of_match,
5086 .pm = &panel_simple_pm_ops,
5087 },
5088 .probe = panel_simple_dsi_probe,
5089 .remove = panel_simple_dsi_remove,
5090 .shutdown = panel_simple_dsi_shutdown,
5091};
5092
5093static int __init panel_simple_init(void)
5094{
5095 int err;
5096
5097 err = platform_driver_register(&panel_simple_platform_driver);
5098 if (err < 0)
5099 return err;
5100
5101 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5102 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5103 if (err < 0)
5104 goto err_did_platform_register;
5105 }
5106
5107 return 0;
5108
5109err_did_platform_register:
5110 platform_driver_unregister(&panel_simple_platform_driver);
5111
5112 return err;
5113}
5114module_init(panel_simple_init);
5115
5116static void __exit panel_simple_exit(void)
5117{
5118 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5119 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5120
5121 platform_driver_unregister(&panel_simple_platform_driver);
5122}
5123module_exit(panel_simple_exit);
5124
5125MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5126MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5127MODULE_LICENSE("GPL and additional rights");