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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include <drm/drm_device.h>
7#include <linux/sysfs.h>
8#include <linux/printk.h>
9
10#include "i915_drv.h"
11#include "i915_reg.h"
12#include "i915_sysfs.h"
13#include "intel_gt.h"
14#include "intel_gt_print.h"
15#include "intel_gt_regs.h"
16#include "intel_gt_sysfs.h"
17#include "intel_gt_sysfs_pm.h"
18#include "intel_pcode.h"
19#include "intel_rc6.h"
20#include "intel_rps.h"
21
22enum intel_gt_sysfs_op {
23 INTEL_GT_SYSFS_MIN = 0,
24 INTEL_GT_SYSFS_MAX,
25};
26
27static int
28sysfs_gt_attribute_w_func(struct kobject *kobj, struct attribute *attr,
29 int (func)(struct intel_gt *gt, u32 val), u32 val)
30{
31 struct intel_gt *gt;
32 int ret;
33
34 if (!is_object_gt(kobj)) {
35 int i;
36 struct device *dev = kobj_to_dev(kobj);
37 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
38
39 for_each_gt(gt, i915, i) {
40 ret = func(gt, val);
41 if (ret)
42 break;
43 }
44 } else {
45 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
46 ret = func(gt, val);
47 }
48
49 return ret;
50}
51
52static u32
53sysfs_gt_attribute_r_func(struct kobject *kobj, struct attribute *attr,
54 u32 (func)(struct intel_gt *gt),
55 enum intel_gt_sysfs_op op)
56{
57 struct intel_gt *gt;
58 u32 ret;
59
60 ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
61
62 if (!is_object_gt(kobj)) {
63 int i;
64 struct device *dev = kobj_to_dev(kobj);
65 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
66
67 for_each_gt(gt, i915, i) {
68 u32 val = func(gt);
69
70 switch (op) {
71 case INTEL_GT_SYSFS_MIN:
72 if (val < ret)
73 ret = val;
74 break;
75
76 case INTEL_GT_SYSFS_MAX:
77 if (val > ret)
78 ret = val;
79 break;
80 }
81 }
82 } else {
83 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
84 ret = func(gt);
85 }
86
87 return ret;
88}
89
90/* RC6 interfaces will show the minimum RC6 residency value */
91#define sysfs_gt_attribute_r_min_func(d, a, f) \
92 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
93
94/* Frequency interfaces will show the maximum frequency value */
95#define sysfs_gt_attribute_r_max_func(d, a, f) \
96 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
97
98#define INTEL_GT_SYSFS_SHOW(_name, _attr_type) \
99 static ssize_t _name##_show_common(struct kobject *kobj, \
100 struct attribute *attr, char *buff) \
101 { \
102 u32 val = sysfs_gt_attribute_r_##_attr_type##_func(kobj, attr, \
103 __##_name##_show); \
104 \
105 return sysfs_emit(buff, "%u\n", val); \
106 } \
107 static ssize_t _name##_show(struct kobject *kobj, \
108 struct kobj_attribute *attr, char *buff) \
109 { \
110 return _name ##_show_common(kobj, &attr->attr, buff); \
111 } \
112 static ssize_t _name##_dev_show(struct device *dev, \
113 struct device_attribute *attr, char *buff) \
114 { \
115 return _name##_show_common(&dev->kobj, &attr->attr, buff); \
116 }
117
118#define INTEL_GT_SYSFS_STORE(_name, _func) \
119 static ssize_t _name##_store_common(struct kobject *kobj, \
120 struct attribute *attr, \
121 const char *buff, size_t count) \
122 { \
123 int ret; \
124 u32 val; \
125 \
126 ret = kstrtou32(buff, 0, &val); \
127 if (ret) \
128 return ret; \
129 \
130 ret = sysfs_gt_attribute_w_func(kobj, attr, _func, val); \
131 \
132 return ret ?: count; \
133 } \
134 static ssize_t _name##_store(struct kobject *kobj, \
135 struct kobj_attribute *attr, const char *buff, \
136 size_t count) \
137 { \
138 return _name##_store_common(kobj, &attr->attr, buff, count); \
139 } \
140 static ssize_t _name##_dev_store(struct device *dev, \
141 struct device_attribute *attr, \
142 const char *buff, size_t count) \
143 { \
144 return _name##_store_common(&dev->kobj, &attr->attr, buff, count); \
145 }
146
147#define INTEL_GT_SYSFS_SHOW_MAX(_name) INTEL_GT_SYSFS_SHOW(_name, max)
148#define INTEL_GT_SYSFS_SHOW_MIN(_name) INTEL_GT_SYSFS_SHOW(_name, min)
149
150#define INTEL_GT_ATTR_RW(_name) \
151 static struct kobj_attribute attr_##_name = __ATTR_RW(_name)
152
153#define INTEL_GT_ATTR_RO(_name) \
154 static struct kobj_attribute attr_##_name = __ATTR_RO(_name)
155
156#define INTEL_GT_DUAL_ATTR_RW(_name) \
157 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0644, \
158 _name##_dev_show, \
159 _name##_dev_store); \
160 INTEL_GT_ATTR_RW(_name)
161
162#define INTEL_GT_DUAL_ATTR_RO(_name) \
163 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0444, \
164 _name##_dev_show, \
165 NULL); \
166 INTEL_GT_ATTR_RO(_name)
167
168static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
169{
170 intel_wakeref_t wakeref;
171 u64 res = 0;
172
173 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
174 res = intel_rc6_residency_us(>->rc6, id);
175
176 return DIV_ROUND_CLOSEST_ULL(res, 1000);
177}
178
179static ssize_t rc6_enable_show(struct kobject *kobj,
180 struct kobj_attribute *attr,
181 char *buff)
182{
183 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
184
185 return sysfs_emit(buff, "%x\n", gt->rc6.enabled);
186}
187
188static ssize_t rc6_enable_dev_show(struct device *dev,
189 struct device_attribute *attr,
190 char *buff)
191{
192 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(&dev->kobj, attr->attr.name);
193
194 return sysfs_emit(buff, "%x\n", gt->rc6.enabled);
195}
196
197static u32 __rc6_residency_ms_show(struct intel_gt *gt)
198{
199 return get_residency(gt, INTEL_RC6_RES_RC6);
200}
201
202static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
203{
204 return get_residency(gt, INTEL_RC6_RES_RC6p);
205}
206
207static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
208{
209 return get_residency(gt, INTEL_RC6_RES_RC6pp);
210}
211
212static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
213{
214 return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
215}
216
217INTEL_GT_SYSFS_SHOW_MIN(rc6_residency_ms);
218INTEL_GT_SYSFS_SHOW_MIN(rc6p_residency_ms);
219INTEL_GT_SYSFS_SHOW_MIN(rc6pp_residency_ms);
220INTEL_GT_SYSFS_SHOW_MIN(media_rc6_residency_ms);
221
222INTEL_GT_DUAL_ATTR_RO(rc6_enable);
223INTEL_GT_DUAL_ATTR_RO(rc6_residency_ms);
224INTEL_GT_DUAL_ATTR_RO(rc6p_residency_ms);
225INTEL_GT_DUAL_ATTR_RO(rc6pp_residency_ms);
226INTEL_GT_DUAL_ATTR_RO(media_rc6_residency_ms);
227
228static struct attribute *rc6_attrs[] = {
229 &attr_rc6_enable.attr,
230 &attr_rc6_residency_ms.attr,
231 NULL
232};
233
234static struct attribute *rc6p_attrs[] = {
235 &attr_rc6p_residency_ms.attr,
236 &attr_rc6pp_residency_ms.attr,
237 NULL
238};
239
240static struct attribute *media_rc6_attrs[] = {
241 &attr_media_rc6_residency_ms.attr,
242 NULL
243};
244
245static struct attribute *rc6_dev_attrs[] = {
246 &dev_attr_rc6_enable.attr,
247 &dev_attr_rc6_residency_ms.attr,
248 NULL
249};
250
251static struct attribute *rc6p_dev_attrs[] = {
252 &dev_attr_rc6p_residency_ms.attr,
253 &dev_attr_rc6pp_residency_ms.attr,
254 NULL
255};
256
257static struct attribute *media_rc6_dev_attrs[] = {
258 &dev_attr_media_rc6_residency_ms.attr,
259 NULL
260};
261
262static const struct attribute_group rc6_attr_group[] = {
263 { .attrs = rc6_attrs, },
264 { .name = power_group_name, .attrs = rc6_dev_attrs, },
265};
266
267static const struct attribute_group rc6p_attr_group[] = {
268 { .attrs = rc6p_attrs, },
269 { .name = power_group_name, .attrs = rc6p_dev_attrs, },
270};
271
272static const struct attribute_group media_rc6_attr_group[] = {
273 { .attrs = media_rc6_attrs, },
274 { .name = power_group_name, .attrs = media_rc6_dev_attrs, },
275};
276
277static int __intel_gt_sysfs_create_group(struct kobject *kobj,
278 const struct attribute_group *grp)
279{
280 return is_object_gt(kobj) ?
281 sysfs_create_group(kobj, &grp[0]) :
282 sysfs_merge_group(kobj, &grp[1]);
283}
284
285static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
286{
287 int ret;
288
289 if (!IS_ENABLED(CONFIG_PM) || !HAS_RC6(gt->i915))
290 return;
291
292 ret = __intel_gt_sysfs_create_group(kobj, rc6_attr_group);
293 if (ret)
294 gt_warn(gt, "failed to create RC6 sysfs files (%pe)\n", ERR_PTR(ret));
295
296 /*
297 * cannot use the is_visible() attribute because
298 * the upper object inherits from the parent group.
299 */
300 if (HAS_RC6p(gt->i915)) {
301 ret = __intel_gt_sysfs_create_group(kobj, rc6p_attr_group);
302 if (ret)
303 gt_warn(gt, "failed to create RC6p sysfs files (%pe)\n", ERR_PTR(ret));
304 }
305
306 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
307 ret = __intel_gt_sysfs_create_group(kobj, media_rc6_attr_group);
308 if (ret)
309 gt_warn(gt, "failed to create media RC6 sysfs files (%pe)\n", ERR_PTR(ret));
310 }
311}
312
313static u32 __act_freq_mhz_show(struct intel_gt *gt)
314{
315 return intel_rps_read_actual_frequency(>->rps);
316}
317
318static u32 __cur_freq_mhz_show(struct intel_gt *gt)
319{
320 return intel_rps_get_requested_frequency(>->rps);
321}
322
323static u32 __boost_freq_mhz_show(struct intel_gt *gt)
324{
325 return intel_rps_get_boost_frequency(>->rps);
326}
327
328static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
329{
330 return intel_rps_set_boost_frequency(>->rps, val);
331}
332
333static u32 __RP0_freq_mhz_show(struct intel_gt *gt)
334{
335 return intel_rps_get_rp0_frequency(>->rps);
336}
337
338static u32 __RPn_freq_mhz_show(struct intel_gt *gt)
339{
340 return intel_rps_get_rpn_frequency(>->rps);
341}
342
343static u32 __RP1_freq_mhz_show(struct intel_gt *gt)
344{
345 return intel_rps_get_rp1_frequency(>->rps);
346}
347
348static u32 __max_freq_mhz_show(struct intel_gt *gt)
349{
350 return intel_rps_get_max_frequency(>->rps);
351}
352
353static int __set_max_freq(struct intel_gt *gt, u32 val)
354{
355 return intel_rps_set_max_frequency(>->rps, val);
356}
357
358static u32 __min_freq_mhz_show(struct intel_gt *gt)
359{
360 return intel_rps_get_min_frequency(>->rps);
361}
362
363static int __set_min_freq(struct intel_gt *gt, u32 val)
364{
365 return intel_rps_set_min_frequency(>->rps, val);
366}
367
368static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)
369{
370 struct intel_rps *rps = >->rps;
371
372 return intel_gpu_freq(rps, rps->efficient_freq);
373}
374
375INTEL_GT_SYSFS_SHOW_MAX(act_freq_mhz);
376INTEL_GT_SYSFS_SHOW_MAX(boost_freq_mhz);
377INTEL_GT_SYSFS_SHOW_MAX(cur_freq_mhz);
378INTEL_GT_SYSFS_SHOW_MAX(RP0_freq_mhz);
379INTEL_GT_SYSFS_SHOW_MAX(RP1_freq_mhz);
380INTEL_GT_SYSFS_SHOW_MAX(RPn_freq_mhz);
381INTEL_GT_SYSFS_SHOW_MAX(max_freq_mhz);
382INTEL_GT_SYSFS_SHOW_MIN(min_freq_mhz);
383INTEL_GT_SYSFS_SHOW_MAX(vlv_rpe_freq_mhz);
384INTEL_GT_SYSFS_STORE(boost_freq_mhz, __boost_freq_mhz_store);
385INTEL_GT_SYSFS_STORE(max_freq_mhz, __set_max_freq);
386INTEL_GT_SYSFS_STORE(min_freq_mhz, __set_min_freq);
387
388#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store, _show_dev, _store_dev) \
389 static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, \
390 _show_dev, _store_dev); \
391 static struct kobj_attribute attr_rps_##_name = __ATTR(rps_##_name, _mode, \
392 _show, _store)
393
394#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
395 INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL, \
396 _name##_dev_show, NULL)
397#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
398 INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store, \
399 _name##_dev_show, _name##_dev_store)
400
401/* The below macros generate static structures */
402INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
403INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
404INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
405INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
406INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
407INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
408INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
409INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
410INTEL_GT_RPS_SYSFS_ATTR_RO(vlv_rpe_freq_mhz);
411
412#define GEN6_ATTR(p, s) { \
413 &p##attr_##s##_act_freq_mhz.attr, \
414 &p##attr_##s##_cur_freq_mhz.attr, \
415 &p##attr_##s##_boost_freq_mhz.attr, \
416 &p##attr_##s##_max_freq_mhz.attr, \
417 &p##attr_##s##_min_freq_mhz.attr, \
418 &p##attr_##s##_RP0_freq_mhz.attr, \
419 &p##attr_##s##_RP1_freq_mhz.attr, \
420 &p##attr_##s##_RPn_freq_mhz.attr, \
421 NULL, \
422 }
423
424#define GEN6_RPS_ATTR GEN6_ATTR(, rps)
425#define GEN6_GT_ATTR GEN6_ATTR(dev_, gt)
426
427static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
428static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
429
430static ssize_t punit_req_freq_mhz_show(struct kobject *kobj,
431 struct kobj_attribute *attr,
432 char *buff)
433{
434 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
435 u32 preq = intel_rps_read_punit_req_frequency(>->rps);
436
437 return sysfs_emit(buff, "%u\n", preq);
438}
439
440static ssize_t slpc_ignore_eff_freq_show(struct kobject *kobj,
441 struct kobj_attribute *attr,
442 char *buff)
443{
444 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
445 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
446
447 return sysfs_emit(buff, "%u\n", slpc->ignore_eff_freq);
448}
449
450static ssize_t slpc_ignore_eff_freq_store(struct kobject *kobj,
451 struct kobj_attribute *attr,
452 const char *buff, size_t count)
453{
454 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
455 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
456 int err;
457 u32 val;
458
459 err = kstrtou32(buff, 0, &val);
460 if (err)
461 return err;
462
463 err = intel_guc_slpc_set_ignore_eff_freq(slpc, val);
464 return err ?: count;
465}
466
467struct intel_gt_bool_throttle_attr {
468 struct attribute attr;
469 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
470 char *buf);
471 i915_reg_t (*reg32)(struct intel_gt *gt);
472 u32 mask;
473};
474
475static ssize_t throttle_reason_bool_show(struct kobject *kobj,
476 struct kobj_attribute *attr,
477 char *buff)
478{
479 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
480 struct intel_gt_bool_throttle_attr *t_attr =
481 (struct intel_gt_bool_throttle_attr *) attr;
482 bool val = rps_read_mask_mmio(>->rps, t_attr->reg32(gt), t_attr->mask);
483
484 return sysfs_emit(buff, "%u\n", val);
485}
486
487#define INTEL_GT_RPS_BOOL_ATTR_RO(sysfs_func__, mask__) \
488struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
489 .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
490 .show = throttle_reason_bool_show, \
491 .reg32 = intel_gt_perf_limit_reasons_reg, \
492 .mask = mask__, \
493}
494
495INTEL_GT_ATTR_RO(punit_req_freq_mhz);
496static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
497static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
498static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
499static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl4, POWER_LIMIT_4_MASK);
500static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_thermal, THERMAL_LIMIT_MASK);
501static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_prochot, PROCHOT_MASK);
502static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl, RATL_MASK);
503static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert, VR_THERMALERT_MASK);
504static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
505
506static const struct attribute *throttle_reason_attrs[] = {
507 &attr_throttle_reason_status.attr,
508 &attr_throttle_reason_pl1.attr,
509 &attr_throttle_reason_pl2.attr,
510 &attr_throttle_reason_pl4.attr,
511 &attr_throttle_reason_thermal.attr,
512 &attr_throttle_reason_prochot.attr,
513 &attr_throttle_reason_ratl.attr,
514 &attr_throttle_reason_vr_thermalert.attr,
515 &attr_throttle_reason_vr_tdc.attr,
516 NULL
517};
518
519/*
520 * Scaling for multipliers (aka frequency factors).
521 * The format of the value in the register is u8.8.
522 *
523 * The presentation to userspace is inspired by the perf event framework.
524 * See:
525 * Documentation/ABI/testing/sysfs-bus-event_source-devices-events
526 * for description of:
527 * /sys/bus/event_source/devices/<pmu>/events/<event>.scale
528 *
529 * Summary: Expose two sysfs files for each multiplier.
530 *
531 * 1. File <attr> contains a raw hardware value.
532 * 2. File <attr>.scale contains the multiplicative scale factor to be
533 * used by userspace to compute the actual value.
534 *
535 * So userspace knows that to get the frequency_factor it multiplies the
536 * provided value by the specified scale factor and vice-versa.
537 *
538 * That way there is no precision loss in the kernel interface and API
539 * is future proof should one day the hardware register change to u16.u16,
540 * on some platform. (Or any other fixed point representation.)
541 *
542 * Example:
543 * File <attr> contains the value 2.5, represented as u8.8 0x0280, which
544 * is comprised of:
545 * - an integer part of 2
546 * - a fractional part of 0x80 (representing 0x80 / 2^8 == 0x80 / 256).
547 * File <attr>.scale contains a string representation of floating point
548 * value 0.00390625 (which is (1 / 256)).
549 * Userspace computes the actual value:
550 * 0x0280 * 0.00390625 -> 2.5
551 * or converts an actual value to the value to be written into <attr>:
552 * 2.5 / 0.00390625 -> 0x0280
553 */
554
555#define U8_8_VAL_MASK 0xffff
556#define U8_8_SCALE_TO_VALUE "0.00390625"
557
558static ssize_t freq_factor_scale_show(struct kobject *kobj,
559 struct kobj_attribute *attr,
560 char *buff)
561{
562 return sysfs_emit(buff, "%s\n", U8_8_SCALE_TO_VALUE);
563}
564
565static u32 media_ratio_mode_to_factor(u32 mode)
566{
567 /* 0 -> 0, 1 -> 256, 2 -> 128 */
568 return !mode ? mode : 256 / mode;
569}
570
571static ssize_t media_freq_factor_show(struct kobject *kobj,
572 struct kobj_attribute *attr,
573 char *buff)
574{
575 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
576 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
577 intel_wakeref_t wakeref;
578 u32 mode;
579
580 /*
581 * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
582 * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
583 */
584 if (IS_XEHPSDV(gt->i915) &&
585 slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
586 /*
587 * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
588 * the media_ratio_mode, just return the cached media ratio
589 */
590 mode = slpc->media_ratio_mode;
591 } else {
592 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
593 mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
594 mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
595 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
596 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
597 }
598
599 return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
600}
601
602static ssize_t media_freq_factor_store(struct kobject *kobj,
603 struct kobj_attribute *attr,
604 const char *buff, size_t count)
605{
606 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
607 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
608 u32 factor, mode;
609 int err;
610
611 err = kstrtou32(buff, 0, &factor);
612 if (err)
613 return err;
614
615 for (mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
616 mode <= SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO; mode++)
617 if (factor == media_ratio_mode_to_factor(mode))
618 break;
619
620 if (mode > SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO)
621 return -EINVAL;
622
623 err = intel_guc_slpc_set_media_ratio_mode(slpc, mode);
624 if (!err) {
625 slpc->media_ratio_mode = mode;
626 DRM_DEBUG("Set slpc->media_ratio_mode to %d", mode);
627 }
628 return err ?: count;
629}
630
631static ssize_t media_RP0_freq_mhz_show(struct kobject *kobj,
632 struct kobj_attribute *attr,
633 char *buff)
634{
635 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
636 u32 val;
637 int err;
638
639 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
640 PCODE_MBOX_FC_SC_READ_FUSED_P0,
641 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
642
643 if (err)
644 return err;
645
646 /* Fused media RP0 read from pcode is in units of 50 MHz */
647 val *= GT_FREQUENCY_MULTIPLIER;
648
649 return sysfs_emit(buff, "%u\n", val);
650}
651
652static ssize_t media_RPn_freq_mhz_show(struct kobject *kobj,
653 struct kobj_attribute *attr,
654 char *buff)
655{
656 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
657 u32 val;
658 int err;
659
660 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
661 PCODE_MBOX_FC_SC_READ_FUSED_PN,
662 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
663
664 if (err)
665 return err;
666
667 /* Fused media RPn read from pcode is in units of 50 MHz */
668 val *= GT_FREQUENCY_MULTIPLIER;
669
670 return sysfs_emit(buff, "%u\n", val);
671}
672
673INTEL_GT_ATTR_RW(media_freq_factor);
674static struct kobj_attribute attr_media_freq_factor_scale =
675 __ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
676INTEL_GT_ATTR_RO(media_RP0_freq_mhz);
677INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
678
679INTEL_GT_ATTR_RW(slpc_ignore_eff_freq);
680
681static const struct attribute *media_perf_power_attrs[] = {
682 &attr_media_freq_factor.attr,
683 &attr_media_freq_factor_scale.attr,
684 &attr_media_RP0_freq_mhz.attr,
685 &attr_media_RPn_freq_mhz.attr,
686 NULL
687};
688
689static ssize_t
690rps_up_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
691 char *buf)
692{
693 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
694 struct intel_rps *rps = >->rps;
695
696 return sysfs_emit(buf, "%u\n", intel_rps_get_up_threshold(rps));
697}
698
699static ssize_t
700rps_up_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
701 const char *buf, size_t count)
702{
703 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
704 struct intel_rps *rps = >->rps;
705 int ret;
706 u8 val;
707
708 ret = kstrtou8(buf, 10, &val);
709 if (ret)
710 return ret;
711
712 ret = intel_rps_set_up_threshold(rps, val);
713
714 return ret == 0 ? count : ret;
715}
716
717static struct kobj_attribute rps_up_threshold_pct =
718 __ATTR(rps_up_threshold_pct,
719 0664,
720 rps_up_threshold_pct_show,
721 rps_up_threshold_pct_store);
722
723static ssize_t
724rps_down_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
725 char *buf)
726{
727 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
728 struct intel_rps *rps = >->rps;
729
730 return sysfs_emit(buf, "%u\n", intel_rps_get_down_threshold(rps));
731}
732
733static ssize_t
734rps_down_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
735 const char *buf, size_t count)
736{
737 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
738 struct intel_rps *rps = >->rps;
739 int ret;
740 u8 val;
741
742 ret = kstrtou8(buf, 10, &val);
743 if (ret)
744 return ret;
745
746 ret = intel_rps_set_down_threshold(rps, val);
747
748 return ret == 0 ? count : ret;
749}
750
751static struct kobj_attribute rps_down_threshold_pct =
752 __ATTR(rps_down_threshold_pct,
753 0664,
754 rps_down_threshold_pct_show,
755 rps_down_threshold_pct_store);
756
757static const struct attribute * const gen6_gt_rps_attrs[] = {
758 &rps_up_threshold_pct.attr,
759 &rps_down_threshold_pct.attr,
760 NULL
761};
762
763static ssize_t
764default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
765{
766 struct intel_gt *gt = kobj_to_gt(kobj->parent);
767
768 return sysfs_emit(buf, "%u\n", gt->defaults.min_freq);
769}
770
771static struct kobj_attribute default_min_freq_mhz =
772__ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL);
773
774static ssize_t
775default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
776{
777 struct intel_gt *gt = kobj_to_gt(kobj->parent);
778
779 return sysfs_emit(buf, "%u\n", gt->defaults.max_freq);
780}
781
782static struct kobj_attribute default_max_freq_mhz =
783__ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
784
785static ssize_t
786default_rps_up_threshold_pct_show(struct kobject *kobj,
787 struct kobj_attribute *attr,
788 char *buf)
789{
790 struct intel_gt *gt = kobj_to_gt(kobj->parent);
791
792 return sysfs_emit(buf, "%u\n", gt->defaults.rps_up_threshold);
793}
794
795static struct kobj_attribute default_rps_up_threshold_pct =
796__ATTR(rps_up_threshold_pct, 0444, default_rps_up_threshold_pct_show, NULL);
797
798static ssize_t
799default_rps_down_threshold_pct_show(struct kobject *kobj,
800 struct kobj_attribute *attr,
801 char *buf)
802{
803 struct intel_gt *gt = kobj_to_gt(kobj->parent);
804
805 return sysfs_emit(buf, "%u\n", gt->defaults.rps_down_threshold);
806}
807
808static struct kobj_attribute default_rps_down_threshold_pct =
809__ATTR(rps_down_threshold_pct, 0444, default_rps_down_threshold_pct_show, NULL);
810
811static const struct attribute * const rps_defaults_attrs[] = {
812 &default_min_freq_mhz.attr,
813 &default_max_freq_mhz.attr,
814 &default_rps_up_threshold_pct.attr,
815 &default_rps_down_threshold_pct.attr,
816 NULL
817};
818
819static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj)
820{
821 const struct attribute * const *attrs;
822 struct attribute *vlv_attr;
823 int ret;
824
825 if (GRAPHICS_VER(gt->i915) < 6)
826 return 0;
827
828 if (is_object_gt(kobj)) {
829 attrs = gen6_rps_attrs;
830 vlv_attr = &attr_rps_vlv_rpe_freq_mhz.attr;
831 } else {
832 attrs = gen6_gt_attrs;
833 vlv_attr = &dev_attr_gt_vlv_rpe_freq_mhz.attr;
834 }
835
836 ret = sysfs_create_files(kobj, attrs);
837 if (ret)
838 return ret;
839
840 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
841 ret = sysfs_create_file(kobj, vlv_attr);
842
843 if (is_object_gt(kobj) && !intel_uc_uses_guc_slpc(>->uc)) {
844 ret = sysfs_create_files(kobj, gen6_gt_rps_attrs);
845 if (ret)
846 return ret;
847 }
848
849 return ret;
850}
851
852void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
853{
854 int ret;
855
856 intel_sysfs_rc6_init(gt, kobj);
857
858 ret = intel_sysfs_rps_init(gt, kobj);
859 if (ret)
860 gt_warn(gt, "failed to create RPS sysfs files (%pe)", ERR_PTR(ret));
861
862 /* end of the legacy interfaces */
863 if (!is_object_gt(kobj))
864 return;
865
866 ret = sysfs_create_file(kobj, &attr_punit_req_freq_mhz.attr);
867 if (ret)
868 gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
869
870 if (intel_uc_uses_guc_slpc(>->uc)) {
871 ret = sysfs_create_file(kobj, &attr_slpc_ignore_eff_freq.attr);
872 if (ret)
873 gt_warn(gt, "failed to create ignore_eff_freq sysfs (%pe)", ERR_PTR(ret));
874 }
875
876 if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
877 ret = sysfs_create_files(kobj, throttle_reason_attrs);
878 if (ret)
879 gt_warn(gt, "failed to create throttle sysfs files (%pe)", ERR_PTR(ret));
880 }
881
882 if (HAS_MEDIA_RATIO_MODE(gt->i915) && intel_uc_uses_guc_slpc(>->uc)) {
883 ret = sysfs_create_files(kobj, media_perf_power_attrs);
884 if (ret)
885 gt_warn(gt, "failed to create media_perf_power_attrs sysfs (%pe)\n",
886 ERR_PTR(ret));
887 }
888
889 ret = sysfs_create_files(gt->sysfs_defaults, rps_defaults_attrs);
890 if (ret)
891 gt_warn(gt, "failed to add rps defaults (%pe)\n", ERR_PTR(ret));
892}