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1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
31#include <linux/slab.h>
32#include <linux/hdmi.h>
33#include <linux/i2c.h>
34#include <linux/module.h>
35#include <linux/vga_switcheroo.h>
36#include <drm/drmP.h>
37#include <drm/drm_edid.h>
38#include <drm/drm_displayid.h>
39
40#define version_greater(edid, maj, min) \
41 (((edid)->version > (maj)) || \
42 ((edid)->version == (maj) && (edid)->revision > (min)))
43
44#define EDID_EST_TIMINGS 16
45#define EDID_STD_TIMINGS 8
46#define EDID_DETAILED_TIMINGS 4
47
48/*
49 * EDID blocks out in the wild have a variety of bugs, try to collect
50 * them here (note that userspace may work around broken monitors first,
51 * but fixes should make their way here so that the kernel "just works"
52 * on as many displays as possible).
53 */
54
55/* First detailed mode wrong, use largest 60Hz mode */
56#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
57/* Reported 135MHz pixel clock is too high, needs adjustment */
58#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
59/* Prefer the largest mode at 75 Hz */
60#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
61/* Detail timing is in cm not mm */
62#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
63/* Detailed timing descriptors have bogus size values, so just take the
64 * maximum size and use that.
65 */
66#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
67/* Monitor forgot to set the first detailed is preferred bit. */
68#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
69/* use +hsync +vsync for detailed mode */
70#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
71/* Force reduced-blanking timings for detailed modes */
72#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
73/* Force 8bpc */
74#define EDID_QUIRK_FORCE_8BPC (1 << 8)
75/* Force 12bpc */
76#define EDID_QUIRK_FORCE_12BPC (1 << 9)
77
78struct detailed_mode_closure {
79 struct drm_connector *connector;
80 struct edid *edid;
81 bool preferred;
82 u32 quirks;
83 int modes;
84};
85
86#define LEVEL_DMT 0
87#define LEVEL_GTF 1
88#define LEVEL_GTF2 2
89#define LEVEL_CVT 3
90
91static struct edid_quirk {
92 char vendor[4];
93 int product_id;
94 u32 quirks;
95} edid_quirk_list[] = {
96 /* Acer AL1706 */
97 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
98 /* Acer F51 */
99 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
100 /* Unknown Acer */
101 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
102
103 /* Belinea 10 15 55 */
104 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
105 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
106
107 /* Envision Peripherals, Inc. EN-7100e */
108 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
109 /* Envision EN2028 */
110 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
111
112 /* Funai Electronics PM36B */
113 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
114 EDID_QUIRK_DETAILED_IN_CM },
115
116 /* LG Philips LCD LP154W01-A5 */
117 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
118 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
119
120 /* Philips 107p5 CRT */
121 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
122
123 /* Proview AY765C */
124 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
125
126 /* Samsung SyncMaster 205BW. Note: irony */
127 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
128 /* Samsung SyncMaster 22[5-6]BW */
129 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
130 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
131
132 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
133 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
134
135 /* ViewSonic VA2026w */
136 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
137
138 /* Medion MD 30217 PG */
139 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
140
141 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
142 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
143};
144
145/*
146 * Autogenerated from the DMT spec.
147 * This table is copied from xfree86/modes/xf86EdidModes.c.
148 */
149static const struct drm_display_mode drm_dmt_modes[] = {
150 /* 0x01 - 640x350@85Hz */
151 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
152 736, 832, 0, 350, 382, 385, 445, 0,
153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
154 /* 0x02 - 640x400@85Hz */
155 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
156 736, 832, 0, 400, 401, 404, 445, 0,
157 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
158 /* 0x03 - 720x400@85Hz */
159 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
160 828, 936, 0, 400, 401, 404, 446, 0,
161 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
162 /* 0x04 - 640x480@60Hz */
163 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
164 752, 800, 0, 480, 490, 492, 525, 0,
165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
166 /* 0x05 - 640x480@72Hz */
167 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
168 704, 832, 0, 480, 489, 492, 520, 0,
169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
170 /* 0x06 - 640x480@75Hz */
171 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
172 720, 840, 0, 480, 481, 484, 500, 0,
173 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
174 /* 0x07 - 640x480@85Hz */
175 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
176 752, 832, 0, 480, 481, 484, 509, 0,
177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
178 /* 0x08 - 800x600@56Hz */
179 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
180 896, 1024, 0, 600, 601, 603, 625, 0,
181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
182 /* 0x09 - 800x600@60Hz */
183 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
184 968, 1056, 0, 600, 601, 605, 628, 0,
185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
186 /* 0x0a - 800x600@72Hz */
187 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
188 976, 1040, 0, 600, 637, 643, 666, 0,
189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
190 /* 0x0b - 800x600@75Hz */
191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
192 896, 1056, 0, 600, 601, 604, 625, 0,
193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
194 /* 0x0c - 800x600@85Hz */
195 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
196 896, 1048, 0, 600, 601, 604, 631, 0,
197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
198 /* 0x0d - 800x600@120Hz RB */
199 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
200 880, 960, 0, 600, 603, 607, 636, 0,
201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
202 /* 0x0e - 848x480@60Hz */
203 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
204 976, 1088, 0, 480, 486, 494, 517, 0,
205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
206 /* 0x0f - 1024x768@43Hz, interlace */
207 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
208 1208, 1264, 0, 768, 768, 776, 817, 0,
209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
210 DRM_MODE_FLAG_INTERLACE) },
211 /* 0x10 - 1024x768@60Hz */
212 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
213 1184, 1344, 0, 768, 771, 777, 806, 0,
214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
215 /* 0x11 - 1024x768@70Hz */
216 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
217 1184, 1328, 0, 768, 771, 777, 806, 0,
218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
219 /* 0x12 - 1024x768@75Hz */
220 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
221 1136, 1312, 0, 768, 769, 772, 800, 0,
222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
223 /* 0x13 - 1024x768@85Hz */
224 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
225 1168, 1376, 0, 768, 769, 772, 808, 0,
226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
227 /* 0x14 - 1024x768@120Hz RB */
228 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
229 1104, 1184, 0, 768, 771, 775, 813, 0,
230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
231 /* 0x15 - 1152x864@75Hz */
232 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
233 1344, 1600, 0, 864, 865, 868, 900, 0,
234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
235 /* 0x55 - 1280x720@60Hz */
236 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
237 1430, 1650, 0, 720, 725, 730, 750, 0,
238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
239 /* 0x16 - 1280x768@60Hz RB */
240 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
241 1360, 1440, 0, 768, 771, 778, 790, 0,
242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
243 /* 0x17 - 1280x768@60Hz */
244 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
245 1472, 1664, 0, 768, 771, 778, 798, 0,
246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
247 /* 0x18 - 1280x768@75Hz */
248 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
249 1488, 1696, 0, 768, 771, 778, 805, 0,
250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
251 /* 0x19 - 1280x768@85Hz */
252 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
253 1496, 1712, 0, 768, 771, 778, 809, 0,
254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
255 /* 0x1a - 1280x768@120Hz RB */
256 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
257 1360, 1440, 0, 768, 771, 778, 813, 0,
258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
259 /* 0x1b - 1280x800@60Hz RB */
260 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
261 1360, 1440, 0, 800, 803, 809, 823, 0,
262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
263 /* 0x1c - 1280x800@60Hz */
264 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
265 1480, 1680, 0, 800, 803, 809, 831, 0,
266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
267 /* 0x1d - 1280x800@75Hz */
268 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
269 1488, 1696, 0, 800, 803, 809, 838, 0,
270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
271 /* 0x1e - 1280x800@85Hz */
272 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
273 1496, 1712, 0, 800, 803, 809, 843, 0,
274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
275 /* 0x1f - 1280x800@120Hz RB */
276 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
277 1360, 1440, 0, 800, 803, 809, 847, 0,
278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
279 /* 0x20 - 1280x960@60Hz */
280 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
281 1488, 1800, 0, 960, 961, 964, 1000, 0,
282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x21 - 1280x960@85Hz */
284 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
285 1504, 1728, 0, 960, 961, 964, 1011, 0,
286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x22 - 1280x960@120Hz RB */
288 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
289 1360, 1440, 0, 960, 963, 967, 1017, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
291 /* 0x23 - 1280x1024@60Hz */
292 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
293 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x24 - 1280x1024@75Hz */
296 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
297 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
299 /* 0x25 - 1280x1024@85Hz */
300 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
301 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x26 - 1280x1024@120Hz RB */
304 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
305 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
307 /* 0x27 - 1360x768@60Hz */
308 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
309 1536, 1792, 0, 768, 771, 777, 795, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
311 /* 0x28 - 1360x768@120Hz RB */
312 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
313 1440, 1520, 0, 768, 771, 776, 813, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
315 /* 0x51 - 1366x768@60Hz */
316 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
317 1579, 1792, 0, 768, 771, 774, 798, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
319 /* 0x56 - 1366x768@60Hz */
320 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
321 1436, 1500, 0, 768, 769, 772, 800, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
323 /* 0x29 - 1400x1050@60Hz RB */
324 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
325 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
327 /* 0x2a - 1400x1050@60Hz */
328 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
329 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
331 /* 0x2b - 1400x1050@75Hz */
332 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
333 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x2c - 1400x1050@85Hz */
336 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
337 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x2d - 1400x1050@120Hz RB */
340 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
341 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
343 /* 0x2e - 1440x900@60Hz RB */
344 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
345 1520, 1600, 0, 900, 903, 909, 926, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
347 /* 0x2f - 1440x900@60Hz */
348 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
349 1672, 1904, 0, 900, 903, 909, 934, 0,
350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
351 /* 0x30 - 1440x900@75Hz */
352 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
353 1688, 1936, 0, 900, 903, 909, 942, 0,
354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
355 /* 0x31 - 1440x900@85Hz */
356 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
357 1696, 1952, 0, 900, 903, 909, 948, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
359 /* 0x32 - 1440x900@120Hz RB */
360 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
361 1520, 1600, 0, 900, 903, 909, 953, 0,
362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
363 /* 0x53 - 1600x900@60Hz */
364 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
365 1704, 1800, 0, 900, 901, 904, 1000, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x33 - 1600x1200@60Hz */
368 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
369 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x34 - 1600x1200@65Hz */
372 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
373 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
375 /* 0x35 - 1600x1200@70Hz */
376 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
377 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x36 - 1600x1200@75Hz */
380 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
381 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x37 - 1600x1200@85Hz */
384 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
385 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x38 - 1600x1200@120Hz RB */
388 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
389 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
391 /* 0x39 - 1680x1050@60Hz RB */
392 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
393 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
395 /* 0x3a - 1680x1050@60Hz */
396 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
397 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x3b - 1680x1050@75Hz */
400 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
401 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
402 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
403 /* 0x3c - 1680x1050@85Hz */
404 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
405 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x3d - 1680x1050@120Hz RB */
408 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
409 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
411 /* 0x3e - 1792x1344@60Hz */
412 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
413 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
415 /* 0x3f - 1792x1344@75Hz */
416 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
417 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x40 - 1792x1344@120Hz RB */
420 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
421 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
423 /* 0x41 - 1856x1392@60Hz */
424 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
425 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x42 - 1856x1392@75Hz */
428 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
429 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
431 /* 0x43 - 1856x1392@120Hz RB */
432 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
433 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 0x52 - 1920x1080@60Hz */
436 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
437 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
439 /* 0x44 - 1920x1200@60Hz RB */
440 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
441 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
443 /* 0x45 - 1920x1200@60Hz */
444 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
445 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x46 - 1920x1200@75Hz */
448 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
449 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
451 /* 0x47 - 1920x1200@85Hz */
452 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
453 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
455 /* 0x48 - 1920x1200@120Hz RB */
456 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
457 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
459 /* 0x49 - 1920x1440@60Hz */
460 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
461 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x4a - 1920x1440@75Hz */
464 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
465 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
466 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x4b - 1920x1440@120Hz RB */
468 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
469 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
471 /* 0x54 - 2048x1152@60Hz */
472 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
473 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x4c - 2560x1600@60Hz RB */
476 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
477 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
479 /* 0x4d - 2560x1600@60Hz */
480 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
481 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 0x4e - 2560x1600@75Hz */
484 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
485 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x4f - 2560x1600@85Hz */
488 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
489 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
491 /* 0x50 - 2560x1600@120Hz RB */
492 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
493 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
495 /* 0x57 - 4096x2160@60Hz RB */
496 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
497 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
499 /* 0x58 - 4096x2160@59.94Hz RB */
500 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
501 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503};
504
505/*
506 * These more or less come from the DMT spec. The 720x400 modes are
507 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
508 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
509 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
510 * mode.
511 *
512 * The DMT modes have been fact-checked; the rest are mild guesses.
513 */
514static const struct drm_display_mode edid_est_modes[] = {
515 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
516 968, 1056, 0, 600, 601, 605, 628, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
518 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
519 896, 1024, 0, 600, 601, 603, 625, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
521 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
522 720, 840, 0, 480, 481, 484, 500, 0,
523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
524 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
525 704, 832, 0, 480, 489, 492, 520, 0,
526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
527 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
528 768, 864, 0, 480, 483, 486, 525, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
530 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
531 752, 800, 0, 480, 490, 492, 525, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
533 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
534 846, 900, 0, 400, 421, 423, 449, 0,
535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
536 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
537 846, 900, 0, 400, 412, 414, 449, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
539 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
540 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
542 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
543 1136, 1312, 0, 768, 769, 772, 800, 0,
544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
545 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
546 1184, 1328, 0, 768, 771, 777, 806, 0,
547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
548 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
549 1184, 1344, 0, 768, 771, 777, 806, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
551 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
552 1208, 1264, 0, 768, 768, 776, 817, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
554 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
555 928, 1152, 0, 624, 625, 628, 667, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
557 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
558 896, 1056, 0, 600, 601, 604, 625, 0,
559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
560 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
561 976, 1040, 0, 600, 637, 643, 666, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
563 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
564 1344, 1600, 0, 864, 865, 868, 900, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
566};
567
568struct minimode {
569 short w;
570 short h;
571 short r;
572 short rb;
573};
574
575static const struct minimode est3_modes[] = {
576 /* byte 6 */
577 { 640, 350, 85, 0 },
578 { 640, 400, 85, 0 },
579 { 720, 400, 85, 0 },
580 { 640, 480, 85, 0 },
581 { 848, 480, 60, 0 },
582 { 800, 600, 85, 0 },
583 { 1024, 768, 85, 0 },
584 { 1152, 864, 75, 0 },
585 /* byte 7 */
586 { 1280, 768, 60, 1 },
587 { 1280, 768, 60, 0 },
588 { 1280, 768, 75, 0 },
589 { 1280, 768, 85, 0 },
590 { 1280, 960, 60, 0 },
591 { 1280, 960, 85, 0 },
592 { 1280, 1024, 60, 0 },
593 { 1280, 1024, 85, 0 },
594 /* byte 8 */
595 { 1360, 768, 60, 0 },
596 { 1440, 900, 60, 1 },
597 { 1440, 900, 60, 0 },
598 { 1440, 900, 75, 0 },
599 { 1440, 900, 85, 0 },
600 { 1400, 1050, 60, 1 },
601 { 1400, 1050, 60, 0 },
602 { 1400, 1050, 75, 0 },
603 /* byte 9 */
604 { 1400, 1050, 85, 0 },
605 { 1680, 1050, 60, 1 },
606 { 1680, 1050, 60, 0 },
607 { 1680, 1050, 75, 0 },
608 { 1680, 1050, 85, 0 },
609 { 1600, 1200, 60, 0 },
610 { 1600, 1200, 65, 0 },
611 { 1600, 1200, 70, 0 },
612 /* byte 10 */
613 { 1600, 1200, 75, 0 },
614 { 1600, 1200, 85, 0 },
615 { 1792, 1344, 60, 0 },
616 { 1792, 1344, 75, 0 },
617 { 1856, 1392, 60, 0 },
618 { 1856, 1392, 75, 0 },
619 { 1920, 1200, 60, 1 },
620 { 1920, 1200, 60, 0 },
621 /* byte 11 */
622 { 1920, 1200, 75, 0 },
623 { 1920, 1200, 85, 0 },
624 { 1920, 1440, 60, 0 },
625 { 1920, 1440, 75, 0 },
626};
627
628static const struct minimode extra_modes[] = {
629 { 1024, 576, 60, 0 },
630 { 1366, 768, 60, 0 },
631 { 1600, 900, 60, 0 },
632 { 1680, 945, 60, 0 },
633 { 1920, 1080, 60, 0 },
634 { 2048, 1152, 60, 0 },
635 { 2048, 1536, 60, 0 },
636};
637
638/*
639 * Probably taken from CEA-861 spec.
640 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
641 *
642 * Index using the VIC.
643 */
644static const struct drm_display_mode edid_cea_modes[] = {
645 /* 0 - dummy, VICs start at 1 */
646 { },
647 /* 1 - 640x480@60Hz */
648 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
649 752, 800, 0, 480, 490, 492, 525, 0,
650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
651 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
652 /* 2 - 720x480@60Hz */
653 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
654 798, 858, 0, 480, 489, 495, 525, 0,
655 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
656 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
657 /* 3 - 720x480@60Hz */
658 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
659 798, 858, 0, 480, 489, 495, 525, 0,
660 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
661 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
662 /* 4 - 1280x720@60Hz */
663 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
664 1430, 1650, 0, 720, 725, 730, 750, 0,
665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
666 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
667 /* 5 - 1920x1080i@60Hz */
668 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
669 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
670 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
671 DRM_MODE_FLAG_INTERLACE),
672 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
673 /* 6 - 720(1440)x480i@60Hz */
674 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
675 801, 858, 0, 480, 488, 494, 525, 0,
676 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
677 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
679 /* 7 - 720(1440)x480i@60Hz */
680 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
681 801, 858, 0, 480, 488, 494, 525, 0,
682 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
683 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
684 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
685 /* 8 - 720(1440)x240@60Hz */
686 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
687 801, 858, 0, 240, 244, 247, 262, 0,
688 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
689 DRM_MODE_FLAG_DBLCLK),
690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
691 /* 9 - 720(1440)x240@60Hz */
692 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
693 801, 858, 0, 240, 244, 247, 262, 0,
694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
695 DRM_MODE_FLAG_DBLCLK),
696 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
697 /* 10 - 2880x480i@60Hz */
698 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
699 3204, 3432, 0, 480, 488, 494, 525, 0,
700 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
701 DRM_MODE_FLAG_INTERLACE),
702 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
703 /* 11 - 2880x480i@60Hz */
704 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
705 3204, 3432, 0, 480, 488, 494, 525, 0,
706 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
707 DRM_MODE_FLAG_INTERLACE),
708 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
709 /* 12 - 2880x240@60Hz */
710 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
711 3204, 3432, 0, 240, 244, 247, 262, 0,
712 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
714 /* 13 - 2880x240@60Hz */
715 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
716 3204, 3432, 0, 240, 244, 247, 262, 0,
717 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
719 /* 14 - 1440x480@60Hz */
720 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
721 1596, 1716, 0, 480, 489, 495, 525, 0,
722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
723 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
724 /* 15 - 1440x480@60Hz */
725 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
726 1596, 1716, 0, 480, 489, 495, 525, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
729 /* 16 - 1920x1080@60Hz */
730 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
731 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
732 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
734 /* 17 - 720x576@50Hz */
735 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
736 796, 864, 0, 576, 581, 586, 625, 0,
737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
738 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
739 /* 18 - 720x576@50Hz */
740 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
741 796, 864, 0, 576, 581, 586, 625, 0,
742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
743 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
744 /* 19 - 1280x720@50Hz */
745 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
746 1760, 1980, 0, 720, 725, 730, 750, 0,
747 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
748 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
749 /* 20 - 1920x1080i@50Hz */
750 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
751 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
752 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
753 DRM_MODE_FLAG_INTERLACE),
754 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
755 /* 21 - 720(1440)x576i@50Hz */
756 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
757 795, 864, 0, 576, 580, 586, 625, 0,
758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
759 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
761 /* 22 - 720(1440)x576i@50Hz */
762 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
763 795, 864, 0, 576, 580, 586, 625, 0,
764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
766 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
767 /* 23 - 720(1440)x288@50Hz */
768 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
769 795, 864, 0, 288, 290, 293, 312, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_DBLCLK),
772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
773 /* 24 - 720(1440)x288@50Hz */
774 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
775 795, 864, 0, 288, 290, 293, 312, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_DBLCLK),
778 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 25 - 2880x576i@50Hz */
780 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
781 3180, 3456, 0, 576, 580, 586, 625, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_INTERLACE),
784 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 26 - 2880x576i@50Hz */
786 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
787 3180, 3456, 0, 576, 580, 586, 625, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_INTERLACE),
790 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 27 - 2880x288@50Hz */
792 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
793 3180, 3456, 0, 288, 290, 293, 312, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
796 /* 28 - 2880x288@50Hz */
797 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
798 3180, 3456, 0, 288, 290, 293, 312, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
800 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
801 /* 29 - 1440x576@50Hz */
802 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
803 1592, 1728, 0, 576, 581, 586, 625, 0,
804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
805 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
806 /* 30 - 1440x576@50Hz */
807 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
808 1592, 1728, 0, 576, 581, 586, 625, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
811 /* 31 - 1920x1080@50Hz */
812 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
813 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
816 /* 32 - 1920x1080@24Hz */
817 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
818 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
820 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 33 - 1920x1080@25Hz */
822 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
823 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
825 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 34 - 1920x1080@30Hz */
827 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
828 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
830 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
831 /* 35 - 2880x480@60Hz */
832 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
833 3192, 3432, 0, 480, 489, 495, 525, 0,
834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
835 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
836 /* 36 - 2880x480@60Hz */
837 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
838 3192, 3432, 0, 480, 489, 495, 525, 0,
839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
840 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
841 /* 37 - 2880x576@50Hz */
842 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
843 3184, 3456, 0, 576, 581, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
845 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
846 /* 38 - 2880x576@50Hz */
847 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
848 3184, 3456, 0, 576, 581, 586, 625, 0,
849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
850 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 39 - 1920x1080i@50Hz */
852 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
853 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
855 DRM_MODE_FLAG_INTERLACE),
856 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
857 /* 40 - 1920x1080i@100Hz */
858 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
859 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
860 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
861 DRM_MODE_FLAG_INTERLACE),
862 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 41 - 1280x720@100Hz */
864 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
865 1760, 1980, 0, 720, 725, 730, 750, 0,
866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
867 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
868 /* 42 - 720x576@100Hz */
869 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
870 796, 864, 0, 576, 581, 586, 625, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
872 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
873 /* 43 - 720x576@100Hz */
874 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
875 796, 864, 0, 576, 581, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
877 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
878 /* 44 - 720(1440)x576i@100Hz */
879 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
880 795, 864, 0, 576, 580, 586, 625, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
882 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
883 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
884 /* 45 - 720(1440)x576i@100Hz */
885 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
886 795, 864, 0, 576, 580, 586, 625, 0,
887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
888 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 46 - 1920x1080i@120Hz */
891 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
892 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
893 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
894 DRM_MODE_FLAG_INTERLACE),
895 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 47 - 1280x720@120Hz */
897 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
898 1430, 1650, 0, 720, 725, 730, 750, 0,
899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
900 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 48 - 720x480@120Hz */
902 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
903 798, 858, 0, 480, 489, 495, 525, 0,
904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
905 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
906 /* 49 - 720x480@120Hz */
907 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
908 798, 858, 0, 480, 489, 495, 525, 0,
909 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
910 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
911 /* 50 - 720(1440)x480i@120Hz */
912 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
913 801, 858, 0, 480, 488, 494, 525, 0,
914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
915 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
916 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
917 /* 51 - 720(1440)x480i@120Hz */
918 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
919 801, 858, 0, 480, 488, 494, 525, 0,
920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
921 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 52 - 720x576@200Hz */
924 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
925 796, 864, 0, 576, 581, 586, 625, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
927 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
928 /* 53 - 720x576@200Hz */
929 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
930 796, 864, 0, 576, 581, 586, 625, 0,
931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
932 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
933 /* 54 - 720(1440)x576i@200Hz */
934 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
935 795, 864, 0, 576, 580, 586, 625, 0,
936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
937 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
938 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
939 /* 55 - 720(1440)x576i@200Hz */
940 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
941 795, 864, 0, 576, 580, 586, 625, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
943 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
944 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 56 - 720x480@240Hz */
946 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
947 798, 858, 0, 480, 489, 495, 525, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
949 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
950 /* 57 - 720x480@240Hz */
951 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
952 798, 858, 0, 480, 489, 495, 525, 0,
953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
954 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 /* 58 - 720(1440)x480i@240 */
956 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
957 801, 858, 0, 480, 488, 494, 525, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
960 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
961 /* 59 - 720(1440)x480i@240 */
962 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
963 801, 858, 0, 480, 488, 494, 525, 0,
964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
965 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
966 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 60 - 1280x720@24Hz */
968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
969 3080, 3300, 0, 720, 725, 730, 750, 0,
970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
971 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972 /* 61 - 1280x720@25Hz */
973 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
974 3740, 3960, 0, 720, 725, 730, 750, 0,
975 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
976 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
977 /* 62 - 1280x720@30Hz */
978 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
979 3080, 3300, 0, 720, 725, 730, 750, 0,
980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
981 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982 /* 63 - 1920x1080@120Hz */
983 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
984 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
985 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
986 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
987 /* 64 - 1920x1080@100Hz */
988 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
989 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
991 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
992};
993
994/*
995 * HDMI 1.4 4k modes. Index using the VIC.
996 */
997static const struct drm_display_mode edid_4k_modes[] = {
998 /* 0 - dummy, VICs start at 1 */
999 { },
1000 /* 1 - 3840x2160@30Hz */
1001 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1002 3840, 4016, 4104, 4400, 0,
1003 2160, 2168, 2178, 2250, 0,
1004 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1005 .vrefresh = 30, },
1006 /* 2 - 3840x2160@25Hz */
1007 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1008 3840, 4896, 4984, 5280, 0,
1009 2160, 2168, 2178, 2250, 0,
1010 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1011 .vrefresh = 25, },
1012 /* 3 - 3840x2160@24Hz */
1013 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1014 3840, 5116, 5204, 5500, 0,
1015 2160, 2168, 2178, 2250, 0,
1016 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1017 .vrefresh = 24, },
1018 /* 4 - 4096x2160@24Hz (SMPTE) */
1019 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1020 4096, 5116, 5204, 5500, 0,
1021 2160, 2168, 2178, 2250, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 24, },
1024};
1025
1026/*** DDC fetch and block validation ***/
1027
1028static const u8 edid_header[] = {
1029 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1030};
1031
1032/**
1033 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1034 * @raw_edid: pointer to raw base EDID block
1035 *
1036 * Sanity check the header of the base EDID block.
1037 *
1038 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1039 */
1040int drm_edid_header_is_valid(const u8 *raw_edid)
1041{
1042 int i, score = 0;
1043
1044 for (i = 0; i < sizeof(edid_header); i++)
1045 if (raw_edid[i] == edid_header[i])
1046 score++;
1047
1048 return score;
1049}
1050EXPORT_SYMBOL(drm_edid_header_is_valid);
1051
1052static int edid_fixup __read_mostly = 6;
1053module_param_named(edid_fixup, edid_fixup, int, 0400);
1054MODULE_PARM_DESC(edid_fixup,
1055 "Minimum number of valid EDID header bytes (0-8, default 6)");
1056
1057static void drm_get_displayid(struct drm_connector *connector,
1058 struct edid *edid);
1059
1060static int drm_edid_block_checksum(const u8 *raw_edid)
1061{
1062 int i;
1063 u8 csum = 0;
1064 for (i = 0; i < EDID_LENGTH; i++)
1065 csum += raw_edid[i];
1066
1067 return csum;
1068}
1069
1070static bool drm_edid_is_zero(const u8 *in_edid, int length)
1071{
1072 if (memchr_inv(in_edid, 0, length))
1073 return false;
1074
1075 return true;
1076}
1077
1078/**
1079 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1080 * @raw_edid: pointer to raw EDID block
1081 * @block: type of block to validate (0 for base, extension otherwise)
1082 * @print_bad_edid: if true, dump bad EDID blocks to the console
1083 * @edid_corrupt: if true, the header or checksum is invalid
1084 *
1085 * Validate a base or extension EDID block and optionally dump bad blocks to
1086 * the console.
1087 *
1088 * Return: True if the block is valid, false otherwise.
1089 */
1090bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1091 bool *edid_corrupt)
1092{
1093 u8 csum;
1094 struct edid *edid = (struct edid *)raw_edid;
1095
1096 if (WARN_ON(!raw_edid))
1097 return false;
1098
1099 if (edid_fixup > 8 || edid_fixup < 0)
1100 edid_fixup = 6;
1101
1102 if (block == 0) {
1103 int score = drm_edid_header_is_valid(raw_edid);
1104 if (score == 8) {
1105 if (edid_corrupt)
1106 *edid_corrupt = false;
1107 } else if (score >= edid_fixup) {
1108 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1109 * The corrupt flag needs to be set here otherwise, the
1110 * fix-up code here will correct the problem, the
1111 * checksum is correct and the test fails
1112 */
1113 if (edid_corrupt)
1114 *edid_corrupt = true;
1115 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1116 memcpy(raw_edid, edid_header, sizeof(edid_header));
1117 } else {
1118 if (edid_corrupt)
1119 *edid_corrupt = true;
1120 goto bad;
1121 }
1122 }
1123
1124 csum = drm_edid_block_checksum(raw_edid);
1125 if (csum) {
1126 if (print_bad_edid) {
1127 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1128 }
1129
1130 if (edid_corrupt)
1131 *edid_corrupt = true;
1132
1133 /* allow CEA to slide through, switches mangle this */
1134 if (raw_edid[0] != 0x02)
1135 goto bad;
1136 }
1137
1138 /* per-block-type checks */
1139 switch (raw_edid[0]) {
1140 case 0: /* base */
1141 if (edid->version != 1) {
1142 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1143 goto bad;
1144 }
1145
1146 if (edid->revision > 4)
1147 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1148 break;
1149
1150 default:
1151 break;
1152 }
1153
1154 return true;
1155
1156bad:
1157 if (print_bad_edid) {
1158 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1159 printk(KERN_ERR "EDID block is all zeroes\n");
1160 } else {
1161 printk(KERN_ERR "Raw EDID:\n");
1162 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1163 raw_edid, EDID_LENGTH, false);
1164 }
1165 }
1166 return false;
1167}
1168EXPORT_SYMBOL(drm_edid_block_valid);
1169
1170/**
1171 * drm_edid_is_valid - sanity check EDID data
1172 * @edid: EDID data
1173 *
1174 * Sanity-check an entire EDID record (including extensions)
1175 *
1176 * Return: True if the EDID data is valid, false otherwise.
1177 */
1178bool drm_edid_is_valid(struct edid *edid)
1179{
1180 int i;
1181 u8 *raw = (u8 *)edid;
1182
1183 if (!edid)
1184 return false;
1185
1186 for (i = 0; i <= edid->extensions; i++)
1187 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1188 return false;
1189
1190 return true;
1191}
1192EXPORT_SYMBOL(drm_edid_is_valid);
1193
1194#define DDC_SEGMENT_ADDR 0x30
1195/**
1196 * drm_do_probe_ddc_edid() - get EDID information via I2C
1197 * @data: I2C device adapter
1198 * @buf: EDID data buffer to be filled
1199 * @block: 128 byte EDID block to start fetching from
1200 * @len: EDID data buffer length to fetch
1201 *
1202 * Try to fetch EDID information by calling I2C driver functions.
1203 *
1204 * Return: 0 on success or -1 on failure.
1205 */
1206static int
1207drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1208{
1209 struct i2c_adapter *adapter = data;
1210 unsigned char start = block * EDID_LENGTH;
1211 unsigned char segment = block >> 1;
1212 unsigned char xfers = segment ? 3 : 2;
1213 int ret, retries = 5;
1214
1215 /*
1216 * The core I2C driver will automatically retry the transfer if the
1217 * adapter reports EAGAIN. However, we find that bit-banging transfers
1218 * are susceptible to errors under a heavily loaded machine and
1219 * generate spurious NAKs and timeouts. Retrying the transfer
1220 * of the individual block a few times seems to overcome this.
1221 */
1222 do {
1223 struct i2c_msg msgs[] = {
1224 {
1225 .addr = DDC_SEGMENT_ADDR,
1226 .flags = 0,
1227 .len = 1,
1228 .buf = &segment,
1229 }, {
1230 .addr = DDC_ADDR,
1231 .flags = 0,
1232 .len = 1,
1233 .buf = &start,
1234 }, {
1235 .addr = DDC_ADDR,
1236 .flags = I2C_M_RD,
1237 .len = len,
1238 .buf = buf,
1239 }
1240 };
1241
1242 /*
1243 * Avoid sending the segment addr to not upset non-compliant
1244 * DDC monitors.
1245 */
1246 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1247
1248 if (ret == -ENXIO) {
1249 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1250 adapter->name);
1251 break;
1252 }
1253 } while (ret != xfers && --retries);
1254
1255 return ret == xfers ? 0 : -1;
1256}
1257
1258/**
1259 * drm_do_get_edid - get EDID data using a custom EDID block read function
1260 * @connector: connector we're probing
1261 * @get_edid_block: EDID block read function
1262 * @data: private data passed to the block read function
1263 *
1264 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1265 * exposes a different interface to read EDID blocks this function can be used
1266 * to get EDID data using a custom block read function.
1267 *
1268 * As in the general case the DDC bus is accessible by the kernel at the I2C
1269 * level, drivers must make all reasonable efforts to expose it as an I2C
1270 * adapter and use drm_get_edid() instead of abusing this function.
1271 *
1272 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1273 */
1274struct edid *drm_do_get_edid(struct drm_connector *connector,
1275 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1276 size_t len),
1277 void *data)
1278{
1279 int i, j = 0, valid_extensions = 0;
1280 u8 *block, *new;
1281 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1282
1283 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1284 return NULL;
1285
1286 /* base block fetch */
1287 for (i = 0; i < 4; i++) {
1288 if (get_edid_block(data, block, 0, EDID_LENGTH))
1289 goto out;
1290 if (drm_edid_block_valid(block, 0, print_bad_edid,
1291 &connector->edid_corrupt))
1292 break;
1293 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1294 connector->null_edid_counter++;
1295 goto carp;
1296 }
1297 }
1298 if (i == 4)
1299 goto carp;
1300
1301 /* if there's no extensions, we're done */
1302 if (block[0x7e] == 0)
1303 return (struct edid *)block;
1304
1305 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1306 if (!new)
1307 goto out;
1308 block = new;
1309
1310 for (j = 1; j <= block[0x7e]; j++) {
1311 for (i = 0; i < 4; i++) {
1312 if (get_edid_block(data,
1313 block + (valid_extensions + 1) * EDID_LENGTH,
1314 j, EDID_LENGTH))
1315 goto out;
1316 if (drm_edid_block_valid(block + (valid_extensions + 1)
1317 * EDID_LENGTH, j,
1318 print_bad_edid,
1319 NULL)) {
1320 valid_extensions++;
1321 break;
1322 }
1323 }
1324
1325 if (i == 4 && print_bad_edid) {
1326 dev_warn(connector->dev->dev,
1327 "%s: Ignoring invalid EDID block %d.\n",
1328 connector->name, j);
1329
1330 connector->bad_edid_counter++;
1331 }
1332 }
1333
1334 if (valid_extensions != block[0x7e]) {
1335 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1336 block[0x7e] = valid_extensions;
1337 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1338 if (!new)
1339 goto out;
1340 block = new;
1341 }
1342
1343 return (struct edid *)block;
1344
1345carp:
1346 if (print_bad_edid) {
1347 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1348 connector->name, j);
1349 }
1350 connector->bad_edid_counter++;
1351
1352out:
1353 kfree(block);
1354 return NULL;
1355}
1356EXPORT_SYMBOL_GPL(drm_do_get_edid);
1357
1358/**
1359 * drm_probe_ddc() - probe DDC presence
1360 * @adapter: I2C adapter to probe
1361 *
1362 * Return: True on success, false on failure.
1363 */
1364bool
1365drm_probe_ddc(struct i2c_adapter *adapter)
1366{
1367 unsigned char out;
1368
1369 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1370}
1371EXPORT_SYMBOL(drm_probe_ddc);
1372
1373/**
1374 * drm_get_edid - get EDID data, if available
1375 * @connector: connector we're probing
1376 * @adapter: I2C adapter to use for DDC
1377 *
1378 * Poke the given I2C channel to grab EDID data if possible. If found,
1379 * attach it to the connector.
1380 *
1381 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1382 */
1383struct edid *drm_get_edid(struct drm_connector *connector,
1384 struct i2c_adapter *adapter)
1385{
1386 struct edid *edid;
1387
1388 if (!drm_probe_ddc(adapter))
1389 return NULL;
1390
1391 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1392 if (edid)
1393 drm_get_displayid(connector, edid);
1394 return edid;
1395}
1396EXPORT_SYMBOL(drm_get_edid);
1397
1398/**
1399 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1400 * @connector: connector we're probing
1401 * @adapter: I2C adapter to use for DDC
1402 *
1403 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1404 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1405 * switch DDC to the GPU which is retrieving EDID.
1406 *
1407 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1408 */
1409struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1410 struct i2c_adapter *adapter)
1411{
1412 struct pci_dev *pdev = connector->dev->pdev;
1413 struct edid *edid;
1414
1415 vga_switcheroo_lock_ddc(pdev);
1416 edid = drm_get_edid(connector, adapter);
1417 vga_switcheroo_unlock_ddc(pdev);
1418
1419 return edid;
1420}
1421EXPORT_SYMBOL(drm_get_edid_switcheroo);
1422
1423/**
1424 * drm_edid_duplicate - duplicate an EDID and the extensions
1425 * @edid: EDID to duplicate
1426 *
1427 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1428 */
1429struct edid *drm_edid_duplicate(const struct edid *edid)
1430{
1431 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1432}
1433EXPORT_SYMBOL(drm_edid_duplicate);
1434
1435/*** EDID parsing ***/
1436
1437/**
1438 * edid_vendor - match a string against EDID's obfuscated vendor field
1439 * @edid: EDID to match
1440 * @vendor: vendor string
1441 *
1442 * Returns true if @vendor is in @edid, false otherwise
1443 */
1444static bool edid_vendor(struct edid *edid, char *vendor)
1445{
1446 char edid_vendor[3];
1447
1448 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1449 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1450 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1451 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1452
1453 return !strncmp(edid_vendor, vendor, 3);
1454}
1455
1456/**
1457 * edid_get_quirks - return quirk flags for a given EDID
1458 * @edid: EDID to process
1459 *
1460 * This tells subsequent routines what fixes they need to apply.
1461 */
1462static u32 edid_get_quirks(struct edid *edid)
1463{
1464 struct edid_quirk *quirk;
1465 int i;
1466
1467 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1468 quirk = &edid_quirk_list[i];
1469
1470 if (edid_vendor(edid, quirk->vendor) &&
1471 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1472 return quirk->quirks;
1473 }
1474
1475 return 0;
1476}
1477
1478#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1479#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1480
1481/**
1482 * edid_fixup_preferred - set preferred modes based on quirk list
1483 * @connector: has mode list to fix up
1484 * @quirks: quirks list
1485 *
1486 * Walk the mode list for @connector, clearing the preferred status
1487 * on existing modes and setting it anew for the right mode ala @quirks.
1488 */
1489static void edid_fixup_preferred(struct drm_connector *connector,
1490 u32 quirks)
1491{
1492 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1493 int target_refresh = 0;
1494 int cur_vrefresh, preferred_vrefresh;
1495
1496 if (list_empty(&connector->probed_modes))
1497 return;
1498
1499 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1500 target_refresh = 60;
1501 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1502 target_refresh = 75;
1503
1504 preferred_mode = list_first_entry(&connector->probed_modes,
1505 struct drm_display_mode, head);
1506
1507 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1508 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1509
1510 if (cur_mode == preferred_mode)
1511 continue;
1512
1513 /* Largest mode is preferred */
1514 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1515 preferred_mode = cur_mode;
1516
1517 cur_vrefresh = cur_mode->vrefresh ?
1518 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1519 preferred_vrefresh = preferred_mode->vrefresh ?
1520 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1521 /* At a given size, try to get closest to target refresh */
1522 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1523 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1524 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1525 preferred_mode = cur_mode;
1526 }
1527 }
1528
1529 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1530}
1531
1532static bool
1533mode_is_rb(const struct drm_display_mode *mode)
1534{
1535 return (mode->htotal - mode->hdisplay == 160) &&
1536 (mode->hsync_end - mode->hdisplay == 80) &&
1537 (mode->hsync_end - mode->hsync_start == 32) &&
1538 (mode->vsync_start - mode->vdisplay == 3);
1539}
1540
1541/*
1542 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1543 * @dev: Device to duplicate against
1544 * @hsize: Mode width
1545 * @vsize: Mode height
1546 * @fresh: Mode refresh rate
1547 * @rb: Mode reduced-blanking-ness
1548 *
1549 * Walk the DMT mode list looking for a match for the given parameters.
1550 *
1551 * Return: A newly allocated copy of the mode, or NULL if not found.
1552 */
1553struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1554 int hsize, int vsize, int fresh,
1555 bool rb)
1556{
1557 int i;
1558
1559 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1560 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1561 if (hsize != ptr->hdisplay)
1562 continue;
1563 if (vsize != ptr->vdisplay)
1564 continue;
1565 if (fresh != drm_mode_vrefresh(ptr))
1566 continue;
1567 if (rb != mode_is_rb(ptr))
1568 continue;
1569
1570 return drm_mode_duplicate(dev, ptr);
1571 }
1572
1573 return NULL;
1574}
1575EXPORT_SYMBOL(drm_mode_find_dmt);
1576
1577typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1578
1579static void
1580cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1581{
1582 int i, n = 0;
1583 u8 d = ext[0x02];
1584 u8 *det_base = ext + d;
1585
1586 n = (127 - d) / 18;
1587 for (i = 0; i < n; i++)
1588 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1589}
1590
1591static void
1592vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1593{
1594 unsigned int i, n = min((int)ext[0x02], 6);
1595 u8 *det_base = ext + 5;
1596
1597 if (ext[0x01] != 1)
1598 return; /* unknown version */
1599
1600 for (i = 0; i < n; i++)
1601 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1602}
1603
1604static void
1605drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1606{
1607 int i;
1608 struct edid *edid = (struct edid *)raw_edid;
1609
1610 if (edid == NULL)
1611 return;
1612
1613 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1614 cb(&(edid->detailed_timings[i]), closure);
1615
1616 for (i = 1; i <= raw_edid[0x7e]; i++) {
1617 u8 *ext = raw_edid + (i * EDID_LENGTH);
1618 switch (*ext) {
1619 case CEA_EXT:
1620 cea_for_each_detailed_block(ext, cb, closure);
1621 break;
1622 case VTB_EXT:
1623 vtb_for_each_detailed_block(ext, cb, closure);
1624 break;
1625 default:
1626 break;
1627 }
1628 }
1629}
1630
1631static void
1632is_rb(struct detailed_timing *t, void *data)
1633{
1634 u8 *r = (u8 *)t;
1635 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1636 if (r[15] & 0x10)
1637 *(bool *)data = true;
1638}
1639
1640/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1641static bool
1642drm_monitor_supports_rb(struct edid *edid)
1643{
1644 if (edid->revision >= 4) {
1645 bool ret = false;
1646 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1647 return ret;
1648 }
1649
1650 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1651}
1652
1653static void
1654find_gtf2(struct detailed_timing *t, void *data)
1655{
1656 u8 *r = (u8 *)t;
1657 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1658 *(u8 **)data = r;
1659}
1660
1661/* Secondary GTF curve kicks in above some break frequency */
1662static int
1663drm_gtf2_hbreak(struct edid *edid)
1664{
1665 u8 *r = NULL;
1666 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1667 return r ? (r[12] * 2) : 0;
1668}
1669
1670static int
1671drm_gtf2_2c(struct edid *edid)
1672{
1673 u8 *r = NULL;
1674 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1675 return r ? r[13] : 0;
1676}
1677
1678static int
1679drm_gtf2_m(struct edid *edid)
1680{
1681 u8 *r = NULL;
1682 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1683 return r ? (r[15] << 8) + r[14] : 0;
1684}
1685
1686static int
1687drm_gtf2_k(struct edid *edid)
1688{
1689 u8 *r = NULL;
1690 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1691 return r ? r[16] : 0;
1692}
1693
1694static int
1695drm_gtf2_2j(struct edid *edid)
1696{
1697 u8 *r = NULL;
1698 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1699 return r ? r[17] : 0;
1700}
1701
1702/**
1703 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1704 * @edid: EDID block to scan
1705 */
1706static int standard_timing_level(struct edid *edid)
1707{
1708 if (edid->revision >= 2) {
1709 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1710 return LEVEL_CVT;
1711 if (drm_gtf2_hbreak(edid))
1712 return LEVEL_GTF2;
1713 return LEVEL_GTF;
1714 }
1715 return LEVEL_DMT;
1716}
1717
1718/*
1719 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1720 * monitors fill with ascii space (0x20) instead.
1721 */
1722static int
1723bad_std_timing(u8 a, u8 b)
1724{
1725 return (a == 0x00 && b == 0x00) ||
1726 (a == 0x01 && b == 0x01) ||
1727 (a == 0x20 && b == 0x20);
1728}
1729
1730/**
1731 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1732 * @connector: connector of for the EDID block
1733 * @edid: EDID block to scan
1734 * @t: standard timing params
1735 *
1736 * Take the standard timing params (in this case width, aspect, and refresh)
1737 * and convert them into a real mode using CVT/GTF/DMT.
1738 */
1739static struct drm_display_mode *
1740drm_mode_std(struct drm_connector *connector, struct edid *edid,
1741 struct std_timing *t)
1742{
1743 struct drm_device *dev = connector->dev;
1744 struct drm_display_mode *m, *mode = NULL;
1745 int hsize, vsize;
1746 int vrefresh_rate;
1747 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1748 >> EDID_TIMING_ASPECT_SHIFT;
1749 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1750 >> EDID_TIMING_VFREQ_SHIFT;
1751 int timing_level = standard_timing_level(edid);
1752
1753 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1754 return NULL;
1755
1756 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1757 hsize = t->hsize * 8 + 248;
1758 /* vrefresh_rate = vfreq + 60 */
1759 vrefresh_rate = vfreq + 60;
1760 /* the vdisplay is calculated based on the aspect ratio */
1761 if (aspect_ratio == 0) {
1762 if (edid->revision < 3)
1763 vsize = hsize;
1764 else
1765 vsize = (hsize * 10) / 16;
1766 } else if (aspect_ratio == 1)
1767 vsize = (hsize * 3) / 4;
1768 else if (aspect_ratio == 2)
1769 vsize = (hsize * 4) / 5;
1770 else
1771 vsize = (hsize * 9) / 16;
1772
1773 /* HDTV hack, part 1 */
1774 if (vrefresh_rate == 60 &&
1775 ((hsize == 1360 && vsize == 765) ||
1776 (hsize == 1368 && vsize == 769))) {
1777 hsize = 1366;
1778 vsize = 768;
1779 }
1780
1781 /*
1782 * If this connector already has a mode for this size and refresh
1783 * rate (because it came from detailed or CVT info), use that
1784 * instead. This way we don't have to guess at interlace or
1785 * reduced blanking.
1786 */
1787 list_for_each_entry(m, &connector->probed_modes, head)
1788 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1789 drm_mode_vrefresh(m) == vrefresh_rate)
1790 return NULL;
1791
1792 /* HDTV hack, part 2 */
1793 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1794 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1795 false);
1796 mode->hdisplay = 1366;
1797 mode->hsync_start = mode->hsync_start - 1;
1798 mode->hsync_end = mode->hsync_end - 1;
1799 return mode;
1800 }
1801
1802 /* check whether it can be found in default mode table */
1803 if (drm_monitor_supports_rb(edid)) {
1804 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1805 true);
1806 if (mode)
1807 return mode;
1808 }
1809 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1810 if (mode)
1811 return mode;
1812
1813 /* okay, generate it */
1814 switch (timing_level) {
1815 case LEVEL_DMT:
1816 break;
1817 case LEVEL_GTF:
1818 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1819 break;
1820 case LEVEL_GTF2:
1821 /*
1822 * This is potentially wrong if there's ever a monitor with
1823 * more than one ranges section, each claiming a different
1824 * secondary GTF curve. Please don't do that.
1825 */
1826 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1827 if (!mode)
1828 return NULL;
1829 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1830 drm_mode_destroy(dev, mode);
1831 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1832 vrefresh_rate, 0, 0,
1833 drm_gtf2_m(edid),
1834 drm_gtf2_2c(edid),
1835 drm_gtf2_k(edid),
1836 drm_gtf2_2j(edid));
1837 }
1838 break;
1839 case LEVEL_CVT:
1840 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1841 false);
1842 break;
1843 }
1844 return mode;
1845}
1846
1847/*
1848 * EDID is delightfully ambiguous about how interlaced modes are to be
1849 * encoded. Our internal representation is of frame height, but some
1850 * HDTV detailed timings are encoded as field height.
1851 *
1852 * The format list here is from CEA, in frame size. Technically we
1853 * should be checking refresh rate too. Whatever.
1854 */
1855static void
1856drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1857 struct detailed_pixel_timing *pt)
1858{
1859 int i;
1860 static const struct {
1861 int w, h;
1862 } cea_interlaced[] = {
1863 { 1920, 1080 },
1864 { 720, 480 },
1865 { 1440, 480 },
1866 { 2880, 480 },
1867 { 720, 576 },
1868 { 1440, 576 },
1869 { 2880, 576 },
1870 };
1871
1872 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1873 return;
1874
1875 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1876 if ((mode->hdisplay == cea_interlaced[i].w) &&
1877 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1878 mode->vdisplay *= 2;
1879 mode->vsync_start *= 2;
1880 mode->vsync_end *= 2;
1881 mode->vtotal *= 2;
1882 mode->vtotal |= 1;
1883 }
1884 }
1885
1886 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1887}
1888
1889/**
1890 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1891 * @dev: DRM device (needed to create new mode)
1892 * @edid: EDID block
1893 * @timing: EDID detailed timing info
1894 * @quirks: quirks to apply
1895 *
1896 * An EDID detailed timing block contains enough info for us to create and
1897 * return a new struct drm_display_mode.
1898 */
1899static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1900 struct edid *edid,
1901 struct detailed_timing *timing,
1902 u32 quirks)
1903{
1904 struct drm_display_mode *mode;
1905 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1906 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1907 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1908 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1909 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1910 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1911 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1912 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1913 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1914
1915 /* ignore tiny modes */
1916 if (hactive < 64 || vactive < 64)
1917 return NULL;
1918
1919 if (pt->misc & DRM_EDID_PT_STEREO) {
1920 DRM_DEBUG_KMS("stereo mode not supported\n");
1921 return NULL;
1922 }
1923 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
1924 DRM_DEBUG_KMS("composite sync not supported\n");
1925 }
1926
1927 /* it is incorrect if hsync/vsync width is zero */
1928 if (!hsync_pulse_width || !vsync_pulse_width) {
1929 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1930 "Wrong Hsync/Vsync pulse width\n");
1931 return NULL;
1932 }
1933
1934 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1935 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1936 if (!mode)
1937 return NULL;
1938
1939 goto set_size;
1940 }
1941
1942 mode = drm_mode_create(dev);
1943 if (!mode)
1944 return NULL;
1945
1946 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
1947 timing->pixel_clock = cpu_to_le16(1088);
1948
1949 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1950
1951 mode->hdisplay = hactive;
1952 mode->hsync_start = mode->hdisplay + hsync_offset;
1953 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1954 mode->htotal = mode->hdisplay + hblank;
1955
1956 mode->vdisplay = vactive;
1957 mode->vsync_start = mode->vdisplay + vsync_offset;
1958 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1959 mode->vtotal = mode->vdisplay + vblank;
1960
1961 /* Some EDIDs have bogus h/vtotal values */
1962 if (mode->hsync_end > mode->htotal)
1963 mode->htotal = mode->hsync_end + 1;
1964 if (mode->vsync_end > mode->vtotal)
1965 mode->vtotal = mode->vsync_end + 1;
1966
1967 drm_mode_do_interlace_quirk(mode, pt);
1968
1969 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
1970 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
1971 }
1972
1973 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1974 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1975 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1976 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
1977
1978set_size:
1979 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1980 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
1981
1982 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1983 mode->width_mm *= 10;
1984 mode->height_mm *= 10;
1985 }
1986
1987 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1988 mode->width_mm = edid->width_cm * 10;
1989 mode->height_mm = edid->height_cm * 10;
1990 }
1991
1992 mode->type = DRM_MODE_TYPE_DRIVER;
1993 mode->vrefresh = drm_mode_vrefresh(mode);
1994 drm_mode_set_name(mode);
1995
1996 return mode;
1997}
1998
1999static bool
2000mode_in_hsync_range(const struct drm_display_mode *mode,
2001 struct edid *edid, u8 *t)
2002{
2003 int hsync, hmin, hmax;
2004
2005 hmin = t[7];
2006 if (edid->revision >= 4)
2007 hmin += ((t[4] & 0x04) ? 255 : 0);
2008 hmax = t[8];
2009 if (edid->revision >= 4)
2010 hmax += ((t[4] & 0x08) ? 255 : 0);
2011 hsync = drm_mode_hsync(mode);
2012
2013 return (hsync <= hmax && hsync >= hmin);
2014}
2015
2016static bool
2017mode_in_vsync_range(const struct drm_display_mode *mode,
2018 struct edid *edid, u8 *t)
2019{
2020 int vsync, vmin, vmax;
2021
2022 vmin = t[5];
2023 if (edid->revision >= 4)
2024 vmin += ((t[4] & 0x01) ? 255 : 0);
2025 vmax = t[6];
2026 if (edid->revision >= 4)
2027 vmax += ((t[4] & 0x02) ? 255 : 0);
2028 vsync = drm_mode_vrefresh(mode);
2029
2030 return (vsync <= vmax && vsync >= vmin);
2031}
2032
2033static u32
2034range_pixel_clock(struct edid *edid, u8 *t)
2035{
2036 /* unspecified */
2037 if (t[9] == 0 || t[9] == 255)
2038 return 0;
2039
2040 /* 1.4 with CVT support gives us real precision, yay */
2041 if (edid->revision >= 4 && t[10] == 0x04)
2042 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2043
2044 /* 1.3 is pathetic, so fuzz up a bit */
2045 return t[9] * 10000 + 5001;
2046}
2047
2048static bool
2049mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2050 struct detailed_timing *timing)
2051{
2052 u32 max_clock;
2053 u8 *t = (u8 *)timing;
2054
2055 if (!mode_in_hsync_range(mode, edid, t))
2056 return false;
2057
2058 if (!mode_in_vsync_range(mode, edid, t))
2059 return false;
2060
2061 if ((max_clock = range_pixel_clock(edid, t)))
2062 if (mode->clock > max_clock)
2063 return false;
2064
2065 /* 1.4 max horizontal check */
2066 if (edid->revision >= 4 && t[10] == 0x04)
2067 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2068 return false;
2069
2070 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2071 return false;
2072
2073 return true;
2074}
2075
2076static bool valid_inferred_mode(const struct drm_connector *connector,
2077 const struct drm_display_mode *mode)
2078{
2079 const struct drm_display_mode *m;
2080 bool ok = false;
2081
2082 list_for_each_entry(m, &connector->probed_modes, head) {
2083 if (mode->hdisplay == m->hdisplay &&
2084 mode->vdisplay == m->vdisplay &&
2085 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2086 return false; /* duplicated */
2087 if (mode->hdisplay <= m->hdisplay &&
2088 mode->vdisplay <= m->vdisplay)
2089 ok = true;
2090 }
2091 return ok;
2092}
2093
2094static int
2095drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2096 struct detailed_timing *timing)
2097{
2098 int i, modes = 0;
2099 struct drm_display_mode *newmode;
2100 struct drm_device *dev = connector->dev;
2101
2102 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2103 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2104 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2105 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2106 if (newmode) {
2107 drm_mode_probed_add(connector, newmode);
2108 modes++;
2109 }
2110 }
2111 }
2112
2113 return modes;
2114}
2115
2116/* fix up 1366x768 mode from 1368x768;
2117 * GFT/CVT can't express 1366 width which isn't dividable by 8
2118 */
2119static void fixup_mode_1366x768(struct drm_display_mode *mode)
2120{
2121 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2122 mode->hdisplay = 1366;
2123 mode->hsync_start--;
2124 mode->hsync_end--;
2125 drm_mode_set_name(mode);
2126 }
2127}
2128
2129static int
2130drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2131 struct detailed_timing *timing)
2132{
2133 int i, modes = 0;
2134 struct drm_display_mode *newmode;
2135 struct drm_device *dev = connector->dev;
2136
2137 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2138 const struct minimode *m = &extra_modes[i];
2139 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2140 if (!newmode)
2141 return modes;
2142
2143 fixup_mode_1366x768(newmode);
2144 if (!mode_in_range(newmode, edid, timing) ||
2145 !valid_inferred_mode(connector, newmode)) {
2146 drm_mode_destroy(dev, newmode);
2147 continue;
2148 }
2149
2150 drm_mode_probed_add(connector, newmode);
2151 modes++;
2152 }
2153
2154 return modes;
2155}
2156
2157static int
2158drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2159 struct detailed_timing *timing)
2160{
2161 int i, modes = 0;
2162 struct drm_display_mode *newmode;
2163 struct drm_device *dev = connector->dev;
2164 bool rb = drm_monitor_supports_rb(edid);
2165
2166 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2167 const struct minimode *m = &extra_modes[i];
2168 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2169 if (!newmode)
2170 return modes;
2171
2172 fixup_mode_1366x768(newmode);
2173 if (!mode_in_range(newmode, edid, timing) ||
2174 !valid_inferred_mode(connector, newmode)) {
2175 drm_mode_destroy(dev, newmode);
2176 continue;
2177 }
2178
2179 drm_mode_probed_add(connector, newmode);
2180 modes++;
2181 }
2182
2183 return modes;
2184}
2185
2186static void
2187do_inferred_modes(struct detailed_timing *timing, void *c)
2188{
2189 struct detailed_mode_closure *closure = c;
2190 struct detailed_non_pixel *data = &timing->data.other_data;
2191 struct detailed_data_monitor_range *range = &data->data.range;
2192
2193 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2194 return;
2195
2196 closure->modes += drm_dmt_modes_for_range(closure->connector,
2197 closure->edid,
2198 timing);
2199
2200 if (!version_greater(closure->edid, 1, 1))
2201 return; /* GTF not defined yet */
2202
2203 switch (range->flags) {
2204 case 0x02: /* secondary gtf, XXX could do more */
2205 case 0x00: /* default gtf */
2206 closure->modes += drm_gtf_modes_for_range(closure->connector,
2207 closure->edid,
2208 timing);
2209 break;
2210 case 0x04: /* cvt, only in 1.4+ */
2211 if (!version_greater(closure->edid, 1, 3))
2212 break;
2213
2214 closure->modes += drm_cvt_modes_for_range(closure->connector,
2215 closure->edid,
2216 timing);
2217 break;
2218 case 0x01: /* just the ranges, no formula */
2219 default:
2220 break;
2221 }
2222}
2223
2224static int
2225add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2226{
2227 struct detailed_mode_closure closure = {
2228 .connector = connector,
2229 .edid = edid,
2230 };
2231
2232 if (version_greater(edid, 1, 0))
2233 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2234 &closure);
2235
2236 return closure.modes;
2237}
2238
2239static int
2240drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2241{
2242 int i, j, m, modes = 0;
2243 struct drm_display_mode *mode;
2244 u8 *est = ((u8 *)timing) + 6;
2245
2246 for (i = 0; i < 6; i++) {
2247 for (j = 7; j >= 0; j--) {
2248 m = (i * 8) + (7 - j);
2249 if (m >= ARRAY_SIZE(est3_modes))
2250 break;
2251 if (est[i] & (1 << j)) {
2252 mode = drm_mode_find_dmt(connector->dev,
2253 est3_modes[m].w,
2254 est3_modes[m].h,
2255 est3_modes[m].r,
2256 est3_modes[m].rb);
2257 if (mode) {
2258 drm_mode_probed_add(connector, mode);
2259 modes++;
2260 }
2261 }
2262 }
2263 }
2264
2265 return modes;
2266}
2267
2268static void
2269do_established_modes(struct detailed_timing *timing, void *c)
2270{
2271 struct detailed_mode_closure *closure = c;
2272 struct detailed_non_pixel *data = &timing->data.other_data;
2273
2274 if (data->type == EDID_DETAIL_EST_TIMINGS)
2275 closure->modes += drm_est3_modes(closure->connector, timing);
2276}
2277
2278/**
2279 * add_established_modes - get est. modes from EDID and add them
2280 * @connector: connector to add mode(s) to
2281 * @edid: EDID block to scan
2282 *
2283 * Each EDID block contains a bitmap of the supported "established modes" list
2284 * (defined above). Tease them out and add them to the global modes list.
2285 */
2286static int
2287add_established_modes(struct drm_connector *connector, struct edid *edid)
2288{
2289 struct drm_device *dev = connector->dev;
2290 unsigned long est_bits = edid->established_timings.t1 |
2291 (edid->established_timings.t2 << 8) |
2292 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2293 int i, modes = 0;
2294 struct detailed_mode_closure closure = {
2295 .connector = connector,
2296 .edid = edid,
2297 };
2298
2299 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2300 if (est_bits & (1<<i)) {
2301 struct drm_display_mode *newmode;
2302 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2303 if (newmode) {
2304 drm_mode_probed_add(connector, newmode);
2305 modes++;
2306 }
2307 }
2308 }
2309
2310 if (version_greater(edid, 1, 0))
2311 drm_for_each_detailed_block((u8 *)edid,
2312 do_established_modes, &closure);
2313
2314 return modes + closure.modes;
2315}
2316
2317static void
2318do_standard_modes(struct detailed_timing *timing, void *c)
2319{
2320 struct detailed_mode_closure *closure = c;
2321 struct detailed_non_pixel *data = &timing->data.other_data;
2322 struct drm_connector *connector = closure->connector;
2323 struct edid *edid = closure->edid;
2324
2325 if (data->type == EDID_DETAIL_STD_MODES) {
2326 int i;
2327 for (i = 0; i < 6; i++) {
2328 struct std_timing *std;
2329 struct drm_display_mode *newmode;
2330
2331 std = &data->data.timings[i];
2332 newmode = drm_mode_std(connector, edid, std);
2333 if (newmode) {
2334 drm_mode_probed_add(connector, newmode);
2335 closure->modes++;
2336 }
2337 }
2338 }
2339}
2340
2341/**
2342 * add_standard_modes - get std. modes from EDID and add them
2343 * @connector: connector to add mode(s) to
2344 * @edid: EDID block to scan
2345 *
2346 * Standard modes can be calculated using the appropriate standard (DMT,
2347 * GTF or CVT. Grab them from @edid and add them to the list.
2348 */
2349static int
2350add_standard_modes(struct drm_connector *connector, struct edid *edid)
2351{
2352 int i, modes = 0;
2353 struct detailed_mode_closure closure = {
2354 .connector = connector,
2355 .edid = edid,
2356 };
2357
2358 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2359 struct drm_display_mode *newmode;
2360
2361 newmode = drm_mode_std(connector, edid,
2362 &edid->standard_timings[i]);
2363 if (newmode) {
2364 drm_mode_probed_add(connector, newmode);
2365 modes++;
2366 }
2367 }
2368
2369 if (version_greater(edid, 1, 0))
2370 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2371 &closure);
2372
2373 /* XXX should also look for standard codes in VTB blocks */
2374
2375 return modes + closure.modes;
2376}
2377
2378static int drm_cvt_modes(struct drm_connector *connector,
2379 struct detailed_timing *timing)
2380{
2381 int i, j, modes = 0;
2382 struct drm_display_mode *newmode;
2383 struct drm_device *dev = connector->dev;
2384 struct cvt_timing *cvt;
2385 const int rates[] = { 60, 85, 75, 60, 50 };
2386 const u8 empty[3] = { 0, 0, 0 };
2387
2388 for (i = 0; i < 4; i++) {
2389 int uninitialized_var(width), height;
2390 cvt = &(timing->data.other_data.data.cvt[i]);
2391
2392 if (!memcmp(cvt->code, empty, 3))
2393 continue;
2394
2395 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2396 switch (cvt->code[1] & 0x0c) {
2397 case 0x00:
2398 width = height * 4 / 3;
2399 break;
2400 case 0x04:
2401 width = height * 16 / 9;
2402 break;
2403 case 0x08:
2404 width = height * 16 / 10;
2405 break;
2406 case 0x0c:
2407 width = height * 15 / 9;
2408 break;
2409 }
2410
2411 for (j = 1; j < 5; j++) {
2412 if (cvt->code[2] & (1 << j)) {
2413 newmode = drm_cvt_mode(dev, width, height,
2414 rates[j], j == 0,
2415 false, false);
2416 if (newmode) {
2417 drm_mode_probed_add(connector, newmode);
2418 modes++;
2419 }
2420 }
2421 }
2422 }
2423
2424 return modes;
2425}
2426
2427static void
2428do_cvt_mode(struct detailed_timing *timing, void *c)
2429{
2430 struct detailed_mode_closure *closure = c;
2431 struct detailed_non_pixel *data = &timing->data.other_data;
2432
2433 if (data->type == EDID_DETAIL_CVT_3BYTE)
2434 closure->modes += drm_cvt_modes(closure->connector, timing);
2435}
2436
2437static int
2438add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2439{
2440 struct detailed_mode_closure closure = {
2441 .connector = connector,
2442 .edid = edid,
2443 };
2444
2445 if (version_greater(edid, 1, 2))
2446 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2447
2448 /* XXX should also look for CVT codes in VTB blocks */
2449
2450 return closure.modes;
2451}
2452
2453static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2454
2455static void
2456do_detailed_mode(struct detailed_timing *timing, void *c)
2457{
2458 struct detailed_mode_closure *closure = c;
2459 struct drm_display_mode *newmode;
2460
2461 if (timing->pixel_clock) {
2462 newmode = drm_mode_detailed(closure->connector->dev,
2463 closure->edid, timing,
2464 closure->quirks);
2465 if (!newmode)
2466 return;
2467
2468 if (closure->preferred)
2469 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2470
2471 /*
2472 * Detailed modes are limited to 10kHz pixel clock resolution,
2473 * so fix up anything that looks like CEA/HDMI mode, but the clock
2474 * is just slightly off.
2475 */
2476 fixup_detailed_cea_mode_clock(newmode);
2477
2478 drm_mode_probed_add(closure->connector, newmode);
2479 closure->modes++;
2480 closure->preferred = 0;
2481 }
2482}
2483
2484/*
2485 * add_detailed_modes - Add modes from detailed timings
2486 * @connector: attached connector
2487 * @edid: EDID block to scan
2488 * @quirks: quirks to apply
2489 */
2490static int
2491add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2492 u32 quirks)
2493{
2494 struct detailed_mode_closure closure = {
2495 .connector = connector,
2496 .edid = edid,
2497 .preferred = 1,
2498 .quirks = quirks,
2499 };
2500
2501 if (closure.preferred && !version_greater(edid, 1, 3))
2502 closure.preferred =
2503 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2504
2505 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2506
2507 return closure.modes;
2508}
2509
2510#define AUDIO_BLOCK 0x01
2511#define VIDEO_BLOCK 0x02
2512#define VENDOR_BLOCK 0x03
2513#define SPEAKER_BLOCK 0x04
2514#define VIDEO_CAPABILITY_BLOCK 0x07
2515#define EDID_BASIC_AUDIO (1 << 6)
2516#define EDID_CEA_YCRCB444 (1 << 5)
2517#define EDID_CEA_YCRCB422 (1 << 4)
2518#define EDID_CEA_VCDB_QS (1 << 6)
2519
2520/*
2521 * Search EDID for CEA extension block.
2522 */
2523static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2524{
2525 u8 *edid_ext = NULL;
2526 int i;
2527
2528 /* No EDID or EDID extensions */
2529 if (edid == NULL || edid->extensions == 0)
2530 return NULL;
2531
2532 /* Find CEA extension */
2533 for (i = 0; i < edid->extensions; i++) {
2534 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2535 if (edid_ext[0] == ext_id)
2536 break;
2537 }
2538
2539 if (i == edid->extensions)
2540 return NULL;
2541
2542 return edid_ext;
2543}
2544
2545static u8 *drm_find_cea_extension(struct edid *edid)
2546{
2547 return drm_find_edid_extension(edid, CEA_EXT);
2548}
2549
2550static u8 *drm_find_displayid_extension(struct edid *edid)
2551{
2552 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2553}
2554
2555/*
2556 * Calculate the alternate clock for the CEA mode
2557 * (60Hz vs. 59.94Hz etc.)
2558 */
2559static unsigned int
2560cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2561{
2562 unsigned int clock = cea_mode->clock;
2563
2564 if (cea_mode->vrefresh % 6 != 0)
2565 return clock;
2566
2567 /*
2568 * edid_cea_modes contains the 59.94Hz
2569 * variant for 240 and 480 line modes,
2570 * and the 60Hz variant otherwise.
2571 */
2572 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2573 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2574 else
2575 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2576
2577 return clock;
2578}
2579
2580static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2581 unsigned int clock_tolerance)
2582{
2583 u8 vic;
2584
2585 if (!to_match->clock)
2586 return 0;
2587
2588 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2589 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2590 unsigned int clock1, clock2;
2591
2592 /* Check both 60Hz and 59.94Hz */
2593 clock1 = cea_mode->clock;
2594 clock2 = cea_mode_alternate_clock(cea_mode);
2595
2596 if (abs(to_match->clock - clock1) > clock_tolerance &&
2597 abs(to_match->clock - clock2) > clock_tolerance)
2598 continue;
2599
2600 if (drm_mode_equal_no_clocks(to_match, cea_mode))
2601 return vic;
2602 }
2603
2604 return 0;
2605}
2606
2607/**
2608 * drm_match_cea_mode - look for a CEA mode matching given mode
2609 * @to_match: display mode
2610 *
2611 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2612 * mode.
2613 */
2614u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2615{
2616 u8 vic;
2617
2618 if (!to_match->clock)
2619 return 0;
2620
2621 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2622 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2623 unsigned int clock1, clock2;
2624
2625 /* Check both 60Hz and 59.94Hz */
2626 clock1 = cea_mode->clock;
2627 clock2 = cea_mode_alternate_clock(cea_mode);
2628
2629 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2630 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2631 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2632 return vic;
2633 }
2634 return 0;
2635}
2636EXPORT_SYMBOL(drm_match_cea_mode);
2637
2638static bool drm_valid_cea_vic(u8 vic)
2639{
2640 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2641}
2642
2643/**
2644 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2645 * the input VIC from the CEA mode list
2646 * @video_code: ID given to each of the CEA modes
2647 *
2648 * Returns picture aspect ratio
2649 */
2650enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2651{
2652 return edid_cea_modes[video_code].picture_aspect_ratio;
2653}
2654EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2655
2656/*
2657 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2658 * specific block).
2659 *
2660 * It's almost like cea_mode_alternate_clock(), we just need to add an
2661 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2662 * one.
2663 */
2664static unsigned int
2665hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2666{
2667 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2668 return hdmi_mode->clock;
2669
2670 return cea_mode_alternate_clock(hdmi_mode);
2671}
2672
2673static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2674 unsigned int clock_tolerance)
2675{
2676 u8 vic;
2677
2678 if (!to_match->clock)
2679 return 0;
2680
2681 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2682 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2683 unsigned int clock1, clock2;
2684
2685 /* Make sure to also match alternate clocks */
2686 clock1 = hdmi_mode->clock;
2687 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2688
2689 if (abs(to_match->clock - clock1) > clock_tolerance &&
2690 abs(to_match->clock - clock2) > clock_tolerance)
2691 continue;
2692
2693 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2694 return vic;
2695 }
2696
2697 return 0;
2698}
2699
2700/*
2701 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2702 * @to_match: display mode
2703 *
2704 * An HDMI mode is one defined in the HDMI vendor specific block.
2705 *
2706 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2707 */
2708static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2709{
2710 u8 vic;
2711
2712 if (!to_match->clock)
2713 return 0;
2714
2715 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2716 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2717 unsigned int clock1, clock2;
2718
2719 /* Make sure to also match alternate clocks */
2720 clock1 = hdmi_mode->clock;
2721 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2722
2723 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2724 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2725 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2726 return vic;
2727 }
2728 return 0;
2729}
2730
2731static bool drm_valid_hdmi_vic(u8 vic)
2732{
2733 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2734}
2735
2736static int
2737add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2738{
2739 struct drm_device *dev = connector->dev;
2740 struct drm_display_mode *mode, *tmp;
2741 LIST_HEAD(list);
2742 int modes = 0;
2743
2744 /* Don't add CEA modes if the CEA extension block is missing */
2745 if (!drm_find_cea_extension(edid))
2746 return 0;
2747
2748 /*
2749 * Go through all probed modes and create a new mode
2750 * with the alternate clock for certain CEA modes.
2751 */
2752 list_for_each_entry(mode, &connector->probed_modes, head) {
2753 const struct drm_display_mode *cea_mode = NULL;
2754 struct drm_display_mode *newmode;
2755 u8 vic = drm_match_cea_mode(mode);
2756 unsigned int clock1, clock2;
2757
2758 if (drm_valid_cea_vic(vic)) {
2759 cea_mode = &edid_cea_modes[vic];
2760 clock2 = cea_mode_alternate_clock(cea_mode);
2761 } else {
2762 vic = drm_match_hdmi_mode(mode);
2763 if (drm_valid_hdmi_vic(vic)) {
2764 cea_mode = &edid_4k_modes[vic];
2765 clock2 = hdmi_mode_alternate_clock(cea_mode);
2766 }
2767 }
2768
2769 if (!cea_mode)
2770 continue;
2771
2772 clock1 = cea_mode->clock;
2773
2774 if (clock1 == clock2)
2775 continue;
2776
2777 if (mode->clock != clock1 && mode->clock != clock2)
2778 continue;
2779
2780 newmode = drm_mode_duplicate(dev, cea_mode);
2781 if (!newmode)
2782 continue;
2783
2784 /* Carry over the stereo flags */
2785 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2786
2787 /*
2788 * The current mode could be either variant. Make
2789 * sure to pick the "other" clock for the new mode.
2790 */
2791 if (mode->clock != clock1)
2792 newmode->clock = clock1;
2793 else
2794 newmode->clock = clock2;
2795
2796 list_add_tail(&newmode->head, &list);
2797 }
2798
2799 list_for_each_entry_safe(mode, tmp, &list, head) {
2800 list_del(&mode->head);
2801 drm_mode_probed_add(connector, mode);
2802 modes++;
2803 }
2804
2805 return modes;
2806}
2807
2808static struct drm_display_mode *
2809drm_display_mode_from_vic_index(struct drm_connector *connector,
2810 const u8 *video_db, u8 video_len,
2811 u8 video_index)
2812{
2813 struct drm_device *dev = connector->dev;
2814 struct drm_display_mode *newmode;
2815 u8 vic;
2816
2817 if (video_db == NULL || video_index >= video_len)
2818 return NULL;
2819
2820 /* CEA modes are numbered 1..127 */
2821 vic = (video_db[video_index] & 127);
2822 if (!drm_valid_cea_vic(vic))
2823 return NULL;
2824
2825 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
2826 if (!newmode)
2827 return NULL;
2828
2829 newmode->vrefresh = 0;
2830
2831 return newmode;
2832}
2833
2834static int
2835do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2836{
2837 int i, modes = 0;
2838
2839 for (i = 0; i < len; i++) {
2840 struct drm_display_mode *mode;
2841 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2842 if (mode) {
2843 drm_mode_probed_add(connector, mode);
2844 modes++;
2845 }
2846 }
2847
2848 return modes;
2849}
2850
2851struct stereo_mandatory_mode {
2852 int width, height, vrefresh;
2853 unsigned int flags;
2854};
2855
2856static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2857 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2858 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2859 { 1920, 1080, 50,
2860 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2861 { 1920, 1080, 60,
2862 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2863 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2864 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2865 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2866 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2867};
2868
2869static bool
2870stereo_match_mandatory(const struct drm_display_mode *mode,
2871 const struct stereo_mandatory_mode *stereo_mode)
2872{
2873 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2874
2875 return mode->hdisplay == stereo_mode->width &&
2876 mode->vdisplay == stereo_mode->height &&
2877 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2878 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2879}
2880
2881static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2882{
2883 struct drm_device *dev = connector->dev;
2884 const struct drm_display_mode *mode;
2885 struct list_head stereo_modes;
2886 int modes = 0, i;
2887
2888 INIT_LIST_HEAD(&stereo_modes);
2889
2890 list_for_each_entry(mode, &connector->probed_modes, head) {
2891 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2892 const struct stereo_mandatory_mode *mandatory;
2893 struct drm_display_mode *new_mode;
2894
2895 if (!stereo_match_mandatory(mode,
2896 &stereo_mandatory_modes[i]))
2897 continue;
2898
2899 mandatory = &stereo_mandatory_modes[i];
2900 new_mode = drm_mode_duplicate(dev, mode);
2901 if (!new_mode)
2902 continue;
2903
2904 new_mode->flags |= mandatory->flags;
2905 list_add_tail(&new_mode->head, &stereo_modes);
2906 modes++;
2907 }
2908 }
2909
2910 list_splice_tail(&stereo_modes, &connector->probed_modes);
2911
2912 return modes;
2913}
2914
2915static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2916{
2917 struct drm_device *dev = connector->dev;
2918 struct drm_display_mode *newmode;
2919
2920 if (!drm_valid_hdmi_vic(vic)) {
2921 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
2922 return 0;
2923 }
2924
2925 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
2926 if (!newmode)
2927 return 0;
2928
2929 drm_mode_probed_add(connector, newmode);
2930
2931 return 1;
2932}
2933
2934static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2935 const u8 *video_db, u8 video_len, u8 video_index)
2936{
2937 struct drm_display_mode *newmode;
2938 int modes = 0;
2939
2940 if (structure & (1 << 0)) {
2941 newmode = drm_display_mode_from_vic_index(connector, video_db,
2942 video_len,
2943 video_index);
2944 if (newmode) {
2945 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
2946 drm_mode_probed_add(connector, newmode);
2947 modes++;
2948 }
2949 }
2950 if (structure & (1 << 6)) {
2951 newmode = drm_display_mode_from_vic_index(connector, video_db,
2952 video_len,
2953 video_index);
2954 if (newmode) {
2955 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2956 drm_mode_probed_add(connector, newmode);
2957 modes++;
2958 }
2959 }
2960 if (structure & (1 << 8)) {
2961 newmode = drm_display_mode_from_vic_index(connector, video_db,
2962 video_len,
2963 video_index);
2964 if (newmode) {
2965 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2966 drm_mode_probed_add(connector, newmode);
2967 modes++;
2968 }
2969 }
2970
2971 return modes;
2972}
2973
2974/*
2975 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
2976 * @connector: connector corresponding to the HDMI sink
2977 * @db: start of the CEA vendor specific block
2978 * @len: length of the CEA block payload, ie. one can access up to db[len]
2979 *
2980 * Parses the HDMI VSDB looking for modes to add to @connector. This function
2981 * also adds the stereo 3d modes when applicable.
2982 */
2983static int
2984do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
2985 const u8 *video_db, u8 video_len)
2986{
2987 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
2988 u8 vic_len, hdmi_3d_len = 0;
2989 u16 mask;
2990 u16 structure_all;
2991
2992 if (len < 8)
2993 goto out;
2994
2995 /* no HDMI_Video_Present */
2996 if (!(db[8] & (1 << 5)))
2997 goto out;
2998
2999 /* Latency_Fields_Present */
3000 if (db[8] & (1 << 7))
3001 offset += 2;
3002
3003 /* I_Latency_Fields_Present */
3004 if (db[8] & (1 << 6))
3005 offset += 2;
3006
3007 /* the declared length is not long enough for the 2 first bytes
3008 * of additional video format capabilities */
3009 if (len < (8 + offset + 2))
3010 goto out;
3011
3012 /* 3D_Present */
3013 offset++;
3014 if (db[8 + offset] & (1 << 7)) {
3015 modes += add_hdmi_mandatory_stereo_modes(connector);
3016
3017 /* 3D_Multi_present */
3018 multi_present = (db[8 + offset] & 0x60) >> 5;
3019 }
3020
3021 offset++;
3022 vic_len = db[8 + offset] >> 5;
3023 hdmi_3d_len = db[8 + offset] & 0x1f;
3024
3025 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3026 u8 vic;
3027
3028 vic = db[9 + offset + i];
3029 modes += add_hdmi_mode(connector, vic);
3030 }
3031 offset += 1 + vic_len;
3032
3033 if (multi_present == 1)
3034 multi_len = 2;
3035 else if (multi_present == 2)
3036 multi_len = 4;
3037 else
3038 multi_len = 0;
3039
3040 if (len < (8 + offset + hdmi_3d_len - 1))
3041 goto out;
3042
3043 if (hdmi_3d_len < multi_len)
3044 goto out;
3045
3046 if (multi_present == 1 || multi_present == 2) {
3047 /* 3D_Structure_ALL */
3048 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3049
3050 /* check if 3D_MASK is present */
3051 if (multi_present == 2)
3052 mask = (db[10 + offset] << 8) | db[11 + offset];
3053 else
3054 mask = 0xffff;
3055
3056 for (i = 0; i < 16; i++) {
3057 if (mask & (1 << i))
3058 modes += add_3d_struct_modes(connector,
3059 structure_all,
3060 video_db,
3061 video_len, i);
3062 }
3063 }
3064
3065 offset += multi_len;
3066
3067 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3068 int vic_index;
3069 struct drm_display_mode *newmode = NULL;
3070 unsigned int newflag = 0;
3071 bool detail_present;
3072
3073 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3074
3075 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3076 break;
3077
3078 /* 2D_VIC_order_X */
3079 vic_index = db[8 + offset + i] >> 4;
3080
3081 /* 3D_Structure_X */
3082 switch (db[8 + offset + i] & 0x0f) {
3083 case 0:
3084 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3085 break;
3086 case 6:
3087 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3088 break;
3089 case 8:
3090 /* 3D_Detail_X */
3091 if ((db[9 + offset + i] >> 4) == 1)
3092 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3093 break;
3094 }
3095
3096 if (newflag != 0) {
3097 newmode = drm_display_mode_from_vic_index(connector,
3098 video_db,
3099 video_len,
3100 vic_index);
3101
3102 if (newmode) {
3103 newmode->flags |= newflag;
3104 drm_mode_probed_add(connector, newmode);
3105 modes++;
3106 }
3107 }
3108
3109 if (detail_present)
3110 i++;
3111 }
3112
3113out:
3114 return modes;
3115}
3116
3117static int
3118cea_db_payload_len(const u8 *db)
3119{
3120 return db[0] & 0x1f;
3121}
3122
3123static int
3124cea_db_tag(const u8 *db)
3125{
3126 return db[0] >> 5;
3127}
3128
3129static int
3130cea_revision(const u8 *cea)
3131{
3132 return cea[1];
3133}
3134
3135static int
3136cea_db_offsets(const u8 *cea, int *start, int *end)
3137{
3138 /* Data block offset in CEA extension block */
3139 *start = 4;
3140 *end = cea[2];
3141 if (*end == 0)
3142 *end = 127;
3143 if (*end < 4 || *end > 127)
3144 return -ERANGE;
3145 return 0;
3146}
3147
3148static bool cea_db_is_hdmi_vsdb(const u8 *db)
3149{
3150 int hdmi_id;
3151
3152 if (cea_db_tag(db) != VENDOR_BLOCK)
3153 return false;
3154
3155 if (cea_db_payload_len(db) < 5)
3156 return false;
3157
3158 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3159
3160 return hdmi_id == HDMI_IEEE_OUI;
3161}
3162
3163#define for_each_cea_db(cea, i, start, end) \
3164 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3165
3166static int
3167add_cea_modes(struct drm_connector *connector, struct edid *edid)
3168{
3169 const u8 *cea = drm_find_cea_extension(edid);
3170 const u8 *db, *hdmi = NULL, *video = NULL;
3171 u8 dbl, hdmi_len, video_len = 0;
3172 int modes = 0;
3173
3174 if (cea && cea_revision(cea) >= 3) {
3175 int i, start, end;
3176
3177 if (cea_db_offsets(cea, &start, &end))
3178 return 0;
3179
3180 for_each_cea_db(cea, i, start, end) {
3181 db = &cea[i];
3182 dbl = cea_db_payload_len(db);
3183
3184 if (cea_db_tag(db) == VIDEO_BLOCK) {
3185 video = db + 1;
3186 video_len = dbl;
3187 modes += do_cea_modes(connector, video, dbl);
3188 }
3189 else if (cea_db_is_hdmi_vsdb(db)) {
3190 hdmi = db;
3191 hdmi_len = dbl;
3192 }
3193 }
3194 }
3195
3196 /*
3197 * We parse the HDMI VSDB after having added the cea modes as we will
3198 * be patching their flags when the sink supports stereo 3D.
3199 */
3200 if (hdmi)
3201 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3202 video_len);
3203
3204 return modes;
3205}
3206
3207static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3208{
3209 const struct drm_display_mode *cea_mode;
3210 int clock1, clock2, clock;
3211 u8 vic;
3212 const char *type;
3213
3214 /*
3215 * allow 5kHz clock difference either way to account for
3216 * the 10kHz clock resolution limit of detailed timings.
3217 */
3218 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3219 if (drm_valid_cea_vic(vic)) {
3220 type = "CEA";
3221 cea_mode = &edid_cea_modes[vic];
3222 clock1 = cea_mode->clock;
3223 clock2 = cea_mode_alternate_clock(cea_mode);
3224 } else {
3225 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3226 if (drm_valid_hdmi_vic(vic)) {
3227 type = "HDMI";
3228 cea_mode = &edid_4k_modes[vic];
3229 clock1 = cea_mode->clock;
3230 clock2 = hdmi_mode_alternate_clock(cea_mode);
3231 } else {
3232 return;
3233 }
3234 }
3235
3236 /* pick whichever is closest */
3237 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3238 clock = clock1;
3239 else
3240 clock = clock2;
3241
3242 if (mode->clock == clock)
3243 return;
3244
3245 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3246 type, vic, mode->clock, clock);
3247 mode->clock = clock;
3248}
3249
3250static void
3251parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
3252{
3253 u8 len = cea_db_payload_len(db);
3254
3255 if (len >= 6) {
3256 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3257 connector->dvi_dual = db[6] & 1;
3258 }
3259 if (len >= 7)
3260 connector->max_tmds_clock = db[7] * 5;
3261 if (len >= 8) {
3262 connector->latency_present[0] = db[8] >> 7;
3263 connector->latency_present[1] = (db[8] >> 6) & 1;
3264 }
3265 if (len >= 9)
3266 connector->video_latency[0] = db[9];
3267 if (len >= 10)
3268 connector->audio_latency[0] = db[10];
3269 if (len >= 11)
3270 connector->video_latency[1] = db[11];
3271 if (len >= 12)
3272 connector->audio_latency[1] = db[12];
3273
3274 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3275 "max TMDS clock %d, "
3276 "latency present %d %d, "
3277 "video latency %d %d, "
3278 "audio latency %d %d\n",
3279 connector->dvi_dual,
3280 connector->max_tmds_clock,
3281 (int) connector->latency_present[0],
3282 (int) connector->latency_present[1],
3283 connector->video_latency[0],
3284 connector->video_latency[1],
3285 connector->audio_latency[0],
3286 connector->audio_latency[1]);
3287}
3288
3289static void
3290monitor_name(struct detailed_timing *t, void *data)
3291{
3292 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3293 *(u8 **)data = t->data.other_data.data.str.str;
3294}
3295
3296/**
3297 * drm_edid_to_eld - build ELD from EDID
3298 * @connector: connector corresponding to the HDMI/DP sink
3299 * @edid: EDID to parse
3300 *
3301 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3302 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3303 * fill in.
3304 */
3305void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3306{
3307 uint8_t *eld = connector->eld;
3308 u8 *cea;
3309 u8 *name;
3310 u8 *db;
3311 int total_sad_count = 0;
3312 int mnl;
3313 int dbl;
3314
3315 memset(eld, 0, sizeof(connector->eld));
3316
3317 cea = drm_find_cea_extension(edid);
3318 if (!cea) {
3319 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3320 return;
3321 }
3322
3323 name = NULL;
3324 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3325 /* max: 13 bytes EDID, 16 bytes ELD */
3326 for (mnl = 0; name && mnl < 13; mnl++) {
3327 if (name[mnl] == 0x0a)
3328 break;
3329 eld[20 + mnl] = name[mnl];
3330 }
3331 eld[4] = (cea[1] << 5) | mnl;
3332 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3333
3334 eld[0] = 2 << 3; /* ELD version: 2 */
3335
3336 eld[16] = edid->mfg_id[0];
3337 eld[17] = edid->mfg_id[1];
3338 eld[18] = edid->prod_code[0];
3339 eld[19] = edid->prod_code[1];
3340
3341 if (cea_revision(cea) >= 3) {
3342 int i, start, end;
3343
3344 if (cea_db_offsets(cea, &start, &end)) {
3345 start = 0;
3346 end = 0;
3347 }
3348
3349 for_each_cea_db(cea, i, start, end) {
3350 db = &cea[i];
3351 dbl = cea_db_payload_len(db);
3352
3353 switch (cea_db_tag(db)) {
3354 int sad_count;
3355
3356 case AUDIO_BLOCK:
3357 /* Audio Data Block, contains SADs */
3358 sad_count = min(dbl / 3, 15 - total_sad_count);
3359 if (sad_count >= 1)
3360 memcpy(eld + 20 + mnl + total_sad_count * 3,
3361 &db[1], sad_count * 3);
3362 total_sad_count += sad_count;
3363 break;
3364 case SPEAKER_BLOCK:
3365 /* Speaker Allocation Data Block */
3366 if (dbl >= 1)
3367 eld[7] = db[1];
3368 break;
3369 case VENDOR_BLOCK:
3370 /* HDMI Vendor-Specific Data Block */
3371 if (cea_db_is_hdmi_vsdb(db))
3372 parse_hdmi_vsdb(connector, db);
3373 break;
3374 default:
3375 break;
3376 }
3377 }
3378 }
3379 eld[5] |= total_sad_count << 4;
3380
3381 eld[DRM_ELD_BASELINE_ELD_LEN] =
3382 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3383
3384 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3385 drm_eld_size(eld), total_sad_count);
3386}
3387EXPORT_SYMBOL(drm_edid_to_eld);
3388
3389/**
3390 * drm_edid_to_sad - extracts SADs from EDID
3391 * @edid: EDID to parse
3392 * @sads: pointer that will be set to the extracted SADs
3393 *
3394 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3395 *
3396 * Note: The returned pointer needs to be freed using kfree().
3397 *
3398 * Return: The number of found SADs or negative number on error.
3399 */
3400int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3401{
3402 int count = 0;
3403 int i, start, end, dbl;
3404 u8 *cea;
3405
3406 cea = drm_find_cea_extension(edid);
3407 if (!cea) {
3408 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3409 return -ENOENT;
3410 }
3411
3412 if (cea_revision(cea) < 3) {
3413 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3414 return -ENOTSUPP;
3415 }
3416
3417 if (cea_db_offsets(cea, &start, &end)) {
3418 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3419 return -EPROTO;
3420 }
3421
3422 for_each_cea_db(cea, i, start, end) {
3423 u8 *db = &cea[i];
3424
3425 if (cea_db_tag(db) == AUDIO_BLOCK) {
3426 int j;
3427 dbl = cea_db_payload_len(db);
3428
3429 count = dbl / 3; /* SAD is 3B */
3430 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3431 if (!*sads)
3432 return -ENOMEM;
3433 for (j = 0; j < count; j++) {
3434 u8 *sad = &db[1 + j * 3];
3435
3436 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3437 (*sads)[j].channels = sad[0] & 0x7;
3438 (*sads)[j].freq = sad[1] & 0x7F;
3439 (*sads)[j].byte2 = sad[2];
3440 }
3441 break;
3442 }
3443 }
3444
3445 return count;
3446}
3447EXPORT_SYMBOL(drm_edid_to_sad);
3448
3449/**
3450 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3451 * @edid: EDID to parse
3452 * @sadb: pointer to the speaker block
3453 *
3454 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3455 *
3456 * Note: The returned pointer needs to be freed using kfree().
3457 *
3458 * Return: The number of found Speaker Allocation Blocks or negative number on
3459 * error.
3460 */
3461int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3462{
3463 int count = 0;
3464 int i, start, end, dbl;
3465 const u8 *cea;
3466
3467 cea = drm_find_cea_extension(edid);
3468 if (!cea) {
3469 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3470 return -ENOENT;
3471 }
3472
3473 if (cea_revision(cea) < 3) {
3474 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3475 return -ENOTSUPP;
3476 }
3477
3478 if (cea_db_offsets(cea, &start, &end)) {
3479 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3480 return -EPROTO;
3481 }
3482
3483 for_each_cea_db(cea, i, start, end) {
3484 const u8 *db = &cea[i];
3485
3486 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3487 dbl = cea_db_payload_len(db);
3488
3489 /* Speaker Allocation Data Block */
3490 if (dbl == 3) {
3491 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3492 if (!*sadb)
3493 return -ENOMEM;
3494 count = dbl;
3495 break;
3496 }
3497 }
3498 }
3499
3500 return count;
3501}
3502EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3503
3504/**
3505 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3506 * @connector: connector associated with the HDMI/DP sink
3507 * @mode: the display mode
3508 *
3509 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3510 * the sink doesn't support audio or video.
3511 */
3512int drm_av_sync_delay(struct drm_connector *connector,
3513 const struct drm_display_mode *mode)
3514{
3515 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3516 int a, v;
3517
3518 if (!connector->latency_present[0])
3519 return 0;
3520 if (!connector->latency_present[1])
3521 i = 0;
3522
3523 a = connector->audio_latency[i];
3524 v = connector->video_latency[i];
3525
3526 /*
3527 * HDMI/DP sink doesn't support audio or video?
3528 */
3529 if (a == 255 || v == 255)
3530 return 0;
3531
3532 /*
3533 * Convert raw EDID values to millisecond.
3534 * Treat unknown latency as 0ms.
3535 */
3536 if (a)
3537 a = min(2 * (a - 1), 500);
3538 if (v)
3539 v = min(2 * (v - 1), 500);
3540
3541 return max(v - a, 0);
3542}
3543EXPORT_SYMBOL(drm_av_sync_delay);
3544
3545/**
3546 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3547 * @encoder: the encoder just changed display mode
3548 *
3549 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3550 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3551 *
3552 * Return: The connector associated with the first HDMI/DP sink that has ELD
3553 * attached to it.
3554 */
3555struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
3556{
3557 struct drm_connector *connector;
3558 struct drm_device *dev = encoder->dev;
3559
3560 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
3561 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3562
3563 drm_for_each_connector(connector, dev)
3564 if (connector->encoder == encoder && connector->eld[0])
3565 return connector;
3566
3567 return NULL;
3568}
3569EXPORT_SYMBOL(drm_select_eld);
3570
3571/**
3572 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3573 * @edid: monitor EDID information
3574 *
3575 * Parse the CEA extension according to CEA-861-B.
3576 *
3577 * Return: True if the monitor is HDMI, false if not or unknown.
3578 */
3579bool drm_detect_hdmi_monitor(struct edid *edid)
3580{
3581 u8 *edid_ext;
3582 int i;
3583 int start_offset, end_offset;
3584
3585 edid_ext = drm_find_cea_extension(edid);
3586 if (!edid_ext)
3587 return false;
3588
3589 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3590 return false;
3591
3592 /*
3593 * Because HDMI identifier is in Vendor Specific Block,
3594 * search it from all data blocks of CEA extension.
3595 */
3596 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3597 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3598 return true;
3599 }
3600
3601 return false;
3602}
3603EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3604
3605/**
3606 * drm_detect_monitor_audio - check monitor audio capability
3607 * @edid: EDID block to scan
3608 *
3609 * Monitor should have CEA extension block.
3610 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3611 * audio' only. If there is any audio extension block and supported
3612 * audio format, assume at least 'basic audio' support, even if 'basic
3613 * audio' is not defined in EDID.
3614 *
3615 * Return: True if the monitor supports audio, false otherwise.
3616 */
3617bool drm_detect_monitor_audio(struct edid *edid)
3618{
3619 u8 *edid_ext;
3620 int i, j;
3621 bool has_audio = false;
3622 int start_offset, end_offset;
3623
3624 edid_ext = drm_find_cea_extension(edid);
3625 if (!edid_ext)
3626 goto end;
3627
3628 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3629
3630 if (has_audio) {
3631 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3632 goto end;
3633 }
3634
3635 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3636 goto end;
3637
3638 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3639 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3640 has_audio = true;
3641 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3642 DRM_DEBUG_KMS("CEA audio format %d\n",
3643 (edid_ext[i + j] >> 3) & 0xf);
3644 goto end;
3645 }
3646 }
3647end:
3648 return has_audio;
3649}
3650EXPORT_SYMBOL(drm_detect_monitor_audio);
3651
3652/**
3653 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3654 * @edid: EDID block to scan
3655 *
3656 * Check whether the monitor reports the RGB quantization range selection
3657 * as supported. The AVI infoframe can then be used to inform the monitor
3658 * which quantization range (full or limited) is used.
3659 *
3660 * Return: True if the RGB quantization range is selectable, false otherwise.
3661 */
3662bool drm_rgb_quant_range_selectable(struct edid *edid)
3663{
3664 u8 *edid_ext;
3665 int i, start, end;
3666
3667 edid_ext = drm_find_cea_extension(edid);
3668 if (!edid_ext)
3669 return false;
3670
3671 if (cea_db_offsets(edid_ext, &start, &end))
3672 return false;
3673
3674 for_each_cea_db(edid_ext, i, start, end) {
3675 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3676 cea_db_payload_len(&edid_ext[i]) == 2) {
3677 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3678 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3679 }
3680 }
3681
3682 return false;
3683}
3684EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3685
3686/**
3687 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
3688 * hdmi deep color modes and update drm_display_info if so.
3689 * @edid: monitor EDID information
3690 * @info: Updated with maximum supported deep color bpc and color format
3691 * if deep color supported.
3692 * @connector: DRM connector, used only for debug output
3693 *
3694 * Parse the CEA extension according to CEA-861-B.
3695 * Return true if HDMI deep color supported, false if not or unknown.
3696 */
3697static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
3698 struct drm_display_info *info,
3699 struct drm_connector *connector)
3700{
3701 u8 *edid_ext, *hdmi;
3702 int i;
3703 int start_offset, end_offset;
3704 unsigned int dc_bpc = 0;
3705
3706 edid_ext = drm_find_cea_extension(edid);
3707 if (!edid_ext)
3708 return false;
3709
3710 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3711 return false;
3712
3713 /*
3714 * Because HDMI identifier is in Vendor Specific Block,
3715 * search it from all data blocks of CEA extension.
3716 */
3717 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3718 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
3719 /* HDMI supports at least 8 bpc */
3720 info->bpc = 8;
3721
3722 hdmi = &edid_ext[i];
3723 if (cea_db_payload_len(hdmi) < 6)
3724 return false;
3725
3726 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3727 dc_bpc = 10;
3728 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3729 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3730 connector->name);
3731 }
3732
3733 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3734 dc_bpc = 12;
3735 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3736 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3737 connector->name);
3738 }
3739
3740 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3741 dc_bpc = 16;
3742 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3743 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3744 connector->name);
3745 }
3746
3747 if (dc_bpc > 0) {
3748 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3749 connector->name, dc_bpc);
3750 info->bpc = dc_bpc;
3751
3752 /*
3753 * Deep color support mandates RGB444 support for all video
3754 * modes and forbids YCRCB422 support for all video modes per
3755 * HDMI 1.3 spec.
3756 */
3757 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3758
3759 /* YCRCB444 is optional according to spec. */
3760 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3761 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3762 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3763 connector->name);
3764 }
3765
3766 /*
3767 * Spec says that if any deep color mode is supported at all,
3768 * then deep color 36 bit must be supported.
3769 */
3770 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3771 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3772 connector->name);
3773 }
3774
3775 return true;
3776 }
3777 else {
3778 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3779 connector->name);
3780 }
3781 }
3782 }
3783
3784 return false;
3785}
3786
3787/**
3788 * drm_add_display_info - pull display info out if present
3789 * @edid: EDID data
3790 * @info: display info (attached to connector)
3791 * @connector: connector whose edid is used to build display info
3792 *
3793 * Grab any available display info and stuff it into the drm_display_info
3794 * structure that's part of the connector. Useful for tracking bpp and
3795 * color spaces.
3796 */
3797static void drm_add_display_info(struct edid *edid,
3798 struct drm_display_info *info,
3799 struct drm_connector *connector)
3800{
3801 u8 *edid_ext;
3802
3803 info->width_mm = edid->width_cm * 10;
3804 info->height_mm = edid->height_cm * 10;
3805
3806 /* driver figures it out in this case */
3807 info->bpc = 0;
3808 info->color_formats = 0;
3809
3810 if (edid->revision < 3)
3811 return;
3812
3813 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3814 return;
3815
3816 /* Get data from CEA blocks if present */
3817 edid_ext = drm_find_cea_extension(edid);
3818 if (edid_ext) {
3819 info->cea_rev = edid_ext[1];
3820
3821 /* The existence of a CEA block should imply RGB support */
3822 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3823 if (edid_ext[3] & EDID_CEA_YCRCB444)
3824 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3825 if (edid_ext[3] & EDID_CEA_YCRCB422)
3826 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3827 }
3828
3829 /* HDMI deep color modes supported? Assign to info, if so */
3830 drm_assign_hdmi_deep_color_info(edid, info, connector);
3831
3832 /* Only defined for 1.4 with digital displays */
3833 if (edid->revision < 4)
3834 return;
3835
3836 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3837 case DRM_EDID_DIGITAL_DEPTH_6:
3838 info->bpc = 6;
3839 break;
3840 case DRM_EDID_DIGITAL_DEPTH_8:
3841 info->bpc = 8;
3842 break;
3843 case DRM_EDID_DIGITAL_DEPTH_10:
3844 info->bpc = 10;
3845 break;
3846 case DRM_EDID_DIGITAL_DEPTH_12:
3847 info->bpc = 12;
3848 break;
3849 case DRM_EDID_DIGITAL_DEPTH_14:
3850 info->bpc = 14;
3851 break;
3852 case DRM_EDID_DIGITAL_DEPTH_16:
3853 info->bpc = 16;
3854 break;
3855 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3856 default:
3857 info->bpc = 0;
3858 break;
3859 }
3860
3861 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3862 connector->name, info->bpc);
3863
3864 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3865 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3866 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3867 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3868 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3869}
3870
3871/**
3872 * drm_add_edid_modes - add modes from EDID data, if available
3873 * @connector: connector we're probing
3874 * @edid: EDID data
3875 *
3876 * Add the specified modes to the connector's mode list.
3877 *
3878 * Return: The number of modes added or 0 if we couldn't find any.
3879 */
3880int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3881{
3882 int num_modes = 0;
3883 u32 quirks;
3884
3885 if (edid == NULL) {
3886 return 0;
3887 }
3888 if (!drm_edid_is_valid(edid)) {
3889 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
3890 connector->name);
3891 return 0;
3892 }
3893
3894 quirks = edid_get_quirks(edid);
3895
3896 /*
3897 * EDID spec says modes should be preferred in this order:
3898 * - preferred detailed mode
3899 * - other detailed modes from base block
3900 * - detailed modes from extension blocks
3901 * - CVT 3-byte code modes
3902 * - standard timing codes
3903 * - established timing codes
3904 * - modes inferred from GTF or CVT range information
3905 *
3906 * We get this pretty much right.
3907 *
3908 * XXX order for additional mode types in extension blocks?
3909 */
3910 num_modes += add_detailed_modes(connector, edid, quirks);
3911 num_modes += add_cvt_modes(connector, edid);
3912 num_modes += add_standard_modes(connector, edid);
3913 num_modes += add_established_modes(connector, edid);
3914 num_modes += add_cea_modes(connector, edid);
3915 num_modes += add_alternate_cea_modes(connector, edid);
3916 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3917 num_modes += add_inferred_modes(connector, edid);
3918
3919 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
3920 edid_fixup_preferred(connector, quirks);
3921
3922 drm_add_display_info(edid, &connector->display_info, connector);
3923
3924 if (quirks & EDID_QUIRK_FORCE_8BPC)
3925 connector->display_info.bpc = 8;
3926
3927 if (quirks & EDID_QUIRK_FORCE_12BPC)
3928 connector->display_info.bpc = 12;
3929
3930 return num_modes;
3931}
3932EXPORT_SYMBOL(drm_add_edid_modes);
3933
3934/**
3935 * drm_add_modes_noedid - add modes for the connectors without EDID
3936 * @connector: connector we're probing
3937 * @hdisplay: the horizontal display limit
3938 * @vdisplay: the vertical display limit
3939 *
3940 * Add the specified modes to the connector's mode list. Only when the
3941 * hdisplay/vdisplay is not beyond the given limit, it will be added.
3942 *
3943 * Return: The number of modes added or 0 if we couldn't find any.
3944 */
3945int drm_add_modes_noedid(struct drm_connector *connector,
3946 int hdisplay, int vdisplay)
3947{
3948 int i, count, num_modes = 0;
3949 struct drm_display_mode *mode;
3950 struct drm_device *dev = connector->dev;
3951
3952 count = ARRAY_SIZE(drm_dmt_modes);
3953 if (hdisplay < 0)
3954 hdisplay = 0;
3955 if (vdisplay < 0)
3956 vdisplay = 0;
3957
3958 for (i = 0; i < count; i++) {
3959 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3960 if (hdisplay && vdisplay) {
3961 /*
3962 * Only when two are valid, they will be used to check
3963 * whether the mode should be added to the mode list of
3964 * the connector.
3965 */
3966 if (ptr->hdisplay > hdisplay ||
3967 ptr->vdisplay > vdisplay)
3968 continue;
3969 }
3970 if (drm_mode_vrefresh(ptr) > 61)
3971 continue;
3972 mode = drm_mode_duplicate(dev, ptr);
3973 if (mode) {
3974 drm_mode_probed_add(connector, mode);
3975 num_modes++;
3976 }
3977 }
3978 return num_modes;
3979}
3980EXPORT_SYMBOL(drm_add_modes_noedid);
3981
3982/**
3983 * drm_set_preferred_mode - Sets the preferred mode of a connector
3984 * @connector: connector whose mode list should be processed
3985 * @hpref: horizontal resolution of preferred mode
3986 * @vpref: vertical resolution of preferred mode
3987 *
3988 * Marks a mode as preferred if it matches the resolution specified by @hpref
3989 * and @vpref.
3990 */
3991void drm_set_preferred_mode(struct drm_connector *connector,
3992 int hpref, int vpref)
3993{
3994 struct drm_display_mode *mode;
3995
3996 list_for_each_entry(mode, &connector->probed_modes, head) {
3997 if (mode->hdisplay == hpref &&
3998 mode->vdisplay == vpref)
3999 mode->type |= DRM_MODE_TYPE_PREFERRED;
4000 }
4001}
4002EXPORT_SYMBOL(drm_set_preferred_mode);
4003
4004/**
4005 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4006 * data from a DRM display mode
4007 * @frame: HDMI AVI infoframe
4008 * @mode: DRM display mode
4009 *
4010 * Return: 0 on success or a negative error code on failure.
4011 */
4012int
4013drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4014 const struct drm_display_mode *mode)
4015{
4016 int err;
4017
4018 if (!frame || !mode)
4019 return -EINVAL;
4020
4021 err = hdmi_avi_infoframe_init(frame);
4022 if (err < 0)
4023 return err;
4024
4025 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4026 frame->pixel_repeat = 1;
4027
4028 frame->video_code = drm_match_cea_mode(mode);
4029
4030 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4031
4032 /*
4033 * Populate picture aspect ratio from either
4034 * user input (if specified) or from the CEA mode list.
4035 */
4036 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4037 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4038 frame->picture_aspect = mode->picture_aspect_ratio;
4039 else if (frame->video_code > 0)
4040 frame->picture_aspect = drm_get_cea_aspect_ratio(
4041 frame->video_code);
4042
4043 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4044 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4045
4046 return 0;
4047}
4048EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4049
4050static enum hdmi_3d_structure
4051s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4052{
4053 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4054
4055 switch (layout) {
4056 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4057 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4058 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4059 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4060 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4061 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4062 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4063 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4064 case DRM_MODE_FLAG_3D_L_DEPTH:
4065 return HDMI_3D_STRUCTURE_L_DEPTH;
4066 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4067 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4068 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4069 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4070 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4071 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4072 default:
4073 return HDMI_3D_STRUCTURE_INVALID;
4074 }
4075}
4076
4077/**
4078 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4079 * data from a DRM display mode
4080 * @frame: HDMI vendor infoframe
4081 * @mode: DRM display mode
4082 *
4083 * Note that there's is a need to send HDMI vendor infoframes only when using a
4084 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4085 * function will return -EINVAL, error that can be safely ignored.
4086 *
4087 * Return: 0 on success or a negative error code on failure.
4088 */
4089int
4090drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4091 const struct drm_display_mode *mode)
4092{
4093 int err;
4094 u32 s3d_flags;
4095 u8 vic;
4096
4097 if (!frame || !mode)
4098 return -EINVAL;
4099
4100 vic = drm_match_hdmi_mode(mode);
4101 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4102
4103 if (!vic && !s3d_flags)
4104 return -EINVAL;
4105
4106 if (vic && s3d_flags)
4107 return -EINVAL;
4108
4109 err = hdmi_vendor_infoframe_init(frame);
4110 if (err < 0)
4111 return err;
4112
4113 if (vic)
4114 frame->vic = vic;
4115 else
4116 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4117
4118 return 0;
4119}
4120EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4121
4122static int drm_parse_display_id(struct drm_connector *connector,
4123 u8 *displayid, int length,
4124 bool is_edid_extension)
4125{
4126 /* if this is an EDID extension the first byte will be 0x70 */
4127 int idx = 0;
4128 struct displayid_hdr *base;
4129 struct displayid_block *block;
4130 u8 csum = 0;
4131 int i;
4132
4133 if (is_edid_extension)
4134 idx = 1;
4135
4136 base = (struct displayid_hdr *)&displayid[idx];
4137
4138 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4139 base->rev, base->bytes, base->prod_id, base->ext_count);
4140
4141 if (base->bytes + 5 > length - idx)
4142 return -EINVAL;
4143
4144 for (i = idx; i <= base->bytes + 5; i++) {
4145 csum += displayid[i];
4146 }
4147 if (csum) {
4148 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
4149 return -EINVAL;
4150 }
4151
4152 block = (struct displayid_block *)&displayid[idx + 4];
4153 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n",
4154 block->tag, block->rev, block->num_bytes);
4155
4156 switch (block->tag) {
4157 case DATA_BLOCK_TILED_DISPLAY: {
4158 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4159
4160 u16 w, h;
4161 u8 tile_v_loc, tile_h_loc;
4162 u8 num_v_tile, num_h_tile;
4163 struct drm_tile_group *tg;
4164
4165 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4166 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4167
4168 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4169 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4170 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4171 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4172
4173 connector->has_tile = true;
4174 if (tile->tile_cap & 0x80)
4175 connector->tile_is_single_monitor = true;
4176
4177 connector->num_h_tile = num_h_tile + 1;
4178 connector->num_v_tile = num_v_tile + 1;
4179 connector->tile_h_loc = tile_h_loc;
4180 connector->tile_v_loc = tile_v_loc;
4181 connector->tile_h_size = w + 1;
4182 connector->tile_v_size = h + 1;
4183
4184 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4185 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4186 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4187 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4188 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4189
4190 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4191 if (!tg) {
4192 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4193 }
4194 if (!tg)
4195 return -ENOMEM;
4196
4197 if (connector->tile_group != tg) {
4198 /* if we haven't got a pointer,
4199 take the reference, drop ref to old tile group */
4200 if (connector->tile_group) {
4201 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4202 }
4203 connector->tile_group = tg;
4204 } else
4205 /* if same tile group, then release the ref we just took. */
4206 drm_mode_put_tile_group(connector->dev, tg);
4207 }
4208 break;
4209 default:
4210 printk("unknown displayid tag %d\n", block->tag);
4211 break;
4212 }
4213 return 0;
4214}
4215
4216static void drm_get_displayid(struct drm_connector *connector,
4217 struct edid *edid)
4218{
4219 void *displayid = NULL;
4220 int ret;
4221 connector->has_tile = false;
4222 displayid = drm_find_displayid_extension(edid);
4223 if (!displayid) {
4224 /* drop reference to any tile group we had */
4225 goto out_drop_ref;
4226 }
4227
4228 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4229 if (ret < 0)
4230 goto out_drop_ref;
4231 if (!connector->has_tile)
4232 goto out_drop_ref;
4233 return;
4234out_drop_ref:
4235 if (connector->tile_group) {
4236 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4237 connector->tile_group = NULL;
4238 }
4239 return;
4240}
1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31#include <linux/bitfield.h>
32#include <linux/cec.h>
33#include <linux/hdmi.h>
34#include <linux/i2c.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/slab.h>
39#include <linux/vga_switcheroo.h>
40
41#include <drm/drm_displayid.h>
42#include <drm/drm_drv.h>
43#include <drm/drm_edid.h>
44#include <drm/drm_eld.h>
45#include <drm/drm_encoder.h>
46#include <drm/drm_print.h>
47
48#include "drm_crtc_internal.h"
49#include "drm_internal.h"
50
51static int oui(u8 first, u8 second, u8 third)
52{
53 return (first << 16) | (second << 8) | third;
54}
55
56#define EDID_EST_TIMINGS 16
57#define EDID_STD_TIMINGS 8
58#define EDID_DETAILED_TIMINGS 4
59
60/*
61 * EDID blocks out in the wild have a variety of bugs, try to collect
62 * them here (note that userspace may work around broken monitors first,
63 * but fixes should make their way here so that the kernel "just works"
64 * on as many displays as possible).
65 */
66
67/* First detailed mode wrong, use largest 60Hz mode */
68#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
69/* Reported 135MHz pixel clock is too high, needs adjustment */
70#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
71/* Prefer the largest mode at 75 Hz */
72#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
73/* Detail timing is in cm not mm */
74#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
75/* Detailed timing descriptors have bogus size values, so just take the
76 * maximum size and use that.
77 */
78#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
79/* use +hsync +vsync for detailed mode */
80#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
81/* Force reduced-blanking timings for detailed modes */
82#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
83/* Force 8bpc */
84#define EDID_QUIRK_FORCE_8BPC (1 << 8)
85/* Force 12bpc */
86#define EDID_QUIRK_FORCE_12BPC (1 << 9)
87/* Force 6bpc */
88#define EDID_QUIRK_FORCE_6BPC (1 << 10)
89/* Force 10bpc */
90#define EDID_QUIRK_FORCE_10BPC (1 << 11)
91/* Non desktop display (i.e. HMD) */
92#define EDID_QUIRK_NON_DESKTOP (1 << 12)
93/* Cap the DSC target bitrate to 15bpp */
94#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
95
96#define MICROSOFT_IEEE_OUI 0xca125c
97
98struct detailed_mode_closure {
99 struct drm_connector *connector;
100 const struct drm_edid *drm_edid;
101 bool preferred;
102 int modes;
103};
104
105#define LEVEL_DMT 0
106#define LEVEL_GTF 1
107#define LEVEL_GTF2 2
108#define LEVEL_CVT 3
109
110#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
111{ \
112 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
113 product_id), \
114 .quirks = _quirks \
115}
116
117static const struct edid_quirk {
118 u32 panel_id;
119 u32 quirks;
120} edid_quirk_list[] = {
121 /* Acer AL1706 */
122 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
123 /* Acer F51 */
124 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
125
126 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
127 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
128
129 /* BenQ GW2765 */
130 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
131
132 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
133 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
134
135 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
137
138 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
139 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
140
141 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
142 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
143
144 /* Belinea 10 15 55 */
145 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
146 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
147
148 /* Envision Peripherals, Inc. EN-7100e */
149 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
150 /* Envision EN2028 */
151 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
152
153 /* Funai Electronics PM36B */
154 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
155 EDID_QUIRK_DETAILED_IN_CM),
156
157 /* LG 27GP950 */
158 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
159
160 /* LG 27GN950 */
161 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
162
163 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
164 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
165
166 /* LG Philips LCD LP154W01-A5 */
167 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
168 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
169
170 /* Samsung SyncMaster 205BW. Note: irony */
171 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
172 /* Samsung SyncMaster 22[5-6]BW */
173 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
174 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
175
176 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
177 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
178
179 /* ViewSonic VA2026w */
180 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
181
182 /* Medion MD 30217 PG */
183 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
184
185 /* Lenovo G50 */
186 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
187
188 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
189 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
190
191 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
192 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
193
194 /* Valve Index Headset */
195 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
212
213 /* HTC Vive and Vive Pro VR Headsets */
214 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
216
217 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
218 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
222
223 /* Windows Mixed Reality Headsets */
224 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
225 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
226 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
227 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
228 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
229 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
230
231 /* Sony PlayStation VR Headset */
232 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
233
234 /* Sensics VR Headsets */
235 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
236
237 /* OSVR HDK and HDK2 VR Headsets */
238 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
239 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
240};
241
242/*
243 * Autogenerated from the DMT spec.
244 * This table is copied from xfree86/modes/xf86EdidModes.c.
245 */
246static const struct drm_display_mode drm_dmt_modes[] = {
247 /* 0x01 - 640x350@85Hz */
248 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
249 736, 832, 0, 350, 382, 385, 445, 0,
250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
251 /* 0x02 - 640x400@85Hz */
252 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
253 736, 832, 0, 400, 401, 404, 445, 0,
254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
255 /* 0x03 - 720x400@85Hz */
256 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
257 828, 936, 0, 400, 401, 404, 446, 0,
258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x04 - 640x480@60Hz */
260 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
261 752, 800, 0, 480, 490, 492, 525, 0,
262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
263 /* 0x05 - 640x480@72Hz */
264 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
265 704, 832, 0, 480, 489, 492, 520, 0,
266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
267 /* 0x06 - 640x480@75Hz */
268 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
269 720, 840, 0, 480, 481, 484, 500, 0,
270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
271 /* 0x07 - 640x480@85Hz */
272 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
273 752, 832, 0, 480, 481, 484, 509, 0,
274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
275 /* 0x08 - 800x600@56Hz */
276 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
277 896, 1024, 0, 600, 601, 603, 625, 0,
278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x09 - 800x600@60Hz */
280 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
281 968, 1056, 0, 600, 601, 605, 628, 0,
282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x0a - 800x600@72Hz */
284 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
285 976, 1040, 0, 600, 637, 643, 666, 0,
286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x0b - 800x600@75Hz */
288 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
289 896, 1056, 0, 600, 601, 604, 625, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
291 /* 0x0c - 800x600@85Hz */
292 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
293 896, 1048, 0, 600, 601, 604, 631, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x0d - 800x600@120Hz RB */
296 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
297 880, 960, 0, 600, 603, 607, 636, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
299 /* 0x0e - 848x480@60Hz */
300 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
301 976, 1088, 0, 480, 486, 494, 517, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x0f - 1024x768@43Hz, interlace */
304 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
305 1208, 1264, 0, 768, 768, 776, 817, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
307 DRM_MODE_FLAG_INTERLACE) },
308 /* 0x10 - 1024x768@60Hz */
309 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
310 1184, 1344, 0, 768, 771, 777, 806, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
312 /* 0x11 - 1024x768@70Hz */
313 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
314 1184, 1328, 0, 768, 771, 777, 806, 0,
315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
316 /* 0x12 - 1024x768@75Hz */
317 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
318 1136, 1312, 0, 768, 769, 772, 800, 0,
319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
320 /* 0x13 - 1024x768@85Hz */
321 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
322 1168, 1376, 0, 768, 769, 772, 808, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
324 /* 0x14 - 1024x768@120Hz RB */
325 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
326 1104, 1184, 0, 768, 771, 775, 813, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
328 /* 0x15 - 1152x864@75Hz */
329 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
330 1344, 1600, 0, 864, 865, 868, 900, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
332 /* 0x55 - 1280x720@60Hz */
333 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
334 1430, 1650, 0, 720, 725, 730, 750, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 0x16 - 1280x768@60Hz RB */
337 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
338 1360, 1440, 0, 768, 771, 778, 790, 0,
339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
340 /* 0x17 - 1280x768@60Hz */
341 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
342 1472, 1664, 0, 768, 771, 778, 798, 0,
343 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
344 /* 0x18 - 1280x768@75Hz */
345 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
346 1488, 1696, 0, 768, 771, 778, 805, 0,
347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 0x19 - 1280x768@85Hz */
349 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
350 1496, 1712, 0, 768, 771, 778, 809, 0,
351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
352 /* 0x1a - 1280x768@120Hz RB */
353 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
354 1360, 1440, 0, 768, 771, 778, 813, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
356 /* 0x1b - 1280x800@60Hz RB */
357 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
358 1360, 1440, 0, 800, 803, 809, 823, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
360 /* 0x1c - 1280x800@60Hz */
361 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
362 1480, 1680, 0, 800, 803, 809, 831, 0,
363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 0x1d - 1280x800@75Hz */
365 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
366 1488, 1696, 0, 800, 803, 809, 838, 0,
367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
368 /* 0x1e - 1280x800@85Hz */
369 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
370 1496, 1712, 0, 800, 803, 809, 843, 0,
371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
372 /* 0x1f - 1280x800@120Hz RB */
373 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
374 1360, 1440, 0, 800, 803, 809, 847, 0,
375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
376 /* 0x20 - 1280x960@60Hz */
377 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
378 1488, 1800, 0, 960, 961, 964, 1000, 0,
379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
380 /* 0x21 - 1280x960@85Hz */
381 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
382 1504, 1728, 0, 960, 961, 964, 1011, 0,
383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 0x22 - 1280x960@120Hz RB */
385 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
386 1360, 1440, 0, 960, 963, 967, 1017, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
388 /* 0x23 - 1280x1024@60Hz */
389 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
390 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 0x24 - 1280x1024@75Hz */
393 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
394 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
396 /* 0x25 - 1280x1024@85Hz */
397 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
398 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
400 /* 0x26 - 1280x1024@120Hz RB */
401 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
402 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
404 /* 0x27 - 1360x768@60Hz */
405 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
406 1536, 1792, 0, 768, 771, 777, 795, 0,
407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
408 /* 0x28 - 1360x768@120Hz RB */
409 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
410 1440, 1520, 0, 768, 771, 776, 813, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
412 /* 0x51 - 1366x768@60Hz */
413 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
414 1579, 1792, 0, 768, 771, 774, 798, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
416 /* 0x56 - 1366x768@60Hz */
417 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
418 1436, 1500, 0, 768, 769, 772, 800, 0,
419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
420 /* 0x29 - 1400x1050@60Hz RB */
421 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
422 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
424 /* 0x2a - 1400x1050@60Hz */
425 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
426 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 0x2b - 1400x1050@75Hz */
429 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
430 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
432 /* 0x2c - 1400x1050@85Hz */
433 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
434 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
436 /* 0x2d - 1400x1050@120Hz RB */
437 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
438 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
440 /* 0x2e - 1440x900@60Hz RB */
441 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
442 1520, 1600, 0, 900, 903, 909, 926, 0,
443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
444 /* 0x2f - 1440x900@60Hz */
445 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
446 1672, 1904, 0, 900, 903, 909, 934, 0,
447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
448 /* 0x30 - 1440x900@75Hz */
449 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
450 1688, 1936, 0, 900, 903, 909, 942, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452 /* 0x31 - 1440x900@85Hz */
453 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
454 1696, 1952, 0, 900, 903, 909, 948, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 0x32 - 1440x900@120Hz RB */
457 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
458 1520, 1600, 0, 900, 903, 909, 953, 0,
459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
460 /* 0x53 - 1600x900@60Hz */
461 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
462 1704, 1800, 0, 900, 901, 904, 1000, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
464 /* 0x33 - 1600x1200@60Hz */
465 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
466 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
468 /* 0x34 - 1600x1200@65Hz */
469 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
470 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
472 /* 0x35 - 1600x1200@70Hz */
473 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
474 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
476 /* 0x36 - 1600x1200@75Hz */
477 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
478 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
480 /* 0x37 - 1600x1200@85Hz */
481 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
482 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
484 /* 0x38 - 1600x1200@120Hz RB */
485 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
486 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
488 /* 0x39 - 1680x1050@60Hz RB */
489 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
490 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
492 /* 0x3a - 1680x1050@60Hz */
493 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
494 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
496 /* 0x3b - 1680x1050@75Hz */
497 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
498 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 0x3c - 1680x1050@85Hz */
501 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
502 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
504 /* 0x3d - 1680x1050@120Hz RB */
505 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
506 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
508 /* 0x3e - 1792x1344@60Hz */
509 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
510 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
512 /* 0x3f - 1792x1344@75Hz */
513 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
514 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
516 /* 0x40 - 1792x1344@120Hz RB */
517 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
518 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
520 /* 0x41 - 1856x1392@60Hz */
521 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
522 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
524 /* 0x42 - 1856x1392@75Hz */
525 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
526 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
528 /* 0x43 - 1856x1392@120Hz RB */
529 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
530 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
532 /* 0x52 - 1920x1080@60Hz */
533 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
534 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
536 /* 0x44 - 1920x1200@60Hz RB */
537 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
538 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
540 /* 0x45 - 1920x1200@60Hz */
541 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
542 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
544 /* 0x46 - 1920x1200@75Hz */
545 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
546 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
548 /* 0x47 - 1920x1200@85Hz */
549 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
550 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
552 /* 0x48 - 1920x1200@120Hz RB */
553 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
554 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
556 /* 0x49 - 1920x1440@60Hz */
557 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
558 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
560 /* 0x4a - 1920x1440@75Hz */
561 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
562 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
564 /* 0x4b - 1920x1440@120Hz RB */
565 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
566 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
568 /* 0x54 - 2048x1152@60Hz */
569 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
570 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
572 /* 0x4c - 2560x1600@60Hz RB */
573 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
574 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
576 /* 0x4d - 2560x1600@60Hz */
577 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
578 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
580 /* 0x4e - 2560x1600@75Hz */
581 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
582 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
583 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
584 /* 0x4f - 2560x1600@85Hz */
585 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
586 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
587 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
588 /* 0x50 - 2560x1600@120Hz RB */
589 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
590 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
592 /* 0x57 - 4096x2160@60Hz RB */
593 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
594 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
596 /* 0x58 - 4096x2160@59.94Hz RB */
597 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
598 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
600};
601
602/*
603 * These more or less come from the DMT spec. The 720x400 modes are
604 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
605 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
606 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
607 * mode.
608 *
609 * The DMT modes have been fact-checked; the rest are mild guesses.
610 */
611static const struct drm_display_mode edid_est_modes[] = {
612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
613 968, 1056, 0, 600, 601, 605, 628, 0,
614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
615 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
616 896, 1024, 0, 600, 601, 603, 625, 0,
617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
619 720, 840, 0, 480, 481, 484, 500, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
622 704, 832, 0, 480, 489, 492, 520, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
625 768, 864, 0, 480, 483, 486, 525, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
628 752, 800, 0, 480, 490, 492, 525, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
631 846, 900, 0, 400, 421, 423, 449, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
633 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
634 846, 900, 0, 400, 412, 414, 449, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
636 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
637 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
640 1136, 1312, 0, 768, 769, 772, 800, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
643 1184, 1328, 0, 768, 771, 777, 806, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
645 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
646 1184, 1344, 0, 768, 771, 777, 806, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
648 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
649 1208, 1264, 0, 768, 768, 776, 817, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
651 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
652 928, 1152, 0, 624, 625, 628, 667, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
655 896, 1056, 0, 600, 601, 604, 625, 0,
656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
657 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
658 976, 1040, 0, 600, 637, 643, 666, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
660 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
661 1344, 1600, 0, 864, 865, 868, 900, 0,
662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
663};
664
665struct minimode {
666 short w;
667 short h;
668 short r;
669 short rb;
670};
671
672static const struct minimode est3_modes[] = {
673 /* byte 6 */
674 { 640, 350, 85, 0 },
675 { 640, 400, 85, 0 },
676 { 720, 400, 85, 0 },
677 { 640, 480, 85, 0 },
678 { 848, 480, 60, 0 },
679 { 800, 600, 85, 0 },
680 { 1024, 768, 85, 0 },
681 { 1152, 864, 75, 0 },
682 /* byte 7 */
683 { 1280, 768, 60, 1 },
684 { 1280, 768, 60, 0 },
685 { 1280, 768, 75, 0 },
686 { 1280, 768, 85, 0 },
687 { 1280, 960, 60, 0 },
688 { 1280, 960, 85, 0 },
689 { 1280, 1024, 60, 0 },
690 { 1280, 1024, 85, 0 },
691 /* byte 8 */
692 { 1360, 768, 60, 0 },
693 { 1440, 900, 60, 1 },
694 { 1440, 900, 60, 0 },
695 { 1440, 900, 75, 0 },
696 { 1440, 900, 85, 0 },
697 { 1400, 1050, 60, 1 },
698 { 1400, 1050, 60, 0 },
699 { 1400, 1050, 75, 0 },
700 /* byte 9 */
701 { 1400, 1050, 85, 0 },
702 { 1680, 1050, 60, 1 },
703 { 1680, 1050, 60, 0 },
704 { 1680, 1050, 75, 0 },
705 { 1680, 1050, 85, 0 },
706 { 1600, 1200, 60, 0 },
707 { 1600, 1200, 65, 0 },
708 { 1600, 1200, 70, 0 },
709 /* byte 10 */
710 { 1600, 1200, 75, 0 },
711 { 1600, 1200, 85, 0 },
712 { 1792, 1344, 60, 0 },
713 { 1792, 1344, 75, 0 },
714 { 1856, 1392, 60, 0 },
715 { 1856, 1392, 75, 0 },
716 { 1920, 1200, 60, 1 },
717 { 1920, 1200, 60, 0 },
718 /* byte 11 */
719 { 1920, 1200, 75, 0 },
720 { 1920, 1200, 85, 0 },
721 { 1920, 1440, 60, 0 },
722 { 1920, 1440, 75, 0 },
723};
724
725static const struct minimode extra_modes[] = {
726 { 1024, 576, 60, 0 },
727 { 1366, 768, 60, 0 },
728 { 1600, 900, 60, 0 },
729 { 1680, 945, 60, 0 },
730 { 1920, 1080, 60, 0 },
731 { 2048, 1152, 60, 0 },
732 { 2048, 1536, 60, 0 },
733};
734
735/*
736 * From CEA/CTA-861 spec.
737 *
738 * Do not access directly, instead always use cea_mode_for_vic().
739 */
740static const struct drm_display_mode edid_cea_modes_1[] = {
741 /* 1 - 640x480@60Hz 4:3 */
742 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
743 752, 800, 0, 480, 490, 492, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 2 - 720x480@60Hz 4:3 */
747 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
748 798, 858, 0, 480, 489, 495, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 3 - 720x480@60Hz 16:9 */
752 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
753 798, 858, 0, 480, 489, 495, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 4 - 1280x720@60Hz 16:9 */
757 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
758 1430, 1650, 0, 720, 725, 730, 750, 0,
759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 5 - 1920x1080i@60Hz 16:9 */
762 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
763 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
765 DRM_MODE_FLAG_INTERLACE),
766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
767 /* 6 - 720(1440)x480i@60Hz 4:3 */
768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
769 801, 858, 0, 480, 488, 494, 525, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
773 /* 7 - 720(1440)x480i@60Hz 16:9 */
774 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
775 801, 858, 0, 480, 488, 494, 525, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 8 - 720(1440)x240@60Hz 4:3 */
780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
781 801, 858, 0, 240, 244, 247, 262, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_DBLCLK),
784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 9 - 720(1440)x240@60Hz 16:9 */
786 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
787 801, 858, 0, 240, 244, 247, 262, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_DBLCLK),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 10 - 2880x480i@60Hz 4:3 */
792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
793 3204, 3432, 0, 480, 488, 494, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE),
796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
797 /* 11 - 2880x480i@60Hz 16:9 */
798 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
799 3204, 3432, 0, 480, 488, 494, 525, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
801 DRM_MODE_FLAG_INTERLACE),
802 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 12 - 2880x240@60Hz 4:3 */
804 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
805 3204, 3432, 0, 240, 244, 247, 262, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
808 /* 13 - 2880x240@60Hz 16:9 */
809 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
810 3204, 3432, 0, 240, 244, 247, 262, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813 /* 14 - 1440x480@60Hz 4:3 */
814 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
815 1596, 1716, 0, 480, 489, 495, 525, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
818 /* 15 - 1440x480@60Hz 16:9 */
819 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
820 1596, 1716, 0, 480, 489, 495, 525, 0,
821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 16 - 1920x1080@60Hz 16:9 */
824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
825 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 17 - 720x576@50Hz 4:3 */
829 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
830 796, 864, 0, 576, 581, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
833 /* 18 - 720x576@50Hz 16:9 */
834 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
835 796, 864, 0, 576, 581, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 19 - 1280x720@50Hz 16:9 */
839 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
840 1760, 1980, 0, 720, 725, 730, 750, 0,
841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 20 - 1920x1080i@50Hz 16:9 */
844 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
845 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
847 DRM_MODE_FLAG_INTERLACE),
848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
849 /* 21 - 720(1440)x576i@50Hz 4:3 */
850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
851 795, 864, 0, 576, 580, 586, 625, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
855 /* 22 - 720(1440)x576i@50Hz 16:9 */
856 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
857 795, 864, 0, 576, 580, 586, 625, 0,
858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
859 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
861 /* 23 - 720(1440)x288@50Hz 4:3 */
862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
863 795, 864, 0, 288, 290, 293, 312, 0,
864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
865 DRM_MODE_FLAG_DBLCLK),
866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
867 /* 24 - 720(1440)x288@50Hz 16:9 */
868 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
869 795, 864, 0, 288, 290, 293, 312, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
871 DRM_MODE_FLAG_DBLCLK),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 25 - 2880x576i@50Hz 4:3 */
874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
875 3180, 3456, 0, 576, 580, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
877 DRM_MODE_FLAG_INTERLACE),
878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
879 /* 26 - 2880x576i@50Hz 16:9 */
880 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
881 3180, 3456, 0, 576, 580, 586, 625, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
883 DRM_MODE_FLAG_INTERLACE),
884 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
885 /* 27 - 2880x288@50Hz 4:3 */
886 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
887 3180, 3456, 0, 288, 290, 293, 312, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
890 /* 28 - 2880x288@50Hz 16:9 */
891 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
892 3180, 3456, 0, 288, 290, 293, 312, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895 /* 29 - 1440x576@50Hz 4:3 */
896 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
897 1592, 1728, 0, 576, 581, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
900 /* 30 - 1440x576@50Hz 16:9 */
901 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
902 1592, 1728, 0, 576, 581, 586, 625, 0,
903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905 /* 31 - 1920x1080@50Hz 16:9 */
906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
907 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 32 - 1920x1080@24Hz 16:9 */
911 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
912 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 33 - 1920x1080@25Hz 16:9 */
916 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
917 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
920 /* 34 - 1920x1080@30Hz 16:9 */
921 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
922 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
923 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 35 - 2880x480@60Hz 4:3 */
926 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
927 3192, 3432, 0, 480, 489, 495, 525, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
930 /* 36 - 2880x480@60Hz 16:9 */
931 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
932 3192, 3432, 0, 480, 489, 495, 525, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 37 - 2880x576@50Hz 4:3 */
936 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
937 3184, 3456, 0, 576, 581, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
940 /* 38 - 2880x576@50Hz 16:9 */
941 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
942 3184, 3456, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 39 - 1920x1080i@50Hz 16:9 */
946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
947 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
949 DRM_MODE_FLAG_INTERLACE),
950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
951 /* 40 - 1920x1080i@100Hz 16:9 */
952 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
953 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
955 DRM_MODE_FLAG_INTERLACE),
956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957 /* 41 - 1280x720@100Hz 16:9 */
958 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
959 1760, 1980, 0, 720, 725, 730, 750, 0,
960 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 42 - 720x576@100Hz 4:3 */
963 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
964 796, 864, 0, 576, 581, 586, 625, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
967 /* 43 - 720x576@100Hz 16:9 */
968 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
969 796, 864, 0, 576, 581, 586, 625, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972 /* 44 - 720(1440)x576i@100Hz 4:3 */
973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
974 795, 864, 0, 576, 580, 586, 625, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
978 /* 45 - 720(1440)x576i@100Hz 16:9 */
979 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
980 795, 864, 0, 576, 580, 586, 625, 0,
981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
982 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 46 - 1920x1080i@120Hz 16:9 */
985 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
986 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
988 DRM_MODE_FLAG_INTERLACE),
989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
990 /* 47 - 1280x720@120Hz 16:9 */
991 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
992 1430, 1650, 0, 720, 725, 730, 750, 0,
993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 48 - 720x480@120Hz 4:3 */
996 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
997 798, 858, 0, 480, 489, 495, 525, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000 /* 49 - 720x480@120Hz 16:9 */
1001 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1002 798, 858, 0, 480, 489, 495, 525, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 50 - 720(1440)x480i@120Hz 4:3 */
1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1007 801, 858, 0, 480, 488, 494, 525, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011 /* 51 - 720(1440)x480i@120Hz 16:9 */
1012 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1013 801, 858, 0, 480, 488, 494, 525, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 52 - 720x576@200Hz 4:3 */
1018 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1019 796, 864, 0, 576, 581, 586, 625, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1022 /* 53 - 720x576@200Hz 16:9 */
1023 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1024 796, 864, 0, 576, 581, 586, 625, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027 /* 54 - 720(1440)x576i@200Hz 4:3 */
1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1029 795, 864, 0, 576, 580, 586, 625, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1033 /* 55 - 720(1440)x576i@200Hz 16:9 */
1034 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1035 795, 864, 0, 576, 580, 586, 625, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 56 - 720x480@240Hz 4:3 */
1040 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1041 798, 858, 0, 480, 489, 495, 525, 0,
1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1044 /* 57 - 720x480@240Hz 16:9 */
1045 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1046 798, 858, 0, 480, 489, 495, 525, 0,
1047 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1049 /* 58 - 720(1440)x480i@240Hz 4:3 */
1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1051 801, 858, 0, 480, 488, 494, 525, 0,
1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1055 /* 59 - 720(1440)x480i@240Hz 16:9 */
1056 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1057 801, 858, 0, 480, 488, 494, 525, 0,
1058 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1059 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1060 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1061 /* 60 - 1280x720@24Hz 16:9 */
1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1063 3080, 3300, 0, 720, 725, 730, 750, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1066 /* 61 - 1280x720@25Hz 16:9 */
1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1068 3740, 3960, 0, 720, 725, 730, 750, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1071 /* 62 - 1280x720@30Hz 16:9 */
1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1073 3080, 3300, 0, 720, 725, 730, 750, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1076 /* 63 - 1920x1080@120Hz 16:9 */
1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1078 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1081 /* 64 - 1920x1080@100Hz 16:9 */
1082 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1083 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1086 /* 65 - 1280x720@24Hz 64:27 */
1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1088 3080, 3300, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 66 - 1280x720@25Hz 64:27 */
1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1093 3740, 3960, 0, 720, 725, 730, 750, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 67 - 1280x720@30Hz 64:27 */
1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1098 3080, 3300, 0, 720, 725, 730, 750, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 68 - 1280x720@50Hz 64:27 */
1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1103 1760, 1980, 0, 720, 725, 730, 750, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 69 - 1280x720@60Hz 64:27 */
1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1108 1430, 1650, 0, 720, 725, 730, 750, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 70 - 1280x720@100Hz 64:27 */
1112 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1113 1760, 1980, 0, 720, 725, 730, 750, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 71 - 1280x720@120Hz 64:27 */
1117 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1118 1430, 1650, 0, 720, 725, 730, 750, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 72 - 1920x1080@24Hz 64:27 */
1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1123 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 73 - 1920x1080@25Hz 64:27 */
1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 74 - 1920x1080@30Hz 64:27 */
1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 75 - 1920x1080@50Hz 64:27 */
1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1138 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 76 - 1920x1080@60Hz 64:27 */
1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1143 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 77 - 1920x1080@100Hz 64:27 */
1147 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1148 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 78 - 1920x1080@120Hz 64:27 */
1152 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1153 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156 /* 79 - 1680x720@24Hz 64:27 */
1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1158 3080, 3300, 0, 720, 725, 730, 750, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161 /* 80 - 1680x720@25Hz 64:27 */
1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1163 2948, 3168, 0, 720, 725, 730, 750, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166 /* 81 - 1680x720@30Hz 64:27 */
1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1168 2420, 2640, 0, 720, 725, 730, 750, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171 /* 82 - 1680x720@50Hz 64:27 */
1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1173 1980, 2200, 0, 720, 725, 730, 750, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176 /* 83 - 1680x720@60Hz 64:27 */
1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1178 1980, 2200, 0, 720, 725, 730, 750, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181 /* 84 - 1680x720@100Hz 64:27 */
1182 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1183 1780, 2000, 0, 720, 725, 730, 825, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186 /* 85 - 1680x720@120Hz 64:27 */
1187 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1188 1780, 2000, 0, 720, 725, 730, 825, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191 /* 86 - 2560x1080@24Hz 64:27 */
1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1193 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196 /* 87 - 2560x1080@25Hz 64:27 */
1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1198 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201 /* 88 - 2560x1080@30Hz 64:27 */
1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1203 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206 /* 89 - 2560x1080@50Hz 64:27 */
1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1208 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211 /* 90 - 2560x1080@60Hz 64:27 */
1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1213 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1216 /* 91 - 2560x1080@100Hz 64:27 */
1217 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1218 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1221 /* 92 - 2560x1080@120Hz 64:27 */
1222 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1223 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1226 /* 93 - 3840x2160@24Hz 16:9 */
1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1228 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1231 /* 94 - 3840x2160@25Hz 16:9 */
1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1233 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1236 /* 95 - 3840x2160@30Hz 16:9 */
1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1238 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1241 /* 96 - 3840x2160@50Hz 16:9 */
1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1243 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1246 /* 97 - 3840x2160@60Hz 16:9 */
1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1248 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1251 /* 98 - 4096x2160@24Hz 256:135 */
1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1253 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1256 /* 99 - 4096x2160@25Hz 256:135 */
1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1258 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1261 /* 100 - 4096x2160@30Hz 256:135 */
1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1263 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1266 /* 101 - 4096x2160@50Hz 256:135 */
1267 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1268 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1271 /* 102 - 4096x2160@60Hz 256:135 */
1272 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1273 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1276 /* 103 - 3840x2160@24Hz 64:27 */
1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1278 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1281 /* 104 - 3840x2160@25Hz 64:27 */
1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1283 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1286 /* 105 - 3840x2160@30Hz 64:27 */
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1288 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1291 /* 106 - 3840x2160@50Hz 64:27 */
1292 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1293 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1296 /* 107 - 3840x2160@60Hz 64:27 */
1297 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1298 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1301 /* 108 - 1280x720@48Hz 16:9 */
1302 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1303 2280, 2500, 0, 720, 725, 730, 750, 0,
1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1306 /* 109 - 1280x720@48Hz 64:27 */
1307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1308 2280, 2500, 0, 720, 725, 730, 750, 0,
1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1311 /* 110 - 1680x720@48Hz 64:27 */
1312 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1313 2530, 2750, 0, 720, 725, 730, 750, 0,
1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1316 /* 111 - 1920x1080@48Hz 16:9 */
1317 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1318 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1321 /* 112 - 1920x1080@48Hz 64:27 */
1322 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1323 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1326 /* 113 - 2560x1080@48Hz 64:27 */
1327 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1328 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1331 /* 114 - 3840x2160@48Hz 16:9 */
1332 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1333 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1336 /* 115 - 4096x2160@48Hz 256:135 */
1337 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1338 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1341 /* 116 - 3840x2160@48Hz 64:27 */
1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1343 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1346 /* 117 - 3840x2160@100Hz 16:9 */
1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1348 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1351 /* 118 - 3840x2160@120Hz 16:9 */
1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1353 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1356 /* 119 - 3840x2160@100Hz 64:27 */
1357 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1358 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1361 /* 120 - 3840x2160@120Hz 64:27 */
1362 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1363 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1366 /* 121 - 5120x2160@24Hz 64:27 */
1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1368 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1371 /* 122 - 5120x2160@25Hz 64:27 */
1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1373 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1376 /* 123 - 5120x2160@30Hz 64:27 */
1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1378 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381 /* 124 - 5120x2160@48Hz 64:27 */
1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1383 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1386 /* 125 - 5120x2160@50Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1388 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391 /* 126 - 5120x2160@60Hz 64:27 */
1392 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1393 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1396 /* 127 - 5120x2160@100Hz 64:27 */
1397 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1398 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1400 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1401};
1402
1403/*
1404 * From CEA/CTA-861 spec.
1405 *
1406 * Do not access directly, instead always use cea_mode_for_vic().
1407 */
1408static const struct drm_display_mode edid_cea_modes_193[] = {
1409 /* 193 - 5120x2160@120Hz 64:27 */
1410 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1411 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1414 /* 194 - 7680x4320@24Hz 16:9 */
1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1416 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1419 /* 195 - 7680x4320@25Hz 16:9 */
1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1421 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1424 /* 196 - 7680x4320@30Hz 16:9 */
1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1426 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1429 /* 197 - 7680x4320@48Hz 16:9 */
1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1431 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1434 /* 198 - 7680x4320@50Hz 16:9 */
1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1436 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1439 /* 199 - 7680x4320@60Hz 16:9 */
1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1441 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1444 /* 200 - 7680x4320@100Hz 16:9 */
1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1446 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1449 /* 201 - 7680x4320@120Hz 16:9 */
1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1451 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1454 /* 202 - 7680x4320@24Hz 64:27 */
1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1456 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1459 /* 203 - 7680x4320@25Hz 64:27 */
1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1461 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1464 /* 204 - 7680x4320@30Hz 64:27 */
1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1466 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1469 /* 205 - 7680x4320@48Hz 64:27 */
1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1471 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1474 /* 206 - 7680x4320@50Hz 64:27 */
1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1476 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1479 /* 207 - 7680x4320@60Hz 64:27 */
1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1481 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1484 /* 208 - 7680x4320@100Hz 64:27 */
1485 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1486 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1489 /* 209 - 7680x4320@120Hz 64:27 */
1490 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1491 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1494 /* 210 - 10240x4320@24Hz 64:27 */
1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1496 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1499 /* 211 - 10240x4320@25Hz 64:27 */
1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1501 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1504 /* 212 - 10240x4320@30Hz 64:27 */
1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1506 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1509 /* 213 - 10240x4320@48Hz 64:27 */
1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1511 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1514 /* 214 - 10240x4320@50Hz 64:27 */
1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1516 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1519 /* 215 - 10240x4320@60Hz 64:27 */
1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1521 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1524 /* 216 - 10240x4320@100Hz 64:27 */
1525 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1526 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1529 /* 217 - 10240x4320@120Hz 64:27 */
1530 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1531 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1534 /* 218 - 4096x2160@100Hz 256:135 */
1535 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1536 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1538 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1539 /* 219 - 4096x2160@120Hz 256:135 */
1540 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1541 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1544};
1545
1546/*
1547 * HDMI 1.4 4k modes. Index using the VIC.
1548 */
1549static const struct drm_display_mode edid_4k_modes[] = {
1550 /* 0 - dummy, VICs start at 1 */
1551 { },
1552 /* 1 - 3840x2160@30Hz */
1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1554 3840, 4016, 4104, 4400, 0,
1555 2160, 2168, 2178, 2250, 0,
1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1558 /* 2 - 3840x2160@25Hz */
1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1560 3840, 4896, 4984, 5280, 0,
1561 2160, 2168, 2178, 2250, 0,
1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1564 /* 3 - 3840x2160@24Hz */
1565 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1566 3840, 5116, 5204, 5500, 0,
1567 2160, 2168, 2178, 2250, 0,
1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1570 /* 4 - 4096x2160@24Hz (SMPTE) */
1571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1572 4096, 5116, 5204, 5500, 0,
1573 2160, 2168, 2178, 2250, 0,
1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1575 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1576};
1577
1578/*** DDC fetch and block validation ***/
1579
1580/*
1581 * The opaque EDID type, internal to drm_edid.c.
1582 */
1583struct drm_edid {
1584 /* Size allocated for edid */
1585 size_t size;
1586 const struct edid *edid;
1587};
1588
1589static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1590
1591static int edid_hfeeodb_block_count(const struct edid *edid)
1592{
1593 int eeodb = edid_hfeeodb_extension_block_count(edid);
1594
1595 return eeodb ? eeodb + 1 : 0;
1596}
1597
1598static int edid_extension_block_count(const struct edid *edid)
1599{
1600 return edid->extensions;
1601}
1602
1603static int edid_block_count(const struct edid *edid)
1604{
1605 return edid_extension_block_count(edid) + 1;
1606}
1607
1608static int edid_size_by_blocks(int num_blocks)
1609{
1610 return num_blocks * EDID_LENGTH;
1611}
1612
1613static int edid_size(const struct edid *edid)
1614{
1615 return edid_size_by_blocks(edid_block_count(edid));
1616}
1617
1618static const void *edid_block_data(const struct edid *edid, int index)
1619{
1620 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1621
1622 return edid + index;
1623}
1624
1625static const void *edid_extension_block_data(const struct edid *edid, int index)
1626{
1627 return edid_block_data(edid, index + 1);
1628}
1629
1630/* EDID block count indicated in EDID, may exceed allocated size */
1631static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1632{
1633 int num_blocks;
1634
1635 /* Starting point */
1636 num_blocks = edid_block_count(drm_edid->edid);
1637
1638 /* HF-EEODB override */
1639 if (drm_edid->size >= edid_size_by_blocks(2)) {
1640 int eeodb;
1641
1642 /*
1643 * Note: HF-EEODB may specify a smaller extension count than the
1644 * regular one. Unlike in buffer allocation, here we can use it.
1645 */
1646 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1647 if (eeodb)
1648 num_blocks = eeodb;
1649 }
1650
1651 return num_blocks;
1652}
1653
1654/* EDID block count, limited by allocated size */
1655static int drm_edid_block_count(const struct drm_edid *drm_edid)
1656{
1657 /* Limit by allocated size */
1658 return min(__drm_edid_block_count(drm_edid),
1659 (int)drm_edid->size / EDID_LENGTH);
1660}
1661
1662/* EDID extension block count, limited by allocated size */
1663static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1664{
1665 return drm_edid_block_count(drm_edid) - 1;
1666}
1667
1668static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1669{
1670 return edid_block_data(drm_edid->edid, index);
1671}
1672
1673static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1674 int index)
1675{
1676 return edid_extension_block_data(drm_edid->edid, index);
1677}
1678
1679/*
1680 * Initializer helper for legacy interfaces, where we have no choice but to
1681 * trust edid size. Not for general purpose use.
1682 */
1683static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1684 const struct edid *edid)
1685{
1686 if (!edid)
1687 return NULL;
1688
1689 memset(drm_edid, 0, sizeof(*drm_edid));
1690
1691 drm_edid->edid = edid;
1692 drm_edid->size = edid_size(edid);
1693
1694 return drm_edid;
1695}
1696
1697/*
1698 * EDID base and extension block iterator.
1699 *
1700 * struct drm_edid_iter iter;
1701 * const u8 *block;
1702 *
1703 * drm_edid_iter_begin(drm_edid, &iter);
1704 * drm_edid_iter_for_each(block, &iter) {
1705 * // do stuff with block
1706 * }
1707 * drm_edid_iter_end(&iter);
1708 */
1709struct drm_edid_iter {
1710 const struct drm_edid *drm_edid;
1711
1712 /* Current block index. */
1713 int index;
1714};
1715
1716static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1717 struct drm_edid_iter *iter)
1718{
1719 memset(iter, 0, sizeof(*iter));
1720
1721 iter->drm_edid = drm_edid;
1722}
1723
1724static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1725{
1726 const void *block = NULL;
1727
1728 if (!iter->drm_edid)
1729 return NULL;
1730
1731 if (iter->index < drm_edid_block_count(iter->drm_edid))
1732 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1733
1734 return block;
1735}
1736
1737#define drm_edid_iter_for_each(__block, __iter) \
1738 while (((__block) = __drm_edid_iter_next(__iter)))
1739
1740static void drm_edid_iter_end(struct drm_edid_iter *iter)
1741{
1742 memset(iter, 0, sizeof(*iter));
1743}
1744
1745static const u8 edid_header[] = {
1746 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1747};
1748
1749static void edid_header_fix(void *edid)
1750{
1751 memcpy(edid, edid_header, sizeof(edid_header));
1752}
1753
1754/**
1755 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1756 * @_edid: pointer to raw base EDID block
1757 *
1758 * Sanity check the header of the base EDID block.
1759 *
1760 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1761 */
1762int drm_edid_header_is_valid(const void *_edid)
1763{
1764 const struct edid *edid = _edid;
1765 int i, score = 0;
1766
1767 for (i = 0; i < sizeof(edid_header); i++) {
1768 if (edid->header[i] == edid_header[i])
1769 score++;
1770 }
1771
1772 return score;
1773}
1774EXPORT_SYMBOL(drm_edid_header_is_valid);
1775
1776static int edid_fixup __read_mostly = 6;
1777module_param_named(edid_fixup, edid_fixup, int, 0400);
1778MODULE_PARM_DESC(edid_fixup,
1779 "Minimum number of valid EDID header bytes (0-8, default 6)");
1780
1781static int edid_block_compute_checksum(const void *_block)
1782{
1783 const u8 *block = _block;
1784 int i;
1785 u8 csum = 0, crc = 0;
1786
1787 for (i = 0; i < EDID_LENGTH - 1; i++)
1788 csum += block[i];
1789
1790 crc = 0x100 - csum;
1791
1792 return crc;
1793}
1794
1795static int edid_block_get_checksum(const void *_block)
1796{
1797 const struct edid *block = _block;
1798
1799 return block->checksum;
1800}
1801
1802static int edid_block_tag(const void *_block)
1803{
1804 const u8 *block = _block;
1805
1806 return block[0];
1807}
1808
1809static bool edid_block_is_zero(const void *edid)
1810{
1811 return !memchr_inv(edid, 0, EDID_LENGTH);
1812}
1813
1814/**
1815 * drm_edid_are_equal - compare two edid blobs.
1816 * @edid1: pointer to first blob
1817 * @edid2: pointer to second blob
1818 * This helper can be used during probing to determine if
1819 * edid had changed.
1820 */
1821bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1822{
1823 int edid1_len, edid2_len;
1824 bool edid1_present = edid1 != NULL;
1825 bool edid2_present = edid2 != NULL;
1826
1827 if (edid1_present != edid2_present)
1828 return false;
1829
1830 if (edid1) {
1831 edid1_len = edid_size(edid1);
1832 edid2_len = edid_size(edid2);
1833
1834 if (edid1_len != edid2_len)
1835 return false;
1836
1837 if (memcmp(edid1, edid2, edid1_len))
1838 return false;
1839 }
1840
1841 return true;
1842}
1843EXPORT_SYMBOL(drm_edid_are_equal);
1844
1845enum edid_block_status {
1846 EDID_BLOCK_OK = 0,
1847 EDID_BLOCK_READ_FAIL,
1848 EDID_BLOCK_NULL,
1849 EDID_BLOCK_ZERO,
1850 EDID_BLOCK_HEADER_CORRUPT,
1851 EDID_BLOCK_HEADER_REPAIR,
1852 EDID_BLOCK_HEADER_FIXED,
1853 EDID_BLOCK_CHECKSUM,
1854 EDID_BLOCK_VERSION,
1855};
1856
1857static enum edid_block_status edid_block_check(const void *_block,
1858 bool is_base_block)
1859{
1860 const struct edid *block = _block;
1861
1862 if (!block)
1863 return EDID_BLOCK_NULL;
1864
1865 if (is_base_block) {
1866 int score = drm_edid_header_is_valid(block);
1867
1868 if (score < clamp(edid_fixup, 0, 8)) {
1869 if (edid_block_is_zero(block))
1870 return EDID_BLOCK_ZERO;
1871 else
1872 return EDID_BLOCK_HEADER_CORRUPT;
1873 }
1874
1875 if (score < 8)
1876 return EDID_BLOCK_HEADER_REPAIR;
1877 }
1878
1879 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1880 if (edid_block_is_zero(block))
1881 return EDID_BLOCK_ZERO;
1882 else
1883 return EDID_BLOCK_CHECKSUM;
1884 }
1885
1886 if (is_base_block) {
1887 if (block->version != 1)
1888 return EDID_BLOCK_VERSION;
1889 }
1890
1891 return EDID_BLOCK_OK;
1892}
1893
1894static bool edid_block_status_valid(enum edid_block_status status, int tag)
1895{
1896 return status == EDID_BLOCK_OK ||
1897 status == EDID_BLOCK_HEADER_FIXED ||
1898 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1899}
1900
1901static bool edid_block_valid(const void *block, bool base)
1902{
1903 return edid_block_status_valid(edid_block_check(block, base),
1904 edid_block_tag(block));
1905}
1906
1907static void edid_block_status_print(enum edid_block_status status,
1908 const struct edid *block,
1909 int block_num)
1910{
1911 switch (status) {
1912 case EDID_BLOCK_OK:
1913 break;
1914 case EDID_BLOCK_READ_FAIL:
1915 pr_debug("EDID block %d read failed\n", block_num);
1916 break;
1917 case EDID_BLOCK_NULL:
1918 pr_debug("EDID block %d pointer is NULL\n", block_num);
1919 break;
1920 case EDID_BLOCK_ZERO:
1921 pr_notice("EDID block %d is all zeroes\n", block_num);
1922 break;
1923 case EDID_BLOCK_HEADER_CORRUPT:
1924 pr_notice("EDID has corrupt header\n");
1925 break;
1926 case EDID_BLOCK_HEADER_REPAIR:
1927 pr_debug("EDID corrupt header needs repair\n");
1928 break;
1929 case EDID_BLOCK_HEADER_FIXED:
1930 pr_debug("EDID corrupt header fixed\n");
1931 break;
1932 case EDID_BLOCK_CHECKSUM:
1933 if (edid_block_status_valid(status, edid_block_tag(block))) {
1934 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1935 block_num, edid_block_tag(block),
1936 edid_block_compute_checksum(block));
1937 } else {
1938 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1939 block_num, edid_block_tag(block),
1940 edid_block_compute_checksum(block));
1941 }
1942 break;
1943 case EDID_BLOCK_VERSION:
1944 pr_notice("EDID has major version %d, instead of 1\n",
1945 block->version);
1946 break;
1947 default:
1948 WARN(1, "EDID block %d unknown edid block status code %d\n",
1949 block_num, status);
1950 break;
1951 }
1952}
1953
1954static void edid_block_dump(const char *level, const void *block, int block_num)
1955{
1956 enum edid_block_status status;
1957 char prefix[20];
1958
1959 status = edid_block_check(block, block_num == 0);
1960 if (status == EDID_BLOCK_ZERO)
1961 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1962 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1963 sprintf(prefix, "\t[%02x] BAD ", block_num);
1964 else
1965 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1966
1967 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1968 block, EDID_LENGTH, false);
1969}
1970
1971/**
1972 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1973 * @_block: pointer to raw EDID block
1974 * @block_num: type of block to validate (0 for base, extension otherwise)
1975 * @print_bad_edid: if true, dump bad EDID blocks to the console
1976 * @edid_corrupt: if true, the header or checksum is invalid
1977 *
1978 * Validate a base or extension EDID block and optionally dump bad blocks to
1979 * the console.
1980 *
1981 * Return: True if the block is valid, false otherwise.
1982 */
1983bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1984 bool *edid_corrupt)
1985{
1986 struct edid *block = (struct edid *)_block;
1987 enum edid_block_status status;
1988 bool is_base_block = block_num == 0;
1989 bool valid;
1990
1991 if (WARN_ON(!block))
1992 return false;
1993
1994 status = edid_block_check(block, is_base_block);
1995 if (status == EDID_BLOCK_HEADER_REPAIR) {
1996 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1997 edid_header_fix(block);
1998
1999 /* Retry with fixed header, update status if that worked. */
2000 status = edid_block_check(block, is_base_block);
2001 if (status == EDID_BLOCK_OK)
2002 status = EDID_BLOCK_HEADER_FIXED;
2003 }
2004
2005 if (edid_corrupt) {
2006 /*
2007 * Unknown major version isn't corrupt but we can't use it. Only
2008 * the base block can reset edid_corrupt to false.
2009 */
2010 if (is_base_block &&
2011 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2012 *edid_corrupt = false;
2013 else if (status != EDID_BLOCK_OK)
2014 *edid_corrupt = true;
2015 }
2016
2017 edid_block_status_print(status, block, block_num);
2018
2019 /* Determine whether we can use this block with this status. */
2020 valid = edid_block_status_valid(status, edid_block_tag(block));
2021
2022 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2023 pr_notice("Raw EDID:\n");
2024 edid_block_dump(KERN_NOTICE, block, block_num);
2025 }
2026
2027 return valid;
2028}
2029EXPORT_SYMBOL(drm_edid_block_valid);
2030
2031/**
2032 * drm_edid_is_valid - sanity check EDID data
2033 * @edid: EDID data
2034 *
2035 * Sanity-check an entire EDID record (including extensions)
2036 *
2037 * Return: True if the EDID data is valid, false otherwise.
2038 */
2039bool drm_edid_is_valid(struct edid *edid)
2040{
2041 int i;
2042
2043 if (!edid)
2044 return false;
2045
2046 for (i = 0; i < edid_block_count(edid); i++) {
2047 void *block = (void *)edid_block_data(edid, i);
2048
2049 if (!drm_edid_block_valid(block, i, true, NULL))
2050 return false;
2051 }
2052
2053 return true;
2054}
2055EXPORT_SYMBOL(drm_edid_is_valid);
2056
2057/**
2058 * drm_edid_valid - sanity check EDID data
2059 * @drm_edid: EDID data
2060 *
2061 * Sanity check an EDID. Cross check block count against allocated size and
2062 * checksum the blocks.
2063 *
2064 * Return: True if the EDID data is valid, false otherwise.
2065 */
2066bool drm_edid_valid(const struct drm_edid *drm_edid)
2067{
2068 int i;
2069
2070 if (!drm_edid)
2071 return false;
2072
2073 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2074 return false;
2075
2076 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2077 const void *block = drm_edid_block_data(drm_edid, i);
2078
2079 if (!edid_block_valid(block, i == 0))
2080 return false;
2081 }
2082
2083 return true;
2084}
2085EXPORT_SYMBOL(drm_edid_valid);
2086
2087static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2088 size_t *alloc_size)
2089{
2090 struct edid *new;
2091 int i, valid_blocks = 0;
2092
2093 /*
2094 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2095 * back to regular extension count here. We don't want to start
2096 * modifying the HF-EEODB extension too.
2097 */
2098 for (i = 0; i < edid_block_count(edid); i++) {
2099 const void *src_block = edid_block_data(edid, i);
2100
2101 if (edid_block_valid(src_block, i == 0)) {
2102 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2103
2104 memmove(dst_block, src_block, EDID_LENGTH);
2105 valid_blocks++;
2106 }
2107 }
2108
2109 /* We already trusted the base block to be valid here... */
2110 if (WARN_ON(!valid_blocks)) {
2111 kfree(edid);
2112 return NULL;
2113 }
2114
2115 edid->extensions = valid_blocks - 1;
2116 edid->checksum = edid_block_compute_checksum(edid);
2117
2118 *alloc_size = edid_size_by_blocks(valid_blocks);
2119
2120 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2121 if (!new)
2122 kfree(edid);
2123
2124 return new;
2125}
2126
2127#define DDC_SEGMENT_ADDR 0x30
2128/**
2129 * drm_do_probe_ddc_edid() - get EDID information via I2C
2130 * @data: I2C device adapter
2131 * @buf: EDID data buffer to be filled
2132 * @block: 128 byte EDID block to start fetching from
2133 * @len: EDID data buffer length to fetch
2134 *
2135 * Try to fetch EDID information by calling I2C driver functions.
2136 *
2137 * Return: 0 on success or -1 on failure.
2138 */
2139static int
2140drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2141{
2142 struct i2c_adapter *adapter = data;
2143 unsigned char start = block * EDID_LENGTH;
2144 unsigned char segment = block >> 1;
2145 unsigned char xfers = segment ? 3 : 2;
2146 int ret, retries = 5;
2147
2148 /*
2149 * The core I2C driver will automatically retry the transfer if the
2150 * adapter reports EAGAIN. However, we find that bit-banging transfers
2151 * are susceptible to errors under a heavily loaded machine and
2152 * generate spurious NAKs and timeouts. Retrying the transfer
2153 * of the individual block a few times seems to overcome this.
2154 */
2155 do {
2156 struct i2c_msg msgs[] = {
2157 {
2158 .addr = DDC_SEGMENT_ADDR,
2159 .flags = 0,
2160 .len = 1,
2161 .buf = &segment,
2162 }, {
2163 .addr = DDC_ADDR,
2164 .flags = 0,
2165 .len = 1,
2166 .buf = &start,
2167 }, {
2168 .addr = DDC_ADDR,
2169 .flags = I2C_M_RD,
2170 .len = len,
2171 .buf = buf,
2172 }
2173 };
2174
2175 /*
2176 * Avoid sending the segment addr to not upset non-compliant
2177 * DDC monitors.
2178 */
2179 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2180
2181 if (ret == -ENXIO) {
2182 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2183 adapter->name);
2184 break;
2185 }
2186 } while (ret != xfers && --retries);
2187
2188 return ret == xfers ? 0 : -1;
2189}
2190
2191static void connector_bad_edid(struct drm_connector *connector,
2192 const struct edid *edid, int num_blocks)
2193{
2194 int i;
2195 u8 last_block;
2196
2197 /*
2198 * 0x7e in the EDID is the number of extension blocks. The EDID
2199 * is 1 (base block) + num_ext_blocks big. That means we can think
2200 * of 0x7e in the EDID of the _index_ of the last block in the
2201 * combined chunk of memory.
2202 */
2203 last_block = edid->extensions;
2204
2205 /* Calculate real checksum for the last edid extension block data */
2206 if (last_block < num_blocks)
2207 connector->real_edid_checksum =
2208 edid_block_compute_checksum(edid + last_block);
2209
2210 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2211 return;
2212
2213 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2214 connector->base.id, connector->name);
2215 for (i = 0; i < num_blocks; i++)
2216 edid_block_dump(KERN_DEBUG, edid + i, i);
2217}
2218
2219/* Get override or firmware EDID */
2220static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2221{
2222 const struct drm_edid *override = NULL;
2223
2224 mutex_lock(&connector->edid_override_mutex);
2225
2226 if (connector->edid_override)
2227 override = drm_edid_dup(connector->edid_override);
2228
2229 mutex_unlock(&connector->edid_override_mutex);
2230
2231 if (!override)
2232 override = drm_edid_load_firmware(connector);
2233
2234 return IS_ERR(override) ? NULL : override;
2235}
2236
2237/* For debugfs edid_override implementation */
2238int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2239{
2240 const struct drm_edid *drm_edid;
2241
2242 mutex_lock(&connector->edid_override_mutex);
2243
2244 drm_edid = connector->edid_override;
2245 if (drm_edid)
2246 seq_write(m, drm_edid->edid, drm_edid->size);
2247
2248 mutex_unlock(&connector->edid_override_mutex);
2249
2250 return 0;
2251}
2252
2253/* For debugfs edid_override implementation */
2254int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2255 size_t size)
2256{
2257 const struct drm_edid *drm_edid;
2258
2259 drm_edid = drm_edid_alloc(edid, size);
2260 if (!drm_edid_valid(drm_edid)) {
2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2262 connector->base.id, connector->name);
2263 drm_edid_free(drm_edid);
2264 return -EINVAL;
2265 }
2266
2267 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2268 connector->base.id, connector->name);
2269
2270 mutex_lock(&connector->edid_override_mutex);
2271
2272 drm_edid_free(connector->edid_override);
2273 connector->edid_override = drm_edid;
2274
2275 mutex_unlock(&connector->edid_override_mutex);
2276
2277 return 0;
2278}
2279
2280/* For debugfs edid_override implementation */
2281int drm_edid_override_reset(struct drm_connector *connector)
2282{
2283 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2284 connector->base.id, connector->name);
2285
2286 mutex_lock(&connector->edid_override_mutex);
2287
2288 drm_edid_free(connector->edid_override);
2289 connector->edid_override = NULL;
2290
2291 mutex_unlock(&connector->edid_override_mutex);
2292
2293 return 0;
2294}
2295
2296/**
2297 * drm_edid_override_connector_update - add modes from override/firmware EDID
2298 * @connector: connector we're probing
2299 *
2300 * Add modes from the override/firmware EDID, if available. Only to be used from
2301 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2302 * failed during drm_get_edid() and caused the override/firmware EDID to be
2303 * skipped.
2304 *
2305 * Return: The number of modes added or 0 if we couldn't find any.
2306 */
2307int drm_edid_override_connector_update(struct drm_connector *connector)
2308{
2309 const struct drm_edid *override;
2310 int num_modes = 0;
2311
2312 override = drm_edid_override_get(connector);
2313 if (override) {
2314 if (drm_edid_connector_update(connector, override) == 0)
2315 num_modes = drm_edid_connector_add_modes(connector);
2316
2317 drm_edid_free(override);
2318
2319 drm_dbg_kms(connector->dev,
2320 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2321 connector->base.id, connector->name, num_modes);
2322 }
2323
2324 return num_modes;
2325}
2326EXPORT_SYMBOL(drm_edid_override_connector_update);
2327
2328typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2329
2330static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2331 read_block_fn read_block,
2332 void *context)
2333{
2334 enum edid_block_status status;
2335 bool is_base_block = block_num == 0;
2336 int try;
2337
2338 for (try = 0; try < 4; try++) {
2339 if (read_block(context, block, block_num, EDID_LENGTH))
2340 return EDID_BLOCK_READ_FAIL;
2341
2342 status = edid_block_check(block, is_base_block);
2343 if (status == EDID_BLOCK_HEADER_REPAIR) {
2344 edid_header_fix(block);
2345
2346 /* Retry with fixed header, update status if that worked. */
2347 status = edid_block_check(block, is_base_block);
2348 if (status == EDID_BLOCK_OK)
2349 status = EDID_BLOCK_HEADER_FIXED;
2350 }
2351
2352 if (edid_block_status_valid(status, edid_block_tag(block)))
2353 break;
2354
2355 /* Fail early for unrepairable base block all zeros. */
2356 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2357 break;
2358 }
2359
2360 return status;
2361}
2362
2363static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2364 read_block_fn read_block, void *context,
2365 size_t *size)
2366{
2367 enum edid_block_status status;
2368 int i, num_blocks, invalid_blocks = 0;
2369 const struct drm_edid *override;
2370 struct edid *edid, *new;
2371 size_t alloc_size = EDID_LENGTH;
2372
2373 override = drm_edid_override_get(connector);
2374 if (override) {
2375 alloc_size = override->size;
2376 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2377 drm_edid_free(override);
2378 if (!edid)
2379 return NULL;
2380 goto ok;
2381 }
2382
2383 edid = kmalloc(alloc_size, GFP_KERNEL);
2384 if (!edid)
2385 return NULL;
2386
2387 status = edid_block_read(edid, 0, read_block, context);
2388
2389 edid_block_status_print(status, edid, 0);
2390
2391 if (status == EDID_BLOCK_READ_FAIL)
2392 goto fail;
2393
2394 /* FIXME: Clarify what a corrupt EDID actually means. */
2395 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2396 connector->edid_corrupt = false;
2397 else
2398 connector->edid_corrupt = true;
2399
2400 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2401 if (status == EDID_BLOCK_ZERO)
2402 connector->null_edid_counter++;
2403
2404 connector_bad_edid(connector, edid, 1);
2405 goto fail;
2406 }
2407
2408 if (!edid_extension_block_count(edid))
2409 goto ok;
2410
2411 alloc_size = edid_size(edid);
2412 new = krealloc(edid, alloc_size, GFP_KERNEL);
2413 if (!new)
2414 goto fail;
2415 edid = new;
2416
2417 num_blocks = edid_block_count(edid);
2418 for (i = 1; i < num_blocks; i++) {
2419 void *block = (void *)edid_block_data(edid, i);
2420
2421 status = edid_block_read(block, i, read_block, context);
2422
2423 edid_block_status_print(status, block, i);
2424
2425 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2426 if (status == EDID_BLOCK_READ_FAIL)
2427 goto fail;
2428 invalid_blocks++;
2429 } else if (i == 1) {
2430 /*
2431 * If the first EDID extension is a CTA extension, and
2432 * the first Data Block is HF-EEODB, override the
2433 * extension block count.
2434 *
2435 * Note: HF-EEODB could specify a smaller extension
2436 * count too, but we can't risk allocating a smaller
2437 * amount.
2438 */
2439 int eeodb = edid_hfeeodb_block_count(edid);
2440
2441 if (eeodb > num_blocks) {
2442 num_blocks = eeodb;
2443 alloc_size = edid_size_by_blocks(num_blocks);
2444 new = krealloc(edid, alloc_size, GFP_KERNEL);
2445 if (!new)
2446 goto fail;
2447 edid = new;
2448 }
2449 }
2450 }
2451
2452 if (invalid_blocks) {
2453 connector_bad_edid(connector, edid, num_blocks);
2454
2455 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2456 }
2457
2458ok:
2459 if (size)
2460 *size = alloc_size;
2461
2462 return edid;
2463
2464fail:
2465 kfree(edid);
2466 return NULL;
2467}
2468
2469/**
2470 * drm_do_get_edid - get EDID data using a custom EDID block read function
2471 * @connector: connector we're probing
2472 * @read_block: EDID block read function
2473 * @context: private data passed to the block read function
2474 *
2475 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2476 * exposes a different interface to read EDID blocks this function can be used
2477 * to get EDID data using a custom block read function.
2478 *
2479 * As in the general case the DDC bus is accessible by the kernel at the I2C
2480 * level, drivers must make all reasonable efforts to expose it as an I2C
2481 * adapter and use drm_get_edid() instead of abusing this function.
2482 *
2483 * The EDID may be overridden using debugfs override_edid or firmware EDID
2484 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2485 * order. Having either of them bypasses actual EDID reads.
2486 *
2487 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2488 */
2489struct edid *drm_do_get_edid(struct drm_connector *connector,
2490 read_block_fn read_block,
2491 void *context)
2492{
2493 return _drm_do_get_edid(connector, read_block, context, NULL);
2494}
2495EXPORT_SYMBOL_GPL(drm_do_get_edid);
2496
2497/**
2498 * drm_edid_raw - Get a pointer to the raw EDID data.
2499 * @drm_edid: drm_edid container
2500 *
2501 * Get a pointer to the raw EDID data.
2502 *
2503 * This is for transition only. Avoid using this like the plague.
2504 *
2505 * Return: Pointer to raw EDID data.
2506 */
2507const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2508{
2509 if (!drm_edid || !drm_edid->size)
2510 return NULL;
2511
2512 /*
2513 * Do not return pointers where relying on EDID extension count would
2514 * lead to buffer overflow.
2515 */
2516 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2517 return NULL;
2518
2519 return drm_edid->edid;
2520}
2521EXPORT_SYMBOL(drm_edid_raw);
2522
2523/* Allocate struct drm_edid container *without* duplicating the edid data */
2524static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2525{
2526 struct drm_edid *drm_edid;
2527
2528 if (!edid || !size || size < EDID_LENGTH)
2529 return NULL;
2530
2531 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2532 if (drm_edid) {
2533 drm_edid->edid = edid;
2534 drm_edid->size = size;
2535 }
2536
2537 return drm_edid;
2538}
2539
2540/**
2541 * drm_edid_alloc - Allocate a new drm_edid container
2542 * @edid: Pointer to raw EDID data
2543 * @size: Size of memory allocated for EDID
2544 *
2545 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2546 * the actual size that has been allocated for the data. There is no validation
2547 * of the raw EDID data against the size, but at least the EDID base block must
2548 * fit in the buffer.
2549 *
2550 * The returned pointer must be freed using drm_edid_free().
2551 *
2552 * Return: drm_edid container, or NULL on errors
2553 */
2554const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2555{
2556 const struct drm_edid *drm_edid;
2557
2558 if (!edid || !size || size < EDID_LENGTH)
2559 return NULL;
2560
2561 edid = kmemdup(edid, size, GFP_KERNEL);
2562 if (!edid)
2563 return NULL;
2564
2565 drm_edid = _drm_edid_alloc(edid, size);
2566 if (!drm_edid)
2567 kfree(edid);
2568
2569 return drm_edid;
2570}
2571EXPORT_SYMBOL(drm_edid_alloc);
2572
2573/**
2574 * drm_edid_dup - Duplicate a drm_edid container
2575 * @drm_edid: EDID to duplicate
2576 *
2577 * The returned pointer must be freed using drm_edid_free().
2578 *
2579 * Returns: drm_edid container copy, or NULL on errors
2580 */
2581const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2582{
2583 if (!drm_edid)
2584 return NULL;
2585
2586 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2587}
2588EXPORT_SYMBOL(drm_edid_dup);
2589
2590/**
2591 * drm_edid_free - Free the drm_edid container
2592 * @drm_edid: EDID to free
2593 */
2594void drm_edid_free(const struct drm_edid *drm_edid)
2595{
2596 if (!drm_edid)
2597 return;
2598
2599 kfree(drm_edid->edid);
2600 kfree(drm_edid);
2601}
2602EXPORT_SYMBOL(drm_edid_free);
2603
2604/**
2605 * drm_probe_ddc() - probe DDC presence
2606 * @adapter: I2C adapter to probe
2607 *
2608 * Return: True on success, false on failure.
2609 */
2610bool
2611drm_probe_ddc(struct i2c_adapter *adapter)
2612{
2613 unsigned char out;
2614
2615 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2616}
2617EXPORT_SYMBOL(drm_probe_ddc);
2618
2619/**
2620 * drm_get_edid - get EDID data, if available
2621 * @connector: connector we're probing
2622 * @adapter: I2C adapter to use for DDC
2623 *
2624 * Poke the given I2C channel to grab EDID data if possible. If found,
2625 * attach it to the connector.
2626 *
2627 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2628 */
2629struct edid *drm_get_edid(struct drm_connector *connector,
2630 struct i2c_adapter *adapter)
2631{
2632 struct edid *edid;
2633
2634 if (connector->force == DRM_FORCE_OFF)
2635 return NULL;
2636
2637 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2638 return NULL;
2639
2640 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2641 drm_connector_update_edid_property(connector, edid);
2642 return edid;
2643}
2644EXPORT_SYMBOL(drm_get_edid);
2645
2646/**
2647 * drm_edid_read_custom - Read EDID data using given EDID block read function
2648 * @connector: Connector to use
2649 * @read_block: EDID block read function
2650 * @context: Private data passed to the block read function
2651 *
2652 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2653 * exposes a different interface to read EDID blocks this function can be used
2654 * to get EDID data using a custom block read function.
2655 *
2656 * As in the general case the DDC bus is accessible by the kernel at the I2C
2657 * level, drivers must make all reasonable efforts to expose it as an I2C
2658 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2659 * this function.
2660 *
2661 * The EDID may be overridden using debugfs override_edid or firmware EDID
2662 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2663 * order. Having either of them bypasses actual EDID reads.
2664 *
2665 * The returned pointer must be freed using drm_edid_free().
2666 *
2667 * Return: Pointer to EDID, or NULL if probe/read failed.
2668 */
2669const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2670 read_block_fn read_block,
2671 void *context)
2672{
2673 const struct drm_edid *drm_edid;
2674 struct edid *edid;
2675 size_t size = 0;
2676
2677 edid = _drm_do_get_edid(connector, read_block, context, &size);
2678 if (!edid)
2679 return NULL;
2680
2681 /* Sanity check for now */
2682 drm_WARN_ON(connector->dev, !size);
2683
2684 drm_edid = _drm_edid_alloc(edid, size);
2685 if (!drm_edid)
2686 kfree(edid);
2687
2688 return drm_edid;
2689}
2690EXPORT_SYMBOL(drm_edid_read_custom);
2691
2692/**
2693 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2694 * @connector: Connector to use
2695 * @adapter: I2C adapter to use for DDC
2696 *
2697 * Read EDID using the given I2C adapter.
2698 *
2699 * The EDID may be overridden using debugfs override_edid or firmware EDID
2700 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2701 * order. Having either of them bypasses actual EDID reads.
2702 *
2703 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2704 * using drm_edid_read() instead of this function.
2705 *
2706 * The returned pointer must be freed using drm_edid_free().
2707 *
2708 * Return: Pointer to EDID, or NULL if probe/read failed.
2709 */
2710const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2711 struct i2c_adapter *adapter)
2712{
2713 const struct drm_edid *drm_edid;
2714
2715 if (connector->force == DRM_FORCE_OFF)
2716 return NULL;
2717
2718 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2719 return NULL;
2720
2721 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2722
2723 /* Note: Do *not* call connector updates here. */
2724
2725 return drm_edid;
2726}
2727EXPORT_SYMBOL(drm_edid_read_ddc);
2728
2729/**
2730 * drm_edid_read - Read EDID data using connector's I2C adapter
2731 * @connector: Connector to use
2732 *
2733 * Read EDID using the connector's I2C adapter.
2734 *
2735 * The EDID may be overridden using debugfs override_edid or firmware EDID
2736 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2737 * order. Having either of them bypasses actual EDID reads.
2738 *
2739 * The returned pointer must be freed using drm_edid_free().
2740 *
2741 * Return: Pointer to EDID, or NULL if probe/read failed.
2742 */
2743const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2744{
2745 if (drm_WARN_ON(connector->dev, !connector->ddc))
2746 return NULL;
2747
2748 return drm_edid_read_ddc(connector, connector->ddc);
2749}
2750EXPORT_SYMBOL(drm_edid_read);
2751
2752static u32 edid_extract_panel_id(const struct edid *edid)
2753{
2754 /*
2755 * We represent the ID as a 32-bit number so it can easily be compared
2756 * with "==".
2757 *
2758 * NOTE that we deal with endianness differently for the top half
2759 * of this ID than for the bottom half. The bottom half (the product
2760 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2761 * that's how everyone seems to interpret it. The top half (the mfg_id)
2762 * gets stored as big endian because that makes
2763 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2764 * to write (it's easier to extract the ASCII). It doesn't really
2765 * matter, though, as long as the number here is unique.
2766 */
2767 return (u32)edid->mfg_id[0] << 24 |
2768 (u32)edid->mfg_id[1] << 16 |
2769 (u32)EDID_PRODUCT_ID(edid);
2770}
2771
2772/**
2773 * drm_edid_get_panel_id - Get a panel's ID through DDC
2774 * @adapter: I2C adapter to use for DDC
2775 *
2776 * This function reads the first block of the EDID of a panel and (assuming
2777 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2778 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2779 * supposed to be different for each different modem of panel.
2780 *
2781 * This function is intended to be used during early probing on devices where
2782 * more than one panel might be present. Because of its intended use it must
2783 * assume that the EDID of the panel is correct, at least as far as the ID
2784 * is concerned (in other words, we don't process any overrides here).
2785 *
2786 * NOTE: it's expected that this function and drm_do_get_edid() will both
2787 * be read the EDID, but there is no caching between them. Since we're only
2788 * reading the first block, hopefully this extra overhead won't be too big.
2789 *
2790 * Return: A 32-bit ID that should be different for each make/model of panel.
2791 * See the functions drm_edid_encode_panel_id() and
2792 * drm_edid_decode_panel_id() for some details on the structure of this
2793 * ID.
2794 */
2795
2796u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2797{
2798 enum edid_block_status status;
2799 void *base_block;
2800 u32 panel_id = 0;
2801
2802 /*
2803 * There are no manufacturer IDs of 0, so if there is a problem reading
2804 * the EDID then we'll just return 0.
2805 */
2806
2807 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2808 if (!base_block)
2809 return 0;
2810
2811 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2812
2813 edid_block_status_print(status, base_block, 0);
2814
2815 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2816 panel_id = edid_extract_panel_id(base_block);
2817 else
2818 edid_block_dump(KERN_NOTICE, base_block, 0);
2819
2820 kfree(base_block);
2821
2822 return panel_id;
2823}
2824EXPORT_SYMBOL(drm_edid_get_panel_id);
2825
2826/**
2827 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2828 * @connector: connector we're probing
2829 * @adapter: I2C adapter to use for DDC
2830 *
2831 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2832 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2833 * switch DDC to the GPU which is retrieving EDID.
2834 *
2835 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2836 */
2837struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2838 struct i2c_adapter *adapter)
2839{
2840 struct drm_device *dev = connector->dev;
2841 struct pci_dev *pdev = to_pci_dev(dev->dev);
2842 struct edid *edid;
2843
2844 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2845 return NULL;
2846
2847 vga_switcheroo_lock_ddc(pdev);
2848 edid = drm_get_edid(connector, adapter);
2849 vga_switcheroo_unlock_ddc(pdev);
2850
2851 return edid;
2852}
2853EXPORT_SYMBOL(drm_get_edid_switcheroo);
2854
2855/**
2856 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2857 * @connector: connector we're probing
2858 * @adapter: I2C adapter to use for DDC
2859 *
2860 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2861 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2862 * temporarily switch DDC to the GPU which is retrieving EDID.
2863 *
2864 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2865 */
2866const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2867 struct i2c_adapter *adapter)
2868{
2869 struct drm_device *dev = connector->dev;
2870 struct pci_dev *pdev = to_pci_dev(dev->dev);
2871 const struct drm_edid *drm_edid;
2872
2873 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2874 return NULL;
2875
2876 vga_switcheroo_lock_ddc(pdev);
2877 drm_edid = drm_edid_read_ddc(connector, adapter);
2878 vga_switcheroo_unlock_ddc(pdev);
2879
2880 return drm_edid;
2881}
2882EXPORT_SYMBOL(drm_edid_read_switcheroo);
2883
2884/**
2885 * drm_edid_duplicate - duplicate an EDID and the extensions
2886 * @edid: EDID to duplicate
2887 *
2888 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2889 */
2890struct edid *drm_edid_duplicate(const struct edid *edid)
2891{
2892 if (!edid)
2893 return NULL;
2894
2895 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2896}
2897EXPORT_SYMBOL(drm_edid_duplicate);
2898
2899/*** EDID parsing ***/
2900
2901/**
2902 * edid_get_quirks - return quirk flags for a given EDID
2903 * @drm_edid: EDID to process
2904 *
2905 * This tells subsequent routines what fixes they need to apply.
2906 */
2907static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2908{
2909 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2910 const struct edid_quirk *quirk;
2911 int i;
2912
2913 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2914 quirk = &edid_quirk_list[i];
2915 if (quirk->panel_id == panel_id)
2916 return quirk->quirks;
2917 }
2918
2919 return 0;
2920}
2921
2922#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2923#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2924
2925/*
2926 * Walk the mode list for connector, clearing the preferred status on existing
2927 * modes and setting it anew for the right mode ala quirks.
2928 */
2929static void edid_fixup_preferred(struct drm_connector *connector)
2930{
2931 const struct drm_display_info *info = &connector->display_info;
2932 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2933 int target_refresh = 0;
2934 int cur_vrefresh, preferred_vrefresh;
2935
2936 if (list_empty(&connector->probed_modes))
2937 return;
2938
2939 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2940 target_refresh = 60;
2941 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2942 target_refresh = 75;
2943
2944 preferred_mode = list_first_entry(&connector->probed_modes,
2945 struct drm_display_mode, head);
2946
2947 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2948 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2949
2950 if (cur_mode == preferred_mode)
2951 continue;
2952
2953 /* Largest mode is preferred */
2954 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2955 preferred_mode = cur_mode;
2956
2957 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2958 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2959 /* At a given size, try to get closest to target refresh */
2960 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2961 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2962 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2963 preferred_mode = cur_mode;
2964 }
2965 }
2966
2967 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2968}
2969
2970static bool
2971mode_is_rb(const struct drm_display_mode *mode)
2972{
2973 return (mode->htotal - mode->hdisplay == 160) &&
2974 (mode->hsync_end - mode->hdisplay == 80) &&
2975 (mode->hsync_end - mode->hsync_start == 32) &&
2976 (mode->vsync_start - mode->vdisplay == 3);
2977}
2978
2979/*
2980 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2981 * @dev: Device to duplicate against
2982 * @hsize: Mode width
2983 * @vsize: Mode height
2984 * @fresh: Mode refresh rate
2985 * @rb: Mode reduced-blanking-ness
2986 *
2987 * Walk the DMT mode list looking for a match for the given parameters.
2988 *
2989 * Return: A newly allocated copy of the mode, or NULL if not found.
2990 */
2991struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2992 int hsize, int vsize, int fresh,
2993 bool rb)
2994{
2995 int i;
2996
2997 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2998 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2999
3000 if (hsize != ptr->hdisplay)
3001 continue;
3002 if (vsize != ptr->vdisplay)
3003 continue;
3004 if (fresh != drm_mode_vrefresh(ptr))
3005 continue;
3006 if (rb != mode_is_rb(ptr))
3007 continue;
3008
3009 return drm_mode_duplicate(dev, ptr);
3010 }
3011
3012 return NULL;
3013}
3014EXPORT_SYMBOL(drm_mode_find_dmt);
3015
3016static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3017{
3018 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3019 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3020 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3021
3022 return descriptor->pixel_clock == 0 &&
3023 descriptor->data.other_data.pad1 == 0 &&
3024 descriptor->data.other_data.type == type;
3025}
3026
3027static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3028{
3029 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3030
3031 return descriptor->pixel_clock != 0;
3032}
3033
3034typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3035
3036static void
3037cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3038{
3039 int i, n;
3040 u8 d = ext[0x02];
3041 const u8 *det_base = ext + d;
3042
3043 if (d < 4 || d > 127)
3044 return;
3045
3046 n = (127 - d) / 18;
3047 for (i = 0; i < n; i++)
3048 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3049}
3050
3051static void
3052vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3053{
3054 unsigned int i, n = min((int)ext[0x02], 6);
3055 const u8 *det_base = ext + 5;
3056
3057 if (ext[0x01] != 1)
3058 return; /* unknown version */
3059
3060 for (i = 0; i < n; i++)
3061 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3062}
3063
3064static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3065 detailed_cb *cb, void *closure)
3066{
3067 struct drm_edid_iter edid_iter;
3068 const u8 *ext;
3069 int i;
3070
3071 if (!drm_edid)
3072 return;
3073
3074 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3075 cb(&drm_edid->edid->detailed_timings[i], closure);
3076
3077 drm_edid_iter_begin(drm_edid, &edid_iter);
3078 drm_edid_iter_for_each(ext, &edid_iter) {
3079 switch (*ext) {
3080 case CEA_EXT:
3081 cea_for_each_detailed_block(ext, cb, closure);
3082 break;
3083 case VTB_EXT:
3084 vtb_for_each_detailed_block(ext, cb, closure);
3085 break;
3086 default:
3087 break;
3088 }
3089 }
3090 drm_edid_iter_end(&edid_iter);
3091}
3092
3093static void
3094is_rb(const struct detailed_timing *descriptor, void *data)
3095{
3096 bool *res = data;
3097
3098 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3099 return;
3100
3101 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3102 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3103
3104 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3105 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3106 *res = true;
3107}
3108
3109/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3110static bool
3111drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3112{
3113 if (drm_edid->edid->revision >= 4) {
3114 bool ret = false;
3115
3116 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3117 return ret;
3118 }
3119
3120 return drm_edid_is_digital(drm_edid);
3121}
3122
3123static void
3124find_gtf2(const struct detailed_timing *descriptor, void *data)
3125{
3126 const struct detailed_timing **res = data;
3127
3128 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3129 return;
3130
3131 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3132
3133 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3134 *res = descriptor;
3135}
3136
3137/* Secondary GTF curve kicks in above some break frequency */
3138static int
3139drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3140{
3141 const struct detailed_timing *descriptor = NULL;
3142
3143 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3144
3145 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3146
3147 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3148}
3149
3150static int
3151drm_gtf2_2c(const struct drm_edid *drm_edid)
3152{
3153 const struct detailed_timing *descriptor = NULL;
3154
3155 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3156
3157 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3158
3159 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3160}
3161
3162static int
3163drm_gtf2_m(const struct drm_edid *drm_edid)
3164{
3165 const struct detailed_timing *descriptor = NULL;
3166
3167 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3168
3169 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3170
3171 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3172}
3173
3174static int
3175drm_gtf2_k(const struct drm_edid *drm_edid)
3176{
3177 const struct detailed_timing *descriptor = NULL;
3178
3179 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3180
3181 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3182
3183 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3184}
3185
3186static int
3187drm_gtf2_2j(const struct drm_edid *drm_edid)
3188{
3189 const struct detailed_timing *descriptor = NULL;
3190
3191 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3192
3193 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3194
3195 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3196}
3197
3198static void
3199get_timing_level(const struct detailed_timing *descriptor, void *data)
3200{
3201 int *res = data;
3202
3203 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3204 return;
3205
3206 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3207
3208 switch (descriptor->data.other_data.data.range.flags) {
3209 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3210 *res = LEVEL_GTF;
3211 break;
3212 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3213 *res = LEVEL_GTF2;
3214 break;
3215 case DRM_EDID_CVT_SUPPORT_FLAG:
3216 *res = LEVEL_CVT;
3217 break;
3218 default:
3219 break;
3220 }
3221}
3222
3223/* Get standard timing level (CVT/GTF/DMT). */
3224static int standard_timing_level(const struct drm_edid *drm_edid)
3225{
3226 const struct edid *edid = drm_edid->edid;
3227
3228 if (edid->revision >= 4) {
3229 /*
3230 * If the range descriptor doesn't
3231 * indicate otherwise default to CVT
3232 */
3233 int ret = LEVEL_CVT;
3234
3235 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3236
3237 return ret;
3238 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3239 return LEVEL_GTF2;
3240 } else if (edid->revision >= 2) {
3241 return LEVEL_GTF;
3242 } else {
3243 return LEVEL_DMT;
3244 }
3245}
3246
3247/*
3248 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3249 * monitors fill with ascii space (0x20) instead.
3250 */
3251static int
3252bad_std_timing(u8 a, u8 b)
3253{
3254 return (a == 0x00 && b == 0x00) ||
3255 (a == 0x01 && b == 0x01) ||
3256 (a == 0x20 && b == 0x20);
3257}
3258
3259static int drm_mode_hsync(const struct drm_display_mode *mode)
3260{
3261 if (mode->htotal <= 0)
3262 return 0;
3263
3264 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3265}
3266
3267static struct drm_display_mode *
3268drm_gtf2_mode(struct drm_device *dev,
3269 const struct drm_edid *drm_edid,
3270 int hsize, int vsize, int vrefresh_rate)
3271{
3272 struct drm_display_mode *mode;
3273
3274 /*
3275 * This is potentially wrong if there's ever a monitor with
3276 * more than one ranges section, each claiming a different
3277 * secondary GTF curve. Please don't do that.
3278 */
3279 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3280 if (!mode)
3281 return NULL;
3282
3283 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3284 drm_mode_destroy(dev, mode);
3285 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3286 vrefresh_rate, 0, 0,
3287 drm_gtf2_m(drm_edid),
3288 drm_gtf2_2c(drm_edid),
3289 drm_gtf2_k(drm_edid),
3290 drm_gtf2_2j(drm_edid));
3291 }
3292
3293 return mode;
3294}
3295
3296/*
3297 * Take the standard timing params (in this case width, aspect, and refresh)
3298 * and convert them into a real mode using CVT/GTF/DMT.
3299 */
3300static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3301 const struct drm_edid *drm_edid,
3302 const struct std_timing *t)
3303{
3304 struct drm_device *dev = connector->dev;
3305 struct drm_display_mode *m, *mode = NULL;
3306 int hsize, vsize;
3307 int vrefresh_rate;
3308 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3309 >> EDID_TIMING_ASPECT_SHIFT;
3310 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3311 >> EDID_TIMING_VFREQ_SHIFT;
3312 int timing_level = standard_timing_level(drm_edid);
3313
3314 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3315 return NULL;
3316
3317 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3318 hsize = t->hsize * 8 + 248;
3319 /* vrefresh_rate = vfreq + 60 */
3320 vrefresh_rate = vfreq + 60;
3321 /* the vdisplay is calculated based on the aspect ratio */
3322 if (aspect_ratio == 0) {
3323 if (drm_edid->edid->revision < 3)
3324 vsize = hsize;
3325 else
3326 vsize = (hsize * 10) / 16;
3327 } else if (aspect_ratio == 1)
3328 vsize = (hsize * 3) / 4;
3329 else if (aspect_ratio == 2)
3330 vsize = (hsize * 4) / 5;
3331 else
3332 vsize = (hsize * 9) / 16;
3333
3334 /* HDTV hack, part 1 */
3335 if (vrefresh_rate == 60 &&
3336 ((hsize == 1360 && vsize == 765) ||
3337 (hsize == 1368 && vsize == 769))) {
3338 hsize = 1366;
3339 vsize = 768;
3340 }
3341
3342 /*
3343 * If this connector already has a mode for this size and refresh
3344 * rate (because it came from detailed or CVT info), use that
3345 * instead. This way we don't have to guess at interlace or
3346 * reduced blanking.
3347 */
3348 list_for_each_entry(m, &connector->probed_modes, head)
3349 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3350 drm_mode_vrefresh(m) == vrefresh_rate)
3351 return NULL;
3352
3353 /* HDTV hack, part 2 */
3354 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3355 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3356 false);
3357 if (!mode)
3358 return NULL;
3359 mode->hdisplay = 1366;
3360 mode->hsync_start = mode->hsync_start - 1;
3361 mode->hsync_end = mode->hsync_end - 1;
3362 return mode;
3363 }
3364
3365 /* check whether it can be found in default mode table */
3366 if (drm_monitor_supports_rb(drm_edid)) {
3367 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3368 true);
3369 if (mode)
3370 return mode;
3371 }
3372 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3373 if (mode)
3374 return mode;
3375
3376 /* okay, generate it */
3377 switch (timing_level) {
3378 case LEVEL_DMT:
3379 break;
3380 case LEVEL_GTF:
3381 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3382 break;
3383 case LEVEL_GTF2:
3384 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3385 break;
3386 case LEVEL_CVT:
3387 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3388 false);
3389 break;
3390 }
3391 return mode;
3392}
3393
3394/*
3395 * EDID is delightfully ambiguous about how interlaced modes are to be
3396 * encoded. Our internal representation is of frame height, but some
3397 * HDTV detailed timings are encoded as field height.
3398 *
3399 * The format list here is from CEA, in frame size. Technically we
3400 * should be checking refresh rate too. Whatever.
3401 */
3402static void
3403drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3404 const struct detailed_pixel_timing *pt)
3405{
3406 int i;
3407 static const struct {
3408 int w, h;
3409 } cea_interlaced[] = {
3410 { 1920, 1080 },
3411 { 720, 480 },
3412 { 1440, 480 },
3413 { 2880, 480 },
3414 { 720, 576 },
3415 { 1440, 576 },
3416 { 2880, 576 },
3417 };
3418
3419 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3420 return;
3421
3422 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3423 if ((mode->hdisplay == cea_interlaced[i].w) &&
3424 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3425 mode->vdisplay *= 2;
3426 mode->vsync_start *= 2;
3427 mode->vsync_end *= 2;
3428 mode->vtotal *= 2;
3429 mode->vtotal |= 1;
3430 }
3431 }
3432
3433 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3434}
3435
3436/*
3437 * Create a new mode from an EDID detailed timing section. An EDID detailed
3438 * timing block contains enough info for us to create and return a new struct
3439 * drm_display_mode.
3440 */
3441static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3442 const struct drm_edid *drm_edid,
3443 const struct detailed_timing *timing)
3444{
3445 const struct drm_display_info *info = &connector->display_info;
3446 struct drm_device *dev = connector->dev;
3447 struct drm_display_mode *mode;
3448 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3449 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3450 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3451 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3452 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3453 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3454 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3455 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3456 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3457
3458 /* ignore tiny modes */
3459 if (hactive < 64 || vactive < 64)
3460 return NULL;
3461
3462 if (pt->misc & DRM_EDID_PT_STEREO) {
3463 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3464 connector->base.id, connector->name);
3465 return NULL;
3466 }
3467 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3468 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3469 connector->base.id, connector->name);
3470 }
3471
3472 /* it is incorrect if hsync/vsync width is zero */
3473 if (!hsync_pulse_width || !vsync_pulse_width) {
3474 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3475 connector->base.id, connector->name);
3476 return NULL;
3477 }
3478
3479 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3480 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3481 if (!mode)
3482 return NULL;
3483
3484 goto set_size;
3485 }
3486
3487 mode = drm_mode_create(dev);
3488 if (!mode)
3489 return NULL;
3490
3491 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3492 mode->clock = 1088 * 10;
3493 else
3494 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3495
3496 mode->hdisplay = hactive;
3497 mode->hsync_start = mode->hdisplay + hsync_offset;
3498 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3499 mode->htotal = mode->hdisplay + hblank;
3500
3501 mode->vdisplay = vactive;
3502 mode->vsync_start = mode->vdisplay + vsync_offset;
3503 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3504 mode->vtotal = mode->vdisplay + vblank;
3505
3506 /* Some EDIDs have bogus h/vsync_end values */
3507 if (mode->hsync_end > mode->htotal) {
3508 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3509 connector->base.id, connector->name,
3510 mode->hsync_end, mode->htotal);
3511 mode->hsync_end = mode->htotal;
3512 }
3513 if (mode->vsync_end > mode->vtotal) {
3514 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3515 connector->base.id, connector->name,
3516 mode->vsync_end, mode->vtotal);
3517 mode->vsync_end = mode->vtotal;
3518 }
3519
3520 drm_mode_do_interlace_quirk(mode, pt);
3521
3522 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3523 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3524 } else {
3525 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3526 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3527 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3528 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3529 }
3530
3531set_size:
3532 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3533 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3534
3535 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3536 mode->width_mm *= 10;
3537 mode->height_mm *= 10;
3538 }
3539
3540 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3541 mode->width_mm = drm_edid->edid->width_cm * 10;
3542 mode->height_mm = drm_edid->edid->height_cm * 10;
3543 }
3544
3545 mode->type = DRM_MODE_TYPE_DRIVER;
3546 drm_mode_set_name(mode);
3547
3548 return mode;
3549}
3550
3551static bool
3552mode_in_hsync_range(const struct drm_display_mode *mode,
3553 const struct edid *edid, const u8 *t)
3554{
3555 int hsync, hmin, hmax;
3556
3557 hmin = t[7];
3558 if (edid->revision >= 4)
3559 hmin += ((t[4] & 0x04) ? 255 : 0);
3560 hmax = t[8];
3561 if (edid->revision >= 4)
3562 hmax += ((t[4] & 0x08) ? 255 : 0);
3563 hsync = drm_mode_hsync(mode);
3564
3565 return (hsync <= hmax && hsync >= hmin);
3566}
3567
3568static bool
3569mode_in_vsync_range(const struct drm_display_mode *mode,
3570 const struct edid *edid, const u8 *t)
3571{
3572 int vsync, vmin, vmax;
3573
3574 vmin = t[5];
3575 if (edid->revision >= 4)
3576 vmin += ((t[4] & 0x01) ? 255 : 0);
3577 vmax = t[6];
3578 if (edid->revision >= 4)
3579 vmax += ((t[4] & 0x02) ? 255 : 0);
3580 vsync = drm_mode_vrefresh(mode);
3581
3582 return (vsync <= vmax && vsync >= vmin);
3583}
3584
3585static u32
3586range_pixel_clock(const struct edid *edid, const u8 *t)
3587{
3588 /* unspecified */
3589 if (t[9] == 0 || t[9] == 255)
3590 return 0;
3591
3592 /* 1.4 with CVT support gives us real precision, yay */
3593 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3594 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3595
3596 /* 1.3 is pathetic, so fuzz up a bit */
3597 return t[9] * 10000 + 5001;
3598}
3599
3600static bool mode_in_range(const struct drm_display_mode *mode,
3601 const struct drm_edid *drm_edid,
3602 const struct detailed_timing *timing)
3603{
3604 const struct edid *edid = drm_edid->edid;
3605 u32 max_clock;
3606 const u8 *t = (const u8 *)timing;
3607
3608 if (!mode_in_hsync_range(mode, edid, t))
3609 return false;
3610
3611 if (!mode_in_vsync_range(mode, edid, t))
3612 return false;
3613
3614 max_clock = range_pixel_clock(edid, t);
3615 if (max_clock)
3616 if (mode->clock > max_clock)
3617 return false;
3618
3619 /* 1.4 max horizontal check */
3620 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3621 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3622 return false;
3623
3624 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3625 return false;
3626
3627 return true;
3628}
3629
3630static bool valid_inferred_mode(const struct drm_connector *connector,
3631 const struct drm_display_mode *mode)
3632{
3633 const struct drm_display_mode *m;
3634 bool ok = false;
3635
3636 list_for_each_entry(m, &connector->probed_modes, head) {
3637 if (mode->hdisplay == m->hdisplay &&
3638 mode->vdisplay == m->vdisplay &&
3639 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3640 return false; /* duplicated */
3641 if (mode->hdisplay <= m->hdisplay &&
3642 mode->vdisplay <= m->vdisplay)
3643 ok = true;
3644 }
3645 return ok;
3646}
3647
3648static int drm_dmt_modes_for_range(struct drm_connector *connector,
3649 const struct drm_edid *drm_edid,
3650 const struct detailed_timing *timing)
3651{
3652 int i, modes = 0;
3653 struct drm_display_mode *newmode;
3654 struct drm_device *dev = connector->dev;
3655
3656 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3657 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3658 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3659 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3660 if (newmode) {
3661 drm_mode_probed_add(connector, newmode);
3662 modes++;
3663 }
3664 }
3665 }
3666
3667 return modes;
3668}
3669
3670/* fix up 1366x768 mode from 1368x768;
3671 * GFT/CVT can't express 1366 width which isn't dividable by 8
3672 */
3673void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3674{
3675 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3676 mode->hdisplay = 1366;
3677 mode->hsync_start--;
3678 mode->hsync_end--;
3679 drm_mode_set_name(mode);
3680 }
3681}
3682
3683static int drm_gtf_modes_for_range(struct drm_connector *connector,
3684 const struct drm_edid *drm_edid,
3685 const struct detailed_timing *timing)
3686{
3687 int i, modes = 0;
3688 struct drm_display_mode *newmode;
3689 struct drm_device *dev = connector->dev;
3690
3691 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3692 const struct minimode *m = &extra_modes[i];
3693
3694 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3695 if (!newmode)
3696 return modes;
3697
3698 drm_mode_fixup_1366x768(newmode);
3699 if (!mode_in_range(newmode, drm_edid, timing) ||
3700 !valid_inferred_mode(connector, newmode)) {
3701 drm_mode_destroy(dev, newmode);
3702 continue;
3703 }
3704
3705 drm_mode_probed_add(connector, newmode);
3706 modes++;
3707 }
3708
3709 return modes;
3710}
3711
3712static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3713 const struct drm_edid *drm_edid,
3714 const struct detailed_timing *timing)
3715{
3716 int i, modes = 0;
3717 struct drm_display_mode *newmode;
3718 struct drm_device *dev = connector->dev;
3719
3720 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3721 const struct minimode *m = &extra_modes[i];
3722
3723 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3724 if (!newmode)
3725 return modes;
3726
3727 drm_mode_fixup_1366x768(newmode);
3728 if (!mode_in_range(newmode, drm_edid, timing) ||
3729 !valid_inferred_mode(connector, newmode)) {
3730 drm_mode_destroy(dev, newmode);
3731 continue;
3732 }
3733
3734 drm_mode_probed_add(connector, newmode);
3735 modes++;
3736 }
3737
3738 return modes;
3739}
3740
3741static int drm_cvt_modes_for_range(struct drm_connector *connector,
3742 const struct drm_edid *drm_edid,
3743 const struct detailed_timing *timing)
3744{
3745 int i, modes = 0;
3746 struct drm_display_mode *newmode;
3747 struct drm_device *dev = connector->dev;
3748 bool rb = drm_monitor_supports_rb(drm_edid);
3749
3750 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3751 const struct minimode *m = &extra_modes[i];
3752
3753 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3754 if (!newmode)
3755 return modes;
3756
3757 drm_mode_fixup_1366x768(newmode);
3758 if (!mode_in_range(newmode, drm_edid, timing) ||
3759 !valid_inferred_mode(connector, newmode)) {
3760 drm_mode_destroy(dev, newmode);
3761 continue;
3762 }
3763
3764 drm_mode_probed_add(connector, newmode);
3765 modes++;
3766 }
3767
3768 return modes;
3769}
3770
3771static void
3772do_inferred_modes(const struct detailed_timing *timing, void *c)
3773{
3774 struct detailed_mode_closure *closure = c;
3775 const struct detailed_non_pixel *data = &timing->data.other_data;
3776 const struct detailed_data_monitor_range *range = &data->data.range;
3777
3778 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3779 return;
3780
3781 closure->modes += drm_dmt_modes_for_range(closure->connector,
3782 closure->drm_edid,
3783 timing);
3784
3785 if (closure->drm_edid->edid->revision < 2)
3786 return; /* GTF not defined yet */
3787
3788 switch (range->flags) {
3789 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3790 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3791 closure->drm_edid,
3792 timing);
3793 break;
3794 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3795 closure->modes += drm_gtf_modes_for_range(closure->connector,
3796 closure->drm_edid,
3797 timing);
3798 break;
3799 case DRM_EDID_CVT_SUPPORT_FLAG:
3800 if (closure->drm_edid->edid->revision < 4)
3801 break;
3802
3803 closure->modes += drm_cvt_modes_for_range(closure->connector,
3804 closure->drm_edid,
3805 timing);
3806 break;
3807 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3808 default:
3809 break;
3810 }
3811}
3812
3813static int add_inferred_modes(struct drm_connector *connector,
3814 const struct drm_edid *drm_edid)
3815{
3816 struct detailed_mode_closure closure = {
3817 .connector = connector,
3818 .drm_edid = drm_edid,
3819 };
3820
3821 if (drm_edid->edid->revision >= 1)
3822 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3823
3824 return closure.modes;
3825}
3826
3827static int
3828drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3829{
3830 int i, j, m, modes = 0;
3831 struct drm_display_mode *mode;
3832 const u8 *est = ((const u8 *)timing) + 6;
3833
3834 for (i = 0; i < 6; i++) {
3835 for (j = 7; j >= 0; j--) {
3836 m = (i * 8) + (7 - j);
3837 if (m >= ARRAY_SIZE(est3_modes))
3838 break;
3839 if (est[i] & (1 << j)) {
3840 mode = drm_mode_find_dmt(connector->dev,
3841 est3_modes[m].w,
3842 est3_modes[m].h,
3843 est3_modes[m].r,
3844 est3_modes[m].rb);
3845 if (mode) {
3846 drm_mode_probed_add(connector, mode);
3847 modes++;
3848 }
3849 }
3850 }
3851 }
3852
3853 return modes;
3854}
3855
3856static void
3857do_established_modes(const struct detailed_timing *timing, void *c)
3858{
3859 struct detailed_mode_closure *closure = c;
3860
3861 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3862 return;
3863
3864 closure->modes += drm_est3_modes(closure->connector, timing);
3865}
3866
3867/*
3868 * Get established modes from EDID and add them. Each EDID block contains a
3869 * bitmap of the supported "established modes" list (defined above). Tease them
3870 * out and add them to the global modes list.
3871 */
3872static int add_established_modes(struct drm_connector *connector,
3873 const struct drm_edid *drm_edid)
3874{
3875 struct drm_device *dev = connector->dev;
3876 const struct edid *edid = drm_edid->edid;
3877 unsigned long est_bits = edid->established_timings.t1 |
3878 (edid->established_timings.t2 << 8) |
3879 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3880 int i, modes = 0;
3881 struct detailed_mode_closure closure = {
3882 .connector = connector,
3883 .drm_edid = drm_edid,
3884 };
3885
3886 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3887 if (est_bits & (1<<i)) {
3888 struct drm_display_mode *newmode;
3889
3890 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3891 if (newmode) {
3892 drm_mode_probed_add(connector, newmode);
3893 modes++;
3894 }
3895 }
3896 }
3897
3898 if (edid->revision >= 1)
3899 drm_for_each_detailed_block(drm_edid, do_established_modes,
3900 &closure);
3901
3902 return modes + closure.modes;
3903}
3904
3905static void
3906do_standard_modes(const struct detailed_timing *timing, void *c)
3907{
3908 struct detailed_mode_closure *closure = c;
3909 const struct detailed_non_pixel *data = &timing->data.other_data;
3910 struct drm_connector *connector = closure->connector;
3911 int i;
3912
3913 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3914 return;
3915
3916 for (i = 0; i < 6; i++) {
3917 const struct std_timing *std = &data->data.timings[i];
3918 struct drm_display_mode *newmode;
3919
3920 newmode = drm_mode_std(connector, closure->drm_edid, std);
3921 if (newmode) {
3922 drm_mode_probed_add(connector, newmode);
3923 closure->modes++;
3924 }
3925 }
3926}
3927
3928/*
3929 * Get standard modes from EDID and add them. Standard modes can be calculated
3930 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3931 * add them to the list.
3932 */
3933static int add_standard_modes(struct drm_connector *connector,
3934 const struct drm_edid *drm_edid)
3935{
3936 int i, modes = 0;
3937 struct detailed_mode_closure closure = {
3938 .connector = connector,
3939 .drm_edid = drm_edid,
3940 };
3941
3942 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3943 struct drm_display_mode *newmode;
3944
3945 newmode = drm_mode_std(connector, drm_edid,
3946 &drm_edid->edid->standard_timings[i]);
3947 if (newmode) {
3948 drm_mode_probed_add(connector, newmode);
3949 modes++;
3950 }
3951 }
3952
3953 if (drm_edid->edid->revision >= 1)
3954 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3955 &closure);
3956
3957 /* XXX should also look for standard codes in VTB blocks */
3958
3959 return modes + closure.modes;
3960}
3961
3962static int drm_cvt_modes(struct drm_connector *connector,
3963 const struct detailed_timing *timing)
3964{
3965 int i, j, modes = 0;
3966 struct drm_display_mode *newmode;
3967 struct drm_device *dev = connector->dev;
3968 const struct cvt_timing *cvt;
3969 static const int rates[] = { 60, 85, 75, 60, 50 };
3970 const u8 empty[3] = { 0, 0, 0 };
3971
3972 for (i = 0; i < 4; i++) {
3973 int width, height;
3974
3975 cvt = &(timing->data.other_data.data.cvt[i]);
3976
3977 if (!memcmp(cvt->code, empty, 3))
3978 continue;
3979
3980 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3981 switch (cvt->code[1] & 0x0c) {
3982 /* default - because compiler doesn't see that we've enumerated all cases */
3983 default:
3984 case 0x00:
3985 width = height * 4 / 3;
3986 break;
3987 case 0x04:
3988 width = height * 16 / 9;
3989 break;
3990 case 0x08:
3991 width = height * 16 / 10;
3992 break;
3993 case 0x0c:
3994 width = height * 15 / 9;
3995 break;
3996 }
3997
3998 for (j = 1; j < 5; j++) {
3999 if (cvt->code[2] & (1 << j)) {
4000 newmode = drm_cvt_mode(dev, width, height,
4001 rates[j], j == 0,
4002 false, false);
4003 if (newmode) {
4004 drm_mode_probed_add(connector, newmode);
4005 modes++;
4006 }
4007 }
4008 }
4009 }
4010
4011 return modes;
4012}
4013
4014static void
4015do_cvt_mode(const struct detailed_timing *timing, void *c)
4016{
4017 struct detailed_mode_closure *closure = c;
4018
4019 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4020 return;
4021
4022 closure->modes += drm_cvt_modes(closure->connector, timing);
4023}
4024
4025static int
4026add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4027{
4028 struct detailed_mode_closure closure = {
4029 .connector = connector,
4030 .drm_edid = drm_edid,
4031 };
4032
4033 if (drm_edid->edid->revision >= 3)
4034 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4035
4036 /* XXX should also look for CVT codes in VTB blocks */
4037
4038 return closure.modes;
4039}
4040
4041static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4042 struct drm_display_mode *mode);
4043
4044static void
4045do_detailed_mode(const struct detailed_timing *timing, void *c)
4046{
4047 struct detailed_mode_closure *closure = c;
4048 struct drm_display_mode *newmode;
4049
4050 if (!is_detailed_timing_descriptor(timing))
4051 return;
4052
4053 newmode = drm_mode_detailed(closure->connector,
4054 closure->drm_edid, timing);
4055 if (!newmode)
4056 return;
4057
4058 if (closure->preferred)
4059 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4060
4061 /*
4062 * Detailed modes are limited to 10kHz pixel clock resolution,
4063 * so fix up anything that looks like CEA/HDMI mode, but the clock
4064 * is just slightly off.
4065 */
4066 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4067
4068 drm_mode_probed_add(closure->connector, newmode);
4069 closure->modes++;
4070 closure->preferred = false;
4071}
4072
4073/*
4074 * add_detailed_modes - Add modes from detailed timings
4075 * @connector: attached connector
4076 * @drm_edid: EDID block to scan
4077 */
4078static int add_detailed_modes(struct drm_connector *connector,
4079 const struct drm_edid *drm_edid)
4080{
4081 struct detailed_mode_closure closure = {
4082 .connector = connector,
4083 .drm_edid = drm_edid,
4084 };
4085
4086 if (drm_edid->edid->revision >= 4)
4087 closure.preferred = true; /* first detailed timing is always preferred */
4088 else
4089 closure.preferred =
4090 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4091
4092 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4093
4094 return closure.modes;
4095}
4096
4097/* CTA-861-H Table 60 - CTA Tag Codes */
4098#define CTA_DB_AUDIO 1
4099#define CTA_DB_VIDEO 2
4100#define CTA_DB_VENDOR 3
4101#define CTA_DB_SPEAKER 4
4102#define CTA_DB_EXTENDED_TAG 7
4103
4104/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4105#define CTA_EXT_DB_VIDEO_CAP 0
4106#define CTA_EXT_DB_VENDOR 1
4107#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4108#define CTA_EXT_DB_420_VIDEO_DATA 14
4109#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4110#define CTA_EXT_DB_HF_EEODB 0x78
4111#define CTA_EXT_DB_HF_SCDB 0x79
4112
4113#define EDID_BASIC_AUDIO (1 << 6)
4114#define EDID_CEA_YCRCB444 (1 << 5)
4115#define EDID_CEA_YCRCB422 (1 << 4)
4116#define EDID_CEA_VCDB_QS (1 << 6)
4117
4118/*
4119 * Search EDID for CEA extension block.
4120 *
4121 * FIXME: Prefer not returning pointers to raw EDID data.
4122 */
4123const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4124 int ext_id, int *ext_index)
4125{
4126 const u8 *edid_ext = NULL;
4127 int i;
4128
4129 /* No EDID or EDID extensions */
4130 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4131 return NULL;
4132
4133 /* Find CEA extension */
4134 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4135 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4136 if (edid_block_tag(edid_ext) == ext_id)
4137 break;
4138 }
4139
4140 if (i >= drm_edid_extension_block_count(drm_edid))
4141 return NULL;
4142
4143 *ext_index = i + 1;
4144
4145 return edid_ext;
4146}
4147
4148/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4149static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4150{
4151 const struct displayid_block *block;
4152 struct displayid_iter iter;
4153 int ext_index = 0;
4154 bool found = false;
4155
4156 /* Look for a top level CEA extension block */
4157 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4158 return true;
4159
4160 /* CEA blocks can also be found embedded in a DisplayID block */
4161 displayid_iter_edid_begin(drm_edid, &iter);
4162 displayid_iter_for_each(block, &iter) {
4163 if (block->tag == DATA_BLOCK_CTA) {
4164 found = true;
4165 break;
4166 }
4167 }
4168 displayid_iter_end(&iter);
4169
4170 return found;
4171}
4172
4173static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4174{
4175 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4176 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4177
4178 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4179 return &edid_cea_modes_1[vic - 1];
4180 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4181 return &edid_cea_modes_193[vic - 193];
4182 return NULL;
4183}
4184
4185static u8 cea_num_vics(void)
4186{
4187 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4188}
4189
4190static u8 cea_next_vic(u8 vic)
4191{
4192 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4193 vic = 193;
4194 return vic;
4195}
4196
4197/*
4198 * Calculate the alternate clock for the CEA mode
4199 * (60Hz vs. 59.94Hz etc.)
4200 */
4201static unsigned int
4202cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4203{
4204 unsigned int clock = cea_mode->clock;
4205
4206 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4207 return clock;
4208
4209 /*
4210 * edid_cea_modes contains the 59.94Hz
4211 * variant for 240 and 480 line modes,
4212 * and the 60Hz variant otherwise.
4213 */
4214 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4215 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4216 else
4217 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4218
4219 return clock;
4220}
4221
4222static bool
4223cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4224{
4225 /*
4226 * For certain VICs the spec allows the vertical
4227 * front porch to vary by one or two lines.
4228 *
4229 * cea_modes[] stores the variant with the shortest
4230 * vertical front porch. We can adjust the mode to
4231 * get the other variants by simply increasing the
4232 * vertical front porch length.
4233 */
4234 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4235 cea_mode_for_vic(9)->vtotal != 262 ||
4236 cea_mode_for_vic(12)->vtotal != 262 ||
4237 cea_mode_for_vic(13)->vtotal != 262 ||
4238 cea_mode_for_vic(23)->vtotal != 312 ||
4239 cea_mode_for_vic(24)->vtotal != 312 ||
4240 cea_mode_for_vic(27)->vtotal != 312 ||
4241 cea_mode_for_vic(28)->vtotal != 312);
4242
4243 if (((vic == 8 || vic == 9 ||
4244 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4245 ((vic == 23 || vic == 24 ||
4246 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4247 mode->vsync_start++;
4248 mode->vsync_end++;
4249 mode->vtotal++;
4250
4251 return true;
4252 }
4253
4254 return false;
4255}
4256
4257static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4258 unsigned int clock_tolerance)
4259{
4260 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4261 u8 vic;
4262
4263 if (!to_match->clock)
4264 return 0;
4265
4266 if (to_match->picture_aspect_ratio)
4267 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4268
4269 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4270 struct drm_display_mode cea_mode;
4271 unsigned int clock1, clock2;
4272
4273 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4274
4275 /* Check both 60Hz and 59.94Hz */
4276 clock1 = cea_mode.clock;
4277 clock2 = cea_mode_alternate_clock(&cea_mode);
4278
4279 if (abs(to_match->clock - clock1) > clock_tolerance &&
4280 abs(to_match->clock - clock2) > clock_tolerance)
4281 continue;
4282
4283 do {
4284 if (drm_mode_match(to_match, &cea_mode, match_flags))
4285 return vic;
4286 } while (cea_mode_alternate_timings(vic, &cea_mode));
4287 }
4288
4289 return 0;
4290}
4291
4292/**
4293 * drm_match_cea_mode - look for a CEA mode matching given mode
4294 * @to_match: display mode
4295 *
4296 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4297 * mode.
4298 */
4299u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4300{
4301 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4302 u8 vic;
4303
4304 if (!to_match->clock)
4305 return 0;
4306
4307 if (to_match->picture_aspect_ratio)
4308 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4309
4310 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4311 struct drm_display_mode cea_mode;
4312 unsigned int clock1, clock2;
4313
4314 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4315
4316 /* Check both 60Hz and 59.94Hz */
4317 clock1 = cea_mode.clock;
4318 clock2 = cea_mode_alternate_clock(&cea_mode);
4319
4320 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4321 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4322 continue;
4323
4324 do {
4325 if (drm_mode_match(to_match, &cea_mode, match_flags))
4326 return vic;
4327 } while (cea_mode_alternate_timings(vic, &cea_mode));
4328 }
4329
4330 return 0;
4331}
4332EXPORT_SYMBOL(drm_match_cea_mode);
4333
4334static bool drm_valid_cea_vic(u8 vic)
4335{
4336 return cea_mode_for_vic(vic) != NULL;
4337}
4338
4339static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4340{
4341 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4342
4343 if (mode)
4344 return mode->picture_aspect_ratio;
4345
4346 return HDMI_PICTURE_ASPECT_NONE;
4347}
4348
4349static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4350{
4351 return edid_4k_modes[video_code].picture_aspect_ratio;
4352}
4353
4354/*
4355 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4356 * specific block).
4357 */
4358static unsigned int
4359hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4360{
4361 return cea_mode_alternate_clock(hdmi_mode);
4362}
4363
4364static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4365 unsigned int clock_tolerance)
4366{
4367 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4368 u8 vic;
4369
4370 if (!to_match->clock)
4371 return 0;
4372
4373 if (to_match->picture_aspect_ratio)
4374 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4375
4376 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4377 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4378 unsigned int clock1, clock2;
4379
4380 /* Make sure to also match alternate clocks */
4381 clock1 = hdmi_mode->clock;
4382 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4383
4384 if (abs(to_match->clock - clock1) > clock_tolerance &&
4385 abs(to_match->clock - clock2) > clock_tolerance)
4386 continue;
4387
4388 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4389 return vic;
4390 }
4391
4392 return 0;
4393}
4394
4395/*
4396 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4397 * @to_match: display mode
4398 *
4399 * An HDMI mode is one defined in the HDMI vendor specific block.
4400 *
4401 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4402 */
4403static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4404{
4405 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4406 u8 vic;
4407
4408 if (!to_match->clock)
4409 return 0;
4410
4411 if (to_match->picture_aspect_ratio)
4412 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4413
4414 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4415 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4416 unsigned int clock1, clock2;
4417
4418 /* Make sure to also match alternate clocks */
4419 clock1 = hdmi_mode->clock;
4420 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4421
4422 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4423 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4424 drm_mode_match(to_match, hdmi_mode, match_flags))
4425 return vic;
4426 }
4427 return 0;
4428}
4429
4430static bool drm_valid_hdmi_vic(u8 vic)
4431{
4432 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4433}
4434
4435static int add_alternate_cea_modes(struct drm_connector *connector,
4436 const struct drm_edid *drm_edid)
4437{
4438 struct drm_device *dev = connector->dev;
4439 struct drm_display_mode *mode, *tmp;
4440 LIST_HEAD(list);
4441 int modes = 0;
4442
4443 /* Don't add CTA modes if the CTA extension block is missing */
4444 if (!drm_edid_has_cta_extension(drm_edid))
4445 return 0;
4446
4447 /*
4448 * Go through all probed modes and create a new mode
4449 * with the alternate clock for certain CEA modes.
4450 */
4451 list_for_each_entry(mode, &connector->probed_modes, head) {
4452 const struct drm_display_mode *cea_mode = NULL;
4453 struct drm_display_mode *newmode;
4454 u8 vic = drm_match_cea_mode(mode);
4455 unsigned int clock1, clock2;
4456
4457 if (drm_valid_cea_vic(vic)) {
4458 cea_mode = cea_mode_for_vic(vic);
4459 clock2 = cea_mode_alternate_clock(cea_mode);
4460 } else {
4461 vic = drm_match_hdmi_mode(mode);
4462 if (drm_valid_hdmi_vic(vic)) {
4463 cea_mode = &edid_4k_modes[vic];
4464 clock2 = hdmi_mode_alternate_clock(cea_mode);
4465 }
4466 }
4467
4468 if (!cea_mode)
4469 continue;
4470
4471 clock1 = cea_mode->clock;
4472
4473 if (clock1 == clock2)
4474 continue;
4475
4476 if (mode->clock != clock1 && mode->clock != clock2)
4477 continue;
4478
4479 newmode = drm_mode_duplicate(dev, cea_mode);
4480 if (!newmode)
4481 continue;
4482
4483 /* Carry over the stereo flags */
4484 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4485
4486 /*
4487 * The current mode could be either variant. Make
4488 * sure to pick the "other" clock for the new mode.
4489 */
4490 if (mode->clock != clock1)
4491 newmode->clock = clock1;
4492 else
4493 newmode->clock = clock2;
4494
4495 list_add_tail(&newmode->head, &list);
4496 }
4497
4498 list_for_each_entry_safe(mode, tmp, &list, head) {
4499 list_del(&mode->head);
4500 drm_mode_probed_add(connector, mode);
4501 modes++;
4502 }
4503
4504 return modes;
4505}
4506
4507static u8 svd_to_vic(u8 svd)
4508{
4509 /* 0-6 bit vic, 7th bit native mode indicator */
4510 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4511 return svd & 127;
4512
4513 return svd;
4514}
4515
4516/*
4517 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4518 * the EDID, or NULL on errors.
4519 */
4520static struct drm_display_mode *
4521drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4522{
4523 const struct drm_display_info *info = &connector->display_info;
4524 struct drm_device *dev = connector->dev;
4525
4526 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4527 return NULL;
4528
4529 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4530}
4531
4532/*
4533 * do_y420vdb_modes - Parse YCBCR 420 only modes
4534 * @connector: connector corresponding to the HDMI sink
4535 * @svds: start of the data block of CEA YCBCR 420 VDB
4536 * @len: length of the CEA YCBCR 420 VDB
4537 *
4538 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4539 * which contains modes which can be supported in YCBCR 420
4540 * output format only.
4541 */
4542static int do_y420vdb_modes(struct drm_connector *connector,
4543 const u8 *svds, u8 svds_len)
4544{
4545 struct drm_device *dev = connector->dev;
4546 int modes = 0, i;
4547
4548 for (i = 0; i < svds_len; i++) {
4549 u8 vic = svd_to_vic(svds[i]);
4550 struct drm_display_mode *newmode;
4551
4552 if (!drm_valid_cea_vic(vic))
4553 continue;
4554
4555 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4556 if (!newmode)
4557 break;
4558 drm_mode_probed_add(connector, newmode);
4559 modes++;
4560 }
4561
4562 return modes;
4563}
4564
4565/**
4566 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4567 * @dev: DRM device
4568 * @video_code: CEA VIC of the mode
4569 *
4570 * Creates a new mode matching the specified CEA VIC.
4571 *
4572 * Returns: A new drm_display_mode on success or NULL on failure
4573 */
4574struct drm_display_mode *
4575drm_display_mode_from_cea_vic(struct drm_device *dev,
4576 u8 video_code)
4577{
4578 const struct drm_display_mode *cea_mode;
4579 struct drm_display_mode *newmode;
4580
4581 cea_mode = cea_mode_for_vic(video_code);
4582 if (!cea_mode)
4583 return NULL;
4584
4585 newmode = drm_mode_duplicate(dev, cea_mode);
4586 if (!newmode)
4587 return NULL;
4588
4589 return newmode;
4590}
4591EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4592
4593/* Add modes based on VICs parsed in parse_cta_vdb() */
4594static int add_cta_vdb_modes(struct drm_connector *connector)
4595{
4596 const struct drm_display_info *info = &connector->display_info;
4597 int i, modes = 0;
4598
4599 if (!info->vics)
4600 return 0;
4601
4602 for (i = 0; i < info->vics_len; i++) {
4603 struct drm_display_mode *mode;
4604
4605 mode = drm_display_mode_from_vic_index(connector, i);
4606 if (mode) {
4607 drm_mode_probed_add(connector, mode);
4608 modes++;
4609 }
4610 }
4611
4612 return modes;
4613}
4614
4615struct stereo_mandatory_mode {
4616 int width, height, vrefresh;
4617 unsigned int flags;
4618};
4619
4620static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4621 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4622 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4623 { 1920, 1080, 50,
4624 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4625 { 1920, 1080, 60,
4626 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4627 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4628 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4629 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4630 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4631};
4632
4633static bool
4634stereo_match_mandatory(const struct drm_display_mode *mode,
4635 const struct stereo_mandatory_mode *stereo_mode)
4636{
4637 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4638
4639 return mode->hdisplay == stereo_mode->width &&
4640 mode->vdisplay == stereo_mode->height &&
4641 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4642 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4643}
4644
4645static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4646{
4647 struct drm_device *dev = connector->dev;
4648 const struct drm_display_mode *mode;
4649 struct list_head stereo_modes;
4650 int modes = 0, i;
4651
4652 INIT_LIST_HEAD(&stereo_modes);
4653
4654 list_for_each_entry(mode, &connector->probed_modes, head) {
4655 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4656 const struct stereo_mandatory_mode *mandatory;
4657 struct drm_display_mode *new_mode;
4658
4659 if (!stereo_match_mandatory(mode,
4660 &stereo_mandatory_modes[i]))
4661 continue;
4662
4663 mandatory = &stereo_mandatory_modes[i];
4664 new_mode = drm_mode_duplicate(dev, mode);
4665 if (!new_mode)
4666 continue;
4667
4668 new_mode->flags |= mandatory->flags;
4669 list_add_tail(&new_mode->head, &stereo_modes);
4670 modes++;
4671 }
4672 }
4673
4674 list_splice_tail(&stereo_modes, &connector->probed_modes);
4675
4676 return modes;
4677}
4678
4679static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4680{
4681 struct drm_device *dev = connector->dev;
4682 struct drm_display_mode *newmode;
4683
4684 if (!drm_valid_hdmi_vic(vic)) {
4685 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4686 connector->base.id, connector->name, vic);
4687 return 0;
4688 }
4689
4690 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4691 if (!newmode)
4692 return 0;
4693
4694 drm_mode_probed_add(connector, newmode);
4695
4696 return 1;
4697}
4698
4699static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4700 int vic_index)
4701{
4702 struct drm_display_mode *newmode;
4703 int modes = 0;
4704
4705 if (structure & (1 << 0)) {
4706 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4707 if (newmode) {
4708 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4709 drm_mode_probed_add(connector, newmode);
4710 modes++;
4711 }
4712 }
4713 if (structure & (1 << 6)) {
4714 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4715 if (newmode) {
4716 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4717 drm_mode_probed_add(connector, newmode);
4718 modes++;
4719 }
4720 }
4721 if (structure & (1 << 8)) {
4722 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4723 if (newmode) {
4724 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4725 drm_mode_probed_add(connector, newmode);
4726 modes++;
4727 }
4728 }
4729
4730 return modes;
4731}
4732
4733static bool hdmi_vsdb_latency_present(const u8 *db)
4734{
4735 return db[8] & BIT(7);
4736}
4737
4738static bool hdmi_vsdb_i_latency_present(const u8 *db)
4739{
4740 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4741}
4742
4743static int hdmi_vsdb_latency_length(const u8 *db)
4744{
4745 if (hdmi_vsdb_i_latency_present(db))
4746 return 4;
4747 else if (hdmi_vsdb_latency_present(db))
4748 return 2;
4749 else
4750 return 0;
4751}
4752
4753/*
4754 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4755 * @connector: connector corresponding to the HDMI sink
4756 * @db: start of the CEA vendor specific block
4757 * @len: length of the CEA block payload, ie. one can access up to db[len]
4758 *
4759 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4760 * also adds the stereo 3d modes when applicable.
4761 */
4762static int
4763do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4764{
4765 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4766 u8 vic_len, hdmi_3d_len = 0;
4767 u16 mask;
4768 u16 structure_all;
4769
4770 if (len < 8)
4771 goto out;
4772
4773 /* no HDMI_Video_Present */
4774 if (!(db[8] & (1 << 5)))
4775 goto out;
4776
4777 offset += hdmi_vsdb_latency_length(db);
4778
4779 /* the declared length is not long enough for the 2 first bytes
4780 * of additional video format capabilities */
4781 if (len < (8 + offset + 2))
4782 goto out;
4783
4784 /* 3D_Present */
4785 offset++;
4786 if (db[8 + offset] & (1 << 7)) {
4787 modes += add_hdmi_mandatory_stereo_modes(connector);
4788
4789 /* 3D_Multi_present */
4790 multi_present = (db[8 + offset] & 0x60) >> 5;
4791 }
4792
4793 offset++;
4794 vic_len = db[8 + offset] >> 5;
4795 hdmi_3d_len = db[8 + offset] & 0x1f;
4796
4797 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4798 u8 vic;
4799
4800 vic = db[9 + offset + i];
4801 modes += add_hdmi_mode(connector, vic);
4802 }
4803 offset += 1 + vic_len;
4804
4805 if (multi_present == 1)
4806 multi_len = 2;
4807 else if (multi_present == 2)
4808 multi_len = 4;
4809 else
4810 multi_len = 0;
4811
4812 if (len < (8 + offset + hdmi_3d_len - 1))
4813 goto out;
4814
4815 if (hdmi_3d_len < multi_len)
4816 goto out;
4817
4818 if (multi_present == 1 || multi_present == 2) {
4819 /* 3D_Structure_ALL */
4820 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4821
4822 /* check if 3D_MASK is present */
4823 if (multi_present == 2)
4824 mask = (db[10 + offset] << 8) | db[11 + offset];
4825 else
4826 mask = 0xffff;
4827
4828 for (i = 0; i < 16; i++) {
4829 if (mask & (1 << i))
4830 modes += add_3d_struct_modes(connector,
4831 structure_all, i);
4832 }
4833 }
4834
4835 offset += multi_len;
4836
4837 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4838 int vic_index;
4839 struct drm_display_mode *newmode = NULL;
4840 unsigned int newflag = 0;
4841 bool detail_present;
4842
4843 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4844
4845 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4846 break;
4847
4848 /* 2D_VIC_order_X */
4849 vic_index = db[8 + offset + i] >> 4;
4850
4851 /* 3D_Structure_X */
4852 switch (db[8 + offset + i] & 0x0f) {
4853 case 0:
4854 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4855 break;
4856 case 6:
4857 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4858 break;
4859 case 8:
4860 /* 3D_Detail_X */
4861 if ((db[9 + offset + i] >> 4) == 1)
4862 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4863 break;
4864 }
4865
4866 if (newflag != 0) {
4867 newmode = drm_display_mode_from_vic_index(connector,
4868 vic_index);
4869
4870 if (newmode) {
4871 newmode->flags |= newflag;
4872 drm_mode_probed_add(connector, newmode);
4873 modes++;
4874 }
4875 }
4876
4877 if (detail_present)
4878 i++;
4879 }
4880
4881out:
4882 return modes;
4883}
4884
4885static int
4886cea_revision(const u8 *cea)
4887{
4888 /*
4889 * FIXME is this correct for the DispID variant?
4890 * The DispID spec doesn't really specify whether
4891 * this is the revision of the CEA extension or
4892 * the DispID CEA data block. And the only value
4893 * given as an example is 0.
4894 */
4895 return cea[1];
4896}
4897
4898/*
4899 * CTA Data Block iterator.
4900 *
4901 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4902 * CTA Data Blocks.
4903 *
4904 * struct cea_db *db:
4905 * struct cea_db_iter iter;
4906 *
4907 * cea_db_iter_edid_begin(edid, &iter);
4908 * cea_db_iter_for_each(db, &iter) {
4909 * // do stuff with db
4910 * }
4911 * cea_db_iter_end(&iter);
4912 */
4913struct cea_db_iter {
4914 struct drm_edid_iter edid_iter;
4915 struct displayid_iter displayid_iter;
4916
4917 /* Current Data Block Collection. */
4918 const u8 *collection;
4919
4920 /* Current Data Block index in current collection. */
4921 int index;
4922
4923 /* End index in current collection. */
4924 int end;
4925};
4926
4927/* CTA-861-H section 7.4 CTA Data BLock Collection */
4928struct cea_db {
4929 u8 tag_length;
4930 u8 data[];
4931} __packed;
4932
4933static int cea_db_tag(const struct cea_db *db)
4934{
4935 return db->tag_length >> 5;
4936}
4937
4938static int cea_db_payload_len(const void *_db)
4939{
4940 /* FIXME: Transition to passing struct cea_db * everywhere. */
4941 const struct cea_db *db = _db;
4942
4943 return db->tag_length & 0x1f;
4944}
4945
4946static const void *cea_db_data(const struct cea_db *db)
4947{
4948 return db->data;
4949}
4950
4951static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4952{
4953 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4954 cea_db_payload_len(db) >= 1 &&
4955 db->data[0] == tag;
4956}
4957
4958static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4959{
4960 const u8 *data = cea_db_data(db);
4961
4962 return cea_db_tag(db) == CTA_DB_VENDOR &&
4963 cea_db_payload_len(db) >= 3 &&
4964 oui(data[2], data[1], data[0]) == vendor_oui;
4965}
4966
4967static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4968 struct cea_db_iter *iter)
4969{
4970 memset(iter, 0, sizeof(*iter));
4971
4972 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4973 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4974}
4975
4976static const struct cea_db *
4977__cea_db_iter_current_block(const struct cea_db_iter *iter)
4978{
4979 const struct cea_db *db;
4980
4981 if (!iter->collection)
4982 return NULL;
4983
4984 db = (const struct cea_db *)&iter->collection[iter->index];
4985
4986 if (iter->index + sizeof(*db) <= iter->end &&
4987 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4988 return db;
4989
4990 return NULL;
4991}
4992
4993/*
4994 * References:
4995 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4996 */
4997static int cea_db_collection_size(const u8 *cta)
4998{
4999 u8 d = cta[2];
5000
5001 if (d < 4 || d > 127)
5002 return 0;
5003
5004 return d - 4;
5005}
5006
5007/*
5008 * References:
5009 * - VESA E-EDID v1.4
5010 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5011 */
5012static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5013{
5014 const u8 *ext;
5015
5016 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5017 int size;
5018
5019 /* Only support CTA Extension revision 3+ */
5020 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5021 continue;
5022
5023 size = cea_db_collection_size(ext);
5024 if (!size)
5025 continue;
5026
5027 iter->index = 4;
5028 iter->end = iter->index + size;
5029
5030 return ext;
5031 }
5032
5033 return NULL;
5034}
5035
5036/*
5037 * References:
5038 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5039 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5040 *
5041 * Note that the above do not specify any connection between DisplayID Data
5042 * Block revision and CTA Extension versions.
5043 */
5044static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5045{
5046 const struct displayid_block *block;
5047
5048 displayid_iter_for_each(block, &iter->displayid_iter) {
5049 if (block->tag != DATA_BLOCK_CTA)
5050 continue;
5051
5052 /*
5053 * The displayid iterator has already verified the block bounds
5054 * in displayid_iter_block().
5055 */
5056 iter->index = sizeof(*block);
5057 iter->end = iter->index + block->num_bytes;
5058
5059 return block;
5060 }
5061
5062 return NULL;
5063}
5064
5065static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5066{
5067 const struct cea_db *db;
5068
5069 if (iter->collection) {
5070 /* Current collection should always be valid. */
5071 db = __cea_db_iter_current_block(iter);
5072 if (WARN_ON(!db)) {
5073 iter->collection = NULL;
5074 return NULL;
5075 }
5076
5077 /* Next block in CTA Data Block Collection */
5078 iter->index += sizeof(*db) + cea_db_payload_len(db);
5079
5080 db = __cea_db_iter_current_block(iter);
5081 if (db)
5082 return db;
5083 }
5084
5085 for (;;) {
5086 /*
5087 * Find the next CTA Data Block Collection. First iterate all
5088 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5089 *
5090 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5091 * Extension, it's recommended that DisplayID extensions are
5092 * exposed after all of the CTA Extensions.
5093 */
5094 iter->collection = __cea_db_iter_edid_next(iter);
5095 if (!iter->collection)
5096 iter->collection = __cea_db_iter_displayid_next(iter);
5097
5098 if (!iter->collection)
5099 return NULL;
5100
5101 db = __cea_db_iter_current_block(iter);
5102 if (db)
5103 return db;
5104 }
5105}
5106
5107#define cea_db_iter_for_each(__db, __iter) \
5108 while (((__db) = __cea_db_iter_next(__iter)))
5109
5110static void cea_db_iter_end(struct cea_db_iter *iter)
5111{
5112 displayid_iter_end(&iter->displayid_iter);
5113 drm_edid_iter_end(&iter->edid_iter);
5114
5115 memset(iter, 0, sizeof(*iter));
5116}
5117
5118static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5119{
5120 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5121 cea_db_payload_len(db) >= 5;
5122}
5123
5124static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5125{
5126 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5127 cea_db_payload_len(db) >= 7;
5128}
5129
5130static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5131{
5132 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5133 cea_db_payload_len(db) >= 2;
5134}
5135
5136static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5137{
5138 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5139 cea_db_payload_len(db) == 21;
5140}
5141
5142static bool cea_db_is_vcdb(const struct cea_db *db)
5143{
5144 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5145 cea_db_payload_len(db) == 2;
5146}
5147
5148static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5149{
5150 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5151 cea_db_payload_len(db) >= 7;
5152}
5153
5154static bool cea_db_is_y420cmdb(const struct cea_db *db)
5155{
5156 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5157}
5158
5159static bool cea_db_is_y420vdb(const struct cea_db *db)
5160{
5161 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5162}
5163
5164static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5165{
5166 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5167 cea_db_payload_len(db) >= 3;
5168}
5169
5170/*
5171 * Get the HF-EEODB override extension block count from EDID.
5172 *
5173 * The passed in EDID may be partially read, as long as it has at least two
5174 * blocks (base block and one extension block) if EDID extension count is > 0.
5175 *
5176 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5177 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5178 * iterators instead.
5179 *
5180 * References:
5181 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5182 */
5183static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5184{
5185 const u8 *cta;
5186
5187 /* No extensions according to base block, no HF-EEODB. */
5188 if (!edid_extension_block_count(edid))
5189 return 0;
5190
5191 /* HF-EEODB is always in the first EDID extension block only */
5192 cta = edid_extension_block_data(edid, 0);
5193 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5194 return 0;
5195
5196 /* Need to have the data block collection, and at least 3 bytes. */
5197 if (cea_db_collection_size(cta) < 3)
5198 return 0;
5199
5200 /*
5201 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5202 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5203 * through 6 of Block 1 of the E-EDID.
5204 */
5205 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5206 return 0;
5207
5208 return cta[4 + 2];
5209}
5210
5211/*
5212 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5213 *
5214 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5215 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5216 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5217 * support YCBCR420 output too.
5218 */
5219static void parse_cta_y420cmdb(struct drm_connector *connector,
5220 const struct cea_db *db, u64 *y420cmdb_map)
5221{
5222 struct drm_display_info *info = &connector->display_info;
5223 int i, map_len = cea_db_payload_len(db) - 1;
5224 const u8 *data = cea_db_data(db) + 1;
5225 u64 map = 0;
5226
5227 if (map_len == 0) {
5228 /* All CEA modes support ycbcr420 sampling also.*/
5229 map = U64_MAX;
5230 goto out;
5231 }
5232
5233 /*
5234 * This map indicates which of the existing CEA block modes
5235 * from VDB can support YCBCR420 output too. So if bit=0 is
5236 * set, first mode from VDB can support YCBCR420 output too.
5237 * We will parse and keep this map, before parsing VDB itself
5238 * to avoid going through the same block again and again.
5239 *
5240 * Spec is not clear about max possible size of this block.
5241 * Clamping max bitmap block size at 8 bytes. Every byte can
5242 * address 8 CEA modes, in this way this map can address
5243 * 8*8 = first 64 SVDs.
5244 */
5245 if (WARN_ON_ONCE(map_len > 8))
5246 map_len = 8;
5247
5248 for (i = 0; i < map_len; i++)
5249 map |= (u64)data[i] << (8 * i);
5250
5251out:
5252 if (map)
5253 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5254
5255 *y420cmdb_map = map;
5256}
5257
5258static int add_cea_modes(struct drm_connector *connector,
5259 const struct drm_edid *drm_edid)
5260{
5261 const struct cea_db *db;
5262 struct cea_db_iter iter;
5263 int modes;
5264
5265 /* CTA VDB block VICs parsed earlier */
5266 modes = add_cta_vdb_modes(connector);
5267
5268 cea_db_iter_edid_begin(drm_edid, &iter);
5269 cea_db_iter_for_each(db, &iter) {
5270 if (cea_db_is_hdmi_vsdb(db)) {
5271 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5272 cea_db_payload_len(db));
5273 } else if (cea_db_is_y420vdb(db)) {
5274 const u8 *vdb420 = cea_db_data(db) + 1;
5275
5276 /* Add 4:2:0(only) modes present in EDID */
5277 modes += do_y420vdb_modes(connector, vdb420,
5278 cea_db_payload_len(db) - 1);
5279 }
5280 }
5281 cea_db_iter_end(&iter);
5282
5283 return modes;
5284}
5285
5286static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5287 struct drm_display_mode *mode)
5288{
5289 const struct drm_display_mode *cea_mode;
5290 int clock1, clock2, clock;
5291 u8 vic;
5292 const char *type;
5293
5294 /*
5295 * allow 5kHz clock difference either way to account for
5296 * the 10kHz clock resolution limit of detailed timings.
5297 */
5298 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5299 if (drm_valid_cea_vic(vic)) {
5300 type = "CEA";
5301 cea_mode = cea_mode_for_vic(vic);
5302 clock1 = cea_mode->clock;
5303 clock2 = cea_mode_alternate_clock(cea_mode);
5304 } else {
5305 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5306 if (drm_valid_hdmi_vic(vic)) {
5307 type = "HDMI";
5308 cea_mode = &edid_4k_modes[vic];
5309 clock1 = cea_mode->clock;
5310 clock2 = hdmi_mode_alternate_clock(cea_mode);
5311 } else {
5312 return;
5313 }
5314 }
5315
5316 /* pick whichever is closest */
5317 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5318 clock = clock1;
5319 else
5320 clock = clock2;
5321
5322 if (mode->clock == clock)
5323 return;
5324
5325 drm_dbg_kms(connector->dev,
5326 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5327 connector->base.id, connector->name,
5328 type, vic, mode->clock, clock);
5329 mode->clock = clock;
5330}
5331
5332static void drm_calculate_luminance_range(struct drm_connector *connector)
5333{
5334 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5335 struct drm_luminance_range_info *luminance_range =
5336 &connector->display_info.luminance_range;
5337 static const u8 pre_computed_values[] = {
5338 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5339 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5340 };
5341 u32 max_avg, min_cll, max, min, q, r;
5342
5343 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5344 return;
5345
5346 max_avg = hdr_metadata->max_fall;
5347 min_cll = hdr_metadata->min_cll;
5348
5349 /*
5350 * From the specification (CTA-861-G), for calculating the maximum
5351 * luminance we need to use:
5352 * Luminance = 50*2**(CV/32)
5353 * Where CV is a one-byte value.
5354 * For calculating this expression we may need float point precision;
5355 * to avoid this complexity level, we take advantage that CV is divided
5356 * by a constant. From the Euclids division algorithm, we know that CV
5357 * can be written as: CV = 32*q + r. Next, we replace CV in the
5358 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5359 * need to pre-compute the value of r/32. For pre-computing the values
5360 * We just used the following Ruby line:
5361 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5362 * The results of the above expressions can be verified at
5363 * pre_computed_values.
5364 */
5365 q = max_avg >> 5;
5366 r = max_avg % 32;
5367 max = (1 << q) * pre_computed_values[r];
5368
5369 /* min luminance: maxLum * (CV/255)^2 / 100 */
5370 q = DIV_ROUND_CLOSEST(min_cll, 255);
5371 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5372
5373 luminance_range->min_luminance = min;
5374 luminance_range->max_luminance = max;
5375}
5376
5377static uint8_t eotf_supported(const u8 *edid_ext)
5378{
5379 return edid_ext[2] &
5380 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5381 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5382 BIT(HDMI_EOTF_SMPTE_ST2084) |
5383 BIT(HDMI_EOTF_BT_2100_HLG));
5384}
5385
5386static uint8_t hdr_metadata_type(const u8 *edid_ext)
5387{
5388 return edid_ext[3] &
5389 BIT(HDMI_STATIC_METADATA_TYPE1);
5390}
5391
5392static void
5393drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5394{
5395 u16 len;
5396
5397 len = cea_db_payload_len(db);
5398
5399 connector->hdr_sink_metadata.hdmi_type1.eotf =
5400 eotf_supported(db);
5401 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5402 hdr_metadata_type(db);
5403
5404 if (len >= 4)
5405 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5406 if (len >= 5)
5407 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5408 if (len >= 6) {
5409 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5410
5411 /* Calculate only when all values are available */
5412 drm_calculate_luminance_range(connector);
5413 }
5414}
5415
5416/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5417static void
5418drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5419{
5420 u8 len = cea_db_payload_len(db);
5421
5422 if (len >= 6 && (db[6] & (1 << 7)))
5423 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5424
5425 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5426 connector->latency_present[0] = true;
5427 connector->video_latency[0] = db[9];
5428 connector->audio_latency[0] = db[10];
5429 }
5430
5431 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5432 connector->latency_present[1] = true;
5433 connector->video_latency[1] = db[11];
5434 connector->audio_latency[1] = db[12];
5435 }
5436
5437 drm_dbg_kms(connector->dev,
5438 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5439 connector->base.id, connector->name,
5440 connector->latency_present[0], connector->latency_present[1],
5441 connector->video_latency[0], connector->video_latency[1],
5442 connector->audio_latency[0], connector->audio_latency[1]);
5443}
5444
5445static void
5446monitor_name(const struct detailed_timing *timing, void *data)
5447{
5448 const char **res = data;
5449
5450 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5451 return;
5452
5453 *res = timing->data.other_data.data.str.str;
5454}
5455
5456static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5457{
5458 const char *edid_name = NULL;
5459 int mnl;
5460
5461 if (!drm_edid || !name)
5462 return 0;
5463
5464 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5465 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5466 if (edid_name[mnl] == 0x0a)
5467 break;
5468
5469 name[mnl] = edid_name[mnl];
5470 }
5471
5472 return mnl;
5473}
5474
5475/**
5476 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5477 * @edid: monitor EDID information
5478 * @name: pointer to a character array to hold the name of the monitor
5479 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5480 *
5481 */
5482void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5483{
5484 int name_length = 0;
5485
5486 if (bufsize <= 0)
5487 return;
5488
5489 if (edid) {
5490 char buf[13];
5491 struct drm_edid drm_edid = {
5492 .edid = edid,
5493 .size = edid_size(edid),
5494 };
5495
5496 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5497 memcpy(name, buf, name_length);
5498 }
5499
5500 name[name_length] = '\0';
5501}
5502EXPORT_SYMBOL(drm_edid_get_monitor_name);
5503
5504static void clear_eld(struct drm_connector *connector)
5505{
5506 memset(connector->eld, 0, sizeof(connector->eld));
5507
5508 connector->latency_present[0] = false;
5509 connector->latency_present[1] = false;
5510 connector->video_latency[0] = 0;
5511 connector->audio_latency[0] = 0;
5512 connector->video_latency[1] = 0;
5513 connector->audio_latency[1] = 0;
5514}
5515
5516/*
5517 * Get 3-byte SAD buffer from struct cea_sad.
5518 */
5519void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5520{
5521 sad[0] = cta_sad->format << 3 | cta_sad->channels;
5522 sad[1] = cta_sad->freq;
5523 sad[2] = cta_sad->byte2;
5524}
5525
5526/*
5527 * Set struct cea_sad from 3-byte SAD buffer.
5528 */
5529void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5530{
5531 cta_sad->format = (sad[0] & 0x78) >> 3;
5532 cta_sad->channels = sad[0] & 0x07;
5533 cta_sad->freq = sad[1] & 0x7f;
5534 cta_sad->byte2 = sad[2];
5535}
5536
5537/*
5538 * drm_edid_to_eld - build ELD from EDID
5539 * @connector: connector corresponding to the HDMI/DP sink
5540 * @drm_edid: EDID to parse
5541 *
5542 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5543 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5544 */
5545static void drm_edid_to_eld(struct drm_connector *connector,
5546 const struct drm_edid *drm_edid)
5547{
5548 const struct drm_display_info *info = &connector->display_info;
5549 const struct cea_db *db;
5550 struct cea_db_iter iter;
5551 uint8_t *eld = connector->eld;
5552 int total_sad_count = 0;
5553 int mnl;
5554
5555 if (!drm_edid)
5556 return;
5557
5558 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5559 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5560 connector->base.id, connector->name,
5561 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5562
5563 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5564 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5565
5566 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5567
5568 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5569 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5570 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5571 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5572
5573 cea_db_iter_edid_begin(drm_edid, &iter);
5574 cea_db_iter_for_each(db, &iter) {
5575 const u8 *data = cea_db_data(db);
5576 int len = cea_db_payload_len(db);
5577 int sad_count;
5578
5579 switch (cea_db_tag(db)) {
5580 case CTA_DB_AUDIO:
5581 /* Audio Data Block, contains SADs */
5582 sad_count = min(len / 3, 15 - total_sad_count);
5583 if (sad_count >= 1)
5584 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5585 data, sad_count * 3);
5586 total_sad_count += sad_count;
5587 break;
5588 case CTA_DB_SPEAKER:
5589 /* Speaker Allocation Data Block */
5590 if (len >= 1)
5591 eld[DRM_ELD_SPEAKER] = data[0];
5592 break;
5593 case CTA_DB_VENDOR:
5594 /* HDMI Vendor-Specific Data Block */
5595 if (cea_db_is_hdmi_vsdb(db))
5596 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5597 break;
5598 default:
5599 break;
5600 }
5601 }
5602 cea_db_iter_end(&iter);
5603
5604 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5605
5606 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5607 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5608 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5609 else
5610 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5611
5612 eld[DRM_ELD_BASELINE_ELD_LEN] =
5613 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5614
5615 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5616 connector->base.id, connector->name,
5617 drm_eld_size(eld), total_sad_count);
5618}
5619
5620static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5621 struct cea_sad **psads)
5622{
5623 const struct cea_db *db;
5624 struct cea_db_iter iter;
5625 int count = 0;
5626
5627 cea_db_iter_edid_begin(drm_edid, &iter);
5628 cea_db_iter_for_each(db, &iter) {
5629 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5630 struct cea_sad *sads;
5631 int i;
5632
5633 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5634 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5635 *psads = sads;
5636 if (!sads)
5637 return -ENOMEM;
5638 for (i = 0; i < count; i++)
5639 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
5640 break;
5641 }
5642 }
5643 cea_db_iter_end(&iter);
5644
5645 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5646
5647 return count;
5648}
5649
5650/**
5651 * drm_edid_to_sad - extracts SADs from EDID
5652 * @edid: EDID to parse
5653 * @sads: pointer that will be set to the extracted SADs
5654 *
5655 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5656 *
5657 * Note: The returned pointer needs to be freed using kfree().
5658 *
5659 * Return: The number of found SADs or negative number on error.
5660 */
5661int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5662{
5663 struct drm_edid drm_edid;
5664
5665 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5666}
5667EXPORT_SYMBOL(drm_edid_to_sad);
5668
5669static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5670 u8 **sadb)
5671{
5672 const struct cea_db *db;
5673 struct cea_db_iter iter;
5674 int count = 0;
5675
5676 cea_db_iter_edid_begin(drm_edid, &iter);
5677 cea_db_iter_for_each(db, &iter) {
5678 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5679 cea_db_payload_len(db) == 3) {
5680 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5681 GFP_KERNEL);
5682 if (!*sadb)
5683 return -ENOMEM;
5684 count = cea_db_payload_len(db);
5685 break;
5686 }
5687 }
5688 cea_db_iter_end(&iter);
5689
5690 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5691
5692 return count;
5693}
5694
5695/**
5696 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5697 * @edid: EDID to parse
5698 * @sadb: pointer to the speaker block
5699 *
5700 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5701 *
5702 * Note: The returned pointer needs to be freed using kfree().
5703 *
5704 * Return: The number of found Speaker Allocation Blocks or negative number on
5705 * error.
5706 */
5707int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5708{
5709 struct drm_edid drm_edid;
5710
5711 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5712 sadb);
5713}
5714EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5715
5716/**
5717 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5718 * @connector: connector associated with the HDMI/DP sink
5719 * @mode: the display mode
5720 *
5721 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5722 * the sink doesn't support audio or video.
5723 */
5724int drm_av_sync_delay(struct drm_connector *connector,
5725 const struct drm_display_mode *mode)
5726{
5727 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5728 int a, v;
5729
5730 if (!connector->latency_present[0])
5731 return 0;
5732 if (!connector->latency_present[1])
5733 i = 0;
5734
5735 a = connector->audio_latency[i];
5736 v = connector->video_latency[i];
5737
5738 /*
5739 * HDMI/DP sink doesn't support audio or video?
5740 */
5741 if (a == 255 || v == 255)
5742 return 0;
5743
5744 /*
5745 * Convert raw EDID values to millisecond.
5746 * Treat unknown latency as 0ms.
5747 */
5748 if (a)
5749 a = min(2 * (a - 1), 500);
5750 if (v)
5751 v = min(2 * (v - 1), 500);
5752
5753 return max(v - a, 0);
5754}
5755EXPORT_SYMBOL(drm_av_sync_delay);
5756
5757static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5758{
5759 const struct cea_db *db;
5760 struct cea_db_iter iter;
5761 bool hdmi = false;
5762
5763 /*
5764 * Because HDMI identifier is in Vendor Specific Block,
5765 * search it from all data blocks of CEA extension.
5766 */
5767 cea_db_iter_edid_begin(drm_edid, &iter);
5768 cea_db_iter_for_each(db, &iter) {
5769 if (cea_db_is_hdmi_vsdb(db)) {
5770 hdmi = true;
5771 break;
5772 }
5773 }
5774 cea_db_iter_end(&iter);
5775
5776 return hdmi;
5777}
5778
5779/**
5780 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5781 * @edid: monitor EDID information
5782 *
5783 * Parse the CEA extension according to CEA-861-B.
5784 *
5785 * Drivers that have added the modes parsed from EDID to drm_display_info
5786 * should use &drm_display_info.is_hdmi instead of calling this function.
5787 *
5788 * Return: True if the monitor is HDMI, false if not or unknown.
5789 */
5790bool drm_detect_hdmi_monitor(const struct edid *edid)
5791{
5792 struct drm_edid drm_edid;
5793
5794 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5795}
5796EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5797
5798static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5799{
5800 struct drm_edid_iter edid_iter;
5801 const struct cea_db *db;
5802 struct cea_db_iter iter;
5803 const u8 *edid_ext;
5804 bool has_audio = false;
5805
5806 drm_edid_iter_begin(drm_edid, &edid_iter);
5807 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5808 if (edid_ext[0] == CEA_EXT) {
5809 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5810 if (has_audio)
5811 break;
5812 }
5813 }
5814 drm_edid_iter_end(&edid_iter);
5815
5816 if (has_audio) {
5817 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5818 goto end;
5819 }
5820
5821 cea_db_iter_edid_begin(drm_edid, &iter);
5822 cea_db_iter_for_each(db, &iter) {
5823 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5824 const u8 *data = cea_db_data(db);
5825 int i;
5826
5827 for (i = 0; i < cea_db_payload_len(db); i += 3)
5828 DRM_DEBUG_KMS("CEA audio format %d\n",
5829 (data[i] >> 3) & 0xf);
5830 has_audio = true;
5831 break;
5832 }
5833 }
5834 cea_db_iter_end(&iter);
5835
5836end:
5837 return has_audio;
5838}
5839
5840/**
5841 * drm_detect_monitor_audio - check monitor audio capability
5842 * @edid: EDID block to scan
5843 *
5844 * Monitor should have CEA extension block.
5845 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5846 * audio' only. If there is any audio extension block and supported
5847 * audio format, assume at least 'basic audio' support, even if 'basic
5848 * audio' is not defined in EDID.
5849 *
5850 * Return: True if the monitor supports audio, false otherwise.
5851 */
5852bool drm_detect_monitor_audio(const struct edid *edid)
5853{
5854 struct drm_edid drm_edid;
5855
5856 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5857}
5858EXPORT_SYMBOL(drm_detect_monitor_audio);
5859
5860
5861/**
5862 * drm_default_rgb_quant_range - default RGB quantization range
5863 * @mode: display mode
5864 *
5865 * Determine the default RGB quantization range for the mode,
5866 * as specified in CEA-861.
5867 *
5868 * Return: The default RGB quantization range for the mode
5869 */
5870enum hdmi_quantization_range
5871drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5872{
5873 /* All CEA modes other than VIC 1 use limited quantization range. */
5874 return drm_match_cea_mode(mode) > 1 ?
5875 HDMI_QUANTIZATION_RANGE_LIMITED :
5876 HDMI_QUANTIZATION_RANGE_FULL;
5877}
5878EXPORT_SYMBOL(drm_default_rgb_quant_range);
5879
5880/* CTA-861 Video Data Block (CTA VDB) */
5881static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5882{
5883 struct drm_display_info *info = &connector->display_info;
5884 int i, vic_index, len = cea_db_payload_len(db);
5885 const u8 *svds = cea_db_data(db);
5886 u8 *vics;
5887
5888 if (!len)
5889 return;
5890
5891 /* Gracefully handle multiple VDBs, however unlikely that is */
5892 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5893 if (!vics)
5894 return;
5895
5896 vic_index = info->vics_len;
5897 info->vics_len += len;
5898 info->vics = vics;
5899
5900 for (i = 0; i < len; i++) {
5901 u8 vic = svd_to_vic(svds[i]);
5902
5903 if (!drm_valid_cea_vic(vic))
5904 vic = 0;
5905
5906 info->vics[vic_index++] = vic;
5907 }
5908}
5909
5910/*
5911 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5912 *
5913 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5914 * using the VICs themselves.
5915 */
5916static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5917{
5918 struct drm_display_info *info = &connector->display_info;
5919 struct drm_hdmi_info *hdmi = &info->hdmi;
5920 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5921
5922 for (i = 0; i < len; i++) {
5923 u8 vic = info->vics[i];
5924
5925 if (vic && y420cmdb_map & BIT_ULL(i))
5926 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5927 }
5928}
5929
5930static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5931{
5932 const struct drm_display_info *info = &connector->display_info;
5933 int i;
5934
5935 if (!vic || !info->vics)
5936 return false;
5937
5938 for (i = 0; i < info->vics_len; i++) {
5939 if (info->vics[i] == vic)
5940 return true;
5941 }
5942
5943 return false;
5944}
5945
5946/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5947static void parse_cta_y420vdb(struct drm_connector *connector,
5948 const struct cea_db *db)
5949{
5950 struct drm_display_info *info = &connector->display_info;
5951 struct drm_hdmi_info *hdmi = &info->hdmi;
5952 const u8 *svds = cea_db_data(db) + 1;
5953 int i;
5954
5955 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5956 u8 vic = svd_to_vic(svds[i]);
5957
5958 if (!drm_valid_cea_vic(vic))
5959 continue;
5960
5961 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5962 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5963 }
5964}
5965
5966static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5967{
5968 struct drm_display_info *info = &connector->display_info;
5969
5970 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5971 connector->base.id, connector->name, db[2]);
5972
5973 if (db[2] & EDID_CEA_VCDB_QS)
5974 info->rgb_quant_range_selectable = true;
5975}
5976
5977static
5978void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5979{
5980 switch (max_frl_rate) {
5981 case 1:
5982 *max_lanes = 3;
5983 *max_rate_per_lane = 3;
5984 break;
5985 case 2:
5986 *max_lanes = 3;
5987 *max_rate_per_lane = 6;
5988 break;
5989 case 3:
5990 *max_lanes = 4;
5991 *max_rate_per_lane = 6;
5992 break;
5993 case 4:
5994 *max_lanes = 4;
5995 *max_rate_per_lane = 8;
5996 break;
5997 case 5:
5998 *max_lanes = 4;
5999 *max_rate_per_lane = 10;
6000 break;
6001 case 6:
6002 *max_lanes = 4;
6003 *max_rate_per_lane = 12;
6004 break;
6005 case 0:
6006 default:
6007 *max_lanes = 0;
6008 *max_rate_per_lane = 0;
6009 }
6010}
6011
6012static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6013 const u8 *db)
6014{
6015 u8 dc_mask;
6016 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6017
6018 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6019 hdmi->y420_dc_modes = dc_mask;
6020}
6021
6022static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6023 const u8 *hf_scds)
6024{
6025 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6026
6027 if (!hdmi_dsc->v_1p2)
6028 return;
6029
6030 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6031 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6032
6033 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6034 hdmi_dsc->bpc_supported = 16;
6035 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6036 hdmi_dsc->bpc_supported = 12;
6037 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6038 hdmi_dsc->bpc_supported = 10;
6039 else
6040 /* Supports min 8 BPC if DSC 1.2 is supported*/
6041 hdmi_dsc->bpc_supported = 8;
6042
6043 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6044 u8 dsc_max_slices;
6045 u8 dsc_max_frl_rate;
6046
6047 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6048 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6049 &hdmi_dsc->max_frl_rate_per_lane);
6050
6051 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6052
6053 switch (dsc_max_slices) {
6054 case 1:
6055 hdmi_dsc->max_slices = 1;
6056 hdmi_dsc->clk_per_slice = 340;
6057 break;
6058 case 2:
6059 hdmi_dsc->max_slices = 2;
6060 hdmi_dsc->clk_per_slice = 340;
6061 break;
6062 case 3:
6063 hdmi_dsc->max_slices = 4;
6064 hdmi_dsc->clk_per_slice = 340;
6065 break;
6066 case 4:
6067 hdmi_dsc->max_slices = 8;
6068 hdmi_dsc->clk_per_slice = 340;
6069 break;
6070 case 5:
6071 hdmi_dsc->max_slices = 8;
6072 hdmi_dsc->clk_per_slice = 400;
6073 break;
6074 case 6:
6075 hdmi_dsc->max_slices = 12;
6076 hdmi_dsc->clk_per_slice = 400;
6077 break;
6078 case 7:
6079 hdmi_dsc->max_slices = 16;
6080 hdmi_dsc->clk_per_slice = 400;
6081 break;
6082 case 0:
6083 default:
6084 hdmi_dsc->max_slices = 0;
6085 hdmi_dsc->clk_per_slice = 0;
6086 }
6087 }
6088
6089 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6090 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6091}
6092
6093/* Sink Capability Data Structure */
6094static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6095 const u8 *hf_scds)
6096{
6097 struct drm_display_info *info = &connector->display_info;
6098 struct drm_hdmi_info *hdmi = &info->hdmi;
6099 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6100 int max_tmds_clock = 0;
6101 u8 max_frl_rate = 0;
6102 bool dsc_support = false;
6103
6104 info->has_hdmi_infoframe = true;
6105
6106 if (hf_scds[6] & 0x80) {
6107 hdmi->scdc.supported = true;
6108 if (hf_scds[6] & 0x40)
6109 hdmi->scdc.read_request = true;
6110 }
6111
6112 /*
6113 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6114 * And as per the spec, three factors confirm this:
6115 * * Availability of a HF-VSDB block in EDID (check)
6116 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6117 * * SCDC support available (let's check)
6118 * Lets check it out.
6119 */
6120
6121 if (hf_scds[5]) {
6122 struct drm_scdc *scdc = &hdmi->scdc;
6123
6124 /* max clock is 5000 KHz times block value */
6125 max_tmds_clock = hf_scds[5] * 5000;
6126
6127 if (max_tmds_clock > 340000) {
6128 info->max_tmds_clock = max_tmds_clock;
6129 }
6130
6131 if (scdc->supported) {
6132 scdc->scrambling.supported = true;
6133
6134 /* Few sinks support scrambling for clocks < 340M */
6135 if ((hf_scds[6] & 0x8))
6136 scdc->scrambling.low_rates = true;
6137 }
6138 }
6139
6140 if (hf_scds[7]) {
6141 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6142 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6143 &hdmi->max_frl_rate_per_lane);
6144 }
6145
6146 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6147
6148 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6149 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6150 dsc_support = true;
6151 }
6152
6153 drm_dbg_kms(connector->dev,
6154 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6155 connector->base.id, connector->name,
6156 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6157}
6158
6159static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6160 const u8 *hdmi)
6161{
6162 struct drm_display_info *info = &connector->display_info;
6163 unsigned int dc_bpc = 0;
6164
6165 /* HDMI supports at least 8 bpc */
6166 info->bpc = 8;
6167
6168 if (cea_db_payload_len(hdmi) < 6)
6169 return;
6170
6171 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6172 dc_bpc = 10;
6173 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6174 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6175 connector->base.id, connector->name);
6176 }
6177
6178 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6179 dc_bpc = 12;
6180 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6181 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6182 connector->base.id, connector->name);
6183 }
6184
6185 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6186 dc_bpc = 16;
6187 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6188 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6189 connector->base.id, connector->name);
6190 }
6191
6192 if (dc_bpc == 0) {
6193 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6194 connector->base.id, connector->name);
6195 return;
6196 }
6197
6198 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6199 connector->base.id, connector->name, dc_bpc);
6200 info->bpc = dc_bpc;
6201
6202 /* YCRCB444 is optional according to spec. */
6203 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6204 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6205 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6206 connector->base.id, connector->name);
6207 }
6208
6209 /*
6210 * Spec says that if any deep color mode is supported at all,
6211 * then deep color 36 bit must be supported.
6212 */
6213 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6214 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6215 connector->base.id, connector->name);
6216 }
6217}
6218
6219/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6220static void
6221drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6222{
6223 struct drm_display_info *info = &connector->display_info;
6224 u8 len = cea_db_payload_len(db);
6225
6226 info->is_hdmi = true;
6227
6228 info->source_physical_address = (db[4] << 8) | db[5];
6229
6230 if (len >= 6)
6231 info->dvi_dual = db[6] & 1;
6232 if (len >= 7)
6233 info->max_tmds_clock = db[7] * 5000;
6234
6235 /*
6236 * Try to infer whether the sink supports HDMI infoframes.
6237 *
6238 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6239 * supports infoframes if HDMI_Video_present is set.
6240 */
6241 if (len >= 8 && db[8] & BIT(5))
6242 info->has_hdmi_infoframe = true;
6243
6244 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6245 connector->base.id, connector->name,
6246 info->dvi_dual, info->max_tmds_clock);
6247
6248 drm_parse_hdmi_deep_color_info(connector, db);
6249}
6250
6251/*
6252 * See EDID extension for head-mounted and specialized monitors, specified at:
6253 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6254 */
6255static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6256 const u8 *db)
6257{
6258 struct drm_display_info *info = &connector->display_info;
6259 u8 version = db[4];
6260 bool desktop_usage = db[5] & BIT(6);
6261
6262 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6263 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6264 info->non_desktop = true;
6265
6266 drm_dbg_kms(connector->dev,
6267 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6268 connector->base.id, connector->name, version, db[5]);
6269}
6270
6271static void drm_parse_cea_ext(struct drm_connector *connector,
6272 const struct drm_edid *drm_edid)
6273{
6274 struct drm_display_info *info = &connector->display_info;
6275 struct drm_edid_iter edid_iter;
6276 const struct cea_db *db;
6277 struct cea_db_iter iter;
6278 const u8 *edid_ext;
6279 u64 y420cmdb_map = 0;
6280
6281 drm_edid_iter_begin(drm_edid, &edid_iter);
6282 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6283 if (edid_ext[0] != CEA_EXT)
6284 continue;
6285
6286 if (!info->cea_rev)
6287 info->cea_rev = edid_ext[1];
6288
6289 if (info->cea_rev != edid_ext[1])
6290 drm_dbg_kms(connector->dev,
6291 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6292 connector->base.id, connector->name,
6293 info->cea_rev, edid_ext[1]);
6294
6295 /* The existence of a CTA extension should imply RGB support */
6296 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6297 if (edid_ext[3] & EDID_CEA_YCRCB444)
6298 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6299 if (edid_ext[3] & EDID_CEA_YCRCB422)
6300 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6301 if (edid_ext[3] & EDID_BASIC_AUDIO)
6302 info->has_audio = true;
6303
6304 }
6305 drm_edid_iter_end(&edid_iter);
6306
6307 cea_db_iter_edid_begin(drm_edid, &iter);
6308 cea_db_iter_for_each(db, &iter) {
6309 /* FIXME: convert parsers to use struct cea_db */
6310 const u8 *data = (const u8 *)db;
6311
6312 if (cea_db_is_hdmi_vsdb(db))
6313 drm_parse_hdmi_vsdb_video(connector, data);
6314 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6315 cea_db_is_hdmi_forum_scdb(db))
6316 drm_parse_hdmi_forum_scds(connector, data);
6317 else if (cea_db_is_microsoft_vsdb(db))
6318 drm_parse_microsoft_vsdb(connector, data);
6319 else if (cea_db_is_y420cmdb(db))
6320 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6321 else if (cea_db_is_y420vdb(db))
6322 parse_cta_y420vdb(connector, db);
6323 else if (cea_db_is_vcdb(db))
6324 drm_parse_vcdb(connector, data);
6325 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6326 drm_parse_hdr_metadata_block(connector, data);
6327 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6328 parse_cta_vdb(connector, db);
6329 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6330 info->has_audio = true;
6331 }
6332 cea_db_iter_end(&iter);
6333
6334 if (y420cmdb_map)
6335 update_cta_y420cmdb(connector, y420cmdb_map);
6336}
6337
6338static
6339void get_monitor_range(const struct detailed_timing *timing, void *c)
6340{
6341 struct detailed_mode_closure *closure = c;
6342 struct drm_display_info *info = &closure->connector->display_info;
6343 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6344 const struct detailed_non_pixel *data = &timing->data.other_data;
6345 const struct detailed_data_monitor_range *range = &data->data.range;
6346 const struct edid *edid = closure->drm_edid->edid;
6347
6348 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6349 return;
6350
6351 /*
6352 * These limits are used to determine the VRR refresh
6353 * rate range. Only the "range limits only" variant
6354 * of the range descriptor seems to guarantee that
6355 * any and all timings are accepted by the sink, as
6356 * opposed to just timings conforming to the indicated
6357 * formula (GTF/GTF2/CVT). Thus other variants of the
6358 * range descriptor are not accepted here.
6359 */
6360 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6361 return;
6362
6363 monitor_range->min_vfreq = range->min_vfreq;
6364 monitor_range->max_vfreq = range->max_vfreq;
6365
6366 if (edid->revision >= 4) {
6367 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6368 monitor_range->min_vfreq += 255;
6369 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6370 monitor_range->max_vfreq += 255;
6371 }
6372}
6373
6374static void drm_get_monitor_range(struct drm_connector *connector,
6375 const struct drm_edid *drm_edid)
6376{
6377 const struct drm_display_info *info = &connector->display_info;
6378 struct detailed_mode_closure closure = {
6379 .connector = connector,
6380 .drm_edid = drm_edid,
6381 };
6382
6383 if (drm_edid->edid->revision < 4)
6384 return;
6385
6386 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6387 return;
6388
6389 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6390
6391 drm_dbg_kms(connector->dev,
6392 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6393 connector->base.id, connector->name,
6394 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6395}
6396
6397static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6398 const struct displayid_block *block)
6399{
6400 struct displayid_vesa_vendor_specific_block *vesa =
6401 (struct displayid_vesa_vendor_specific_block *)block;
6402 struct drm_display_info *info = &connector->display_info;
6403
6404 if (block->num_bytes < 3) {
6405 drm_dbg_kms(connector->dev,
6406 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6407 connector->base.id, connector->name, block->num_bytes);
6408 return;
6409 }
6410
6411 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6412 return;
6413
6414 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6415 drm_dbg_kms(connector->dev,
6416 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6417 connector->base.id, connector->name);
6418 return;
6419 }
6420
6421 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6422 default:
6423 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6424 connector->base.id, connector->name);
6425 fallthrough;
6426 case 0:
6427 info->mso_stream_count = 0;
6428 break;
6429 case 1:
6430 info->mso_stream_count = 2; /* 2 or 4 links */
6431 break;
6432 case 2:
6433 info->mso_stream_count = 4; /* 4 links */
6434 break;
6435 }
6436
6437 if (!info->mso_stream_count) {
6438 info->mso_pixel_overlap = 0;
6439 return;
6440 }
6441
6442 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6443 if (info->mso_pixel_overlap > 8) {
6444 drm_dbg_kms(connector->dev,
6445 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6446 connector->base.id, connector->name,
6447 info->mso_pixel_overlap);
6448 info->mso_pixel_overlap = 8;
6449 }
6450
6451 drm_dbg_kms(connector->dev,
6452 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6453 connector->base.id, connector->name,
6454 info->mso_stream_count, info->mso_pixel_overlap);
6455}
6456
6457static void drm_update_mso(struct drm_connector *connector,
6458 const struct drm_edid *drm_edid)
6459{
6460 const struct displayid_block *block;
6461 struct displayid_iter iter;
6462
6463 displayid_iter_edid_begin(drm_edid, &iter);
6464 displayid_iter_for_each(block, &iter) {
6465 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6466 drm_parse_vesa_mso_data(connector, block);
6467 }
6468 displayid_iter_end(&iter);
6469}
6470
6471/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6472 * all of the values which would have been set from EDID
6473 */
6474static void drm_reset_display_info(struct drm_connector *connector)
6475{
6476 struct drm_display_info *info = &connector->display_info;
6477
6478 info->width_mm = 0;
6479 info->height_mm = 0;
6480
6481 info->bpc = 0;
6482 info->color_formats = 0;
6483 info->cea_rev = 0;
6484 info->max_tmds_clock = 0;
6485 info->dvi_dual = false;
6486 info->is_hdmi = false;
6487 info->has_audio = false;
6488 info->has_hdmi_infoframe = false;
6489 info->rgb_quant_range_selectable = false;
6490 memset(&info->hdmi, 0, sizeof(info->hdmi));
6491
6492 info->edid_hdmi_rgb444_dc_modes = 0;
6493 info->edid_hdmi_ycbcr444_dc_modes = 0;
6494
6495 info->non_desktop = 0;
6496 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6497 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6498
6499 info->mso_stream_count = 0;
6500 info->mso_pixel_overlap = 0;
6501 info->max_dsc_bpp = 0;
6502
6503 kfree(info->vics);
6504 info->vics = NULL;
6505 info->vics_len = 0;
6506
6507 info->quirks = 0;
6508
6509 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6510}
6511
6512static void update_displayid_info(struct drm_connector *connector,
6513 const struct drm_edid *drm_edid)
6514{
6515 struct drm_display_info *info = &connector->display_info;
6516 const struct displayid_block *block;
6517 struct displayid_iter iter;
6518
6519 displayid_iter_edid_begin(drm_edid, &iter);
6520 displayid_iter_for_each(block, &iter) {
6521 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6522 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6523 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6524 info->non_desktop = true;
6525
6526 /*
6527 * We're only interested in the base section here, no need to
6528 * iterate further.
6529 */
6530 break;
6531 }
6532 displayid_iter_end(&iter);
6533}
6534
6535static void update_display_info(struct drm_connector *connector,
6536 const struct drm_edid *drm_edid)
6537{
6538 struct drm_display_info *info = &connector->display_info;
6539 const struct edid *edid;
6540
6541 drm_reset_display_info(connector);
6542 clear_eld(connector);
6543
6544 if (!drm_edid)
6545 return;
6546
6547 edid = drm_edid->edid;
6548
6549 info->quirks = edid_get_quirks(drm_edid);
6550
6551 info->width_mm = edid->width_cm * 10;
6552 info->height_mm = edid->height_cm * 10;
6553
6554 drm_get_monitor_range(connector, drm_edid);
6555
6556 if (edid->revision < 3)
6557 goto out;
6558
6559 if (!drm_edid_is_digital(drm_edid))
6560 goto out;
6561
6562 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6563 drm_parse_cea_ext(connector, drm_edid);
6564
6565 update_displayid_info(connector, drm_edid);
6566
6567 /*
6568 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6569 *
6570 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6571 * tells us to assume 8 bpc color depth if the EDID doesn't have
6572 * extensions which tell otherwise.
6573 */
6574 if (info->bpc == 0 && edid->revision == 3 &&
6575 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6576 info->bpc = 8;
6577 drm_dbg_kms(connector->dev,
6578 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6579 connector->base.id, connector->name, info->bpc);
6580 }
6581
6582 /* Only defined for 1.4 with digital displays */
6583 if (edid->revision < 4)
6584 goto out;
6585
6586 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6587 case DRM_EDID_DIGITAL_DEPTH_6:
6588 info->bpc = 6;
6589 break;
6590 case DRM_EDID_DIGITAL_DEPTH_8:
6591 info->bpc = 8;
6592 break;
6593 case DRM_EDID_DIGITAL_DEPTH_10:
6594 info->bpc = 10;
6595 break;
6596 case DRM_EDID_DIGITAL_DEPTH_12:
6597 info->bpc = 12;
6598 break;
6599 case DRM_EDID_DIGITAL_DEPTH_14:
6600 info->bpc = 14;
6601 break;
6602 case DRM_EDID_DIGITAL_DEPTH_16:
6603 info->bpc = 16;
6604 break;
6605 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6606 default:
6607 info->bpc = 0;
6608 break;
6609 }
6610
6611 drm_dbg_kms(connector->dev,
6612 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6613 connector->base.id, connector->name, info->bpc);
6614
6615 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6616 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6617 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6618 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6619
6620 drm_update_mso(connector, drm_edid);
6621
6622out:
6623 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6624 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6625 connector->base.id, connector->name,
6626 info->non_desktop ? " (redundant quirk)" : "");
6627 info->non_desktop = true;
6628 }
6629
6630 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6631 info->max_dsc_bpp = 15;
6632
6633 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6634 info->bpc = 6;
6635
6636 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6637 info->bpc = 8;
6638
6639 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6640 info->bpc = 10;
6641
6642 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6643 info->bpc = 12;
6644
6645 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6646 drm_edid_to_eld(connector, drm_edid);
6647}
6648
6649static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6650 struct displayid_detailed_timings_1 *timings,
6651 bool type_7)
6652{
6653 struct drm_display_mode *mode;
6654 unsigned pixel_clock = (timings->pixel_clock[0] |
6655 (timings->pixel_clock[1] << 8) |
6656 (timings->pixel_clock[2] << 16)) + 1;
6657 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6658 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6659 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6660 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6661 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6662 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6663 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6664 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6665 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6666 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6667
6668 mode = drm_mode_create(dev);
6669 if (!mode)
6670 return NULL;
6671
6672 /* resolution is kHz for type VII, and 10 kHz for type I */
6673 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6674 mode->hdisplay = hactive;
6675 mode->hsync_start = mode->hdisplay + hsync;
6676 mode->hsync_end = mode->hsync_start + hsync_width;
6677 mode->htotal = mode->hdisplay + hblank;
6678
6679 mode->vdisplay = vactive;
6680 mode->vsync_start = mode->vdisplay + vsync;
6681 mode->vsync_end = mode->vsync_start + vsync_width;
6682 mode->vtotal = mode->vdisplay + vblank;
6683
6684 mode->flags = 0;
6685 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6686 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6687 mode->type = DRM_MODE_TYPE_DRIVER;
6688
6689 if (timings->flags & 0x80)
6690 mode->type |= DRM_MODE_TYPE_PREFERRED;
6691 drm_mode_set_name(mode);
6692
6693 return mode;
6694}
6695
6696static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6697 const struct displayid_block *block)
6698{
6699 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6700 int i;
6701 int num_timings;
6702 struct drm_display_mode *newmode;
6703 int num_modes = 0;
6704 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6705 /* blocks must be multiple of 20 bytes length */
6706 if (block->num_bytes % 20)
6707 return 0;
6708
6709 num_timings = block->num_bytes / 20;
6710 for (i = 0; i < num_timings; i++) {
6711 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6712
6713 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6714 if (!newmode)
6715 continue;
6716
6717 drm_mode_probed_add(connector, newmode);
6718 num_modes++;
6719 }
6720 return num_modes;
6721}
6722
6723static int add_displayid_detailed_modes(struct drm_connector *connector,
6724 const struct drm_edid *drm_edid)
6725{
6726 const struct displayid_block *block;
6727 struct displayid_iter iter;
6728 int num_modes = 0;
6729
6730 displayid_iter_edid_begin(drm_edid, &iter);
6731 displayid_iter_for_each(block, &iter) {
6732 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6733 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6734 num_modes += add_displayid_detailed_1_modes(connector, block);
6735 }
6736 displayid_iter_end(&iter);
6737
6738 return num_modes;
6739}
6740
6741static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6742 const struct drm_edid *drm_edid)
6743{
6744 const struct drm_display_info *info = &connector->display_info;
6745 int num_modes = 0;
6746
6747 if (!drm_edid)
6748 return 0;
6749
6750 /*
6751 * EDID spec says modes should be preferred in this order:
6752 * - preferred detailed mode
6753 * - other detailed modes from base block
6754 * - detailed modes from extension blocks
6755 * - CVT 3-byte code modes
6756 * - standard timing codes
6757 * - established timing codes
6758 * - modes inferred from GTF or CVT range information
6759 *
6760 * We get this pretty much right.
6761 *
6762 * XXX order for additional mode types in extension blocks?
6763 */
6764 num_modes += add_detailed_modes(connector, drm_edid);
6765 num_modes += add_cvt_modes(connector, drm_edid);
6766 num_modes += add_standard_modes(connector, drm_edid);
6767 num_modes += add_established_modes(connector, drm_edid);
6768 num_modes += add_cea_modes(connector, drm_edid);
6769 num_modes += add_alternate_cea_modes(connector, drm_edid);
6770 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6771 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6772 num_modes += add_inferred_modes(connector, drm_edid);
6773
6774 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6775 edid_fixup_preferred(connector);
6776
6777 return num_modes;
6778}
6779
6780static void _drm_update_tile_info(struct drm_connector *connector,
6781 const struct drm_edid *drm_edid);
6782
6783static int _drm_edid_connector_property_update(struct drm_connector *connector,
6784 const struct drm_edid *drm_edid)
6785{
6786 struct drm_device *dev = connector->dev;
6787 int ret;
6788
6789 if (connector->edid_blob_ptr) {
6790 const struct edid *old_edid = connector->edid_blob_ptr->data;
6791
6792 if (old_edid) {
6793 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6794 connector->epoch_counter++;
6795 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6796 connector->base.id, connector->name,
6797 connector->epoch_counter);
6798 }
6799 }
6800 }
6801
6802 ret = drm_property_replace_global_blob(dev,
6803 &connector->edid_blob_ptr,
6804 drm_edid ? drm_edid->size : 0,
6805 drm_edid ? drm_edid->edid : NULL,
6806 &connector->base,
6807 dev->mode_config.edid_property);
6808 if (ret) {
6809 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6810 connector->base.id, connector->name, ret);
6811 goto out;
6812 }
6813
6814 ret = drm_object_property_set_value(&connector->base,
6815 dev->mode_config.non_desktop_property,
6816 connector->display_info.non_desktop);
6817 if (ret) {
6818 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6819 connector->base.id, connector->name, ret);
6820 goto out;
6821 }
6822
6823 ret = drm_connector_set_tile_property(connector);
6824 if (ret) {
6825 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6826 connector->base.id, connector->name, ret);
6827 goto out;
6828 }
6829
6830out:
6831 return ret;
6832}
6833
6834/**
6835 * drm_edid_connector_update - Update connector information from EDID
6836 * @connector: Connector
6837 * @drm_edid: EDID
6838 *
6839 * Update the connector display info, ELD, HDR metadata, relevant properties,
6840 * etc. from the passed in EDID.
6841 *
6842 * If EDID is NULL, reset the information.
6843 *
6844 * Must be called before calling drm_edid_connector_add_modes().
6845 *
6846 * Return: 0 on success, negative error on errors.
6847 */
6848int drm_edid_connector_update(struct drm_connector *connector,
6849 const struct drm_edid *drm_edid)
6850{
6851 update_display_info(connector, drm_edid);
6852
6853 _drm_update_tile_info(connector, drm_edid);
6854
6855 return _drm_edid_connector_property_update(connector, drm_edid);
6856}
6857EXPORT_SYMBOL(drm_edid_connector_update);
6858
6859/**
6860 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6861 * @connector: Connector
6862 *
6863 * Add the modes from the previously updated EDID property to the connector
6864 * probed modes list.
6865 *
6866 * drm_edid_connector_update() must have been called before this to update the
6867 * EDID property.
6868 *
6869 * Return: The number of modes added, or 0 if we couldn't find any.
6870 */
6871int drm_edid_connector_add_modes(struct drm_connector *connector)
6872{
6873 const struct drm_edid *drm_edid = NULL;
6874 int count;
6875
6876 if (connector->edid_blob_ptr)
6877 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6878 connector->edid_blob_ptr->length);
6879
6880 count = _drm_edid_connector_add_modes(connector, drm_edid);
6881
6882 drm_edid_free(drm_edid);
6883
6884 return count;
6885}
6886EXPORT_SYMBOL(drm_edid_connector_add_modes);
6887
6888/**
6889 * drm_connector_update_edid_property - update the edid property of a connector
6890 * @connector: drm connector
6891 * @edid: new value of the edid property
6892 *
6893 * This function creates a new blob modeset object and assigns its id to the
6894 * connector's edid property.
6895 * Since we also parse tile information from EDID's displayID block, we also
6896 * set the connector's tile property here. See drm_connector_set_tile_property()
6897 * for more details.
6898 *
6899 * This function is deprecated. Use drm_edid_connector_update() instead.
6900 *
6901 * Returns:
6902 * Zero on success, negative errno on failure.
6903 */
6904int drm_connector_update_edid_property(struct drm_connector *connector,
6905 const struct edid *edid)
6906{
6907 struct drm_edid drm_edid;
6908
6909 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6910}
6911EXPORT_SYMBOL(drm_connector_update_edid_property);
6912
6913/**
6914 * drm_add_edid_modes - add modes from EDID data, if available
6915 * @connector: connector we're probing
6916 * @edid: EDID data
6917 *
6918 * Add the specified modes to the connector's mode list. Also fills out the
6919 * &drm_display_info structure and ELD in @connector with any information which
6920 * can be derived from the edid.
6921 *
6922 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6923 *
6924 * Return: The number of modes added or 0 if we couldn't find any.
6925 */
6926int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6927{
6928 struct drm_edid _drm_edid;
6929 const struct drm_edid *drm_edid;
6930
6931 if (edid && !drm_edid_is_valid(edid)) {
6932 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6933 connector->base.id, connector->name);
6934 edid = NULL;
6935 }
6936
6937 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6938
6939 update_display_info(connector, drm_edid);
6940
6941 return _drm_edid_connector_add_modes(connector, drm_edid);
6942}
6943EXPORT_SYMBOL(drm_add_edid_modes);
6944
6945/**
6946 * drm_add_modes_noedid - add modes for the connectors without EDID
6947 * @connector: connector we're probing
6948 * @hdisplay: the horizontal display limit
6949 * @vdisplay: the vertical display limit
6950 *
6951 * Add the specified modes to the connector's mode list. Only when the
6952 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6953 *
6954 * Return: The number of modes added or 0 if we couldn't find any.
6955 */
6956int drm_add_modes_noedid(struct drm_connector *connector,
6957 int hdisplay, int vdisplay)
6958{
6959 int i, count, num_modes = 0;
6960 struct drm_display_mode *mode;
6961 struct drm_device *dev = connector->dev;
6962
6963 count = ARRAY_SIZE(drm_dmt_modes);
6964 if (hdisplay < 0)
6965 hdisplay = 0;
6966 if (vdisplay < 0)
6967 vdisplay = 0;
6968
6969 for (i = 0; i < count; i++) {
6970 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6971
6972 if (hdisplay && vdisplay) {
6973 /*
6974 * Only when two are valid, they will be used to check
6975 * whether the mode should be added to the mode list of
6976 * the connector.
6977 */
6978 if (ptr->hdisplay > hdisplay ||
6979 ptr->vdisplay > vdisplay)
6980 continue;
6981 }
6982 if (drm_mode_vrefresh(ptr) > 61)
6983 continue;
6984 mode = drm_mode_duplicate(dev, ptr);
6985 if (mode) {
6986 drm_mode_probed_add(connector, mode);
6987 num_modes++;
6988 }
6989 }
6990 return num_modes;
6991}
6992EXPORT_SYMBOL(drm_add_modes_noedid);
6993
6994static bool is_hdmi2_sink(const struct drm_connector *connector)
6995{
6996 /*
6997 * FIXME: sil-sii8620 doesn't have a connector around when
6998 * we need one, so we have to be prepared for a NULL connector.
6999 */
7000 if (!connector)
7001 return true;
7002
7003 return connector->display_info.hdmi.scdc.supported ||
7004 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7005}
7006
7007static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7008 const struct drm_display_mode *mode)
7009{
7010 bool has_hdmi_infoframe = connector ?
7011 connector->display_info.has_hdmi_infoframe : false;
7012
7013 if (!has_hdmi_infoframe)
7014 return 0;
7015
7016 /* No HDMI VIC when signalling 3D video format */
7017 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7018 return 0;
7019
7020 return drm_match_hdmi_mode(mode);
7021}
7022
7023static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7024 const struct drm_display_mode *mode)
7025{
7026 /*
7027 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7028 * we should send its VIC in vendor infoframes, else send the
7029 * VIC in AVI infoframes. Lets check if this mode is present in
7030 * HDMI 1.4b 4K modes
7031 */
7032 if (drm_mode_hdmi_vic(connector, mode))
7033 return 0;
7034
7035 return drm_match_cea_mode(mode);
7036}
7037
7038/*
7039 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7040 * conform to HDMI 1.4.
7041 *
7042 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7043 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7044 *
7045 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7046 * version.
7047 */
7048static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7049{
7050 if (!is_hdmi2_sink(connector) && vic > 64 &&
7051 !cta_vdb_has_vic(connector, vic))
7052 return 0;
7053
7054 return vic;
7055}
7056
7057/**
7058 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7059 * data from a DRM display mode
7060 * @frame: HDMI AVI infoframe
7061 * @connector: the connector
7062 * @mode: DRM display mode
7063 *
7064 * Return: 0 on success or a negative error code on failure.
7065 */
7066int
7067drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7068 const struct drm_connector *connector,
7069 const struct drm_display_mode *mode)
7070{
7071 enum hdmi_picture_aspect picture_aspect;
7072 u8 vic, hdmi_vic;
7073
7074 if (!frame || !mode)
7075 return -EINVAL;
7076
7077 hdmi_avi_infoframe_init(frame);
7078
7079 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7080 frame->pixel_repeat = 1;
7081
7082 vic = drm_mode_cea_vic(connector, mode);
7083 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7084
7085 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7086
7087 /*
7088 * As some drivers don't support atomic, we can't use connector state.
7089 * So just initialize the frame with default values, just the same way
7090 * as it's done with other properties here.
7091 */
7092 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7093 frame->itc = 0;
7094
7095 /*
7096 * Populate picture aspect ratio from either
7097 * user input (if specified) or from the CEA/HDMI mode lists.
7098 */
7099 picture_aspect = mode->picture_aspect_ratio;
7100 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7101 if (vic)
7102 picture_aspect = drm_get_cea_aspect_ratio(vic);
7103 else if (hdmi_vic)
7104 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7105 }
7106
7107 /*
7108 * The infoframe can't convey anything but none, 4:3
7109 * and 16:9, so if the user has asked for anything else
7110 * we can only satisfy it by specifying the right VIC.
7111 */
7112 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7113 if (vic) {
7114 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7115 return -EINVAL;
7116 } else if (hdmi_vic) {
7117 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7118 return -EINVAL;
7119 } else {
7120 return -EINVAL;
7121 }
7122
7123 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7124 }
7125
7126 frame->video_code = vic_for_avi_infoframe(connector, vic);
7127 frame->picture_aspect = picture_aspect;
7128 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7129 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7130
7131 return 0;
7132}
7133EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7134
7135/**
7136 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7137 * quantization range information
7138 * @frame: HDMI AVI infoframe
7139 * @connector: the connector
7140 * @mode: DRM display mode
7141 * @rgb_quant_range: RGB quantization range (Q)
7142 */
7143void
7144drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7145 const struct drm_connector *connector,
7146 const struct drm_display_mode *mode,
7147 enum hdmi_quantization_range rgb_quant_range)
7148{
7149 const struct drm_display_info *info = &connector->display_info;
7150
7151 /*
7152 * CEA-861:
7153 * "A Source shall not send a non-zero Q value that does not correspond
7154 * to the default RGB Quantization Range for the transmitted Picture
7155 * unless the Sink indicates support for the Q bit in a Video
7156 * Capabilities Data Block."
7157 *
7158 * HDMI 2.0 recommends sending non-zero Q when it does match the
7159 * default RGB quantization range for the mode, even when QS=0.
7160 */
7161 if (info->rgb_quant_range_selectable ||
7162 rgb_quant_range == drm_default_rgb_quant_range(mode))
7163 frame->quantization_range = rgb_quant_range;
7164 else
7165 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7166
7167 /*
7168 * CEA-861-F:
7169 * "When transmitting any RGB colorimetry, the Source should set the
7170 * YQ-field to match the RGB Quantization Range being transmitted
7171 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7172 * set YQ=1) and the Sink shall ignore the YQ-field."
7173 *
7174 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7175 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7176 * good way to tell which version of CEA-861 the sink supports, so
7177 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7178 * on CEA-861-F.
7179 */
7180 if (!is_hdmi2_sink(connector) ||
7181 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7182 frame->ycc_quantization_range =
7183 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7184 else
7185 frame->ycc_quantization_range =
7186 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7187}
7188EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7189
7190static enum hdmi_3d_structure
7191s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7192{
7193 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7194
7195 switch (layout) {
7196 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7197 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7198 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7199 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7200 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7201 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7202 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7203 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7204 case DRM_MODE_FLAG_3D_L_DEPTH:
7205 return HDMI_3D_STRUCTURE_L_DEPTH;
7206 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7207 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7208 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7209 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7210 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7211 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7212 default:
7213 return HDMI_3D_STRUCTURE_INVALID;
7214 }
7215}
7216
7217/**
7218 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7219 * data from a DRM display mode
7220 * @frame: HDMI vendor infoframe
7221 * @connector: the connector
7222 * @mode: DRM display mode
7223 *
7224 * Note that there's is a need to send HDMI vendor infoframes only when using a
7225 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7226 * function will return -EINVAL, error that can be safely ignored.
7227 *
7228 * Return: 0 on success or a negative error code on failure.
7229 */
7230int
7231drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7232 const struct drm_connector *connector,
7233 const struct drm_display_mode *mode)
7234{
7235 /*
7236 * FIXME: sil-sii8620 doesn't have a connector around when
7237 * we need one, so we have to be prepared for a NULL connector.
7238 */
7239 bool has_hdmi_infoframe = connector ?
7240 connector->display_info.has_hdmi_infoframe : false;
7241 int err;
7242
7243 if (!frame || !mode)
7244 return -EINVAL;
7245
7246 if (!has_hdmi_infoframe)
7247 return -EINVAL;
7248
7249 err = hdmi_vendor_infoframe_init(frame);
7250 if (err < 0)
7251 return err;
7252
7253 /*
7254 * Even if it's not absolutely necessary to send the infoframe
7255 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7256 * know that the sink can handle it. This is based on a
7257 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7258 * have trouble realizing that they should switch from 3D to 2D
7259 * mode if the source simply stops sending the infoframe when
7260 * it wants to switch from 3D to 2D.
7261 */
7262 frame->vic = drm_mode_hdmi_vic(connector, mode);
7263 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7264
7265 return 0;
7266}
7267EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7268
7269static void drm_parse_tiled_block(struct drm_connector *connector,
7270 const struct displayid_block *block)
7271{
7272 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7273 u16 w, h;
7274 u8 tile_v_loc, tile_h_loc;
7275 u8 num_v_tile, num_h_tile;
7276 struct drm_tile_group *tg;
7277
7278 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7279 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7280
7281 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7282 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7283 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7284 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7285
7286 connector->has_tile = true;
7287 if (tile->tile_cap & 0x80)
7288 connector->tile_is_single_monitor = true;
7289
7290 connector->num_h_tile = num_h_tile + 1;
7291 connector->num_v_tile = num_v_tile + 1;
7292 connector->tile_h_loc = tile_h_loc;
7293 connector->tile_v_loc = tile_v_loc;
7294 connector->tile_h_size = w + 1;
7295 connector->tile_v_size = h + 1;
7296
7297 drm_dbg_kms(connector->dev,
7298 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7299 connector->base.id, connector->name,
7300 tile->tile_cap,
7301 connector->tile_h_size, connector->tile_v_size,
7302 connector->num_h_tile, connector->num_v_tile,
7303 connector->tile_h_loc, connector->tile_v_loc,
7304 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7305
7306 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7307 if (!tg)
7308 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7309 if (!tg)
7310 return;
7311
7312 if (connector->tile_group != tg) {
7313 /* if we haven't got a pointer,
7314 take the reference, drop ref to old tile group */
7315 if (connector->tile_group)
7316 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7317 connector->tile_group = tg;
7318 } else {
7319 /* if same tile group, then release the ref we just took. */
7320 drm_mode_put_tile_group(connector->dev, tg);
7321 }
7322}
7323
7324static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7325 const struct displayid_block *block)
7326{
7327 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 &&
7328 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7329 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7330 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7331}
7332
7333static void _drm_update_tile_info(struct drm_connector *connector,
7334 const struct drm_edid *drm_edid)
7335{
7336 const struct displayid_block *block;
7337 struct displayid_iter iter;
7338
7339 connector->has_tile = false;
7340
7341 displayid_iter_edid_begin(drm_edid, &iter);
7342 displayid_iter_for_each(block, &iter) {
7343 if (displayid_is_tiled_block(&iter, block))
7344 drm_parse_tiled_block(connector, block);
7345 }
7346 displayid_iter_end(&iter);
7347
7348 if (!connector->has_tile && connector->tile_group) {
7349 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7350 connector->tile_group = NULL;
7351 }
7352}
7353
7354/**
7355 * drm_edid_is_digital - is digital?
7356 * @drm_edid: The EDID
7357 *
7358 * Return true if input is digital.
7359 */
7360bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7361{
7362 return drm_edid && drm_edid->edid &&
7363 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7364}
7365EXPORT_SYMBOL(drm_edid_is_digital);